diff --git a/verilog/dv/cocotb/tests/debug/debug.c b/verilog/dv/cocotb/tests/debug/debug.c
index b54e35ff..33ed397e 100644
--- a/verilog/dv/cocotb/tests/debug/debug.c
+++ b/verilog/dv/cocotb/tests/debug/debug.c
@@ -32,14 +32,12 @@ void main()
     reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
     reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
 
-    (*(volatile uint32_t*) CSR_DEBUG_MODE_OUT_ADDR ) = 1; // enable debug mode
-
-
     // Now, apply the configuration
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
+    
+    (*(volatile uint32_t*) CSR_DEBUG_MODE_OUT_ADDR ) = 1; // enable debug mode
 
-    // reg_uart_enable = 1;
     // start of the test
     reg_debug_1 = 0xAA;
 
diff --git a/verilog/dv/cocotb/tests/debug/debug.py b/verilog/dv/cocotb/tests/debug/debug.py
index 7dbc900d..3b19f552 100644
--- a/verilog/dv/cocotb/tests/debug/debug.py
+++ b/verilog/dv/cocotb/tests/debug/debug.py
@@ -19,7 +19,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def debug(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=375862)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=33840)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -82,7 +82,7 @@ async def uart_get_char(caravelEnv):
 async def wb_write(caravelEnv,addr,data):
     addr_bits = bin(addr)[2:].zfill(32)[::-1]
     data_bits = bin(data)[2:].zfill(32)[::-1]
-    cocotb.log.info(f"[TEST] address bits = {addr_bits} {type(addr_bits)}")
+    cocotb.log.debug(f"[TEST] address bits = {addr_bits} {type(addr_bits)}")
     await uart_send_char(caravelEnv, '10000000') # write cmd
     await uart_send_char(caravelEnv, '10000000') # size
     await uart_send_char(caravelEnv, addr_bits[24:32])