mirror of https://github.com/efabless/caravel.git
Merge branch 'update_soc' of github.com:efabless/caravel into update_soc
This commit is contained in:
Passant
commit
28aed3b8d7
File diff suppressed because it is too large
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#!/bin/bash
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#
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# run_caravan_lvs_3.sh ---
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#
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# Run LVS on caravan. Read GDS using the recipe developed for open_pdks.
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# Read I/O cells from vendor GDS first so that they get replaced.
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#
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echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
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echo ${PDK:=sky130A} > /dev/null
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echo ${CARAVEL_ROOT:=/home/tim/gits/caravel} > /dev/null
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echo ${LITEX_ROOT:=/home/tim/gits/caravel_mgmt_soc_litex} > /dev/null
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echo "Running LVS on caravan."
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if [ $# -eq 0 ]; then
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echo "No arguments---running LVS on existing spice if it exists."
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elif [ $1 == "extract" ]; then
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echo "Forced new extraction."
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rm -f caravan.spice
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else
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echo "Ending without running LVS."
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exit 0
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fi
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if [ ! -f caravan.spice ]; then
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magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
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drc off
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crashbackups stop
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# ! This recipe taken from open_pdks/sky130/custom/scripts/gds_import_io.tcl
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gds flatten true
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gds flatglob *_cdns_*
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gds flatglob *sky130_fd_pr__*_example_*
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# ! flatten within the 120x2 ESD device
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gds flatglob *sky130_fd_io__gnd2gnd_*
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# The following cells have to be flattened for the gpiov2 pad to read in
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# correctly, and produce a layout that can be extracted and generate an
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# LVS clean netlist.
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### flatten within the analog mux isolated P region
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gds flatglob *sky130_fd_io__amx*
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gds flatglob *sky130_fd_io__xor*
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gds flatglob *sky130_fd_io__gpiov2_amx*
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gds flatglob *sky130_fd_io__gpiov2_amux*
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### flatten within the isolated VSSIO domain
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gds flatglob *sky130_fd_io__feas_com_pupredrvr*
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gds flatglob *sky130_fd_io__com_pupredrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__com_pdpredrvr_pbiasv2*
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gds flatglob *sky130_fd_io__gpiov2_pdpredrvr_strong*
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### flatten in opathv2
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gds flatglob *sky130_fd_io__com_pudrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__com_pdpredrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__gpiov2_obpredrvr*
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gds flatglob *sky130_fd_io__hvsbt_*
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### flatten in ipath
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gds flatglob *sky130_fd_io__gpiov2_ictl_logic*
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### avoid splitting a netlist that passes in contorted ways through the
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### layout hierarchy
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gds flatglob *sky130_fd_io__gpio_pddrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__gpiov2_pddrvr_strong*
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gds read $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/gds/sky130_fd_io.gds
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gds read $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/gds/sky130_ef_io.gds
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# Now assert that existing views must take precedence
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gds noduplicates true
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# GDS is still written in legacy mode
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cif istyle sky130(legacy)
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# And read in the full chip (except for cells already read)
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gds read $CARAVEL_ROOT/gds/caravan-signoff.gds.gz
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load caravan
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select top cell
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expand
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extract do local
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extract no all
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extract unique
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extract all
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ext2spice lvs
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ext2spice
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EOF
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rm -f *.ext
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fi
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cat > netgenD.tcl << EOF
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puts stdout "Reading netlist caravan.spice"
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set circuit1 [readnet spice caravan.spice]
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puts stdout "Reading SPICE netlists of I/O"
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set circuit2 [readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/sky130_fd_io.spice]
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/sky130_ef_io.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice \$circuit2
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puts stdout "Reading all gate-level verilog submodules"
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readnet verilog $CARAVEL_ROOT/verilog/rtl/defines.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/constant_block.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/digital_pll.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_control_block.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block_0403.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block_0801.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block_1803.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_logic_high.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_signal_buffering_alt.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/mprj_logic_high.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/mgmt_protect.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/spare_logic_block.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/caravel_clocking.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/user_id_programming.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/xres_buf.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/buff_flash_clkrst.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/housekeeping.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/chip_io_alt.v \$circuit2
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puts stdout "Reading LiteX gate-level verilog submodules"
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readnet verilog $LITEX_ROOT/verilog/gl/RAM128.v \$circuit2
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readnet verilog $LITEX_ROOT/verilog/gl/RAM256.v \$circuit2
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readnet verilog $LITEX_ROOT/verilog/gl/mgmt_core_wrapper.v \$circuit2
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puts stdout "Reading top gate-level verilog module"
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readnet verilog $CARAVEL_ROOT/verilog/gl/caravan-signoff.v \$circuit2
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# Cells in management core wrapper (layout) are prefixed with RL_ or KF_
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set cells1 [cells list -all \$circuit1]
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set cells2 [cells list -all \$circuit2]
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foreach cell \$cells1 {
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if {[regexp "\\[A-Z\\]\\[A-Z\\]_(.+)" \$cell match cellname]} {
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if {([lsearch \$cells2 \$cell] < 0) && ([lsearch \$cells2 \$cellname] >= 0) && ([lsearch \$cells1 \$cellname] < 0)} {
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equate classes "\$circuit1 \$cell" "\$circuit2 \$cellname"
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puts stdout "Matching pins of \$cell in circuit 1 and \$cellname in circuit 2"
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equate pins "\$circuit1 \$cell" "\$circuit2 \$cellname"
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}
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}
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# Ignore fill cells in standard cell sets that have two-letter prefixes.
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if {[regexp {\\[A-Z\\]\\[A-Z\\]_sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
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ignore class "\$circuit1 \$cell"
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}
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}
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# Run LVS
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flatten class "\$circuit2 user_project_wrapper"
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lvs "\$circuit1 caravan" "\$circuit2 caravan" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravan_3_comp.out
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EOF
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export NETGEN_COLUMNS=90
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export MAGIC_EXT_USE_GDS=1
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netgen -batch source netgenD.tcl
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# rm netgenD.tcl
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exit 0
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@ -0,0 +1,156 @@
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#!/bin/bash
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#
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# run_caravel_lvs_3.sh ---
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#
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# Run LVS on caravel. Read GDS using the recipe developed for open_pdks.
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# Read I/O cells from vendor GDS first so that they get replaced.
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#
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echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
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echo ${PDK:=sky130A} > /dev/null
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echo ${CARAVEL_ROOT:=/home/tim/gits/caravel} > /dev/null
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echo ${LITEX_ROOT:=/home/tim/gits/caravel_mgmt_soc_litex} > /dev/null
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echo "Running LVS on caravel."
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if [ $# -eq 0 ]; then
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echo "No arguments---running LVS on existing spice if it exists."
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elif [ $1 == "extract" ]; then
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echo "Forced new extraction."
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rm -f caravel.spice
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else
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echo "Ending without running LVS."
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exit 0
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fi
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if [ ! -f caravel.spice ]; then
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magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
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drc off
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crashbackups stop
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# ! This recipe taken from open_pdks/sky130/custom/scripts/gds_import_io.tcl
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gds flatten true
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gds flatglob *_cdns_*
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gds flatglob *sky130_fd_pr__*_example_*
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# ! flatten within the 120x2 ESD device
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gds flatglob *sky130_fd_io__gnd2gnd_*
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# The following cells have to be flattened for the gpiov2 pad to read in
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# correctly, and produce a layout that can be extracted and generate an
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# LVS clean netlist.
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### flatten within the analog mux isolated P region
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gds flatglob *sky130_fd_io__amx*
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gds flatglob *sky130_fd_io__xor*
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gds flatglob *sky130_fd_io__gpiov2_amx*
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gds flatglob *sky130_fd_io__gpiov2_amux*
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### flatten within the isolated VSSIO domain
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gds flatglob *sky130_fd_io__feas_com_pupredrvr*
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gds flatglob *sky130_fd_io__com_pupredrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__com_pdpredrvr_pbiasv2*
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gds flatglob *sky130_fd_io__gpiov2_pdpredrvr_strong*
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### flatten in opathv2
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gds flatglob *sky130_fd_io__com_pudrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__com_pdpredrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__gpiov2_obpredrvr*
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gds flatglob *sky130_fd_io__hvsbt_*
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### flatten in ipath
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gds flatglob *sky130_fd_io__gpiov2_ictl_logic*
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### avoid splitting a netlist that passes in contorted ways through the
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### layout hierarchy
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gds flatglob *sky130_fd_io__gpio_pddrvr_strong_slowv2*
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gds flatglob *sky130_fd_io__gpiov2_pddrvr_strong*
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gds read $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/gds/sky130_fd_io.gds
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gds read $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/gds/sky130_ef_io.gds
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# Now assert that existing views must take precedence
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gds noduplicates true
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# GDS is still written in legacy mode
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cif istyle sky130(legacy)
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# And read in the full chip (except for cells already read)
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gds read $CARAVEL_ROOT/gds/caravel-signoff.gds.gz
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load caravel
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select top cell
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expand
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extract do local
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extract no all
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extract unique
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extract all
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ext2spice lvs
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ext2spice
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EOF
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rm -f *.ext
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fi
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cat > netgenD.tcl << EOF
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puts stdout "Reading netlist caravel.spice"
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set circuit1 [readnet spice caravel.spice]
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puts stdout "Reading SPICE netlists of I/O"
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set circuit2 [readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/sky130_fd_io.spice]
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/sky130_ef_io.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice \$circuit2
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readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice \$circuit2
|
||||
puts stdout "Reading all gate-level verilog submodules"
|
||||
readnet verilog $CARAVEL_ROOT/verilog/rtl/defines.v \$circuit2
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||||
readnet verilog $CARAVEL_ROOT/verilog/gl/constant_block.v \$circuit2
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||||
readnet verilog $CARAVEL_ROOT/verilog/gl/digital_pll.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_control_block.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block_0403.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block_0801.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_defaults_block_1803.v \$circuit2
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readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_logic_high.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/gpio_signal_buffering.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/mprj_logic_high.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/mgmt_protect.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/spare_logic_block.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/caravel_clocking.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/user_id_programming.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/xres_buf.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/buff_flash_clkrst.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/housekeeping.v \$circuit2
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/chip_io.v \$circuit2
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||||
puts stdout "Reading LiteX gate-level verilog submodules"
|
||||
readnet verilog $LITEX_ROOT/verilog/gl/RAM128.v \$circuit2
|
||||
readnet verilog $LITEX_ROOT/verilog/gl/RAM256.v \$circuit2
|
||||
readnet verilog $LITEX_ROOT/verilog/gl/mgmt_core_wrapper.v \$circuit2
|
||||
puts stdout "Reading top gate-level verilog module"
|
||||
readnet verilog $CARAVEL_ROOT/verilog/gl/caravel-signoff.v \$circuit2
|
||||
|
||||
# Cells in management core wrapper (layout) are prefixed with RL_ or KF_
|
||||
set cells1 [cells list -all \$circuit1]
|
||||
set cells2 [cells list -all \$circuit2]
|
||||
foreach cell \$cells1 {
|
||||
if {[regexp "\\[A-Z\\]\\[A-Z\\]_(.+)" \$cell match cellname]} {
|
||||
if {([lsearch \$cells2 \$cell] < 0) && ([lsearch \$cells2 \$cellname] >= 0) && ([lsearch \$cells1 \$cellname] < 0)} {
|
||||
equate classes "\$circuit1 \$cell" "\$circuit2 \$cellname"
|
||||
puts stdout "Matching pins of \$cell in circuit 1 and \$cellname in circuit 2"
|
||||
equate pins "\$circuit1 \$cell" "\$circuit2 \$cellname"
|
||||
}
|
||||
}
|
||||
# Ignore fill cells in standard cell sets that have two-letter prefixes.
|
||||
if {[regexp {\\[A-Z\\]\\[A-Z\\]_sky130_fd_sc_[^_]+__fill_[[:digit:]]+} \$cell match]} {
|
||||
ignore class "\$circuit1 \$cell"
|
||||
}
|
||||
}
|
||||
|
||||
# Run LVS
|
||||
flatten class "\$circuit2 user_project_wrapper"
|
||||
lvs "\$circuit1 caravel" "\$circuit2 caravel" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravel_3_comp.out
|
||||
EOF
|
||||
|
||||
export NETGEN_COLUMNS=90
|
||||
export MAGIC_EXT_USE_GDS=1
|
||||
netgen -batch source netgenD.tcl
|
||||
# rm netgenD.tcl
|
||||
|
||||
exit 0
|
||||
Loading…
Reference in New Issue