Merge branch 'cocotb' of github.com:efabless/caravel into cocotb

manifest

@@ -3,7 +3,7 @@
 684085713662e37a26f9f981d35be7c6c7ff6e9a  verilog/rtl/__user_analog_project_wrapper.v
 79cdb50a7dd60f69b63c0b6440b0dea35386387d  verilog/rtl/__user_project_gpio_example.v
 5f8e2d6670ce912bc209201d23430f62730e2627  verilog/rtl/__user_project_la_example.v
-f43d11cf1be9d4530d4ac0fa043cb56958041c03  verilog/rtl/__user_project_wrapper.v
+cc82a78753f5f5d0a1519bd81adbcff8a4296d91  verilog/rtl/__user_project_wrapper.v
 f93c57988b0044d2bff4470a84b5eddc158f2094  verilog/rtl/caravan.v
 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d  verilog/rtl/caravan_netlists.v
 a3d12a2d2d3596800bec47d1266dce2399a2fcc6  verilog/rtl/caravan_openframe.v

scripts/signoff_automation.py

@@ -64,6 +64,7 @@ def run_lvs(caravel_root, mcw_root, log_dir, signoff_dir, pdk_root, lvs_root, pd
     myenv["CARAVEL_ROOT"] = caravel_root
     myenv["MCW_ROOT"] = mcw_root
     myenv["SIGNOFF_ROOT"] = os.path.join(signoff_dir, "caravel")
+    myenv["WORK_DIR"] = os.path.join(caravel_root, "extra_be_checks")
 
     if not os.path.exists(f"{lvs_root}"):
         subprocess.run(
@@ -76,11 +77,12 @@ def run_lvs(caravel_root, mcw_root, log_dir, signoff_dir, pdk_root, lvs_root, pd
             ],
             cwd=f"{caravel_root}/scripts",
             stdout=subprocess.PIPE,
+            stderr=subprocess.PIPE,
         )
 
     lvs_cmd = [
         "bash",
-        "./extra_be_checks/run_full_lvs",
+        "./run_full_lvs",
         "caravel",
         f"{caravel_root}/verilog/gl/caravel.v",
         "caravel",
@@ -89,9 +91,8 @@ def run_lvs(caravel_root, mcw_root, log_dir, signoff_dir, pdk_root, lvs_root, pd
     p1 = subprocess.Popen(
         lvs_cmd,
         env=myenv,
+        cwd=f"{caravel_root}/scripts/extra_be_checks",
         universal_newlines=True,
-        stdout=subprocess.PIPE,
-        stderr=subprocess.PIPE,
     )
     return p1
 
@@ -101,7 +102,7 @@ def run_verification(caravel_root, pdk_root, pdk_env, sim, simulator="vcs"):
     myenv["PDK_ROOT"] = pdk_root
     myenv["PDK"] = pdk_env
     if simulator == "vcs":
-        lvs_cmd = [
+        ver_cmd = [
             "python3",
             "verify_cocotb.py",
             "-tag",
@@ -111,7 +112,7 @@ def run_verification(caravel_root, pdk_root, pdk_env, sim, simulator="vcs"):
             "-v",
         ]
     else:
-        lvs_cmd = [
+        ver_cmd = [
             "python3",
             "verify_cocotb.py",
             "-tag",
@@ -120,7 +121,7 @@ def run_verification(caravel_root, pdk_root, pdk_env, sim, simulator="vcs"):
             f"r_{sim}",
         ]
     p1 = subprocess.Popen(
-        lvs_cmd,
+        ver_cmd,
         cwd=f"{caravel_root}/verilog/dv/cocotb",
         env=myenv,
         universal_newlines=True,
@@ -346,7 +347,7 @@ if __name__ == "__main__":
         sta_p = run_sta(
             caravel_root,
             mcw_root,
-            f"{caravel_root}/scripts/mpw-2-sta-debug/files/custom/lib",
+            f"{caravel_root}/scripts/mpw-2-sta-debug/pt_libs",
             log_dir,
             signoff_dir,
         )

scripts/tech-files/build.tcl

@@ -8,6 +8,7 @@ load mgmt_core_wrapper;
 property LEFview true;
 property GDS_FILE $::env(MCW_ROOT)/gds/mgmt_core_wrapper.gds;
 property GDS_START 0;
+gds read $::env(CARAVEL_ROOT)/openlane/caravel/caravel_power_routing-shifted.gds;
 load user_project_wrapper;
 load user_id_programming;
 load user_id_textblock;
@@ -18,4 +19,4 @@ expand;
 cif *hier write disable;
 cif *array write disable;
 gds write $::env(CARAVEL_ROOT)/gds/caravel.gds;
-quit -noprompt;
+quit -noprompt;

verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py

@@ -134,7 +134,7 @@ async def bitbang_cpu_all_0011(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_1100(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/gpio/gpio.py

@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def gpio_all_o(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=586652)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/gpio/gpio_all_o.c

@@ -77,7 +77,7 @@ void main(){
         
         // try to give input 
         reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
-        int timeout = 1000;
+        int timeout = 100;
         while (reg_mprj_datal != 0x8F66FD7B){
                 timeout--;
                 if (timeout==0){

verilog/dv/cocotb/tests/gpio/gpio_user.py

@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def gpio_all_o_user(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=585321)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=542674)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/rtl/__user_project_wrapper.v

@@ -119,7 +119,9 @@ assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_
 assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user; 
 // `endif
 
-
+`ifndef GPIO_TESTING
+assign wbs_ack_o_user = 0;
+`endif
 // // reserve the last 4 regs for debugging registers in case of user gpio testing 
 // `ifdef GPIO_TESTING
 // assign wbs_cyc_i_user  = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0;