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caravel
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[DATA] Update caravel

This commit is contained in:
manarabdelaty 2021-11-20 17:28:59 +02:00
parent 331fdee2bb
commit 1c18c1dae9
6 changed files with 15300 additions and 14658 deletions
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28900
def/caravel.def
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gds/caravel.gds.gz
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5
openlane/caravel/config.tcl
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@ -69,15 +69,16 @@ set ::env(EXTRA_LEFS) "\
set ::env(EXTRA_GDS_FILES) "\ set ::env(EXTRA_GDS_FILES) "\
$gds_root/chip_io.gds \ $gds_root/chip_io.gds \
$gds_root/user_project_wrapper_empty.gds \ $gds_root/user_project_wrapper.gds \
$gds_root/mgmt_protect.gds \ $gds_root/mgmt_protect.gds \
$gds_root/gpio_control_block.gds \ $gds_root/gpio_control_block.gds \
$gds_root/gpio_defaults_block.gds \
$gds_root/user_id_programming.gds \ $gds_root/user_id_programming.gds \
$gds_root/housekeeping.gds \ $gds_root/housekeeping.gds \
$gds_root/digital_pll.gds \ $gds_root/digital_pll.gds \
$gds_root/caravel_clocking.gds \ $gds_root/caravel_clocking.gds \
$gds_root/simple_por.gds\ $gds_root/simple_por.gds\
$gds_root/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds\ $gds_root/xres_buf.gds\
$mgmt_area_gds_root/mgmt_core_wrapper.gds \ $mgmt_area_gds_root/mgmt_core_wrapper.gds \
" "

4
openlane/caravel_clocking/config.tcl
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@ -66,7 +66,9 @@ set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 6 set ::env(GLB_RT_MAXLAYER) 6
# prevent signal routing on li1 # prevent signal routing on li1
set ::env(GLB_RT_OBS) "li1 94.38500 0.09500 97.39500 55.21000" set ::env(GLB_RT_OBS) "\
li1 0 54.64000 100.0 60,\
li1 94.29500 0 100 60"
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1

2
signoff/caravel_clocking/final_summary_report.csv
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@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow_completed,0h2m49s,-1,89000.0,0.006,44500.0,67.18,627.26,267,0,0,0,0,0,0,0,0,0,0,-1,4950,1815,-3.73,-5.41,-1,-4.99,-1,-24.41,-36.68,-1,-28.88,-1,3295625.0,0.0,26.02,16.28,3.8,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,40,77,0,117,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.7,0,sky130_fd_sc_hd,0,3 0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow_completed,0h2m46s,-1,89000.0,0.006,44500.0,67.18,584.66,267,0,0,0,0,0,0,0,0,0,0,-1,4949,1821,-3.73,-5.41,-1,-4.99,-1,-24.41,-36.68,-1,-28.88,-1,3295625.0,0.0,26.02,16.28,3.8,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,72,71,6,40,77,0,117,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.7,0,sky130_fd_sc_hd,0,3

1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells suggested_clock_frequency suggested_clock_period CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GLB_RT_ADJUSTMENT STD_CELL_LIBRARY CELL_PAD DIODE_INSERTION_STRATEGY
2 0 /home/ma/ef/caravel_openframe/openlane/caravel_clocking caravel_clocking caravel_clocking flow_completed 0h2m49s 0h2m46s -1 89000.0 0.006 44500.0 67.18 627.26 584.66 267 0 0 0 0 0 0 0 0 0 0 -1 4950 4949 1815 1821 -3.73 -5.41 -1 -4.99 -1 -24.41 -36.68 -1 -28.88 -1 3295625.0 0.0 26.02 16.28 3.8 0.0 0.0 202 252 67 117 0 0 0 200 0 0 0 0 0 0 0 4 72 71 6 40 77 0 117 90.9090909090909 11.0 10.0 DELAY 0 5 50 1 15.5 16.9 0.7 0 sky130_fd_sc_hd 0 3

1047
spi/lvs/housekeeping.spice
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