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Merge pull request #240 from efabless/cocotb 

Cocotb script updates
This commit is contained in:
Marwan Abbas 2022-10-15 11:55:41 +02:00 committed by GitHub
parent 2fdc9cb31e 2d56c68ef2
commit 1559e7c41d
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 76 additions and 70 deletions
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54
verilog/dv/cocotb/tests.json
View File

@ -5,68 +5,68 @@
,"bitbang_no_cpu_all_o" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":[],
"GL_SDF":[],
"description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"}
,"bitbang_cpu_all_o" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt output using bitbang and check them"}
,"gpio_all_o" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt output using automatic approach firmware and check them"}
,"gpio_all_o_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user output using automatic approach firmware and check them"}
,"gpio_all_i" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input using automatic approach firmware and check them"}
,"gpio_all_i_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user input using automatic approach firmware and check them"}
,"gpio_all_i_pu" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"}
,"gpio_all_i_pu_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user input pull up using automatic approach firmware and check them"}
,"gpio_all_i_pd" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"}
,"gpio_all_i_pd_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user input pull down using automatic approach firmware and check them"}
,"gpio_all_bidir_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user bidir using automatic approach firmware and check them"}
,"bitbang_cpu_all_10" :{"level":0,
@ -101,21 +101,21 @@
"description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"}
,"bitbang_cpu_all_i" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
,"bitbang_spi_o" :{"level":0,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"SW":true,
"description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"}
,"bitbang_spi_i" :{"level":0,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"SW":true,
"description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"}

3
verilog/dv/cocotb/tests/mem/mem_dff.c
View File

@ -30,7 +30,4 @@ void main()
if (!is_fail)
reg_debug_1 = 0x1B;
// test finish
reg_debug_1 = 0xFF;
}

3
verilog/dv/cocotb/tests/mem/mem_dff2.c
View File

@ -30,7 +30,4 @@ void main()
if (!is_fail)
reg_debug_1 = 0x1B;
// test finish
reg_debug_1 = 0xFF;
}

39
verilog/dv/cocotb/tests/mem/mem_stress.py
View File

@ -13,15 +13,13 @@ reg = Regs()
@cocotb.test()
@repot_test
async def mem_dff2(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1426536)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mem stress test")
pass_list = (0x1B)
fail_list = (0x1E)
phases_fails = 1
phases_passes = 0
pass_list = [0x1B]
fail_list = [0x1E]
reg1 =0 # buffer
while True:
if cpu.read_debug_reg1() == 0xFF: # test finish
@ -29,45 +27,34 @@ async def mem_dff2(dut):
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
cocotb.log.info(f"[TEST] pass writing and reading all dff2 memory ")
break
elif reg1 in fail_list: # pass phase
cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
break
await ClockCycles(caravelEnv.clk,100)
if phases_fails > 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
@cocotb.test()
@repot_test
async def mem_dff(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
caravelEnv,clock = await test_configure(dut,timeout_cycles=2378120)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mem stress test")
pass_list = (0x1B)
fail_list = (0x1E)
phases_fails = 1
phases_passes = 0
pass_list = [0x1B]
fail_list = [0x1E]
reg1 =0 # buffer
while True:
if cpu.read_debug_reg1() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
cocotb.log.info(f"[TEST] pass writing and reading all dff memory ")
cocotb.log.info(f"[TEST] pass writing and reading all dff memory ")
break
elif reg1 in fail_list: # pass phase
cocotb.log.error(f"[TEST] failed access address {hex(0x00000400 + cpu.read_debug_reg2())}")
break
await ClockCycles(caravelEnv.clk,100)
if phases_fails > 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")

47
verilog/dv/cocotb/verify_cocotb.py
View File

@ -16,6 +16,8 @@ import shutil
iverilog = True
vcs = False
coverage = False
remove_waves = True
def go_up(path, n):
for i in range(n):
path = os.path.dirname(path)
@ -36,10 +38,6 @@ def change_dff(str,new_str,file_path):
with open(file_path, 'r') as file :
filedata = file.read()
if new_str == "> dff2":
if new_str in filedata: # to avoid type dff22 types
return
# Replace the target string
filedata = filedata.replace(str, new_str)
# Write the file out again
@ -117,7 +115,7 @@ class RunTest:
if (self.sim_type=="GL_SDF"):
macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"{self.corner[-1]}{self.corner[-1]}\\\" +define+CORNER=\\\"{self.corner[0:3]}\\\"'
# corner example is corner nom-t so `SDF_POSTFIX = tt and `CORNER = nom
os.makedirs(f"annotation_logs",exist_ok=True)
# os.makedirs(f"annotation_logs",exist_ok=True)
dirs = f"{dirs} +incdir+\\\"{os.getenv('MCW_ROOT')}/verilog/\\\" "
# +incdir+\\\"{os.getenv('CARAVEL_ROOT')}/signoff/caravel/primetime-signoff/\\\"
full_test_name = f"{self.sim_type}-{self.test_name}-{self.corner}"
@ -139,6 +137,10 @@ class RunTest:
os.system(f"vcs +lint=TFIPC-L {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
#delete wave when passed
if self.passed == "passed" and remove_waves:
os.system(f'rm {self.cocotb_path}/{self.sim_path}*.vpd')
os.system(f'rm {self.cocotb_path}/{self.sim_path}*.vcd')
os.system("rm AN.DB/ cm.log results.xml ucli.key -rf")
if os.path.exists(f"{self.cocotb_path}/sdfAnnotateInfo"):
shutil.move(f"{self.cocotb_path}/sdfAnnotateInfo", f"{self.sim_path}/sdfAnnotateInfo")
@ -160,6 +162,7 @@ class RunTest:
def hex_generate(self):
tests_use_dff2 = ["mem_dff"]
tests_use_dff = ["mem_dff2"]
#open docker
test_path =self.test_path()
self.cd_make()
@ -175,15 +178,18 @@ class RunTest:
CPUFLAGS = f"-march=rv32i -mabi=ilp32 -D__vexriscv__ "
verilog_path = f"{os.getenv('VERILOG_PATH')}"
test_dir = f"{os.getenv('VERILOG_PATH')}/dv/tests-caravel/mem" # linker script include // TODO: to fix this in the future from the mgmt repo
print(test_dir)
#change linker script to for mem tests
if self.test_name in tests_use_dff2:
LINKER_SCRIPT = self.linkerScript_for_mem("dff2",LINKER_SCRIPT)
elif self.test_name in tests_use_dff:
LINKER_SCRIPT = self.linkerScript_for_mem("dff",LINKER_SCRIPT)
elf_command = (f"{GCC_PATH}/{GCC_PREFIX}-gcc -g -I{verilog_path}/dv/firmware -I{verilog_path}/dv/generated -I{verilog_path}/dv/ "
f"-I{verilog_path}/common {CPUFLAGS} -Wl,-Bstatic,-T,{LINKER_SCRIPT},"
f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}")
hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} "
sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
#change linker script to dff2
if self.test_name in tests_use_dff2:
change_dff(str="> dff",new_str="> dff2",file_path=LINKER_SCRIPT)
hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
@ -193,8 +199,24 @@ class RunTest:
if hex_gen_state != 0 :
print(f"fatal: Error when generating hex")
sys.exit()
if self.test_name in tests_use_dff2:
change_dff(str="> dff2",new_str="> dff",file_path=LINKER_SCRIPT)
#change linker script to for mem tests
def linkerScript_for_mem(self,ram,LINKER_SCRIPT):
new_LINKER_SCRIPT = f"{self.cocotb_path}/{self.sim_path}/sections.lds"
shutil.copyfile(LINKER_SCRIPT, new_LINKER_SCRIPT)
if ram == "dff2":
change_dff(str="> dff ",new_str="> dff2 ",file_path=new_LINKER_SCRIPT)
change_dff(str="> dff\n",new_str="> dff2\n",file_path=new_LINKER_SCRIPT)
change_dff(str="ORIGIN(dff)",new_str="ORIGIN(dff2)",file_path=new_LINKER_SCRIPT)
change_dff(str="LENGTH(dff)",new_str="LENGTH(dff2)",file_path=new_LINKER_SCRIPT)
elif ram == "dff":
change_dff(str="> dff2 ",new_str="> dff ",file_path=new_LINKER_SCRIPT)
change_dff(str="ORIGIN(dff2)",new_str="ORIGIN(dff)",file_path=new_LINKER_SCRIPT)
change_dff(str="LENGTH(dff2)",new_str="LENGTH(dff)",file_path=new_LINKER_SCRIPT)
else:
print(f"ERROR: wrong trype of ram {ram} need to be used for now the oldy rams that can be used for flashing and data are dff and dff2")
sys.exit()
return new_LINKER_SCRIPT
def cd_make(self):
os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make")
@ -388,6 +410,7 @@ parser.add_argument('-maxerr', help='max number of errors for every test before
parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used')
parser.add_argument('-cov',action='store_true', help='enable code coverage')
parser.add_argument('-corner','-c', nargs='+' ,help='Corner type in case of GL_SDF run has to be provided')
parser.add_argument('-keep_pass_wave',action='store_true', help='Normally the waves of passed tests would be removed using this option will not remove them ')
args = parser.parse_args()
if (args.vcs) :
iverilog = False
@ -398,6 +421,8 @@ if args.sim == None:
args.sim= ["RTL"]
if args.corner == None:
args.corner= ["nom-t"]
if args.keep_pass_wave:
remove_waves = False
print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}")
main(args)