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Merge branch 'caravel_redesign' of github.com:efabless/caravel into caravel_redesign

This commit is contained in:
Passant 2022-10-09 07:40:56 -07:00
parent ef688785f3 7538c8c776
commit 127057eb4b
13 changed files with 77705 additions and 32897 deletions
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30485
def/chip_io.def
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def/chip_io_alt.def Normal file
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gds/chip_io.gds.gz
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lef/chip_io.lef
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lef/chip_io_alt.lef
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mag/chip_io.mag
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mag/chip_io_alt.mag
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mag/chip_io_gpio_connects.mag Normal file
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@ -0,0 +1,63 @@
magic
tech sky130A
magscale 1 2
timestamp 1665248140
<< checkpaint >>
rect 675407 99896 675887 115709
<< metal1 >>
rect 675682 113371 675734 115709
rect 675586 112665 675638 112671
rect 675586 112487 675638 112493
rect 675490 109630 675542 109636
rect 675490 109452 675542 109458
rect 675492 101631 675540 109452
rect 675588 108347 675636 112487
rect 675586 108341 675638 108347
rect 675586 108163 675638 108169
rect 675490 101625 675542 101631
rect 675490 101567 675542 101573
rect 675492 100265 675540 101567
rect 675588 100462 675636 108163
rect 675586 100456 675638 100462
rect 675586 100278 675638 100284
rect 675588 100265 675636 100278
rect 675682 99896 675734 113199
<< via1 >>
rect 675682 113199 675734 113371
rect 675586 112493 675638 112665
rect 675490 109458 675542 109630
rect 675586 108169 675638 108341
rect 675490 101573 675542 101625
rect 675586 100284 675638 100456
<< metal2 >>
rect 675676 113311 675682 113371
rect 675407 113255 675682 113311
rect 675676 113199 675682 113255
rect 675734 113311 675740 113371
rect 675734 113255 675887 113311
rect 675734 113199 675740 113255
rect 675407 112665 675887 112667
rect 675407 112611 675586 112665
rect 675580 112493 675586 112611
rect 675638 112611 675887 112665
rect 675638 112493 675644 112611
rect 675407 109630 675887 109631
rect 675407 109575 675490 109630
rect 675484 109458 675490 109575
rect 675542 109575 675887 109630
rect 675542 109458 675548 109575
rect 675407 108341 675887 108343
rect 675407 108287 675586 108341
rect 675580 108169 675586 108287
rect 675638 108287 675887 108341
rect 675638 108169 675644 108287
rect 675407 101625 675887 101627
rect 675407 101573 675490 101625
rect 675542 101573 675887 101625
rect 675407 101571 675887 101573
rect 675580 100339 675586 100456
rect 675407 100284 675586 100339
rect 675638 100339 675644 100456
rect 675638 100284 675887 100339
rect 675407 100283 675887 100284
<< end >>

6
manifest
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@ -8,8 +8,8 @@ a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
b4b8fecbdc56c5d8acca9b904415f30e3159d1d5 verilog/rtl/caravel.v b4b8fecbdc56c5d8acca9b904415f30e3159d1d5 verilog/rtl/caravel.v
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v 2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v 82d3766e5ed2a29ff06150aab1c7b0f4c5651551 verilog/rtl/chip_io.v
8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v 97c958944dd74a87f75d9fe2309837e567468722 verilog/rtl/chip_io_alt.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v 941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
@ -22,7 +22,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v 9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
d71adbc70dbb0ed879d3b75419bd807c866a9680 verilog/rtl/mprj_io.v d8a1a767b32b33baab480950945fad9ec70fcf0f verilog/rtl/mprj_io.v
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v 4edbfd0ad80b69a799a399ffc717b560fcae615b verilog/rtl/pads.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v 669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v

8
verilog/rtl/chip_io.v
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@ -104,14 +104,13 @@ module chip_io(
inout [`MPRJ_IO_PADS-10:0] mprj_analog_io inout [`MPRJ_IO_PADS-10:0] mprj_analog_io
); );
// To be considered: Master hold signal on all user pads (?) // To be considered: Master hold signal on all user pads (?)
// For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain) // For now, set holdh_n to 1 internally (NOTE: This is in the
// VDDIO 3.3V domain)
// and setting enh to porb_h. // and setting enh to porb_h.
wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
wire [`MPRJ_IO_PADS-1:0] mprj_io_enh; wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}}; assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
wire analog_a, analog_b; wire analog_a, analog_b;
@ -395,7 +394,6 @@ module chip_io(
.io(mprj_io), .io(mprj_io),
.io_out(mprj_io_out), .io_out(mprj_io_out),
.oeb(mprj_io_oeb), .oeb(mprj_io_oeb),
.hldh_n(mprj_io_hldh_n),
.enh(mprj_io_enh), .enh(mprj_io_enh),
.inp_dis(mprj_io_inp_dis), .inp_dis(mprj_io_inp_dis),
.ib_mode_sel(mprj_io_ib_mode_sel), .ib_mode_sel(mprj_io_ib_mode_sel),

10
verilog/rtl/chip_io_alt.v
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@ -140,13 +140,12 @@ module chip_io_alt #(
wire analog_a, analog_b; wire analog_a, analog_b;
wire vddio_q, vssio_q; wire vddio_q, vssio_q;
// To be considered: Master hold signal on all user pads (?) // To be considered: Master hold signal on all user pads (?)
// For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain) // For now, set holdh_n to 1 internally (NOTE: This is in the
// and setting enh to porb_h. // VDDIO 3.3V domain) and setting enh to porb_h.
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_hldh_n;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_enh; wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_enh;
assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}}; assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
// Instantiate power and ground pads for management domain // Instantiate power and ground pads for management domain
@ -469,7 +468,6 @@ module chip_io_alt #(
mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}), mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}),
.io_out(mprj_io_out), .io_out(mprj_io_out),
.oeb(mprj_io_oeb), .oeb(mprj_io_oeb),
.hldh_n(mprj_io_hldh_n),
.enh(mprj_io_enh), .enh(mprj_io_enh),
.inp_dis(mprj_io_inp_dis), .inp_dis(mprj_io_inp_dis),
.ib_mode_sel(mprj_io_ib_mode_sel), .ib_mode_sel(mprj_io_ib_mode_sel),

24
verilog/rtl/mprj_io.v
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@ -48,7 +48,6 @@ module mprj_io #(
inout [TOTAL_PADS-1:0] io, inout [TOTAL_PADS-1:0] io,
input [TOTAL_PADS-1:0] io_out, input [TOTAL_PADS-1:0] io_out,
input [TOTAL_PADS-1:0] oeb, input [TOTAL_PADS-1:0] oeb,
input [TOTAL_PADS-1:0] hldh_n,
input [TOTAL_PADS-1:0] enh, input [TOTAL_PADS-1:0] enh,
input [TOTAL_PADS-1:0] inp_dis, input [TOTAL_PADS-1:0] inp_dis,
input [TOTAL_PADS-1:0] ib_mode_sel, input [TOTAL_PADS-1:0] ib_mode_sel,
@ -65,7 +64,8 @@ module mprj_io #(
inout [TOTAL_PADS-10:0] analog_noesd_io inout [TOTAL_PADS-10:0] analog_noesd_io
); );
wire [TOTAL_PADS-1:0] loop1_io; wire [TOTAL_PADS-1:0] loop0_io; // Internal loopback to 3.3V domain ground
wire [TOTAL_PADS-1:0] loop1_io; // Internal loopback to 3.3V domain power
wire [6:0] no_connect_1a, no_connect_1b; wire [6:0] no_connect_1a, no_connect_1b;
wire [1:0] no_connect_2a, no_connect_2b; wire [1:0] no_connect_2a, no_connect_2b;
@ -76,11 +76,11 @@ module mprj_io #(
`endif `endif
.OUT(io_out[AREA1PADS - 1:0]), .OUT(io_out[AREA1PADS - 1:0]),
.OE_N(oeb[AREA1PADS - 1:0]), .OE_N(oeb[AREA1PADS - 1:0]),
.HLD_H_N(hldh_n[AREA1PADS - 1:0]), .HLD_H_N(loop1_iop[AREA1PADS - 1:0]),
.ENABLE_H(enh[AREA1PADS - 1:0]), .ENABLE_H(enh[AREA1PADS - 1:0]),
.ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]), .ENABLE_INP_H(loop0_io[AREA1PADS - 1:0]),
.ENABLE_VDDA_H(porb_h), .ENABLE_VDDA_H(porb_h),
.ENABLE_VSWITCH_H(loop1_io[AREA1PADS - 1:0]), .ENABLE_VSWITCH_H(loop0_io[AREA1PADS - 1:0]),
.ENABLE_VDDIO(vccd_conb[AREA1PADS - 1:0]), .ENABLE_VDDIO(vccd_conb[AREA1PADS - 1:0]),
.INP_DIS(inp_dis[AREA1PADS - 1:0]), .INP_DIS(inp_dis[AREA1PADS - 1:0]),
.IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]), .IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]),
@ -96,8 +96,8 @@ module mprj_io #(
.PAD_A_ESD_1_H(), .PAD_A_ESD_1_H(),
.IN(io_in[AREA1PADS - 1:0]), .IN(io_in[AREA1PADS - 1:0]),
.IN_H(io_in_3v3[AREA1PADS - 1:0]), .IN_H(io_in_3v3[AREA1PADS - 1:0]),
.TIE_HI_ESD(), .TIE_HI_ESD(loop1_io[AREA1PADS - 1:0]),
.TIE_LO_ESD(loop1_io[AREA1PADS - 1:0]) .TIE_LO_ESD(loop0_io[AREA1PADS - 1:0])
); );
sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] ( sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] (
@ -107,11 +107,11 @@ module mprj_io #(
`endif `endif
.OUT(io_out[TOTAL_PADS - 1:AREA1PADS]), .OUT(io_out[TOTAL_PADS - 1:AREA1PADS]),
.OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]), .OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]),
.HLD_H_N(hldh_n[TOTAL_PADS - 1:AREA1PADS]), .HLD_H_N(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
.ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]),
.ENABLE_INP_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_INP_H(loop0_io[TOTAL_PADS - 1:AREA1PADS]),
.ENABLE_VDDA_H(porb_h), .ENABLE_VDDA_H(porb_h),
.ENABLE_VSWITCH_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_VSWITCH_H(loop0_io[TOTAL_PADS - 1:AREA1PADS]),
.ENABLE_VDDIO(vccd_conb[TOTAL_PADS - 1:AREA1PADS]), .ENABLE_VDDIO(vccd_conb[TOTAL_PADS - 1:AREA1PADS]),
.INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]), .INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]),
.IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]), .IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]),
@ -127,8 +127,8 @@ module mprj_io #(
.PAD_A_ESD_1_H(), .PAD_A_ESD_1_H(),
.IN(io_in[TOTAL_PADS - 1:AREA1PADS]), .IN(io_in[TOTAL_PADS - 1:AREA1PADS]),
.IN_H(io_in_3v3[TOTAL_PADS - 1:AREA1PADS]), .IN_H(io_in_3v3[TOTAL_PADS - 1:AREA1PADS]),
.TIE_HI_ESD(), .TIE_HI_ESD(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
.TIE_LO_ESD(loop1_io[TOTAL_PADS - 1:AREA1PADS]) .TIE_LO_ESD(loop0_io[TOTAL_PADS - 1:AREA1PADS])
); );
endmodule endmodule