diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index 08e3eebd..b6493ad7 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -77,7 +77,7 @@ module gpio_control_block #( // Serial data chain for pad configuration input serial_data_in, - output serial_data_out, + output reg serial_data_out, // User-facing signals input user_gpio_out, // User space to pad @@ -130,27 +130,10 @@ module gpio_control_block #( reg gpio_ana_sel; reg gpio_ana_pol; - /* Derived output values */ - wire pad_gpio_holdover; - wire pad_gpio_slow_sel; - wire pad_gpio_vtrip_sel; - wire pad_gpio_inenb; - wire pad_gpio_ib_mode_sel; - wire pad_gpio_ana_en; - wire pad_gpio_ana_sel; - wire pad_gpio_ana_pol; - wire [2:0] pad_gpio_dm; - wire pad_gpio_outenb; - wire pad_gpio_out; - wire pad_gpio_in; wire one_unbuf; wire zero_unbuf; - wire one; - wire zero; - wire user_gpio_in; wire gpio_logic1; - reg serial_data_out; /* Serial shift for the above (latched) values */ reg [PAD_CTRL_BITS-1:0] shift_register; diff --git a/verilog/rtl/gpio_defaults_block.v b/verilog/rtl/gpio_defaults_block.v index e17b65dd..f86c6b9c 100644 --- a/verilog/rtl/gpio_defaults_block.v +++ b/verilog/rtl/gpio_defaults_block.v @@ -34,7 +34,6 @@ module gpio_defaults_block #( `endif output [12:0] gpio_defaults ); - wire [12:0] gpio_defaults; wire [12:0] gpio_defaults_high; wire [12:0] gpio_defaults_low; diff --git a/verilog/rtl/housekeeping.v b/verilog/rtl/housekeeping.v index 9917e461..ae37bd2a 100644 --- a/verilog/rtl/housekeeping.v +++ b/verilog/rtl/housekeeping.v @@ -74,20 +74,20 @@ module housekeeping #( input wb_we_i, input wb_cyc_i, input wb_stb_i, - output wb_ack_o, - output [31:0] wb_dat_o, + output reg wb_ack_o, + output reg [31:0] wb_dat_o, // Primary reset input porb, // Clocking control parameters - output pll_ena, - output pll_dco_ena, - output [4:0] pll_div, - output [2:0] pll_sel, - output [2:0] pll90_sel, - output [25:0] pll_trim, - output pll_bypass, + output reg pll_ena, + output reg pll_dco_ena, + output reg [4:0] pll_div, + output reg [2:0] pll_sel, + output reg [2:0] pll90_sel, + output reg [25:0] pll_trim, + output reg pll_bypass, // Module enable status from SoC input qspi_enabled, // Flash SPI is in quad mode @@ -123,7 +123,7 @@ module housekeeping #( output [`MPRJ_IO_PADS-1:0] mgmt_gpio_oeb, // Power control output (reserved for future use with LDOs) - output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out, + output reg [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out, // CPU trap state status (for system monitoring) input trap, @@ -187,13 +187,6 @@ module housekeeping #( localparam OEB = 1; // Offset of output enable (bar) in shift register localparam INP_DIS = 3; // Offset of input disable in shift register - reg [25:0] pll_trim; - reg [4:0] pll_div; - reg [2:0] pll_sel; - reg [2:0] pll90_sel; - reg pll_dco_ena; - reg pll_ena; - reg pll_bypass; reg reset_reg; reg irq_spi; reg serial_bb_clock; @@ -219,25 +212,17 @@ module housekeeping #( reg [IO_CTRL_BITS-1:0] gpio_configure [`MPRJ_IO_PADS-1:0]; reg [`MPRJ_IO_PADS-1:0] mgmt_gpio_data; - reg [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out; /* mgmt_gpio_data_buf holds the lower bits during a back-door * write to GPIO data so that all 32 bits can update at once. */ reg [23:0] mgmt_gpio_data_buf; - wire usr1_vcc_pwrgood; - wire usr2_vcc_pwrgood; - wire usr1_vdd_pwrgood; - wire usr2_vdd_pwrgood; wire [7:0] odata; wire [7:0] idata; wire [7:0] iaddr; - wire [2:0] irq; - - wire trap; wire rdstb; wire wrstb; wire pass_thru_mgmt; // Mode detected by housekeeping_spi @@ -254,11 +239,6 @@ module housekeeping #( wire cwstb; // Combination of SPI write strobe and back door write strobe wire csclk; // Combination of SPI SCK and back door access trigger - wire serial_data_1; - wire serial_data_2; - wire serial_clock; - wire serial_resetn; - wire serial_load; // Output clock signals buffer wires wire mgmt_gpio_out_9_prebuff, mgmt_gpio_out_14_prebuff, mgmt_gpio_out_15_prebuff, pad_flash_clk_prebuff; @@ -268,9 +248,6 @@ wire mgmt_gpio_out_9_prebuff, mgmt_gpio_out_14_prebuff, mgmt_gpio_out_15_prebuff wire [31:0] sram_ro_data; `endif - // Housekeeping side 3-wire interface to GPIOs (see below) - wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out; - // Pass-through mode handling. Signals may only be applied when the // core processor is in reset. @@ -335,8 +312,6 @@ wire mgmt_gpio_out_9_prebuff, mgmt_gpio_out_14_prebuff, mgmt_gpio_out_15_prebuff reg wbbd_sck; /* wishbone access trigger (back-door clock) */ reg wbbd_write; /* wishbone write trigger (back-door strobe) */ reg wbbd_busy; /* Raised during a wishbone read or write */ - reg wb_ack_o; /* acknowledge signal back to wishbone bus */ - reg [31:0] wb_dat_o; /* data output to wishbone bus */ // This defines a state machine that accesses the SPI registers through // the back door wishbone interface. The process is relatively slow diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v index 58664b79..3c6034d8 100644 --- a/verilog/rtl/mgmt_protect.v +++ b/verilog/rtl/mgmt_protect.v @@ -107,10 +107,6 @@ module mgmt_protect ( wire mprj_vdd_logic1; wire mprj2_vdd_logic1; - wire user1_vcc_powergood; - wire user2_vcc_powergood; - wire user1_vdd_powergood; - wire user2_vdd_powergood; wire [127:0] la_data_in_mprj_bar; wire [2:0] user_irq_bar; diff --git a/verilog/rtl/spare_logic_block.v b/verilog/rtl/spare_logic_block.v index e12d0de5..ffb81d91 100644 --- a/verilog/rtl/spare_logic_block.v +++ b/verilog/rtl/spare_logic_block.v @@ -39,17 +39,8 @@ module spare_logic_block ( wire [3:0] spare_logic_nc; - wire [3:0] spare_xi; - wire spare_xib; - wire [1:0] spare_xna; - wire [1:0] spare_xno; - wire [1:0] spare_xmx; - wire [1:0] spare_xfq; - wire [1:0] spare_xfqn; - wire [26:0] spare_logic1; wire [26:0] spare_logic0; - wire [26:0] spare_xz; // Rename the logic0 outputs at the block pins. assign spare_xz = spare_logic0; diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v index 4c8d6c9f..53a76b51 100644 --- a/verilog/rtl/user_id_programming.v +++ b/verilog/rtl/user_id_programming.v @@ -28,7 +28,6 @@ module user_id_programming #( `endif output [31:0] mask_rev ); - wire [31:0] mask_rev; wire [31:0] user_proj_id_high; wire [31:0] user_proj_id_low;