From 71e309a923e1f91990308e2d9bfde104aa69d33c Mon Sep 17 00:00:00 2001
From: kareem <kareem.farid@efabless.com>
Date: Mon, 10 Oct 2022 05:13:48 -0700
Subject: [PATCH 1/2] some rtl changes

- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
---
 verilog/rtl/caravel.v | 35 ++++++++++++++++++-----------------
 verilog/rtl/chip_io.v |  2 --
 2 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index a6477271..374d5bc2 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -196,7 +196,6 @@ module caravel (
     // Flash SPI communication (management SoC to housekeeping)
     wire flash_clk_core,     flash_csb_core;
     wire flash_clk_oeb_core, flash_csb_oeb_core;
-    wire flash_clk_ieb_core, flash_csb_ieb_core;
     wire flash_io0_oeb_core, flash_io1_oeb_core;
     wire flash_io2_oeb_core, flash_io3_oeb_core;
     wire flash_io0_ieb_core, flash_io1_ieb_core;
@@ -237,22 +236,22 @@ module caravel (
 		.vccd2_pad	(vccd2),		// User area 2 1.8V supply
 		.vssd1_pad	(vssd1),		// User area 1 digital ground
 		.vssd2_pad	(vssd2),		// User area 2 digital ground
+        .vddio	(vddio_core),
+        .vssio	(vssio_core),
+        .vdda	(vdda_core),
+        .vssa	(vssa_core),
+        .vccd	(vccd_core),
+        .vssd	(vssd_core),
+        .vdda1	(vdda1_core),
+        .vdda2	(vdda2_core),
+        .vssa1	(vssa1_core),
+        .vssa2	(vssa2_core),
+        .vccd1	(vccd1_core),
+        .vccd2	(vccd2_core),
+        .vssd1	(vssd1_core),
+        .vssd2	(vssd2_core),
 	`endif
 	// Core Side Pins
-	.vddio	(vddio_core),
-	.vssio	(vssio_core),
-	.vdda	(vdda_core),
-	.vssa	(vssa_core),
-	.vccd	(vccd_core),
-	.vssd	(vssd_core),
-	.vdda1	(vdda1_core),
-	.vdda2	(vdda2_core),
-	.vssa1	(vssa1_core),
-	.vssa2	(vssa2_core),
-	.vccd1	(vccd1_core),
-	.vccd2	(vccd2_core),
-	.vssd1	(vssd1_core),
-	.vssd2	(vssd2_core),
 	.gpio(gpio),
 	.mprj_io(mprj_io),
 	.clock(clock),
@@ -278,8 +277,6 @@ module caravel (
 	.flash_clk_oeb_core(flash_clk_oeb),
 	.flash_io0_oeb_core(flash_io0_oeb),
 	.flash_io1_oeb_core(flash_io1_oeb),
-	.flash_csb_ieb_core(flash_csb_ieb),
-	.flash_clk_ieb_core(flash_clk_ieb),
 	.flash_io0_ieb_core(flash_io0_ieb),
 	.flash_io1_ieb_core(flash_io1_ieb),
 	.flash_io0_do_core(flash_io0_do),
@@ -1503,5 +1500,9 @@ module caravel (
 		.spare_xfqn(spare_xfqn_nc)
     );
 
+    `ifdef TOP_ROUTING
+    caravel_power_routing caravel_power_routing();
+    `endif
+
 endmodule
 // `default_nettype wire
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 576d1759..a9626868 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -75,8 +75,6 @@ module chip_io(
 	input  flash_clk_oeb_core,
 	input  flash_io0_oeb_core,
 	input  flash_io1_oeb_core,
-	input  flash_csb_ieb_core,	// NOTE: unused, fix me!
-	input  flash_clk_ieb_core,	// NOTE: unused, fix me!
 	input  flash_io0_ieb_core,
 	input  flash_io1_ieb_core,
 	input  flash_io0_do_core,

From 623be602c259996b417bdc25045caea08ab5184f Mon Sep 17 00:00:00 2001
From: kareefardi <kareefardi@users.noreply.github.com>
Date: Mon, 10 Oct 2022 12:22:26 +0000
Subject: [PATCH 2/2] Apply automatic changes to Manifest and README.rst

---
 manifest | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/manifest b/manifest
index 0239ee74..3fceb45c 100644
--- a/manifest
+++ b/manifest
@@ -5,10 +5,11 @@ b5ad3558a91e508fad154b91565c7d664b247020  verilog/rtl/__user_project_wrapper.v
 f93c57988b0044d2bff4470a84b5eddc158f2094  verilog/rtl/caravan.v
 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d  verilog/rtl/caravan_netlists.v
 a3d12a2d2d3596800bec47d1266dce2399a2fcc6  verilog/rtl/caravan_openframe.v
-b4b8fecbdc56c5d8acca9b904415f30e3159d1d5  verilog/rtl/caravel.v
+0087afb30dea45ddc49c98a9959e73a264233cfa  verilog/rtl/caravel.v
 2fe34f043edbe87c626e5616ad54f82c9ba067c2  verilog/rtl/caravel_clocking.v
 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650  verilog/rtl/caravel_openframe.v
-82d3766e5ed2a29ff06150aab1c7b0f4c5651551  verilog/rtl/chip_io.v
+d97cb60c8d125d6098111d4f0aa00410515770eb  verilog/rtl/caravel_power_routing.v
+bc1e961e41d1d3a383a018279a08bf4108911f53  verilog/rtl/chip_io.v
 97c958944dd74a87f75d9fe2309837e567468722  verilog/rtl/chip_io_alt.v
 126aff02aa229dc346301c552d785dec76a4d68e  verilog/rtl/clock_div.v
 941bd7636e7558b045faa3d8c6ba2d91b4c4b798  verilog/rtl/constant_block.v