From 112ed537519bb9b5328153a005c2c9ab405c1ba1 Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu, 11 Nov 2021 08:48:14 -0500
Subject: [PATCH] Modified the Makefile so that "make lvs-gds-" works better
 (maybe not perfectly) when run on chip-io or anything with a pad cell.

---
 Makefile | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index d16710f0..3e09b623 100644
--- a/Makefile
+++ b/Makefile
@@ -313,7 +313,9 @@ LVS_GDS_BLOCKS = $(foreach block, $(BLOCKS), lvs-gds-$(block))
 $(LVS_GDS_BLOCKS): lvs-gds-% : ./gds/%.gds ./verilog/gl/%.v
 	echo "Extracting $*"
 	mkdir -p ./gds/tmp
-	echo "gds read ./$*.gds;\
+	echo "	gds flatglob \"*_example_*\";\
+		gds flatten true;\
+		gds read ./$*.gds;\
 		load $* -dereference;\
 		select top cell;\
 		extract no all;\
@@ -673,4 +675,4 @@ README.rst: README.src.rst docs/source/getting-started.rst docs/source/tool-vers
 				-e's@https://github.com/efabless/caravel/blob/master/openlane/@./@g' \
 				-e's@.. note::@**NOTE:**@g' \
 				-e's@.. warning::@**WARNING:**@g' \
-				> openlane/README.rst
\ No newline at end of file
+				> openlane/README.rst