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change instance names for gpio control blocks to avoid arrays not starting at 0

This commit is contained in:
mo-hosni 2024-03-13 20:45:19 +02:00
parent acfa7772b1
commit 0dbdb4df96
1 changed files with 3 additions and 3 deletions
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6
verilog/rtl/caravel_core.v
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@ -1324,7 +1324,7 @@ module caravel_core (
/* Section 2 GPIOs (GPIO 19 to 26) */ /* Section 2 GPIOs (GPIO 19 to 26) */
gpio_control_block gpio_control_in_2 [7:0] ( gpio_control_block gpio_control_in_2_1 [7:0] (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.vccd(vccd), .vccd(vccd),
.vssd(vssd), .vssd(vssd),
@ -1377,7 +1377,7 @@ module caravel_core (
/* Section 2 GPIOs (GPIO 27 to 31) DFT jtag */ /* Section 2 GPIOs (GPIO 27 to 31) DFT jtag */
gpio_control_block_mgmt gpio_control_in_2 [12:8] ( gpio_control_block_mgmt gpio_control_in_2_2 [4:0] (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.vccd(vccd), .vccd(vccd),
.vssd(vssd), .vssd(vssd),
@ -1429,7 +1429,7 @@ module caravel_core (
); );
/* Section 2 GPIOs (GPIO 32 to 34) */ /* Section 2 GPIOs (GPIO 32 to 34) */
gpio_control_block_mgmt gpio_control_in_2 [15:13] ( gpio_control_block_mgmt gpio_control_in_2_3 [2:0] (
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
.vccd(vccd), .vccd(vccd),
.vssd(vssd), .vssd(vssd),