From 096f5035f5ea4ca89e09b00d59de2d55511f2482 Mon Sep 17 00:00:00 2001 From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Date: Fri, 21 Oct 2022 16:43:34 +0200 Subject: [PATCH] cocotb - updates related to enable simulating caraval using iverilog (#320) * cocotb - updates related to enable simulating caraval using iverilog * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady --- manifest | 2 +- verilog/dv/cocotb/caravel_top.sv | 5 ++- verilog/dv/cocotb/tests.json | 34 ++++++++++----------- verilog/dv/cocotb/verify_cocotb.py | 13 ++++++-- verilog/rtl/__user_analog_project_wrapper.v | 29 ++++++++++++++++++ 5 files changed, 61 insertions(+), 22 deletions(-) diff --git a/manifest b/manifest index 16bf7ae2..9bebc9be 100644 --- a/manifest +++ b/manifest @@ -1,6 +1,6 @@ 535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v -684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v +cf40562ae6508f3dc5e81420e31f7b5886dc3c8f verilog/rtl/__user_analog_project_wrapper.v 79cdb50a7dd60f69b63c0b6440b0dea35386387d verilog/rtl/__user_project_gpio_example.v 5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v cc82a78753f5f5d0a1519bd81adbcff8a4296d91 verilog/rtl/__user_project_wrapper.v diff --git a/verilog/dv/cocotb/caravel_top.sv b/verilog/dv/cocotb/caravel_top.sv index cbbc1701..1772ab64 100644 --- a/verilog/dv/cocotb/caravel_top.sv +++ b/verilog/dv/cocotb/caravel_top.sv @@ -74,8 +74,11 @@ end wire flash_io1_tb; - +`ifdef CARAVAN +caravan uut ( +`else caravel uut ( +`endif .vddio (vddio_tb), .vddio_2 (vddio_2_tb), .vssio (vssio_tb), diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 3a67a636..411d1821 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -4,8 +4,8 @@ "_comment1" :"GL regressions run this test in gatelevel, GL_SDF regression run this test with SDF included" ,"gpio_all_i" :{"level":0, "SW":true, - "RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","r_caravan_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt input using automatic approach firmware and check them"} @@ -30,15 +30,15 @@ ,"gpio_all_i_user" :{"level":0, "SW":true, - "RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","setup","r_caravan_rtl","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as user input using automatic approach firmware and check them"} ,"gpio_all_i_pu" :{"level":0, "SW":true, - "RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","setup","r_caravan_rtl","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"} @@ -51,15 +51,15 @@ ,"gpio_all_i_pd" :{"level":0, "SW":true, - "RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","setup","r_caravan_rtl","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"} ,"gpio_all_i_pd_user" :{"level":0, "SW":true, "RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as user input pull down using automatic approach firmware and check them"} @@ -72,8 +72,8 @@ ,"gpio_all_o" :{"level":0, "SW":true, - "RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","setup","r_caravan_rtl","gpio_rtl","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","gpio_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} @@ -85,8 +85,8 @@ "description":"configure all gpios as user output using automatic approach firmware and check them"} ,"hk_regs_wr_wb_cpu" :{"level":0, "SW":false, - "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"bit bash test for housekeeping registers"} ,"IRQ_timer" :{"level":2, @@ -125,8 +125,8 @@ "description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"} ,"hk_regs_wr_spi" :{"level":0, "SW":false, - "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","r_caravan_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","push_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"} @@ -207,8 +207,8 @@ ,"mgmt_gpio_bidir" :{"level":0, "SW":true, - "RTL":["r_rtl","setup","nightly","weekly","tape_out"], - "GL":["r_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","r_caravan_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","r_caravan_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "} diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index eb4a2e91..346fd7fb 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -18,7 +18,7 @@ iverilog = True vcs = False coverage = False zip_waves = True - +caravan = False def go_up(path, n): for i in range(n): path = os.path.dirname(path) @@ -108,9 +108,13 @@ class RunTest: elif(self.sim_type=="GLSDF"): print(f"iverilog can't run SDF for test {self.test_name} Please use anothor simulator like cvc" ) return - + user_project = f"{CARAVEL_PATH}/rtl/__user_project_wrapper.v {CARAVEL_PATH}/rtl/__user_project_gpio_example.v {CARAVEL_PATH}/rtl/__user_project_la_example.v" + if caravan: + print ("Use caravan") + macros = f'-DCARAVAN {macros} ' + user_project = f"{CARAVEL_PATH}/rtl/__user_analog_project_wrapper.v" iverilog_command = (f"iverilog -Ttyp {macros} {includes} -o {self.sim_path}/sim.vvp" - f" {CARAVEL_PATH}/rtl/__user_project_wrapper.v {CARAVEL_PATH}/rtl/__user_project_gpio_example.v {CARAVEL_PATH}/rtl/__user_project_la_example.v caravel_top.sv" + f" {user_project} caravel_top.sv" f" && TESTCASE={self.test_name} MODULE=caravel_tests vvp -M $(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus {self.sim_path}/sim.vvp") docker_command = f"docker run -it {env_vars} -v {os.getenv('CARAVEL_ROOT')}:{os.getenv('CARAVEL_ROOT')} -v {os.getenv('MCW_ROOT')}:{os.getenv('MCW_ROOT')} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {iverilog_command}' >> {self.full_file}" self.full_terminal = open(self.full_file, "a") @@ -474,6 +478,7 @@ parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler i parser.add_argument('-cov',action='store_true', help='enable code coverage') parser.add_argument('-corner','-c', nargs='+' ,help='Corner type in case of GL_SDF run has to be provided') parser.add_argument('-keep_pass_unzip',action='store_true', help='Normally the waves and logs of passed tests would be zipped. Using this option they wouldn\'t be zipped') +parser.add_argument('-caravan',action='store_true', help='simulate caravan instead of caravel') args = parser.parse_args() if (args.vcs) : iverilog = False @@ -486,6 +491,8 @@ if args.corner == None: args.corner= ["nom-t"] if args.keep_pass_unzip: zip_waves = False +if args.caravan: + caravan = True print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}") main(args) diff --git a/verilog/rtl/__user_analog_project_wrapper.v b/verilog/rtl/__user_analog_project_wrapper.v index 6360f0b4..e2d91a64 100644 --- a/verilog/rtl/__user_analog_project_wrapper.v +++ b/verilog/rtl/__user_analog_project_wrapper.v @@ -121,4 +121,33 @@ module user_analog_project_wrapper ( // Dummy assignment so that we can take it through the openlane flow assign io_out = io_in; +// splitting the address space to user address space and debug address space +// debug address space are the last 2 registers of user_project_wrapper address space +wire wbs_cyc_i_user; +wire wbs_ack_o_user; +wire [31:0] wbs_dat_o_user; + +wire wbs_cyc_i_debug; +wire wbs_ack_o_debug; +wire [31:0] wbs_dat_o_debug; + +assign wbs_cyc_i_user = (wbs_adr_i[31:3] != 29'h601FFFF) ? wbs_cyc_i : 0; +assign wbs_cyc_i_debug = (wbs_adr_i[31:3] == 29'h601FFFF) ? wbs_cyc_i : 0; +assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_user; +assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user; +assign wbs_ack_o_user = 0; + +debug_regs debug( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wbs_cyc_i(wbs_cyc_i_debug), + .wbs_stb_i(wbs_stb_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o_debug), + .wbs_dat_o(wbs_dat_o_debug) +); + endmodule // user_analog_project_wrapper