mirror of https://github.com/efabless/caravel.git
added sdc file output from OL
This commit is contained in:
marwaneltoukhy
parent
60584f56ce
commit
08a8e6d87f
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@ -1,6 +1,6 @@
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###############################################################################
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# Created by write_sdc
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# Tue Oct 11 23:00:28 2022
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# Thu Oct 13 16:41:59 2022
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###############################################################################
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current_design housekeeping
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###############################################################################
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@ -8,371 +8,372 @@ current_design housekeeping
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###############################################################################
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create_clock -name wb_clk_i -period 25.0000 [get_ports {wb_clk_i}]
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set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
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set_clock_uncertainty 0.3000 wb_clk_i
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set_clock_uncertainty 0.2000 wb_clk_i
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set_propagated_clock [get_clocks {wb_clk_i}]
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create_clock -name user_clock -period 25.0000 [get_ports {user_clock}]
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set_clock_transition 0.1500 [get_clocks {user_clock}]
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set_clock_uncertainty 0.3000 user_clock
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set_clock_uncertainty 0.2000 user_clock
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set_propagated_clock [get_clocks {user_clock}]
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create_clock -name sck -period 100.0000 [get_ports {mgmt_gpio_in[4]}]
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set_clock_transition 0.1500 [get_clocks {sck}]
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set_clock_uncertainty 0.3000 sck
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set_clock_uncertainty 0.2000 sck
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set_propagated_clock [get_clocks {sck}]
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create_generated_clock -name wbbd_sck -source [get_ports {wb_clk_i}] -divide_by 2 [get_pins {_7205_/Q}]
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set_clock_uncertainty 0.2000 wbbd_sck
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set_propagated_clock [get_clocks {wbbd_sck}]
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set_clock_groups -name group1 -logically_exclusive \
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-group [get_clocks {sck}]\
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-group [get_clocks {wb_clk_i}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_mode}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_oeb}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_out}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[0]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[10]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[11]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[12]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[13]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[14]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[15]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[16]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[17]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[18]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[19]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[1]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[20]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[21]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[22]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[23]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[24]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[25]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[26]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[27]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[28]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[29]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[2]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[30]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[31]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[3]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[4]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[5]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[6]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[7]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[8]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[9]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[0]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[10]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[11]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[12]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[13]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[14]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[15]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[16]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[17]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[18]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[19]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[1]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[20]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[21]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[22]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[23]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[24]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[25]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[26]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[27]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[28]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[29]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[2]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[30]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[31]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[32]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[33]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[34]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[35]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[36]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[37]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[3]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_mode}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_oeb}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_out}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[0]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[10]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[11]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[12]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[13]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[14]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[15]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[16]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[17]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[18]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[19]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[1]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[20]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[21]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[22]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[23]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[24]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[25]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[26]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[27]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[28]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[29]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[2]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[30]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[31]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[3]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[4]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[5]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[6]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[7]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[8]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mask_rev_in[9]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[0]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[10]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[11]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[12]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[13]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[14]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[15]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[16]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[17]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[18]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[19]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[1]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[20]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[21]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[22]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[23]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[24]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[25]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[26]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[27]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[28]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[29]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[2]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[30]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[31]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[32]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[33]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[34]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[35]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[36]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[37]}]
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set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[3]}]
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set_input_delay 0.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[4]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[5]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[6]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[7]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[8]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[9]}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_di}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_di}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {porb}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {qspi_enabled}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_tx}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_csb}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_enabled}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sck}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdo}]
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set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdoenb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_clk}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_csb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_do}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {trap}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {uart_enabled}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_in[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_di}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_di}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {porb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {qspi_enabled}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_tx}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_csb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_enabled}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sck}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdo}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdoenb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_clk}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_csb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_do}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_oeb}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {trap}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {uart_enabled}]
|
||||
set_input_delay 0.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {user_clock}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vcc_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vdd_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vcc_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vdd_pwrgood}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[11]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[12]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[13]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[14]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[15]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[16]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[17]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[18]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[19]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[20]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[21]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[22]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[23]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[24]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[25]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[26]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[27]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[28]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[29]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[30]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[31]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[4]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[5]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[6]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[7]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[8]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[9]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rstn_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[32]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[33]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[34]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[35]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[36]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[37]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_do}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_ieb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_do}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_ieb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_oeb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_bypass}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_dco_ena}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_ena}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[9]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {reset}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_rx}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_1}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_2}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_load}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_resetn}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdi}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_di}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[10]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[11]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[12]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[13]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[14]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[15]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[16]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[17]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[18]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[19]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[20]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[21]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[22]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[23]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[24]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[25]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[26]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[27]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[28]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[29]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[30]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[31]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[3]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[4]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[5]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[6]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[7]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[8]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vcc_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr1_vdd_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vcc_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {usr2_vdd_pwrgood}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[10]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[11]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[12]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[13]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[14]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[15]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[16]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[17]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[18]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[19]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[20]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[21]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[22]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[23]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[24]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[25]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[26]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[27]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[28]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[29]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[30]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[31]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[4]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[10]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[11]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[12]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[13]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[14]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[15]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[16]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[17]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[18]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[19]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[20]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[21]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[22]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[23]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[24]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[25]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[26]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[27]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[28]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[29]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[30]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[31]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[4]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[5]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[6]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[7]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[8]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_i[9]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rstn_i}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[0]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[1]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[2]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[3]}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}]
|
||||
set_input_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {debug_in}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[26]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[27]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[28]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[29]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[30]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[31]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[32]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[33]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[34]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[35]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[36]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[37]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_oeb[9]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[26]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[27]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[28]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[29]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[30]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[31]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[32]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[33]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[34]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[35]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[36]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[37]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {mgmt_gpio_out[9]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_clk_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_csb_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_do}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_ieb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io0_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_do}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_ieb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pad_flash_io1_oeb}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll90_sel[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_bypass}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_dco_ena}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_div[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_ena}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_sel[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pll_trim[9]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {pwr_ctrl_out[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {reset}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {ser_rx}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_1}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_data_2}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_load}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {serial_resetn}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spi_sdi}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io0_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io1_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io2_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {spimemio_flash_io3_di}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[0]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[10]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[11]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[12]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[13]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[14]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[15]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[16]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[17]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[18]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[19]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[1]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[20]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[21]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[22]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[23]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[24]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[25]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[26]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[27]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[28]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[29]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[2]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[30]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[31]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[3]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[4]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[5]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[6]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[7]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[8]}]
|
||||
set_output_delay 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[9]}]
|
||||
set_false_path\
|
||||
-from [list [get_ports {porb}]\
|
||||
[get_ports {wb_rstn_i}]]
|
||||
|
|
@ -564,4 +565,11 @@ set_timing_derate -late 1.0500
|
|||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_transition 0.7500 [current_design]
|
||||
set_max_transition 0.4000 [get_ports {pad_flash_clk}]
|
||||
set_max_transition 0.4000 [get_ports {mgmt_gpio_out[15]}]
|
||||
set_max_transition 0.4000 [get_ports {mgmt_gpio_out[14]}]
|
||||
set_max_transition 0.4000 [get_ports {mgmt_gpio_out[9]}]
|
||||
set_max_transition -clock_path 0.4000 [get_clocks {sck}]
|
||||
set_max_transition -clock_path 0.4000 [get_clocks {user_clock}]
|
||||
set_max_transition -clock_path 0.4000 [get_clocks {wb_clk_i}]
|
||||
set_max_fanout 20.0000 [current_design]
|
||||
|
|
|
|||
Loading…
Reference in New Issue