diff --git a/manifest b/manifest
index 4d3806a6..c5eed1c9 100644
--- a/manifest
+++ b/manifest
@@ -2,10 +2,10 @@
 87735eb5981740ca4d4b48e6b0321c8bb0023800  verilog/rtl/__uprj_netlists.v
 684085713662e37a26f9f981d35be7c6c7ff6e9a  verilog/rtl/__user_analog_project_wrapper.v
 b5ad3558a91e508fad154b91565c7d664b247020  verilog/rtl/__user_project_wrapper.v
-ad30a2c7df753845db0ea65c1f3387c3e55b8f06  verilog/rtl/caravan.v
+610cf8c391cb48d931f45c628c74b5dbbe7b3dc7  verilog/rtl/caravan.v
 a855d65d6fc59352e4f8a994e451418d113586fc  verilog/rtl/caravan_netlists.v
 a3d12a2d2d3596800bec47d1266dce2399a2fcc6  verilog/rtl/caravan_openframe.v
-0b5b9fc879625af003415776671bc44cdc774470  verilog/rtl/caravel.v
+cb320bf7e981979c4e823270d823395ea609c77e  verilog/rtl/caravel.v
 2fe34f043edbe87c626e5616ad54f82c9ba067c2  verilog/rtl/caravel_clocking.v
 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650  verilog/rtl/caravel_openframe.v
 d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76  verilog/rtl/chip_io.v
diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index bf673a9a..d4e8603c 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -666,7 +666,7 @@ module caravan (
 
     // Clocking control
 
-    caravel_clocking clocking(
+    caravel_clocking clock_ctrl (
 	`ifdef USE_POWER_PINS
 	    .VPWR(vccd_core),
 	    .VGND(vssd_core),
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 3b6b9bb9..706cb21a 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -611,7 +611,7 @@ module caravel (
 
     // Clocking control
 
-    caravel_clocking clocking(
+    caravel_clocking clock_ctrl (
     `ifdef USE_POWER_PINS
 		.VPWR(vccd_core),
 		.VGND(vssd_core),