mirror of https://github.com/efabless/caravel.git
commit
05baf48756
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@ -1,28 +1,22 @@
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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# .readthedocs.yml
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# .readthedocs.yaml
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# Read the Docs configuration file
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# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
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# Required
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version: 2
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# Set the version of Python and other tools you might need
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build:
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os: ubuntu-22.04
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tools:
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python: "3.10"
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# Build documentation in the docs/ directory with Sphinx
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sphinx:
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configuration: docs/source/conf.py
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conda:
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environment: docs/environment.yml
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# We recommend specifying your dependencies to enable reproducible builds:
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# https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html
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python:
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install:
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- requirements: docs/requirements.txt
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@ -6,3 +6,4 @@ sphinx-autobuild
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recommonmark
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sphinx_markdown_tables
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sphinxcontrib-wavedrom
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sphinx_rtd_theme
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4
manifest
4
manifest
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@ -22,7 +22,7 @@ ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v
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d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
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e54c181033aa019f0edcaed5ffc71e54c3888970 verilog/rtl/chip_io.v
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1088531d6a69d82b976d4aca7ae923423680a715 verilog/rtl/chip_io_alt.v
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e293e138c6e6f5df76db78bdaa34a35003f6ba5f verilog/rtl/chip_io_openframe.v
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b080fd6193e1aee1cd476d8a4c117d65ae1e1178 verilog/rtl/chip_io_openframe.v
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126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
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941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
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58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
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@ -47,7 +47,7 @@ c96ba94e5779ea6afe452d89632eaada73e26aab verilog/rtl/mprj_io.v
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e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v
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3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
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5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
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33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v
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189532aff9e5e2ebbd99befd05cbf50e948b14af verilog/rtl/openframe_netlists.v
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b53c154e6acaf44e858c936c8027d0229608676e verilog/rtl/pads.v
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669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
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83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d verilog/rtl/simple_por.v
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