From 00364eb09250a250b5f6651edd1b84f7af94ddb8 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 9 Oct 2022 07:53:25 -0700 Subject: [PATCH] Add gpio_all_o_user test --- verilog/dv/cocotb/caravel_tests.py | 1 + verilog/dv/cocotb/tests.json | 6 ++ verilog/dv/cocotb/tests/gpio/gpio.py | 4 +- .../dv/cocotb/tests/gpio/gpio_all_o_user.c | 93 +++++++++++++++++++ verilog/dv/cocotb/tests/gpio/gpio_user.py | 69 ++++++++++++++ verilog/dv/cocotb/verify_cocotb.py | 2 + verilog/rtl/__user_project_gpio_example.v | 80 ++++++++++++++++ verilog/rtl/__user_project_wrapper.v | 48 +++++++++- verilog/rtl/debug_regs.v | 22 ++--- 9 files changed, 308 insertions(+), 17 deletions(-) create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_user.py create mode 100644 verilog/rtl/__user_project_gpio_example.v diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index b2034fe7..10922a96 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -36,6 +36,7 @@ from tests.irq.IRQ_external import * from tests.irq.IRQ_timer import * from tests.irq.IRQ_uart import * from tests.gpio.gpio import * +from tests.gpio.gpio_user import * from tests.mgmt_gpio.mgmt_gpio import * from tests.timer.timer import * from tests.uart.uart import * diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 0c3f0ed7..308efdf4 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -21,6 +21,12 @@ "GL":["r_gl","push_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} + ,"gpio_all_o_user" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"configure all gpios as user output using automatic approach firmware and check them"} ,"gpio_all_i" :{"level":0, "SW":true, "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 3dcb60f0..cb1aed80 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -21,7 +21,7 @@ async def gpio_all_o(dut): cpu.cpu_release_reset() await wait_reg1(cpu,caravelEnv,0xAA) - cocotb.log.info("[TEST] finish configuring using bitbang") + cocotb.log.info("[TEST] finish configuring ") i= 0x20 for j in range(5): await wait_reg2(cpu,caravelEnv,37-j) @@ -330,7 +330,7 @@ async def gpio_all_bidir(dut): cpu.cpu_release_reset() uut = dut.uut await wait_reg1(cpu,caravelEnv,0x1A) - cocotb.log.info("[TEST] finish configuring using bitbang") + cocotb.log.info("[TEST] finish configuring ") i= 0x20 for j in range(5): await wait_reg2(cpu,caravelEnv,37-j) diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c b/verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c new file mode 100644 index 00000000..851b25ea --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c @@ -0,0 +1,93 @@ +#include +#include +#include "../bitbang/bitbang_functions.c" +// Debug reg DEBUG_ON +#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0) +#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4) + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + reg_hkspi_disable = 1; + reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_1 = 0xAA; // finish configuration + reg_mprj_userl = 0x0; + reg_mprj_userh = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_userh = i; + reg_debug_2 = 37-j; + reg_mprj_userh = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_userh = 0x3f; + reg_mprj_userl = i; + reg_debug_2 = 32-j; + reg_mprj_userh = 0x00; + reg_mprj_userl = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } + + // try to give input + reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_userl + int timeout = 1000; + while (reg_mprj_userl != 0x8F66FD7B){ + timeout--; + if (timeout==0){ + break; + } + } + reg_debug_2 = reg_mprj_userl; + reg_debug_1 = 0XFF; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_userl +} + diff --git a/verilog/dv/cocotb/tests/gpio/gpio_user.py b/verilog/dv/cocotb/tests/gpio/gpio_user.py new file mode 100644 index 00000000..3266ae4d --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_user.py @@ -0,0 +1,69 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE +from cocotb.binary import BinaryValue + +reg = Regs() + +@cocotb.test() +@repot_test +async def gpio_all_o_user(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=376123) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + await wait_reg1(cpu,caravelEnv,0xAA) + cocotb.log.info("[TEST] finish configuring as user output") + i= 0x20 + for j in range(5): + await wait_reg2(cpu,caravelEnv,37-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,0)).integer != i<<32: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') + i = i >> 1 + i |= 0x20 + + i= 0x80000000 + for j in range(32): + await wait_reg2(cpu,caravelEnv,32-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') + if caravelEnv.monitor_gpio((31,0)).integer != i : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + await wait_reg1(cpu,caravelEnv,0XBB) + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]") + caravelEnv.drive_gpio_in((31,0),data_in) + reg2 =0 + await wait_reg1(cpu,caravelEnv,0XFF) + try: + reg2 =cpu.read_debug_reg2() + if reg2 == data_in: + cocotb.log.error(f"[TEST] Error: data {hex(data_in)} driven on gpio[31:0] is seen by firmware while gpios are configured as output") + else: + cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output it can see {reg2}") + except Exception as e: + cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output") + return + + + await ClockCycles(caravelEnv.clk, 10) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index bb02e722..e8837d38 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -83,6 +83,8 @@ class RunTest: macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS ' if self.test_name == "la": macros = f'{macros} +define+LA_TESTING' + if self.test_name == "gpio_all_o_user": + macros = f'{macros} +define+GPIO_TESTING' # shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex') # if os.path.exists(f'{self.test_full_dir}/test_data'): # shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data') diff --git a/verilog/rtl/__user_project_gpio_example.v b/verilog/rtl/__user_project_gpio_example.v new file mode 100644 index 00000000..4bcdfc39 --- /dev/null +++ b/verilog/rtl/__user_project_gpio_example.v @@ -0,0 +1,80 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_project_la_example + * + * This is a user project for testing the gpio testing only + * + *------------------------------------------------------------- + */ + +module user_project_gpio_example ( + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output reg wbs_ack_o, + output reg[31:0] wbs_dat_o, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb + +); + reg [31:0] io_l; + reg [5:0] io_h; + + + always @(posedge wb_clk_i or posedge wb_rst_i) begin + if (wb_rst_i) begin + io_l <=0; + io_h <=0; + wbs_dat_o <=0; + wbs_ack_o <=0; + end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0))begin // write + // write to io_l + io_l[7:0] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[0])? wbs_dat_i[7:0] :io_l[7:0]; + io_l[15:8] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[1])? wbs_dat_i[15:8] :io_l[15:8]; + io_l[23:16] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[2])? wbs_dat_i[23:16] :io_l[23:16]; + io_l[31:24] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[3])? wbs_dat_i[31:24] :io_l[31:24]; + // io_h + io_h[5:0] <= ((wbs_adr_i[3:0]==4'h4) && wbs_sel_i[0])? wbs_dat_i[5:0] :io_h[5:0]; + + wbs_ack_o <= 1; + end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0)) begin // read + wbs_dat_o <= (wbs_adr_i[3:0]==4'h0)? io_in[31:0] : io_in[`MPRJ_IO_PADS-1:32]; + wbs_ack_o <= 1; + end else begin + wbs_ack_o <= 0; + wbs_dat_o <= 0; + end + end + + assign io_out = {io_h,io_l}; + assign io_oeb = 38'h0; + +endmodule + +`default_nettype wire diff --git a/verilog/rtl/__user_project_wrapper.v b/verilog/rtl/__user_project_wrapper.v index ebcf54cc..bda6291a 100644 --- a/verilog/rtl/__user_project_wrapper.v +++ b/verilog/rtl/__user_project_wrapper.v @@ -79,6 +79,7 @@ module user_project_wrapper #( ); // Dummy assignments so that we can take it through the openlane flow +`ifndef GPIO_TESTING `ifdef SIM // Needed for running GL simulation assign io_out = 0; @@ -86,6 +87,7 @@ assign io_oeb = 0; `else assign io_out = io_in; `endif +`endif // GPIO_TESTING `ifdef LA_TESTING user_project_la_example la_testing(la_data_in,la_data_out,la_oenb); @@ -99,15 +101,53 @@ wire [31:0] wbs_dat_o_user; wire wbs_cyc_i_debug; wire wbs_ack_o_debug; +`ifdef GPIO_TESTING +wire wbs_ack_o_gpio; +wire [31:0] wbs_dat_o_gpio; +`endif wire [31:0] wbs_dat_o_debug; // reserve the last 2 regs for debugging registers -assign wbs_cyc_i_user = (wbs_adr_i[19:3] != 17'h1ffff) ? wbs_cyc_i : 0; -assign wbs_cyc_i_debug = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_cyc_i : 0; +`ifndef GPIO_TESTING +assign wbs_cyc_i_user = (wbs_adr_i[31:3] != 29'h601FFFF) ? wbs_cyc_i : 0; +assign wbs_cyc_i_debug = (wbs_adr_i[31:3] == 29'h601FFFF) ? wbs_cyc_i : 0; +`endif -assign wbs_ack_o = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_ack_o_debug : wbs_ack_o_debug; -assign wbs_dat_o = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_dat_o_debug : wbs_dat_o_user; +`ifndef GPIO_TESTING +assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_debug; +assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user; +`endif + + +// reserve the last 4 regs for debugging registers in case of user gpio testing +`ifdef GPIO_TESTING +assign wbs_cyc_i_user = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0; +assign wbs_cyc_i_debug = (wbs_adr_i[31:4] == 28'h300FFFF) ? wbs_cyc_i : 0; +`endif + +`ifdef GPIO_TESTING +assign wbs_ack_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_ack_o_debug : wbs_ack_o_gpio : wbs_ack_o_debug; +assign wbs_dat_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_dat_o_debug : wbs_dat_o_gpio : wbs_dat_o_user; +`endif + + +`ifdef GPIO_TESTING +user_project_gpio_example gpio_testing( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wbs_cyc_i(wbs_cyc_i_debug), + .wbs_stb_i(wbs_stb_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o_gpio), + .wbs_dat_o(wbs_dat_o_gpio), + .io_in(io_in), + .io_out(io_out), + .io_oeb(io_oeb)); +`endif debug_regs debug( .wb_clk_i(wb_clk_i), diff --git a/verilog/rtl/debug_regs.v b/verilog/rtl/debug_regs.v index 85043928..2551a3c4 100644 --- a/verilog/rtl/debug_regs.v +++ b/verilog/rtl/debug_regs.v @@ -21,20 +21,20 @@ module debug_regs ( debug_reg_2 <=0; wbs_dat_o <=0; wbs_ack_o <=0; - end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o)begin // write + end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8))begin // write // write to reg1 - debug_reg_1[7:0] <= (!wbs_adr_i[2] && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_1[7:0]; - debug_reg_1[15:8] <= (!wbs_adr_i[2] && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_1[15:8]; - debug_reg_1[23:16] <= (!wbs_adr_i[2] && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_1[23:16]; - debug_reg_1[31:24] <= (!wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_1[31:24]; + debug_reg_1[7:0] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_1[7:0]; + debug_reg_1[15:8] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_1[15:8]; + debug_reg_1[23:16] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_1[23:16]; + debug_reg_1[31:24] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_1[31:24]; // write to reg2 - debug_reg_2[7:0] <= (wbs_adr_i[2] && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_2[7:0]; - debug_reg_2[15:8] <= (wbs_adr_i[2] && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_2[15:8]; - debug_reg_2[23:16] <= (wbs_adr_i[2] && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_2[23:16]; - debug_reg_2[31:24] <= (wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24]; + debug_reg_2[7:0] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_2[7:0]; + debug_reg_2[15:8] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_2[15:8]; + debug_reg_2[23:16] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_2[23:16]; + debug_reg_2[31:24] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24]; wbs_ack_o <= 1; - end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o) begin // read - wbs_dat_o <= (wbs_adr_i[2]) ? debug_reg_2 : debug_reg_1; + end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8)) begin // read + wbs_dat_o <= ((wbs_adr_i[3:0]==4'hC)) ? debug_reg_2 : debug_reg_1; wbs_ack_o <= 1; end else begin wbs_ack_o <= 0;