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caravel/def/caravan.def

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[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN caravan ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 3588000 5188000 ) ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
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ROW ROW_280 unithd 5520 772480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_281 unithd 5520 775200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_282 unithd 5520 777920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_283 unithd 5520 780640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_284 unithd 5520 783360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_285 unithd 5520 786080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_286 unithd 5520 788800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_287 unithd 5520 791520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_288 unithd 5520 794240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_289 unithd 5520 796960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_290 unithd 5520 799680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_291 unithd 5520 802400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_292 unithd 5520 805120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_293 unithd 5520 807840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_294 unithd 5520 810560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_295 unithd 5520 813280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_296 unithd 5520 816000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_297 unithd 5520 818720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_298 unithd 5520 821440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_299 unithd 5520 824160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_300 unithd 5520 826880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_301 unithd 5520 829600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_302 unithd 5520 832320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_303 unithd 5520 835040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_304 unithd 5520 837760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_305 unithd 5520 840480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_306 unithd 5520 843200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_307 unithd 5520 845920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_308 unithd 5520 848640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_309 unithd 5520 851360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_310 unithd 5520 854080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_311 unithd 5520 856800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_312 unithd 5520 859520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_313 unithd 5520 862240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_314 unithd 5520 864960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_315 unithd 5520 867680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_316 unithd 5520 870400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_317 unithd 5520 873120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_318 unithd 5520 875840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_319 unithd 5520 878560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_320 unithd 5520 881280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_321 unithd 5520 884000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_322 unithd 5520 886720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_323 unithd 5520 889440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_324 unithd 5520 892160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_325 unithd 5520 894880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_326 unithd 5520 897600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_327 unithd 5520 900320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_328 unithd 5520 903040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_329 unithd 5520 905760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_330 unithd 5520 908480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_331 unithd 5520 911200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_332 unithd 5520 913920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_333 unithd 5520 916640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_334 unithd 5520 919360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_335 unithd 5520 922080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_336 unithd 5520 924800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_337 unithd 5520 927520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_338 unithd 5520 930240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_339 unithd 5520 932960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_340 unithd 5520 935680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_341 unithd 5520 938400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_342 unithd 5520 941120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_343 unithd 5520 943840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_344 unithd 5520 946560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_345 unithd 5520 949280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_346 unithd 5520 952000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_347 unithd 5520 954720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_348 unithd 5520 957440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_349 unithd 5520 960160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_350 unithd 5520 962880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_351 unithd 5520 965600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_352 unithd 5520 968320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_353 unithd 5520 971040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_354 unithd 5520 973760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_355 unithd 5520 976480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_356 unithd 5520 979200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_357 unithd 5520 981920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_358 unithd 5520 984640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_359 unithd 5520 987360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_360 unithd 5520 990080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_361 unithd 5520 992800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_362 unithd 5520 995520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_363 unithd 5520 998240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_364 unithd 5520 1000960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_365 unithd 5520 1003680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_366 unithd 5520 1006400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_367 unithd 5520 1009120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_368 unithd 5520 1011840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_369 unithd 5520 1014560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_370 unithd 5520 1017280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_371 unithd 5520 1020000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_372 unithd 5520 1022720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_373 unithd 5520 1025440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_374 unithd 5520 1028160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_375 unithd 5520 1030880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_376 unithd 5520 1033600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_377 unithd 5520 1036320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_378 unithd 5520 1039040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_379 unithd 5520 1041760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_380 unithd 5520 1044480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_381 unithd 5520 1047200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_382 unithd 5520 1049920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_383 unithd 5520 1052640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_384 unithd 5520 1055360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_385 unithd 5520 1058080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_386 unithd 5520 1060800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_387 unithd 5520 1063520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_388 unithd 5520 1066240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_389 unithd 5520 1068960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_390 unithd 5520 1071680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_391 unithd 5520 1074400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_392 unithd 5520 1077120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_393 unithd 5520 1079840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_394 unithd 5520 1082560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_395 unithd 5520 1085280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_396 unithd 5520 1088000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_397 unithd 5520 1090720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_398 unithd 5520 1093440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_399 unithd 5520 1096160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_400 unithd 5520 1098880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_401 unithd 5520 1101600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_402 unithd 5520 1104320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_403 unithd 5520 1107040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_404 unithd 5520 1109760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_405 unithd 5520 1112480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_406 unithd 5520 1115200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_407 unithd 5520 1117920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_408 unithd 5520 1120640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_409 unithd 5520 1123360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_410 unithd 5520 1126080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_411 unithd 5520 1128800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_412 unithd 5520 1131520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_413 unithd 5520 1134240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_414 unithd 5520 1136960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_415 unithd 5520 1139680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_416 unithd 5520 1142400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_417 unithd 5520 1145120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_418 unithd 5520 1147840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_419 unithd 5520 1150560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_420 unithd 5520 1153280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_421 unithd 5520 1156000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_422 unithd 5520 1158720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_423 unithd 5520 1161440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_424 unithd 5520 1164160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_425 unithd 5520 1166880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_426 unithd 5520 1169600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_427 unithd 5520 1172320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_428 unithd 5520 1175040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_429 unithd 5520 1177760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_430 unithd 5520 1180480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_431 unithd 5520 1183200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_432 unithd 5520 1185920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_433 unithd 5520 1188640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_434 unithd 5520 1191360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_435 unithd 5520 1194080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_436 unithd 5520 1196800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_437 unithd 5520 1199520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_438 unithd 5520 1202240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_439 unithd 5520 1204960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_440 unithd 5520 1207680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_441 unithd 5520 1210400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_442 unithd 5520 1213120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_443 unithd 5520 1215840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_444 unithd 5520 1218560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_445 unithd 5520 1221280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_446 unithd 5520 1224000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_447 unithd 5520 1226720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_448 unithd 5520 1229440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_449 unithd 5520 1232160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_450 unithd 5520 1234880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_451 unithd 5520 1237600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_452 unithd 5520 1240320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_453 unithd 5520 1243040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_454 unithd 5520 1245760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_455 unithd 5520 1248480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_456 unithd 5520 1251200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_457 unithd 5520 1253920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_458 unithd 5520 1256640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_459 unithd 5520 1259360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_460 unithd 5520 1262080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_461 unithd 5520 1264800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_462 unithd 5520 1267520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_463 unithd 5520 1270240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_464 unithd 5520 1272960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_465 unithd 5520 1275680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_466 unithd 5520 1278400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_467 unithd 5520 1281120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_468 unithd 5520 1283840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_469 unithd 5520 1286560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_470 unithd 5520 1289280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_471 unithd 5520 1292000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_472 unithd 5520 1294720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_473 unithd 5520 1297440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_474 unithd 5520 1300160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_475 unithd 5520 1302880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_476 unithd 5520 1305600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_477 unithd 5520 1308320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_478 unithd 5520 1311040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_479 unithd 5520 1313760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_480 unithd 5520 1316480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_481 unithd 5520 1319200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_482 unithd 5520 1321920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_483 unithd 5520 1324640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_484 unithd 5520 1327360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_485 unithd 5520 1330080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_486 unithd 5520 1332800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_487 unithd 5520 1335520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_488 unithd 5520 1338240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_489 unithd 5520 1340960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_490 unithd 5520 1343680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_491 unithd 5520 1346400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_492 unithd 5520 1349120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_493 unithd 5520 1351840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_494 unithd 5520 1354560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_495 unithd 5520 1357280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_496 unithd 5520 1360000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_497 unithd 5520 1362720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_498 unithd 5520 1365440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_499 unithd 5520 1368160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_500 unithd 5520 1370880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_501 unithd 5520 1373600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_502 unithd 5520 1376320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_503 unithd 5520 1379040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_504 unithd 5520 1381760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_505 unithd 5520 1384480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_506 unithd 5520 1387200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_507 unithd 5520 1389920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_508 unithd 5520 1392640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_509 unithd 5520 1395360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_510 unithd 5520 1398080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_511 unithd 5520 1400800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_512 unithd 5520 1403520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_513 unithd 5520 1406240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_514 unithd 5520 1408960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_515 unithd 5520 1411680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_516 unithd 5520 1414400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_517 unithd 5520 1417120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_518 unithd 5520 1419840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_519 unithd 5520 1422560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_520 unithd 5520 1425280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_521 unithd 5520 1428000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_522 unithd 5520 1430720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_523 unithd 5520 1433440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_524 unithd 5520 1436160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_525 unithd 5520 1438880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_526 unithd 5520 1441600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_527 unithd 5520 1444320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_528 unithd 5520 1447040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_529 unithd 5520 1449760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_530 unithd 5520 1452480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_531 unithd 5520 1455200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_532 unithd 5520 1457920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_533 unithd 5520 1460640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_534 unithd 5520 1463360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_535 unithd 5520 1466080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_536 unithd 5520 1468800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_537 unithd 5520 1471520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_538 unithd 5520 1474240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_539 unithd 5520 1476960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_540 unithd 5520 1479680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_541 unithd 5520 1482400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_542 unithd 5520 1485120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_543 unithd 5520 1487840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_544 unithd 5520 1490560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_545 unithd 5520 1493280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_546 unithd 5520 1496000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_547 unithd 5520 1498720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_548 unithd 5520 1501440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_549 unithd 5520 1504160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_550 unithd 5520 1506880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_551 unithd 5520 1509600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_552 unithd 5520 1512320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_553 unithd 5520 1515040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_554 unithd 5520 1517760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_555 unithd 5520 1520480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_556 unithd 5520 1523200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_557 unithd 5520 1525920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_558 unithd 5520 1528640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_559 unithd 5520 1531360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_560 unithd 5520 1534080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_561 unithd 5520 1536800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_562 unithd 5520 1539520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_563 unithd 5520 1542240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_564 unithd 5520 1544960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_565 unithd 5520 1547680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_566 unithd 5520 1550400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_567 unithd 5520 1553120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_568 unithd 5520 1555840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_569 unithd 5520 1558560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_570 unithd 5520 1561280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_571 unithd 5520 1564000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_572 unithd 5520 1566720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_573 unithd 5520 1569440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_574 unithd 5520 1572160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_575 unithd 5520 1574880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_576 unithd 5520 1577600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_577 unithd 5520 1580320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_578 unithd 5520 1583040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_579 unithd 5520 1585760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_580 unithd 5520 1588480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_581 unithd 5520 1591200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_582 unithd 5520 1593920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_583 unithd 5520 1596640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_584 unithd 5520 1599360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_585 unithd 5520 1602080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_586 unithd 5520 1604800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_587 unithd 5520 1607520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_588 unithd 5520 1610240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_589 unithd 5520 1612960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_590 unithd 5520 1615680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_591 unithd 5520 1618400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_592 unithd 5520 1621120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_593 unithd 5520 1623840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_594 unithd 5520 1626560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_595 unithd 5520 1629280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_596 unithd 5520 1632000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_597 unithd 5520 1634720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_598 unithd 5520 1637440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_599 unithd 5520 1640160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_600 unithd 5520 1642880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_601 unithd 5520 1645600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_602 unithd 5520 1648320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_603 unithd 5520 1651040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_604 unithd 5520 1653760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_605 unithd 5520 1656480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_606 unithd 5520 1659200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_607 unithd 5520 1661920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_608 unithd 5520 1664640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_609 unithd 5520 1667360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_610 unithd 5520 1670080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_611 unithd 5520 1672800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_612 unithd 5520 1675520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_613 unithd 5520 1678240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_614 unithd 5520 1680960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_615 unithd 5520 1683680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_616 unithd 5520 1686400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_617 unithd 5520 1689120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_618 unithd 5520 1691840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_619 unithd 5520 1694560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_620 unithd 5520 1697280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_621 unithd 5520 1700000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_622 unithd 5520 1702720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_623 unithd 5520 1705440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_624 unithd 5520 1708160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_625 unithd 5520 1710880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_626 unithd 5520 1713600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_627 unithd 5520 1716320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_628 unithd 5520 1719040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_629 unithd 5520 1721760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_630 unithd 5520 1724480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_631 unithd 5520 1727200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_632 unithd 5520 1729920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_633 unithd 5520 1732640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_634 unithd 5520 1735360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_635 unithd 5520 1738080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_636 unithd 5520 1740800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_637 unithd 5520 1743520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_638 unithd 5520 1746240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_639 unithd 5520 1748960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_640 unithd 5520 1751680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_641 unithd 5520 1754400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_642 unithd 5520 1757120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_643 unithd 5520 1759840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_644 unithd 5520 1762560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_645 unithd 5520 1765280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_646 unithd 5520 1768000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_647 unithd 5520 1770720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_648 unithd 5520 1773440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_649 unithd 5520 1776160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_650 unithd 5520 1778880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_651 unithd 5520 1781600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_652 unithd 5520 1784320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_653 unithd 5520 1787040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_654 unithd 5520 1789760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_655 unithd 5520 1792480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_656 unithd 5520 1795200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_657 unithd 5520 1797920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_658 unithd 5520 1800640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_659 unithd 5520 1803360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_660 unithd 5520 1806080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_661 unithd 5520 1808800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_662 unithd 5520 1811520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_663 unithd 5520 1814240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_664 unithd 5520 1816960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_665 unithd 5520 1819680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_666 unithd 5520 1822400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_667 unithd 5520 1825120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_668 unithd 5520 1827840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_669 unithd 5520 1830560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_670 unithd 5520 1833280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_671 unithd 5520 1836000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_672 unithd 5520 1838720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_673 unithd 5520 1841440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_674 unithd 5520 1844160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_675 unithd 5520 1846880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_676 unithd 5520 1849600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_677 unithd 5520 1852320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_678 unithd 5520 1855040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_679 unithd 5520 1857760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_680 unithd 5520 1860480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_681 unithd 5520 1863200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_682 unithd 5520 1865920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_683 unithd 5520 1868640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_684 unithd 5520 1871360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_685 unithd 5520 1874080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_686 unithd 5520 1876800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_687 unithd 5520 1879520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_688 unithd 5520 1882240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_689 unithd 5520 1884960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_690 unithd 5520 1887680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_691 unithd 5520 1890400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_692 unithd 5520 1893120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_693 unithd 5520 1895840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_694 unithd 5520 1898560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_695 unithd 5520 1901280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_696 unithd 5520 1904000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_697 unithd 5520 1906720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_698 unithd 5520 1909440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_699 unithd 5520 1912160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_700 unithd 5520 1914880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_701 unithd 5520 1917600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_702 unithd 5520 1920320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_703 unithd 5520 1923040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_704 unithd 5520 1925760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_705 unithd 5520 1928480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_706 unithd 5520 1931200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_707 unithd 5520 1933920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_708 unithd 5520 1936640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_709 unithd 5520 1939360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_710 unithd 5520 1942080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_711 unithd 5520 1944800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_712 unithd 5520 1947520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_713 unithd 5520 1950240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_714 unithd 5520 1952960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_715 unithd 5520 1955680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_716 unithd 5520 1958400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_717 unithd 5520 1961120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_718 unithd 5520 1963840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_719 unithd 5520 1966560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_720 unithd 5520 1969280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_721 unithd 5520 1972000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_722 unithd 5520 1974720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_723 unithd 5520 1977440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_724 unithd 5520 1980160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_725 unithd 5520 1982880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_726 unithd 5520 1985600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_727 unithd 5520 1988320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_728 unithd 5520 1991040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_729 unithd 5520 1993760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_730 unithd 5520 1996480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_731 unithd 5520 1999200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_732 unithd 5520 2001920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_733 unithd 5520 2004640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_734 unithd 5520 2007360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_735 unithd 5520 2010080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_736 unithd 5520 2012800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_737 unithd 5520 2015520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_738 unithd 5520 2018240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_739 unithd 5520 2020960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_740 unithd 5520 2023680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_741 unithd 5520 2026400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_742 unithd 5520 2029120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_743 unithd 5520 2031840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_744 unithd 5520 2034560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_745 unithd 5520 2037280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_746 unithd 5520 2040000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_747 unithd 5520 2042720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_748 unithd 5520 2045440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_749 unithd 5520 2048160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_750 unithd 5520 2050880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_751 unithd 5520 2053600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_752 unithd 5520 2056320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_753 unithd 5520 2059040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_754 unithd 5520 2061760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_755 unithd 5520 2064480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_756 unithd 5520 2067200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_757 unithd 5520 2069920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_758 unithd 5520 2072640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_759 unithd 5520 2075360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_760 unithd 5520 2078080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_761 unithd 5520 2080800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_762 unithd 5520 2083520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_763 unithd 5520 2086240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_764 unithd 5520 2088960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_765 unithd 5520 2091680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_766 unithd 5520 2094400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_767 unithd 5520 2097120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_768 unithd 5520 2099840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_769 unithd 5520 2102560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_770 unithd 5520 2105280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_771 unithd 5520 2108000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_772 unithd 5520 2110720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_773 unithd 5520 2113440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_774 unithd 5520 2116160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_775 unithd 5520 2118880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_776 unithd 5520 2121600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_777 unithd 5520 2124320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_778 unithd 5520 2127040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_779 unithd 5520 2129760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_780 unithd 5520 2132480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_781 unithd 5520 2135200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_782 unithd 5520 2137920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_783 unithd 5520 2140640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_784 unithd 5520 2143360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_785 unithd 5520 2146080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_786 unithd 5520 2148800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_787 unithd 5520 2151520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_788 unithd 5520 2154240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_789 unithd 5520 2156960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_790 unithd 5520 2159680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_791 unithd 5520 2162400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_792 unithd 5520 2165120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_793 unithd 5520 2167840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_794 unithd 5520 2170560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_795 unithd 5520 2173280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_796 unithd 5520 2176000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_797 unithd 5520 2178720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_798 unithd 5520 2181440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_799 unithd 5520 2184160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_800 unithd 5520 2186880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_801 unithd 5520 2189600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_802 unithd 5520 2192320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_803 unithd 5520 2195040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_804 unithd 5520 2197760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_805 unithd 5520 2200480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_806 unithd 5520 2203200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_807 unithd 5520 2205920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_808 unithd 5520 2208640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_809 unithd 5520 2211360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_810 unithd 5520 2214080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_811 unithd 5520 2216800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_812 unithd 5520 2219520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_813 unithd 5520 2222240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_814 unithd 5520 2224960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_815 unithd 5520 2227680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_816 unithd 5520 2230400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_817 unithd 5520 2233120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_818 unithd 5520 2235840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_819 unithd 5520 2238560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_820 unithd 5520 2241280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_821 unithd 5520 2244000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_822 unithd 5520 2246720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_823 unithd 5520 2249440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_824 unithd 5520 2252160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_825 unithd 5520 2254880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_826 unithd 5520 2257600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_827 unithd 5520 2260320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_828 unithd 5520 2263040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_829 unithd 5520 2265760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_830 unithd 5520 2268480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_831 unithd 5520 2271200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_832 unithd 5520 2273920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_833 unithd 5520 2276640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_834 unithd 5520 2279360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_835 unithd 5520 2282080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_836 unithd 5520 2284800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_837 unithd 5520 2287520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_838 unithd 5520 2290240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_839 unithd 5520 2292960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_840 unithd 5520 2295680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_841 unithd 5520 2298400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_842 unithd 5520 2301120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_843 unithd 5520 2303840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_844 unithd 5520 2306560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_845 unithd 5520 2309280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_846 unithd 5520 2312000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_847 unithd 5520 2314720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_848 unithd 5520 2317440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_849 unithd 5520 2320160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_850 unithd 5520 2322880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_851 unithd 5520 2325600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_852 unithd 5520 2328320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_853 unithd 5520 2331040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_854 unithd 5520 2333760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_855 unithd 5520 2336480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_856 unithd 5520 2339200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_857 unithd 5520 2341920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_858 unithd 5520 2344640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_859 unithd 5520 2347360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_860 unithd 5520 2350080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_861 unithd 5520 2352800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_862 unithd 5520 2355520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_863 unithd 5520 2358240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_864 unithd 5520 2360960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_865 unithd 5520 2363680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_866 unithd 5520 2366400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_867 unithd 5520 2369120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_868 unithd 5520 2371840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_869 unithd 5520 2374560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_870 unithd 5520 2377280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_871 unithd 5520 2380000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_872 unithd 5520 2382720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_873 unithd 5520 2385440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_874 unithd 5520 2388160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_875 unithd 5520 2390880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_876 unithd 5520 2393600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_877 unithd 5520 2396320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_878 unithd 5520 2399040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_879 unithd 5520 2401760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_880 unithd 5520 2404480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_881 unithd 5520 2407200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_882 unithd 5520 2409920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_883 unithd 5520 2412640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_884 unithd 5520 2415360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_885 unithd 5520 2418080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_886 unithd 5520 2420800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_887 unithd 5520 2423520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_888 unithd 5520 2426240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_889 unithd 5520 2428960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_890 unithd 5520 2431680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_891 unithd 5520 2434400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_892 unithd 5520 2437120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_893 unithd 5520 2439840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_894 unithd 5520 2442560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_895 unithd 5520 2445280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_896 unithd 5520 2448000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_897 unithd 5520 2450720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_898 unithd 5520 2453440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_899 unithd 5520 2456160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_900 unithd 5520 2458880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_901 unithd 5520 2461600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_902 unithd 5520 2464320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_903 unithd 5520 2467040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_904 unithd 5520 2469760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_905 unithd 5520 2472480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_906 unithd 5520 2475200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_907 unithd 5520 2477920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_908 unithd 5520 2480640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_909 unithd 5520 2483360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_910 unithd 5520 2486080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_911 unithd 5520 2488800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_912 unithd 5520 2491520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_913 unithd 5520 2494240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_914 unithd 5520 2496960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_915 unithd 5520 2499680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_916 unithd 5520 2502400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_917 unithd 5520 2505120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_918 unithd 5520 2507840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_919 unithd 5520 2510560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_920 unithd 5520 2513280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_921 unithd 5520 2516000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_922 unithd 5520 2518720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_923 unithd 5520 2521440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_924 unithd 5520 2524160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_925 unithd 5520 2526880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_926 unithd 5520 2529600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_927 unithd 5520 2532320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_928 unithd 5520 2535040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_929 unithd 5520 2537760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_930 unithd 5520 2540480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_931 unithd 5520 2543200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_932 unithd 5520 2545920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_933 unithd 5520 2548640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_934 unithd 5520 2551360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_935 unithd 5520 2554080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_936 unithd 5520 2556800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_937 unithd 5520 2559520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_938 unithd 5520 2562240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_939 unithd 5520 2564960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_940 unithd 5520 2567680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_941 unithd 5520 2570400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_942 unithd 5520 2573120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_943 unithd 5520 2575840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_944 unithd 5520 2578560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_945 unithd 5520 2581280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_946 unithd 5520 2584000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_947 unithd 5520 2586720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_948 unithd 5520 2589440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_949 unithd 5520 2592160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_950 unithd 5520 2594880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_951 unithd 5520 2597600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_952 unithd 5520 2600320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_953 unithd 5520 2603040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_954 unithd 5520 2605760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_955 unithd 5520 2608480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_956 unithd 5520 2611200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_957 unithd 5520 2613920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_958 unithd 5520 2616640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_959 unithd 5520 2619360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_960 unithd 5520 2622080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_961 unithd 5520 2624800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_962 unithd 5520 2627520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_963 unithd 5520 2630240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_964 unithd 5520 2632960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_965 unithd 5520 2635680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_966 unithd 5520 2638400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_967 unithd 5520 2641120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_968 unithd 5520 2643840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_969 unithd 5520 2646560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_970 unithd 5520 2649280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_971 unithd 5520 2652000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_972 unithd 5520 2654720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_973 unithd 5520 2657440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_974 unithd 5520 2660160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_975 unithd 5520 2662880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_976 unithd 5520 2665600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_977 unithd 5520 2668320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_978 unithd 5520 2671040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_979 unithd 5520 2673760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_980 unithd 5520 2676480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_981 unithd 5520 2679200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_982 unithd 5520 2681920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_983 unithd 5520 2684640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_984 unithd 5520 2687360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_985 unithd 5520 2690080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_986 unithd 5520 2692800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_987 unithd 5520 2695520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_988 unithd 5520 2698240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_989 unithd 5520 2700960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_990 unithd 5520 2703680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_991 unithd 5520 2706400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_992 unithd 5520 2709120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_993 unithd 5520 2711840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_994 unithd 5520 2714560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_995 unithd 5520 2717280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_996 unithd 5520 2720000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_997 unithd 5520 2722720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_998 unithd 5520 2725440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_999 unithd 5520 2728160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1000 unithd 5520 2730880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1001 unithd 5520 2733600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1002 unithd 5520 2736320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1003 unithd 5520 2739040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1004 unithd 5520 2741760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1005 unithd 5520 2744480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1006 unithd 5520 2747200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1007 unithd 5520 2749920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1008 unithd 5520 2752640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1009 unithd 5520 2755360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1010 unithd 5520 2758080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1011 unithd 5520 2760800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1012 unithd 5520 2763520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1013 unithd 5520 2766240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1014 unithd 5520 2768960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1015 unithd 5520 2771680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1016 unithd 5520 2774400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1017 unithd 5520 2777120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1018 unithd 5520 2779840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1019 unithd 5520 2782560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1020 unithd 5520 2785280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1021 unithd 5520 2788000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1022 unithd 5520 2790720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1023 unithd 5520 2793440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1024 unithd 5520 2796160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1025 unithd 5520 2798880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1026 unithd 5520 2801600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1027 unithd 5520 2804320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1028 unithd 5520 2807040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1029 unithd 5520 2809760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1030 unithd 5520 2812480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1031 unithd 5520 2815200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1032 unithd 5520 2817920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1033 unithd 5520 2820640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1034 unithd 5520 2823360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1035 unithd 5520 2826080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1036 unithd 5520 2828800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1037 unithd 5520 2831520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1038 unithd 5520 2834240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1039 unithd 5520 2836960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1040 unithd 5520 2839680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1041 unithd 5520 2842400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1042 unithd 5520 2845120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1043 unithd 5520 2847840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1044 unithd 5520 2850560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1045 unithd 5520 2853280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1046 unithd 5520 2856000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1047 unithd 5520 2858720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1048 unithd 5520 2861440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1049 unithd 5520 2864160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1050 unithd 5520 2866880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1051 unithd 5520 2869600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1052 unithd 5520 2872320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1053 unithd 5520 2875040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1054 unithd 5520 2877760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1055 unithd 5520 2880480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1056 unithd 5520 2883200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1057 unithd 5520 2885920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1058 unithd 5520 2888640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1059 unithd 5520 2891360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1060 unithd 5520 2894080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1061 unithd 5520 2896800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1062 unithd 5520 2899520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1063 unithd 5520 2902240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1064 unithd 5520 2904960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1065 unithd 5520 2907680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1066 unithd 5520 2910400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1067 unithd 5520 2913120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1068 unithd 5520 2915840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1069 unithd 5520 2918560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1070 unithd 5520 2921280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1071 unithd 5520 2924000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1072 unithd 5520 2926720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1073 unithd 5520 2929440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1074 unithd 5520 2932160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1075 unithd 5520 2934880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1076 unithd 5520 2937600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1077 unithd 5520 2940320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1078 unithd 5520 2943040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1079 unithd 5520 2945760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1080 unithd 5520 2948480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1081 unithd 5520 2951200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1082 unithd 5520 2953920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1083 unithd 5520 2956640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1084 unithd 5520 2959360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1085 unithd 5520 2962080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1086 unithd 5520 2964800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1087 unithd 5520 2967520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1088 unithd 5520 2970240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1089 unithd 5520 2972960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1090 unithd 5520 2975680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1091 unithd 5520 2978400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1092 unithd 5520 2981120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1093 unithd 5520 2983840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1094 unithd 5520 2986560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1095 unithd 5520 2989280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1096 unithd 5520 2992000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1097 unithd 5520 2994720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1098 unithd 5520 2997440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1099 unithd 5520 3000160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1100 unithd 5520 3002880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1101 unithd 5520 3005600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1102 unithd 5520 3008320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1103 unithd 5520 3011040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1104 unithd 5520 3013760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1105 unithd 5520 3016480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1106 unithd 5520 3019200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1107 unithd 5520 3021920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1108 unithd 5520 3024640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1109 unithd 5520 3027360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1110 unithd 5520 3030080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1111 unithd 5520 3032800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1112 unithd 5520 3035520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1113 unithd 5520 3038240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1114 unithd 5520 3040960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1115 unithd 5520 3043680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1116 unithd 5520 3046400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1117 unithd 5520 3049120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1118 unithd 5520 3051840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1119 unithd 5520 3054560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1120 unithd 5520 3057280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1121 unithd 5520 3060000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1122 unithd 5520 3062720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1123 unithd 5520 3065440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1124 unithd 5520 3068160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1125 unithd 5520 3070880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1126 unithd 5520 3073600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1127 unithd 5520 3076320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1128 unithd 5520 3079040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1129 unithd 5520 3081760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1130 unithd 5520 3084480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1131 unithd 5520 3087200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1132 unithd 5520 3089920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1133 unithd 5520 3092640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1134 unithd 5520 3095360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1135 unithd 5520 3098080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1136 unithd 5520 3100800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1137 unithd 5520 3103520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1138 unithd 5520 3106240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1139 unithd 5520 3108960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1140 unithd 5520 3111680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1141 unithd 5520 3114400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1142 unithd 5520 3117120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1143 unithd 5520 3119840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1144 unithd 5520 3122560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1145 unithd 5520 3125280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1146 unithd 5520 3128000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1147 unithd 5520 3130720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1148 unithd 5520 3133440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1149 unithd 5520 3136160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1150 unithd 5520 3138880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1151 unithd 5520 3141600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1152 unithd 5520 3144320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1153 unithd 5520 3147040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1154 unithd 5520 3149760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1155 unithd 5520 3152480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1156 unithd 5520 3155200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1157 unithd 5520 3157920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1158 unithd 5520 3160640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1159 unithd 5520 3163360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1160 unithd 5520 3166080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1161 unithd 5520 3168800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1162 unithd 5520 3171520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1163 unithd 5520 3174240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1164 unithd 5520 3176960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1165 unithd 5520 3179680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1166 unithd 5520 3182400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1167 unithd 5520 3185120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1168 unithd 5520 3187840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1169 unithd 5520 3190560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1170 unithd 5520 3193280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1171 unithd 5520 3196000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1172 unithd 5520 3198720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1173 unithd 5520 3201440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1174 unithd 5520 3204160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1175 unithd 5520 3206880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1176 unithd 5520 3209600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1177 unithd 5520 3212320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1178 unithd 5520 3215040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1179 unithd 5520 3217760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1180 unithd 5520 3220480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1181 unithd 5520 3223200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1182 unithd 5520 3225920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1183 unithd 5520 3228640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1184 unithd 5520 3231360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1185 unithd 5520 3234080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1186 unithd 5520 3236800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1187 unithd 5520 3239520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1188 unithd 5520 3242240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1189 unithd 5520 3244960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1190 unithd 5520 3247680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1191 unithd 5520 3250400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1192 unithd 5520 3253120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1193 unithd 5520 3255840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1194 unithd 5520 3258560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1195 unithd 5520 3261280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1196 unithd 5520 3264000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1197 unithd 5520 3266720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1198 unithd 5520 3269440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1199 unithd 5520 3272160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1200 unithd 5520 3274880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1201 unithd 5520 3277600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1202 unithd 5520 3280320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1203 unithd 5520 3283040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1204 unithd 5520 3285760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1205 unithd 5520 3288480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1206 unithd 5520 3291200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1207 unithd 5520 3293920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1208 unithd 5520 3296640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1209 unithd 5520 3299360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1210 unithd 5520 3302080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1211 unithd 5520 3304800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1212 unithd 5520 3307520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1213 unithd 5520 3310240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1214 unithd 5520 3312960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1215 unithd 5520 3315680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1216 unithd 5520 3318400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1217 unithd 5520 3321120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1218 unithd 5520 3323840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1219 unithd 5520 3326560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1220 unithd 5520 3329280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1221 unithd 5520 3332000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1222 unithd 5520 3334720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1223 unithd 5520 3337440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1224 unithd 5520 3340160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1225 unithd 5520 3342880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1226 unithd 5520 3345600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1227 unithd 5520 3348320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1228 unithd 5520 3351040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1229 unithd 5520 3353760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1230 unithd 5520 3356480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1231 unithd 5520 3359200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1232 unithd 5520 3361920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1233 unithd 5520 3364640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1234 unithd 5520 3367360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1235 unithd 5520 3370080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1236 unithd 5520 3372800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1237 unithd 5520 3375520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1238 unithd 5520 3378240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1239 unithd 5520 3380960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1240 unithd 5520 3383680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1241 unithd 5520 3386400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1242 unithd 5520 3389120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1243 unithd 5520 3391840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1244 unithd 5520 3394560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1245 unithd 5520 3397280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1246 unithd 5520 3400000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1247 unithd 5520 3402720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1248 unithd 5520 3405440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1249 unithd 5520 3408160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1250 unithd 5520 3410880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1251 unithd 5520 3413600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1252 unithd 5520 3416320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1253 unithd 5520 3419040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1254 unithd 5520 3421760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1255 unithd 5520 3424480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1256 unithd 5520 3427200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1257 unithd 5520 3429920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1258 unithd 5520 3432640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1259 unithd 5520 3435360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1260 unithd 5520 3438080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1261 unithd 5520 3440800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1262 unithd 5520 3443520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1263 unithd 5520 3446240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1264 unithd 5520 3448960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1265 unithd 5520 3451680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1266 unithd 5520 3454400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1267 unithd 5520 3457120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1268 unithd 5520 3459840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1269 unithd 5520 3462560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1270 unithd 5520 3465280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1271 unithd 5520 3468000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1272 unithd 5520 3470720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1273 unithd 5520 3473440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1274 unithd 5520 3476160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1275 unithd 5520 3478880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1276 unithd 5520 3481600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1277 unithd 5520 3484320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1278 unithd 5520 3487040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1279 unithd 5520 3489760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1280 unithd 5520 3492480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1281 unithd 5520 3495200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1282 unithd 5520 3497920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1283 unithd 5520 3500640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1284 unithd 5520 3503360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1285 unithd 5520 3506080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1286 unithd 5520 3508800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1287 unithd 5520 3511520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1288 unithd 5520 3514240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1289 unithd 5520 3516960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1290 unithd 5520 3519680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1291 unithd 5520 3522400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1292 unithd 5520 3525120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1293 unithd 5520 3527840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1294 unithd 5520 3530560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1295 unithd 5520 3533280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1296 unithd 5520 3536000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1297 unithd 5520 3538720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1298 unithd 5520 3541440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1299 unithd 5520 3544160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1300 unithd 5520 3546880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1301 unithd 5520 3549600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1302 unithd 5520 3552320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1303 unithd 5520 3555040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1304 unithd 5520 3557760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1305 unithd 5520 3560480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1306 unithd 5520 3563200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1307 unithd 5520 3565920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1308 unithd 5520 3568640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1309 unithd 5520 3571360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1310 unithd 5520 3574080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1311 unithd 5520 3576800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1312 unithd 5520 3579520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1313 unithd 5520 3582240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1314 unithd 5520 3584960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1315 unithd 5520 3587680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1316 unithd 5520 3590400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1317 unithd 5520 3593120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1318 unithd 5520 3595840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1319 unithd 5520 3598560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1320 unithd 5520 3601280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1321 unithd 5520 3604000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1322 unithd 5520 3606720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1323 unithd 5520 3609440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1324 unithd 5520 3612160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1325 unithd 5520 3614880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1326 unithd 5520 3617600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1327 unithd 5520 3620320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1328 unithd 5520 3623040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1329 unithd 5520 3625760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1330 unithd 5520 3628480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1331 unithd 5520 3631200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1332 unithd 5520 3633920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1333 unithd 5520 3636640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1334 unithd 5520 3639360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1335 unithd 5520 3642080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1336 unithd 5520 3644800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1337 unithd 5520 3647520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1338 unithd 5520 3650240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1339 unithd 5520 3652960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1340 unithd 5520 3655680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1341 unithd 5520 3658400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1342 unithd 5520 3661120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1343 unithd 5520 3663840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1344 unithd 5520 3666560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1345 unithd 5520 3669280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1346 unithd 5520 3672000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1347 unithd 5520 3674720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1348 unithd 5520 3677440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1349 unithd 5520 3680160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1350 unithd 5520 3682880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1351 unithd 5520 3685600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1352 unithd 5520 3688320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1353 unithd 5520 3691040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1354 unithd 5520 3693760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1355 unithd 5520 3696480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1356 unithd 5520 3699200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1357 unithd 5520 3701920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1358 unithd 5520 3704640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1359 unithd 5520 3707360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1360 unithd 5520 3710080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1361 unithd 5520 3712800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1362 unithd 5520 3715520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1363 unithd 5520 3718240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1364 unithd 5520 3720960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1365 unithd 5520 3723680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1366 unithd 5520 3726400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1367 unithd 5520 3729120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1368 unithd 5520 3731840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1369 unithd 5520 3734560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1370 unithd 5520 3737280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1371 unithd 5520 3740000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1372 unithd 5520 3742720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1373 unithd 5520 3745440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1374 unithd 5520 3748160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1375 unithd 5520 3750880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1376 unithd 5520 3753600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1377 unithd 5520 3756320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1378 unithd 5520 3759040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1379 unithd 5520 3761760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1380 unithd 5520 3764480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1381 unithd 5520 3767200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1382 unithd 5520 3769920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1383 unithd 5520 3772640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1384 unithd 5520 3775360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1385 unithd 5520 3778080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1386 unithd 5520 3780800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1387 unithd 5520 3783520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1388 unithd 5520 3786240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1389 unithd 5520 3788960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1390 unithd 5520 3791680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1391 unithd 5520 3794400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1392 unithd 5520 3797120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1393 unithd 5520 3799840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1394 unithd 5520 3802560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1395 unithd 5520 3805280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1396 unithd 5520 3808000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1397 unithd 5520 3810720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1398 unithd 5520 3813440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1399 unithd 5520 3816160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1400 unithd 5520 3818880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1401 unithd 5520 3821600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1402 unithd 5520 3824320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1403 unithd 5520 3827040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1404 unithd 5520 3829760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1405 unithd 5520 3832480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1406 unithd 5520 3835200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1407 unithd 5520 3837920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1408 unithd 5520 3840640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1409 unithd 5520 3843360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1410 unithd 5520 3846080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1411 unithd 5520 3848800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1412 unithd 5520 3851520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1413 unithd 5520 3854240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1414 unithd 5520 3856960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1415 unithd 5520 3859680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1416 unithd 5520 3862400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1417 unithd 5520 3865120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1418 unithd 5520 3867840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1419 unithd 5520 3870560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1420 unithd 5520 3873280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1421 unithd 5520 3876000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1422 unithd 5520 3878720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1423 unithd 5520 3881440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1424 unithd 5520 3884160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1425 unithd 5520 3886880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1426 unithd 5520 3889600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1427 unithd 5520 3892320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1428 unithd 5520 3895040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1429 unithd 5520 3897760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1430 unithd 5520 3900480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1431 unithd 5520 3903200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1432 unithd 5520 3905920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1433 unithd 5520 3908640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1434 unithd 5520 3911360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1435 unithd 5520 3914080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1436 unithd 5520 3916800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1437 unithd 5520 3919520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1438 unithd 5520 3922240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1439 unithd 5520 3924960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1440 unithd 5520 3927680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1441 unithd 5520 3930400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1442 unithd 5520 3933120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1443 unithd 5520 3935840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1444 unithd 5520 3938560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1445 unithd 5520 3941280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1446 unithd 5520 3944000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1447 unithd 5520 3946720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1448 unithd 5520 3949440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1449 unithd 5520 3952160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1450 unithd 5520 3954880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1451 unithd 5520 3957600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1452 unithd 5520 3960320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1453 unithd 5520 3963040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1454 unithd 5520 3965760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1455 unithd 5520 3968480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1456 unithd 5520 3971200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1457 unithd 5520 3973920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1458 unithd 5520 3976640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1459 unithd 5520 3979360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1460 unithd 5520 3982080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1461 unithd 5520 3984800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1462 unithd 5520 3987520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1463 unithd 5520 3990240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1464 unithd 5520 3992960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1465 unithd 5520 3995680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1466 unithd 5520 3998400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1467 unithd 5520 4001120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1468 unithd 5520 4003840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1469 unithd 5520 4006560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1470 unithd 5520 4009280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1471 unithd 5520 4012000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1472 unithd 5520 4014720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1473 unithd 5520 4017440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1474 unithd 5520 4020160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1475 unithd 5520 4022880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1476 unithd 5520 4025600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1477 unithd 5520 4028320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1478 unithd 5520 4031040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1479 unithd 5520 4033760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1480 unithd 5520 4036480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1481 unithd 5520 4039200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1482 unithd 5520 4041920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1483 unithd 5520 4044640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1484 unithd 5520 4047360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1485 unithd 5520 4050080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1486 unithd 5520 4052800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1487 unithd 5520 4055520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1488 unithd 5520 4058240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1489 unithd 5520 4060960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1490 unithd 5520 4063680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1491 unithd 5520 4066400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1492 unithd 5520 4069120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1493 unithd 5520 4071840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1494 unithd 5520 4074560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1495 unithd 5520 4077280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1496 unithd 5520 4080000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1497 unithd 5520 4082720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1498 unithd 5520 4085440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1499 unithd 5520 4088160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1500 unithd 5520 4090880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1501 unithd 5520 4093600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1502 unithd 5520 4096320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1503 unithd 5520 4099040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1504 unithd 5520 4101760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1505 unithd 5520 4104480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1506 unithd 5520 4107200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1507 unithd 5520 4109920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1508 unithd 5520 4112640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1509 unithd 5520 4115360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1510 unithd 5520 4118080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1511 unithd 5520 4120800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1512 unithd 5520 4123520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1513 unithd 5520 4126240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1514 unithd 5520 4128960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1515 unithd 5520 4131680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1516 unithd 5520 4134400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1517 unithd 5520 4137120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1518 unithd 5520 4139840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1519 unithd 5520 4142560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1520 unithd 5520 4145280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1521 unithd 5520 4148000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1522 unithd 5520 4150720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1523 unithd 5520 4153440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1524 unithd 5520 4156160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1525 unithd 5520 4158880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1526 unithd 5520 4161600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1527 unithd 5520 4164320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1528 unithd 5520 4167040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1529 unithd 5520 4169760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1530 unithd 5520 4172480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1531 unithd 5520 4175200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1532 unithd 5520 4177920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1533 unithd 5520 4180640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1534 unithd 5520 4183360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1535 unithd 5520 4186080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1536 unithd 5520 4188800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1537 unithd 5520 4191520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1538 unithd 5520 4194240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1539 unithd 5520 4196960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1540 unithd 5520 4199680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1541 unithd 5520 4202400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1542 unithd 5520 4205120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1543 unithd 5520 4207840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1544 unithd 5520 4210560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1545 unithd 5520 4213280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1546 unithd 5520 4216000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1547 unithd 5520 4218720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1548 unithd 5520 4221440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1549 unithd 5520 4224160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1550 unithd 5520 4226880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1551 unithd 5520 4229600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1552 unithd 5520 4232320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1553 unithd 5520 4235040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1554 unithd 5520 4237760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1555 unithd 5520 4240480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1556 unithd 5520 4243200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1557 unithd 5520 4245920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1558 unithd 5520 4248640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1559 unithd 5520 4251360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1560 unithd 5520 4254080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1561 unithd 5520 4256800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1562 unithd 5520 4259520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1563 unithd 5520 4262240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1564 unithd 5520 4264960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1565 unithd 5520 4267680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1566 unithd 5520 4270400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1567 unithd 5520 4273120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1568 unithd 5520 4275840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1569 unithd 5520 4278560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1570 unithd 5520 4281280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1571 unithd 5520 4284000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1572 unithd 5520 4286720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1573 unithd 5520 4289440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1574 unithd 5520 4292160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1575 unithd 5520 4294880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1576 unithd 5520 4297600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1577 unithd 5520 4300320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1578 unithd 5520 4303040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1579 unithd 5520 4305760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1580 unithd 5520 4308480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1581 unithd 5520 4311200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1582 unithd 5520 4313920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1583 unithd 5520 4316640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1584 unithd 5520 4319360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1585 unithd 5520 4322080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1586 unithd 5520 4324800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1587 unithd 5520 4327520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1588 unithd 5520 4330240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1589 unithd 5520 4332960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1590 unithd 5520 4335680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1591 unithd 5520 4338400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1592 unithd 5520 4341120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1593 unithd 5520 4343840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1594 unithd 5520 4346560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1595 unithd 5520 4349280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1596 unithd 5520 4352000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1597 unithd 5520 4354720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1598 unithd 5520 4357440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1599 unithd 5520 4360160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1600 unithd 5520 4362880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1601 unithd 5520 4365600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1602 unithd 5520 4368320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1603 unithd 5520 4371040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1604 unithd 5520 4373760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1605 unithd 5520 4376480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1606 unithd 5520 4379200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1607 unithd 5520 4381920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1608 unithd 5520 4384640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1609 unithd 5520 4387360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1610 unithd 5520 4390080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1611 unithd 5520 4392800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1612 unithd 5520 4395520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1613 unithd 5520 4398240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1614 unithd 5520 4400960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1615 unithd 5520 4403680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1616 unithd 5520 4406400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1617 unithd 5520 4409120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1618 unithd 5520 4411840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1619 unithd 5520 4414560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1620 unithd 5520 4417280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1621 unithd 5520 4420000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1622 unithd 5520 4422720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1623 unithd 5520 4425440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1624 unithd 5520 4428160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1625 unithd 5520 4430880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1626 unithd 5520 4433600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1627 unithd 5520 4436320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1628 unithd 5520 4439040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1629 unithd 5520 4441760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1630 unithd 5520 4444480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1631 unithd 5520 4447200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1632 unithd 5520 4449920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1633 unithd 5520 4452640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1634 unithd 5520 4455360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1635 unithd 5520 4458080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1636 unithd 5520 4460800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1637 unithd 5520 4463520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1638 unithd 5520 4466240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1639 unithd 5520 4468960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1640 unithd 5520 4471680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1641 unithd 5520 4474400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1642 unithd 5520 4477120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1643 unithd 5520 4479840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1644 unithd 5520 4482560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1645 unithd 5520 4485280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1646 unithd 5520 4488000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1647 unithd 5520 4490720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1648 unithd 5520 4493440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1649 unithd 5520 4496160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1650 unithd 5520 4498880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1651 unithd 5520 4501600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1652 unithd 5520 4504320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1653 unithd 5520 4507040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1654 unithd 5520 4509760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1655 unithd 5520 4512480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1656 unithd 5520 4515200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1657 unithd 5520 4517920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1658 unithd 5520 4520640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1659 unithd 5520 4523360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1660 unithd 5520 4526080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1661 unithd 5520 4528800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1662 unithd 5520 4531520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1663 unithd 5520 4534240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1664 unithd 5520 4536960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1665 unithd 5520 4539680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1666 unithd 5520 4542400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1667 unithd 5520 4545120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1668 unithd 5520 4547840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1669 unithd 5520 4550560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1670 unithd 5520 4553280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1671 unithd 5520 4556000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1672 unithd 5520 4558720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1673 unithd 5520 4561440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1674 unithd 5520 4564160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1675 unithd 5520 4566880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1676 unithd 5520 4569600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1677 unithd 5520 4572320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1678 unithd 5520 4575040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1679 unithd 5520 4577760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1680 unithd 5520 4580480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1681 unithd 5520 4583200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1682 unithd 5520 4585920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1683 unithd 5520 4588640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1684 unithd 5520 4591360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1685 unithd 5520 4594080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1686 unithd 5520 4596800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1687 unithd 5520 4599520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1688 unithd 5520 4602240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1689 unithd 5520 4604960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1690 unithd 5520 4607680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1691 unithd 5520 4610400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1692 unithd 5520 4613120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1693 unithd 5520 4615840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1694 unithd 5520 4618560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1695 unithd 5520 4621280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1696 unithd 5520 4624000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1697 unithd 5520 4626720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1698 unithd 5520 4629440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1699 unithd 5520 4632160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1700 unithd 5520 4634880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1701 unithd 5520 4637600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1702 unithd 5520 4640320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1703 unithd 5520 4643040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1704 unithd 5520 4645760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1705 unithd 5520 4648480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1706 unithd 5520 4651200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1707 unithd 5520 4653920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1708 unithd 5520 4656640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1709 unithd 5520 4659360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1710 unithd 5520 4662080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1711 unithd 5520 4664800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1712 unithd 5520 4667520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1713 unithd 5520 4670240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1714 unithd 5520 4672960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1715 unithd 5520 4675680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1716 unithd 5520 4678400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1717 unithd 5520 4681120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1718 unithd 5520 4683840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1719 unithd 5520 4686560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1720 unithd 5520 4689280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1721 unithd 5520 4692000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1722 unithd 5520 4694720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1723 unithd 5520 4697440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1724 unithd 5520 4700160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1725 unithd 5520 4702880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1726 unithd 5520 4705600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1727 unithd 5520 4708320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1728 unithd 5520 4711040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1729 unithd 5520 4713760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1730 unithd 5520 4716480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1731 unithd 5520 4719200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1732 unithd 5520 4721920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1733 unithd 5520 4724640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1734 unithd 5520 4727360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1735 unithd 5520 4730080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1736 unithd 5520 4732800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1737 unithd 5520 4735520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1738 unithd 5520 4738240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1739 unithd 5520 4740960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1740 unithd 5520 4743680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1741 unithd 5520 4746400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1742 unithd 5520 4749120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1743 unithd 5520 4751840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1744 unithd 5520 4754560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1745 unithd 5520 4757280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1746 unithd 5520 4760000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1747 unithd 5520 4762720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1748 unithd 5520 4765440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1749 unithd 5520 4768160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1750 unithd 5520 4770880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1751 unithd 5520 4773600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1752 unithd 5520 4776320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1753 unithd 5520 4779040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1754 unithd 5520 4781760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1755 unithd 5520 4784480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1756 unithd 5520 4787200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1757 unithd 5520 4789920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1758 unithd 5520 4792640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1759 unithd 5520 4795360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1760 unithd 5520 4798080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1761 unithd 5520 4800800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1762 unithd 5520 4803520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1763 unithd 5520 4806240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1764 unithd 5520 4808960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1765 unithd 5520 4811680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1766 unithd 5520 4814400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1767 unithd 5520 4817120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1768 unithd 5520 4819840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1769 unithd 5520 4822560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1770 unithd 5520 4825280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1771 unithd 5520 4828000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1772 unithd 5520 4830720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1773 unithd 5520 4833440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1774 unithd 5520 4836160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1775 unithd 5520 4838880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1776 unithd 5520 4841600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1777 unithd 5520 4844320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1778 unithd 5520 4847040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1779 unithd 5520 4849760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1780 unithd 5520 4852480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1781 unithd 5520 4855200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1782 unithd 5520 4857920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1783 unithd 5520 4860640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1784 unithd 5520 4863360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1785 unithd 5520 4866080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1786 unithd 5520 4868800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1787 unithd 5520 4871520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1788 unithd 5520 4874240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1789 unithd 5520 4876960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1790 unithd 5520 4879680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1791 unithd 5520 4882400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1792 unithd 5520 4885120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1793 unithd 5520 4887840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1794 unithd 5520 4890560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1795 unithd 5520 4893280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1796 unithd 5520 4896000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1797 unithd 5520 4898720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1798 unithd 5520 4901440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1799 unithd 5520 4904160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1800 unithd 5520 4906880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1801 unithd 5520 4909600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1802 unithd 5520 4912320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1803 unithd 5520 4915040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1804 unithd 5520 4917760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1805 unithd 5520 4920480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1806 unithd 5520 4923200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1807 unithd 5520 4925920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1808 unithd 5520 4928640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1809 unithd 5520 4931360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1810 unithd 5520 4934080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1811 unithd 5520 4936800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1812 unithd 5520 4939520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1813 unithd 5520 4942240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1814 unithd 5520 4944960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1815 unithd 5520 4947680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1816 unithd 5520 4950400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1817 unithd 5520 4953120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1818 unithd 5520 4955840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1819 unithd 5520 4958560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1820 unithd 5520 4961280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1821 unithd 5520 4964000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1822 unithd 5520 4966720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1823 unithd 5520 4969440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1824 unithd 5520 4972160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1825 unithd 5520 4974880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1826 unithd 5520 4977600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1827 unithd 5520 4980320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1828 unithd 5520 4983040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1829 unithd 5520 4985760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1830 unithd 5520 4988480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1831 unithd 5520 4991200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1832 unithd 5520 4993920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1833 unithd 5520 4996640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1834 unithd 5520 4999360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1835 unithd 5520 5002080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1836 unithd 5520 5004800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1837 unithd 5520 5007520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1838 unithd 5520 5010240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1839 unithd 5520 5012960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1840 unithd 5520 5015680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1841 unithd 5520 5018400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1842 unithd 5520 5021120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1843 unithd 5520 5023840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1844 unithd 5520 5026560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1845 unithd 5520 5029280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1846 unithd 5520 5032000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1847 unithd 5520 5034720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1848 unithd 5520 5037440 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1849 unithd 5520 5040160 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1850 unithd 5520 5042880 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1851 unithd 5520 5045600 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1852 unithd 5520 5048320 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1853 unithd 5520 5051040 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1854 unithd 5520 5053760 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1855 unithd 5520 5056480 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1856 unithd 5520 5059200 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1857 unithd 5520 5061920 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1858 unithd 5520 5064640 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1859 unithd 5520 5067360 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1860 unithd 5520 5070080 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1861 unithd 5520 5072800 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1862 unithd 5520 5075520 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1863 unithd 5520 5078240 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1864 unithd 5520 5080960 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1865 unithd 5520 5083680 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1866 unithd 5520 5086400 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1867 unithd 5520 5089120 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1868 unithd 5520 5091840 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1869 unithd 5520 5094560 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1870 unithd 5520 5097280 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1871 unithd 5520 5100000 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1872 unithd 5520 5102720 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1873 unithd 5520 5105440 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1874 unithd 5520 5108160 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1875 unithd 5520 5110880 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1876 unithd 5520 5113600 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1877 unithd 5520 5116320 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1878 unithd 5520 5119040 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1879 unithd 5520 5121760 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1880 unithd 5520 5124480 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1881 unithd 5520 5127200 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1882 unithd 5520 5129920 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1883 unithd 5520 5132640 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1884 unithd 5520 5135360 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1885 unithd 5520 5138080 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1886 unithd 5520 5140800 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1887 unithd 5520 5143520 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1888 unithd 5520 5146240 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1889 unithd 5520 5148960 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1890 unithd 5520 5151680 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1891 unithd 5520 5154400 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1892 unithd 5520 5157120 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1893 unithd 5520 5159840 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1894 unithd 5520 5162560 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1895 unithd 5520 5165280 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1896 unithd 5520 5168000 N DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1897 unithd 5520 5170720 FS DO 7776 BY 1 STEP 460 0 ;
ROW ROW_1898 unithd 5520 5173440 N DO 7776 BY 1 STEP 460 0 ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
TRACKS X 230 DO 7800 STEP 460 LAYER li1 ;
TRACKS Y 170 DO 15259 STEP 340 LAYER li1 ;
TRACKS X 170 DO 10553 STEP 340 LAYER met1 ;
TRACKS Y 170 DO 15259 STEP 340 LAYER met1 ;
TRACKS X 230 DO 7800 STEP 460 LAYER met2 ;
TRACKS Y 230 DO 11278 STEP 460 LAYER met2 ;
TRACKS X 340 DO 5276 STEP 680 LAYER met3 ;
TRACKS Y 340 DO 7629 STEP 680 LAYER met3 ;
TRACKS X 460 DO 3900 STEP 920 LAYER met4 ;
TRACKS Y 460 DO 5639 STEP 920 LAYER met4 ;
TRACKS X 1700 DO 1055 STEP 3400 LAYER met5 ;
TRACKS Y 1700 DO 1526 STEP 3400 LAYER met5 ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
COMPONENTS 7 ;
- caravel_logo caravel_logo + PLACED ( 1080000 25500 ) N ;
- caravel_motto caravel_motto + PLACED ( 1350000 -35000 ) N ;
- chip_core caravan_core + PLACED ( 211500 210500 ) N ;
- copyright_block copyright_block + PLACED ( 482000 85000 ) N ;
- open_source open_source + PLACED ( 768000 15000 ) N ;
- padframe chip_io_alt + PLACED ( 0 0 ) N ;
- user_id_textblock user_id_textblock + PLACED ( 175000 35000 ) N ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
END COMPONENTS
PINS 63 ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- clock + NET clock + DIRECTION INPUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31300 -31225 ) ( 31300 31225 )
+ PLACED ( 969500 64215 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_clk + NET flash_clk + DIRECTION OUTPUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31300 -31225 ) ( 31300 31225 )
+ PLACED ( 1786500 64215 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_csb + NET flash_csb + DIRECTION OUTPUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31300 -31225 ) ( 31300 31225 )
+ PLACED ( 1512500 64215 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_io0 + NET flash_io0 + DIRECTION OUTPUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31300 -31225 ) ( 31300 31225 )
+ PLACED ( 2060500 64215 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_io1 + NET flash_io1 + DIRECTION OUTPUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31300 -31225 ) ( 31300 31225 )
+ PLACED ( 2334500 64215 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- gpio + NET gpio + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31300 -31225 ) ( 31300 31225 )
+ PLACED ( 2608500 64215 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[0] + NET mprj_io[0] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 537500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[10] + NET mprj_io[10] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 3453500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[11] + NET mprj_io[11] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 3678500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[12] + NET mprj_io[12] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 3903500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[13] + NET mprj_io[13] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 4349500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[14] + NET mprj_io[14] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 3523532 4795530 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[15] + NET mprj_io[15] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 3172470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[16] + NET mprj_io[16] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 2663470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[17] + NET mprj_io[17] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 2406470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[18] + NET mprj_io[18] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 1961470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[19] + NET mprj_io[19] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 1452470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[1] + NET mprj_io[1] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 763500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[20] + NET mprj_io[20] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 1189470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[21] + NET mprj_io[21] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 937470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[22] + NET mprj_io[22] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 680470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[23] + NET mprj_io[23] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 423470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[24] + NET mprj_io[24] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 64467 4813470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[25] + NET mprj_io[25] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 3964500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[26] + NET mprj_io[26] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 3748500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[27] + NET mprj_io[27] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 3532500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[28] + NET mprj_io[28] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 3316500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[29] + NET mprj_io[29] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 3100500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[2] + NET mprj_io[2] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 988500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[30] + NET mprj_io[30] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 2884500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[31] + NET mprj_io[31] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 2668500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[32] + NET mprj_io[32] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 2030500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[33] + NET mprj_io[33] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 1814500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[34] + NET mprj_io[34] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 1598500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[35] + NET mprj_io[35] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 1382500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[36] + NET mprj_io[36] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 1166500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[37] + NET mprj_io[37] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 64215 950500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[3] + NET mprj_io[3] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 1214500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[4] + NET mprj_io[4] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 1439500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[5] + NET mprj_io[5] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 1664500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[6] + NET mprj_io[6] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 1890500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[7] + NET mprj_io[7] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 2776500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[8] + NET mprj_io[8] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 3002500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[9] + NET mprj_io[9] + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -31225 -31300 ) ( 31225 31300 )
+ PLACED ( 3523785 3227500 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- resetb + NET resetb + DIRECTION INPUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -18592 -27915 ) ( 18593 27915 )
+ PLACED ( 702157 63630 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vccd + NET vccd + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -33632 -27200 ) ( 33633 27200 )
+ PLACED ( 64467 377470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vccd1 + NET vccd1 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -33632 -27200 ) ( 33633 27200 )
+ PLACED ( 3523532 4575530 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vccd2 + NET vccd2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -33632 -27200 ) ( 33633 27200 )
+ PLACED ( 64467 4597470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vdda + NET vdda + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 3151530 64467 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vdda1 + NET vdda1 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 3523532 4129530 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vdda1_2 + NET vdda1_2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 3523532 2556530 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vdda2 + NET vdda2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 64467 2452470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vddio + NET vddio + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 64467 588470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vddio_2 + NET vddio_2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 64467 4386470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssa + NET vssa + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 431530 64467 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssa1 + NET vssa1 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 2915470 5123532 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssa1_2 + NET vssa1_2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 3523532 2115530 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssa2 + NET vssa2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30412 -30420 ) ( 30413 30420 )
+ PLACED ( 64467 4175470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssd + NET vssd + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -27200 -33632 ) ( 27200 33633 )
+ PLACED ( 1243530 64467 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssd1 + NET vssd1 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -33632 -27200 ) ( 33633 27200 )
+ PLACED ( 3523532 2336530 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssd2 + NET vssd2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -33632 -27200 ) ( 33633 27200 )
+ PLACED ( 64467 2241470 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssio + NET vssio + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 2882530 64467 ) N ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssio_2 + NET vssio_2 + DIRECTION INOUT + USE SIGNAL
+ PORT
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
+ LAYER met5 ( -30420 -30412 ) ( 30420 30413 )
+ PLACED ( 1704470 5123532 ) N ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
END PINS
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
NETS 584 ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- clock ( PIN clock ) ( padframe clock ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- clock_core ( padframe clock_core ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_clk ( PIN flash_clk ) ( padframe flash_clk ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- flash_clk_frame ( padframe flash_clk_core ) + USE SIGNAL ;
- flash_clk_oeb ( padframe flash_clk_oeb_core ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_csb ( PIN flash_csb ) ( padframe flash_csb ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- flash_csb_frame ( padframe flash_csb_core ) + USE SIGNAL ;
- flash_csb_oeb ( padframe flash_csb_oeb_core ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_io0 ( PIN flash_io0 ) ( padframe flash_io0 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- flash_io0_di ( padframe flash_io0_di_core ) + USE SIGNAL ;
- flash_io0_do ( padframe flash_io0_do_core ) + USE SIGNAL ;
- flash_io0_ieb ( padframe flash_io0_ieb_core ) + USE SIGNAL ;
- flash_io0_oeb ( padframe flash_io0_oeb_core ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- flash_io1 ( PIN flash_io1 ) ( padframe flash_io1 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- flash_io1_di ( padframe flash_io1_di_core ) + USE SIGNAL ;
- flash_io1_do ( padframe flash_io1_do_core ) + USE SIGNAL ;
- flash_io1_ieb ( padframe flash_io1_ieb_core ) + USE SIGNAL ;
- flash_io1_oeb ( padframe flash_io1_oeb_core ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- gpio ( PIN gpio ) ( padframe gpio ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- gpio_in_core ( padframe gpio_in_core ) + USE SIGNAL ;
- gpio_inenb_core ( padframe gpio_inenb_core ) + USE SIGNAL ;
- gpio_mode0_core ( padframe gpio_mode0_core ) + USE SIGNAL ;
- gpio_mode1_core ( padframe gpio_mode1_core ) + USE SIGNAL ;
- gpio_out_core ( padframe gpio_out_core ) + USE SIGNAL ;
- gpio_outenb_core ( padframe gpio_outenb_core ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- mprj_io[0] ( PIN mprj_io[0] ) ( padframe mprj_io[0] ) + USE SIGNAL ;
- mprj_io[10] ( PIN mprj_io[10] ) ( padframe mprj_io[10] ) + USE SIGNAL ;
- mprj_io[11] ( PIN mprj_io[11] ) ( padframe mprj_io[11] ) + USE SIGNAL ;
- mprj_io[12] ( PIN mprj_io[12] ) ( padframe mprj_io[12] ) + USE SIGNAL ;
- mprj_io[13] ( PIN mprj_io[13] ) ( padframe mprj_io[13] ) + USE SIGNAL ;
- mprj_io[14] ( PIN mprj_io[14] ) ( padframe mprj_io[14] ) + USE SIGNAL ;
- mprj_io[15] ( PIN mprj_io[15] ) ( padframe mprj_io[15] ) + USE SIGNAL ;
- mprj_io[16] ( PIN mprj_io[16] ) ( padframe mprj_io[16] ) + USE SIGNAL ;
- mprj_io[17] ( PIN mprj_io[17] ) ( padframe mprj_io[17] ) + USE SIGNAL ;
- mprj_io[18] ( PIN mprj_io[18] ) ( padframe mprj_io[18] ) + USE SIGNAL ;
- mprj_io[19] ( PIN mprj_io[19] ) ( padframe mprj_io[19] ) + USE SIGNAL ;
- mprj_io[1] ( PIN mprj_io[1] ) ( padframe mprj_io[1] ) + USE SIGNAL ;
- mprj_io[20] ( PIN mprj_io[20] ) ( padframe mprj_io[20] ) + USE SIGNAL ;
- mprj_io[21] ( PIN mprj_io[21] ) ( padframe mprj_io[21] ) + USE SIGNAL ;
- mprj_io[22] ( PIN mprj_io[22] ) ( padframe mprj_io[22] ) + USE SIGNAL ;
- mprj_io[23] ( PIN mprj_io[23] ) ( padframe mprj_io[23] ) + USE SIGNAL ;
- mprj_io[24] ( PIN mprj_io[24] ) ( padframe mprj_io[24] ) + USE SIGNAL ;
- mprj_io[25] ( PIN mprj_io[25] ) ( padframe mprj_io[25] ) + USE SIGNAL ;
- mprj_io[26] ( PIN mprj_io[26] ) ( padframe mprj_io[26] ) + USE SIGNAL ;
- mprj_io[27] ( PIN mprj_io[27] ) ( padframe mprj_io[27] ) + USE SIGNAL ;
- mprj_io[28] ( PIN mprj_io[28] ) ( padframe mprj_io[28] ) + USE SIGNAL ;
- mprj_io[29] ( PIN mprj_io[29] ) ( padframe mprj_io[29] ) + USE SIGNAL ;
- mprj_io[2] ( PIN mprj_io[2] ) ( padframe mprj_io[2] ) + USE SIGNAL ;
- mprj_io[30] ( PIN mprj_io[30] ) ( padframe mprj_io[30] ) + USE SIGNAL ;
- mprj_io[31] ( PIN mprj_io[31] ) ( padframe mprj_io[31] ) + USE SIGNAL ;
- mprj_io[32] ( PIN mprj_io[32] ) ( padframe mprj_io[32] ) + USE SIGNAL ;
- mprj_io[33] ( PIN mprj_io[33] ) ( padframe mprj_io[33] ) + USE SIGNAL ;
- mprj_io[34] ( PIN mprj_io[34] ) ( padframe mprj_io[34] ) + USE SIGNAL ;
- mprj_io[35] ( PIN mprj_io[35] ) ( padframe mprj_io[35] ) + USE SIGNAL ;
- mprj_io[36] ( PIN mprj_io[36] ) ( padframe mprj_io[36] ) + USE SIGNAL ;
- mprj_io[37] ( PIN mprj_io[37] ) ( padframe mprj_io[37] ) + USE SIGNAL ;
- mprj_io[3] ( PIN mprj_io[3] ) ( padframe mprj_io[3] ) + USE SIGNAL ;
- mprj_io[4] ( PIN mprj_io[4] ) ( padframe mprj_io[4] ) + USE SIGNAL ;
- mprj_io[5] ( PIN mprj_io[5] ) ( padframe mprj_io[5] ) + USE SIGNAL ;
- mprj_io[6] ( PIN mprj_io[6] ) ( padframe mprj_io[6] ) + USE SIGNAL ;
- mprj_io[7] ( PIN mprj_io[7] ) ( padframe mprj_io[7] ) + USE SIGNAL ;
- mprj_io[8] ( PIN mprj_io[8] ) ( padframe mprj_io[8] ) + USE SIGNAL ;
- mprj_io[9] ( PIN mprj_io[9] ) ( padframe mprj_io[9] ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- mprj_io_analog_en\[0\] ( padframe mprj_io_analog_en[0] ) + USE SIGNAL ;
- mprj_io_analog_en\[10\] ( padframe mprj_io_analog_en[10] ) + USE SIGNAL ;
- mprj_io_analog_en\[11\] ( padframe mprj_io_analog_en[11] ) + USE SIGNAL ;
- mprj_io_analog_en\[12\] ( padframe mprj_io_analog_en[12] ) + USE SIGNAL ;
- mprj_io_analog_en\[13\] ( padframe mprj_io_analog_en[13] ) + USE SIGNAL ;
- mprj_io_analog_en\[14\] ( padframe mprj_io_analog_en[14] ) + USE SIGNAL ;
- mprj_io_analog_en\[15\] ( padframe mprj_io_analog_en[15] ) + USE SIGNAL ;
- mprj_io_analog_en\[16\] ( padframe mprj_io_analog_en[16] ) + USE SIGNAL ;
- mprj_io_analog_en\[17\] ( padframe mprj_io_analog_en[17] ) + USE SIGNAL ;
- mprj_io_analog_en\[18\] ( padframe mprj_io_analog_en[18] ) + USE SIGNAL ;
- mprj_io_analog_en\[19\] ( padframe mprj_io_analog_en[19] ) + USE SIGNAL ;
- mprj_io_analog_en\[1\] ( padframe mprj_io_analog_en[1] ) + USE SIGNAL ;
- mprj_io_analog_en\[20\] ( padframe mprj_io_analog_en[20] ) + USE SIGNAL ;
- mprj_io_analog_en\[21\] ( padframe mprj_io_analog_en[21] ) + USE SIGNAL ;
- mprj_io_analog_en\[22\] ( padframe mprj_io_analog_en[22] ) + USE SIGNAL ;
- mprj_io_analog_en\[23\] ( padframe mprj_io_analog_en[23] ) + USE SIGNAL ;
- mprj_io_analog_en\[24\] ( padframe mprj_io_analog_en[24] ) + USE SIGNAL ;
- mprj_io_analog_en\[25\] ( padframe mprj_io_analog_en[25] ) + USE SIGNAL ;
- mprj_io_analog_en\[26\] ( padframe mprj_io_analog_en[26] ) + USE SIGNAL ;
- mprj_io_analog_en\[2\] ( padframe mprj_io_analog_en[2] ) + USE SIGNAL ;
- mprj_io_analog_en\[3\] ( padframe mprj_io_analog_en[3] ) + USE SIGNAL ;
- mprj_io_analog_en\[4\] ( padframe mprj_io_analog_en[4] ) + USE SIGNAL ;
- mprj_io_analog_en\[5\] ( padframe mprj_io_analog_en[5] ) + USE SIGNAL ;
- mprj_io_analog_en\[6\] ( padframe mprj_io_analog_en[6] ) + USE SIGNAL ;
- mprj_io_analog_en\[7\] ( padframe mprj_io_analog_en[7] ) + USE SIGNAL ;
- mprj_io_analog_en\[8\] ( padframe mprj_io_analog_en[8] ) + USE SIGNAL ;
- mprj_io_analog_en\[9\] ( padframe mprj_io_analog_en[9] ) + USE SIGNAL ;
- mprj_io_analog_pol\[0\] ( padframe mprj_io_analog_pol[0] ) + USE SIGNAL ;
- mprj_io_analog_pol\[10\] ( padframe mprj_io_analog_pol[10] ) + USE SIGNAL ;
- mprj_io_analog_pol\[11\] ( padframe mprj_io_analog_pol[11] ) + USE SIGNAL ;
- mprj_io_analog_pol\[12\] ( padframe mprj_io_analog_pol[12] ) + USE SIGNAL ;
- mprj_io_analog_pol\[13\] ( padframe mprj_io_analog_pol[13] ) + USE SIGNAL ;
- mprj_io_analog_pol\[14\] ( padframe mprj_io_analog_pol[14] ) + USE SIGNAL ;
- mprj_io_analog_pol\[15\] ( padframe mprj_io_analog_pol[15] ) + USE SIGNAL ;
- mprj_io_analog_pol\[16\] ( padframe mprj_io_analog_pol[16] ) + USE SIGNAL ;
- mprj_io_analog_pol\[17\] ( padframe mprj_io_analog_pol[17] ) + USE SIGNAL ;
- mprj_io_analog_pol\[18\] ( padframe mprj_io_analog_pol[18] ) + USE SIGNAL ;
- mprj_io_analog_pol\[19\] ( padframe mprj_io_analog_pol[19] ) + USE SIGNAL ;
- mprj_io_analog_pol\[1\] ( padframe mprj_io_analog_pol[1] ) + USE SIGNAL ;
- mprj_io_analog_pol\[20\] ( padframe mprj_io_analog_pol[20] ) + USE SIGNAL ;
- mprj_io_analog_pol\[21\] ( padframe mprj_io_analog_pol[21] ) + USE SIGNAL ;
- mprj_io_analog_pol\[22\] ( padframe mprj_io_analog_pol[22] ) + USE SIGNAL ;
- mprj_io_analog_pol\[23\] ( padframe mprj_io_analog_pol[23] ) + USE SIGNAL ;
- mprj_io_analog_pol\[24\] ( padframe mprj_io_analog_pol[24] ) + USE SIGNAL ;
- mprj_io_analog_pol\[25\] ( padframe mprj_io_analog_pol[25] ) + USE SIGNAL ;
- mprj_io_analog_pol\[26\] ( padframe mprj_io_analog_pol[26] ) + USE SIGNAL ;
- mprj_io_analog_pol\[2\] ( padframe mprj_io_analog_pol[2] ) + USE SIGNAL ;
- mprj_io_analog_pol\[3\] ( padframe mprj_io_analog_pol[3] ) + USE SIGNAL ;
- mprj_io_analog_pol\[4\] ( padframe mprj_io_analog_pol[4] ) + USE SIGNAL ;
- mprj_io_analog_pol\[5\] ( padframe mprj_io_analog_pol[5] ) + USE SIGNAL ;
- mprj_io_analog_pol\[6\] ( padframe mprj_io_analog_pol[6] ) + USE SIGNAL ;
- mprj_io_analog_pol\[7\] ( padframe mprj_io_analog_pol[7] ) + USE SIGNAL ;
- mprj_io_analog_pol\[8\] ( padframe mprj_io_analog_pol[8] ) + USE SIGNAL ;
- mprj_io_analog_pol\[9\] ( padframe mprj_io_analog_pol[9] ) + USE SIGNAL ;
- mprj_io_analog_sel\[0\] ( padframe mprj_io_analog_sel[0] ) + USE SIGNAL ;
- mprj_io_analog_sel\[10\] ( padframe mprj_io_analog_sel[10] ) + USE SIGNAL ;
- mprj_io_analog_sel\[11\] ( padframe mprj_io_analog_sel[11] ) + USE SIGNAL ;
- mprj_io_analog_sel\[12\] ( padframe mprj_io_analog_sel[12] ) + USE SIGNAL ;
- mprj_io_analog_sel\[13\] ( padframe mprj_io_analog_sel[13] ) + USE SIGNAL ;
- mprj_io_analog_sel\[14\] ( padframe mprj_io_analog_sel[14] ) + USE SIGNAL ;
- mprj_io_analog_sel\[15\] ( padframe mprj_io_analog_sel[15] ) + USE SIGNAL ;
- mprj_io_analog_sel\[16\] ( padframe mprj_io_analog_sel[16] ) + USE SIGNAL ;
- mprj_io_analog_sel\[17\] ( padframe mprj_io_analog_sel[17] ) + USE SIGNAL ;
- mprj_io_analog_sel\[18\] ( padframe mprj_io_analog_sel[18] ) + USE SIGNAL ;
- mprj_io_analog_sel\[19\] ( padframe mprj_io_analog_sel[19] ) + USE SIGNAL ;
- mprj_io_analog_sel\[1\] ( padframe mprj_io_analog_sel[1] ) + USE SIGNAL ;
- mprj_io_analog_sel\[20\] ( padframe mprj_io_analog_sel[20] ) + USE SIGNAL ;
- mprj_io_analog_sel\[21\] ( padframe mprj_io_analog_sel[21] ) + USE SIGNAL ;
- mprj_io_analog_sel\[22\] ( padframe mprj_io_analog_sel[22] ) + USE SIGNAL ;
- mprj_io_analog_sel\[23\] ( padframe mprj_io_analog_sel[23] ) + USE SIGNAL ;
- mprj_io_analog_sel\[24\] ( padframe mprj_io_analog_sel[24] ) + USE SIGNAL ;
- mprj_io_analog_sel\[25\] ( padframe mprj_io_analog_sel[25] ) + USE SIGNAL ;
- mprj_io_analog_sel\[26\] ( padframe mprj_io_analog_sel[26] ) + USE SIGNAL ;
- mprj_io_analog_sel\[2\] ( padframe mprj_io_analog_sel[2] ) + USE SIGNAL ;
- mprj_io_analog_sel\[3\] ( padframe mprj_io_analog_sel[3] ) + USE SIGNAL ;
- mprj_io_analog_sel\[4\] ( padframe mprj_io_analog_sel[4] ) + USE SIGNAL ;
- mprj_io_analog_sel\[5\] ( padframe mprj_io_analog_sel[5] ) + USE SIGNAL ;
- mprj_io_analog_sel\[6\] ( padframe mprj_io_analog_sel[6] ) + USE SIGNAL ;
- mprj_io_analog_sel\[7\] ( padframe mprj_io_analog_sel[7] ) + USE SIGNAL ;
- mprj_io_analog_sel\[8\] ( padframe mprj_io_analog_sel[8] ) + USE SIGNAL ;
- mprj_io_analog_sel\[9\] ( padframe mprj_io_analog_sel[9] ) + USE SIGNAL ;
- mprj_io_dm\[0\] ( padframe mprj_io_dm[0] ) + USE SIGNAL ;
- mprj_io_dm\[10\] ( padframe mprj_io_dm[10] ) + USE SIGNAL ;
- mprj_io_dm\[11\] ( padframe mprj_io_dm[11] ) + USE SIGNAL ;
- mprj_io_dm\[12\] ( padframe mprj_io_dm[12] ) + USE SIGNAL ;
- mprj_io_dm\[13\] ( padframe mprj_io_dm[13] ) + USE SIGNAL ;
- mprj_io_dm\[14\] ( padframe mprj_io_dm[14] ) + USE SIGNAL ;
- mprj_io_dm\[15\] ( padframe mprj_io_dm[15] ) + USE SIGNAL ;
- mprj_io_dm\[16\] ( padframe mprj_io_dm[16] ) + USE SIGNAL ;
- mprj_io_dm\[17\] ( padframe mprj_io_dm[17] ) + USE SIGNAL ;
- mprj_io_dm\[18\] ( padframe mprj_io_dm[18] ) + USE SIGNAL ;
- mprj_io_dm\[19\] ( padframe mprj_io_dm[19] ) + USE SIGNAL ;
- mprj_io_dm\[1\] ( padframe mprj_io_dm[1] ) + USE SIGNAL ;
- mprj_io_dm\[20\] ( padframe mprj_io_dm[20] ) + USE SIGNAL ;
- mprj_io_dm\[21\] ( padframe mprj_io_dm[21] ) + USE SIGNAL ;
- mprj_io_dm\[22\] ( padframe mprj_io_dm[22] ) + USE SIGNAL ;
- mprj_io_dm\[23\] ( padframe mprj_io_dm[23] ) + USE SIGNAL ;
- mprj_io_dm\[24\] ( padframe mprj_io_dm[24] ) + USE SIGNAL ;
- mprj_io_dm\[25\] ( padframe mprj_io_dm[25] ) + USE SIGNAL ;
- mprj_io_dm\[26\] ( padframe mprj_io_dm[26] ) + USE SIGNAL ;
- mprj_io_dm\[27\] ( padframe mprj_io_dm[27] ) + USE SIGNAL ;
- mprj_io_dm\[28\] ( padframe mprj_io_dm[28] ) + USE SIGNAL ;
- mprj_io_dm\[29\] ( padframe mprj_io_dm[29] ) + USE SIGNAL ;
- mprj_io_dm\[2\] ( padframe mprj_io_dm[2] ) + USE SIGNAL ;
- mprj_io_dm\[30\] ( padframe mprj_io_dm[30] ) + USE SIGNAL ;
- mprj_io_dm\[31\] ( padframe mprj_io_dm[31] ) + USE SIGNAL ;
- mprj_io_dm\[32\] ( padframe mprj_io_dm[32] ) + USE SIGNAL ;
- mprj_io_dm\[33\] ( padframe mprj_io_dm[33] ) + USE SIGNAL ;
- mprj_io_dm\[34\] ( padframe mprj_io_dm[34] ) + USE SIGNAL ;
- mprj_io_dm\[35\] ( padframe mprj_io_dm[35] ) + USE SIGNAL ;
- mprj_io_dm\[36\] ( padframe mprj_io_dm[36] ) + USE SIGNAL ;
- mprj_io_dm\[37\] ( padframe mprj_io_dm[37] ) + USE SIGNAL ;
- mprj_io_dm\[38\] ( padframe mprj_io_dm[38] ) + USE SIGNAL ;
- mprj_io_dm\[39\] ( padframe mprj_io_dm[39] ) + USE SIGNAL ;
- mprj_io_dm\[3\] ( padframe mprj_io_dm[3] ) + USE SIGNAL ;
- mprj_io_dm\[40\] ( padframe mprj_io_dm[40] ) + USE SIGNAL ;
- mprj_io_dm\[41\] ( padframe mprj_io_dm[41] ) + USE SIGNAL ;
- mprj_io_dm\[42\] ( padframe mprj_io_dm[42] ) + USE SIGNAL ;
- mprj_io_dm\[43\] ( padframe mprj_io_dm[43] ) + USE SIGNAL ;
- mprj_io_dm\[44\] ( padframe mprj_io_dm[44] ) + USE SIGNAL ;
- mprj_io_dm\[45\] ( padframe mprj_io_dm[45] ) + USE SIGNAL ;
- mprj_io_dm\[46\] ( padframe mprj_io_dm[46] ) + USE SIGNAL ;
- mprj_io_dm\[47\] ( padframe mprj_io_dm[47] ) + USE SIGNAL ;
- mprj_io_dm\[48\] ( padframe mprj_io_dm[48] ) + USE SIGNAL ;
- mprj_io_dm\[49\] ( padframe mprj_io_dm[49] ) + USE SIGNAL ;
- mprj_io_dm\[4\] ( padframe mprj_io_dm[4] ) + USE SIGNAL ;
- mprj_io_dm\[50\] ( padframe mprj_io_dm[50] ) + USE SIGNAL ;
- mprj_io_dm\[51\] ( padframe mprj_io_dm[51] ) + USE SIGNAL ;
- mprj_io_dm\[52\] ( padframe mprj_io_dm[52] ) + USE SIGNAL ;
- mprj_io_dm\[53\] ( padframe mprj_io_dm[53] ) + USE SIGNAL ;
- mprj_io_dm\[54\] ( padframe mprj_io_dm[54] ) + USE SIGNAL ;
- mprj_io_dm\[55\] ( padframe mprj_io_dm[55] ) + USE SIGNAL ;
- mprj_io_dm\[56\] ( padframe mprj_io_dm[56] ) + USE SIGNAL ;
- mprj_io_dm\[57\] ( padframe mprj_io_dm[57] ) + USE SIGNAL ;
- mprj_io_dm\[58\] ( padframe mprj_io_dm[58] ) + USE SIGNAL ;
- mprj_io_dm\[59\] ( padframe mprj_io_dm[59] ) + USE SIGNAL ;
- mprj_io_dm\[5\] ( padframe mprj_io_dm[5] ) + USE SIGNAL ;
- mprj_io_dm\[60\] ( padframe mprj_io_dm[60] ) + USE SIGNAL ;
- mprj_io_dm\[61\] ( padframe mprj_io_dm[61] ) + USE SIGNAL ;
- mprj_io_dm\[62\] ( padframe mprj_io_dm[62] ) + USE SIGNAL ;
- mprj_io_dm\[63\] ( padframe mprj_io_dm[63] ) + USE SIGNAL ;
- mprj_io_dm\[64\] ( padframe mprj_io_dm[64] ) + USE SIGNAL ;
- mprj_io_dm\[65\] ( padframe mprj_io_dm[65] ) + USE SIGNAL ;
- mprj_io_dm\[66\] ( padframe mprj_io_dm[66] ) + USE SIGNAL ;
- mprj_io_dm\[67\] ( padframe mprj_io_dm[67] ) + USE SIGNAL ;
- mprj_io_dm\[68\] ( padframe mprj_io_dm[68] ) + USE SIGNAL ;
- mprj_io_dm\[69\] ( padframe mprj_io_dm[69] ) + USE SIGNAL ;
- mprj_io_dm\[6\] ( padframe mprj_io_dm[6] ) + USE SIGNAL ;
- mprj_io_dm\[70\] ( padframe mprj_io_dm[70] ) + USE SIGNAL ;
- mprj_io_dm\[71\] ( padframe mprj_io_dm[71] ) + USE SIGNAL ;
- mprj_io_dm\[72\] ( padframe mprj_io_dm[72] ) + USE SIGNAL ;
- mprj_io_dm\[73\] ( padframe mprj_io_dm[73] ) + USE SIGNAL ;
- mprj_io_dm\[74\] ( padframe mprj_io_dm[74] ) + USE SIGNAL ;
- mprj_io_dm\[75\] ( padframe mprj_io_dm[75] ) + USE SIGNAL ;
- mprj_io_dm\[76\] ( padframe mprj_io_dm[76] ) + USE SIGNAL ;
- mprj_io_dm\[77\] ( padframe mprj_io_dm[77] ) + USE SIGNAL ;
- mprj_io_dm\[78\] ( padframe mprj_io_dm[78] ) + USE SIGNAL ;
- mprj_io_dm\[79\] ( padframe mprj_io_dm[79] ) + USE SIGNAL ;
- mprj_io_dm\[7\] ( padframe mprj_io_dm[7] ) + USE SIGNAL ;
- mprj_io_dm\[80\] ( padframe mprj_io_dm[80] ) + USE SIGNAL ;
- mprj_io_dm\[8\] ( padframe mprj_io_dm[8] ) + USE SIGNAL ;
- mprj_io_dm\[9\] ( padframe mprj_io_dm[9] ) + USE SIGNAL ;
- mprj_io_holdover\[0\] ( padframe mprj_io_holdover[0] ) + USE SIGNAL ;
- mprj_io_holdover\[10\] ( padframe mprj_io_holdover[10] ) + USE SIGNAL ;
- mprj_io_holdover\[11\] ( padframe mprj_io_holdover[11] ) + USE SIGNAL ;
- mprj_io_holdover\[12\] ( padframe mprj_io_holdover[12] ) + USE SIGNAL ;
- mprj_io_holdover\[13\] ( padframe mprj_io_holdover[13] ) + USE SIGNAL ;
- mprj_io_holdover\[14\] ( padframe mprj_io_holdover[14] ) + USE SIGNAL ;
- mprj_io_holdover\[15\] ( padframe mprj_io_holdover[15] ) + USE SIGNAL ;
- mprj_io_holdover\[16\] ( padframe mprj_io_holdover[16] ) + USE SIGNAL ;
- mprj_io_holdover\[17\] ( padframe mprj_io_holdover[17] ) + USE SIGNAL ;
- mprj_io_holdover\[18\] ( padframe mprj_io_holdover[18] ) + USE SIGNAL ;
- mprj_io_holdover\[19\] ( padframe mprj_io_holdover[19] ) + USE SIGNAL ;
- mprj_io_holdover\[1\] ( padframe mprj_io_holdover[1] ) + USE SIGNAL ;
- mprj_io_holdover\[20\] ( padframe mprj_io_holdover[20] ) + USE SIGNAL ;
- mprj_io_holdover\[21\] ( padframe mprj_io_holdover[21] ) + USE SIGNAL ;
- mprj_io_holdover\[22\] ( padframe mprj_io_holdover[22] ) + USE SIGNAL ;
- mprj_io_holdover\[23\] ( padframe mprj_io_holdover[23] ) + USE SIGNAL ;
- mprj_io_holdover\[24\] ( padframe mprj_io_holdover[24] ) + USE SIGNAL ;
- mprj_io_holdover\[25\] ( padframe mprj_io_holdover[25] ) + USE SIGNAL ;
- mprj_io_holdover\[26\] ( padframe mprj_io_holdover[26] ) + USE SIGNAL ;
- mprj_io_holdover\[2\] ( padframe mprj_io_holdover[2] ) + USE SIGNAL ;
- mprj_io_holdover\[3\] ( padframe mprj_io_holdover[3] ) + USE SIGNAL ;
- mprj_io_holdover\[4\] ( padframe mprj_io_holdover[4] ) + USE SIGNAL ;
- mprj_io_holdover\[5\] ( padframe mprj_io_holdover[5] ) + USE SIGNAL ;
- mprj_io_holdover\[6\] ( padframe mprj_io_holdover[6] ) + USE SIGNAL ;
- mprj_io_holdover\[7\] ( padframe mprj_io_holdover[7] ) + USE SIGNAL ;
- mprj_io_holdover\[8\] ( padframe mprj_io_holdover[8] ) + USE SIGNAL ;
- mprj_io_holdover\[9\] ( padframe mprj_io_holdover[9] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[0\] ( padframe mprj_io_ib_mode_sel[0] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[10\] ( padframe mprj_io_ib_mode_sel[10] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[11\] ( padframe mprj_io_ib_mode_sel[11] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[12\] ( padframe mprj_io_ib_mode_sel[12] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[13\] ( padframe mprj_io_ib_mode_sel[13] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[14\] ( padframe mprj_io_ib_mode_sel[14] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[15\] ( padframe mprj_io_ib_mode_sel[15] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[16\] ( padframe mprj_io_ib_mode_sel[16] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[17\] ( padframe mprj_io_ib_mode_sel[17] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[18\] ( padframe mprj_io_ib_mode_sel[18] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[19\] ( padframe mprj_io_ib_mode_sel[19] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[1\] ( padframe mprj_io_ib_mode_sel[1] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[20\] ( padframe mprj_io_ib_mode_sel[20] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[21\] ( padframe mprj_io_ib_mode_sel[21] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[22\] ( padframe mprj_io_ib_mode_sel[22] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[23\] ( padframe mprj_io_ib_mode_sel[23] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[24\] ( padframe mprj_io_ib_mode_sel[24] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[25\] ( padframe mprj_io_ib_mode_sel[25] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[26\] ( padframe mprj_io_ib_mode_sel[26] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[2\] ( padframe mprj_io_ib_mode_sel[2] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[3\] ( padframe mprj_io_ib_mode_sel[3] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[4\] ( padframe mprj_io_ib_mode_sel[4] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[5\] ( padframe mprj_io_ib_mode_sel[5] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[6\] ( padframe mprj_io_ib_mode_sel[6] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[7\] ( padframe mprj_io_ib_mode_sel[7] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[8\] ( padframe mprj_io_ib_mode_sel[8] ) + USE SIGNAL ;
- mprj_io_ib_mode_sel\[9\] ( padframe mprj_io_ib_mode_sel[9] ) + USE SIGNAL ;
- mprj_io_in\[0\] ( padframe mprj_io_in[0] ) + USE SIGNAL ;
- mprj_io_in\[10\] ( padframe mprj_io_in[10] ) + USE SIGNAL ;
- mprj_io_in\[11\] ( padframe mprj_io_in[11] ) + USE SIGNAL ;
- mprj_io_in\[12\] ( padframe mprj_io_in[12] ) + USE SIGNAL ;
- mprj_io_in\[13\] ( padframe mprj_io_in[13] ) + USE SIGNAL ;
- mprj_io_in\[14\] ( padframe mprj_io_in[14] ) + USE SIGNAL ;
- mprj_io_in\[15\] ( padframe mprj_io_in[15] ) + USE SIGNAL ;
- mprj_io_in\[16\] ( padframe mprj_io_in[16] ) + USE SIGNAL ;
- mprj_io_in\[17\] ( padframe mprj_io_in[17] ) + USE SIGNAL ;
- mprj_io_in\[18\] ( padframe mprj_io_in[18] ) + USE SIGNAL ;
- mprj_io_in\[19\] ( padframe mprj_io_in[19] ) + USE SIGNAL ;
- mprj_io_in\[1\] ( padframe mprj_io_in[1] ) + USE SIGNAL ;
- mprj_io_in\[20\] ( padframe mprj_io_in[20] ) + USE SIGNAL ;
- mprj_io_in\[21\] ( padframe mprj_io_in[21] ) + USE SIGNAL ;
- mprj_io_in\[22\] ( padframe mprj_io_in[22] ) + USE SIGNAL ;
- mprj_io_in\[23\] ( padframe mprj_io_in[23] ) + USE SIGNAL ;
- mprj_io_in\[24\] ( padframe mprj_io_in[24] ) + USE SIGNAL ;
- mprj_io_in\[25\] ( padframe mprj_io_in[25] ) + USE SIGNAL ;
- mprj_io_in\[26\] ( padframe mprj_io_in[26] ) + USE SIGNAL ;
- mprj_io_in\[2\] ( padframe mprj_io_in[2] ) + USE SIGNAL ;
- mprj_io_in\[3\] ( padframe mprj_io_in[3] ) + USE SIGNAL ;
- mprj_io_in\[4\] ( padframe mprj_io_in[4] ) + USE SIGNAL ;
- mprj_io_in\[5\] ( padframe mprj_io_in[5] ) + USE SIGNAL ;
- mprj_io_in\[6\] ( padframe mprj_io_in[6] ) + USE SIGNAL ;
- mprj_io_in\[7\] ( padframe mprj_io_in[7] ) + USE SIGNAL ;
- mprj_io_in\[8\] ( padframe mprj_io_in[8] ) + USE SIGNAL ;
- mprj_io_in\[9\] ( padframe mprj_io_in[9] ) + USE SIGNAL ;
- mprj_io_in_3v3\[0\] ( padframe mprj_io_in_3v3[0] ) + USE SIGNAL ;
- mprj_io_in_3v3\[10\] ( padframe mprj_io_in_3v3[10] ) + USE SIGNAL ;
- mprj_io_in_3v3\[11\] ( padframe mprj_io_in_3v3[11] ) + USE SIGNAL ;
- mprj_io_in_3v3\[12\] ( padframe mprj_io_in_3v3[12] ) + USE SIGNAL ;
- mprj_io_in_3v3\[13\] ( padframe mprj_io_in_3v3[13] ) + USE SIGNAL ;
- mprj_io_in_3v3\[14\] ( padframe mprj_io_in_3v3[14] ) + USE SIGNAL ;
- mprj_io_in_3v3\[15\] ( padframe mprj_io_in_3v3[15] ) + USE SIGNAL ;
- mprj_io_in_3v3\[16\] ( padframe mprj_io_in_3v3[16] ) + USE SIGNAL ;
- mprj_io_in_3v3\[17\] ( padframe mprj_io_in_3v3[17] ) + USE SIGNAL ;
- mprj_io_in_3v3\[18\] ( padframe mprj_io_in_3v3[18] ) + USE SIGNAL ;
- mprj_io_in_3v3\[19\] ( padframe mprj_io_in_3v3[19] ) + USE SIGNAL ;
- mprj_io_in_3v3\[1\] ( padframe mprj_io_in_3v3[1] ) + USE SIGNAL ;
- mprj_io_in_3v3\[20\] ( padframe mprj_io_in_3v3[20] ) + USE SIGNAL ;
- mprj_io_in_3v3\[21\] ( padframe mprj_io_in_3v3[21] ) + USE SIGNAL ;
- mprj_io_in_3v3\[22\] ( padframe mprj_io_in_3v3[22] ) + USE SIGNAL ;
- mprj_io_in_3v3\[23\] ( padframe mprj_io_in_3v3[23] ) + USE SIGNAL ;
- mprj_io_in_3v3\[24\] ( padframe mprj_io_in_3v3[24] ) + USE SIGNAL ;
- mprj_io_in_3v3\[25\] ( padframe mprj_io_in_3v3[25] ) + USE SIGNAL ;
- mprj_io_in_3v3\[26\] ( padframe mprj_io_in_3v3[26] ) + USE SIGNAL ;
- mprj_io_in_3v3\[2\] ( padframe mprj_io_in_3v3[2] ) + USE SIGNAL ;
- mprj_io_in_3v3\[3\] ( padframe mprj_io_in_3v3[3] ) + USE SIGNAL ;
- mprj_io_in_3v3\[4\] ( padframe mprj_io_in_3v3[4] ) + USE SIGNAL ;
- mprj_io_in_3v3\[5\] ( padframe mprj_io_in_3v3[5] ) + USE SIGNAL ;
- mprj_io_in_3v3\[6\] ( padframe mprj_io_in_3v3[6] ) + USE SIGNAL ;
- mprj_io_in_3v3\[7\] ( padframe mprj_io_in_3v3[7] ) + USE SIGNAL ;
- mprj_io_in_3v3\[8\] ( padframe mprj_io_in_3v3[8] ) + USE SIGNAL ;
- mprj_io_in_3v3\[9\] ( padframe mprj_io_in_3v3[9] ) + USE SIGNAL ;
- mprj_io_inp_dis\[0\] ( padframe mprj_io_inp_dis[0] ) + USE SIGNAL ;
- mprj_io_inp_dis\[10\] ( padframe mprj_io_inp_dis[10] ) + USE SIGNAL ;
- mprj_io_inp_dis\[11\] ( padframe mprj_io_inp_dis[11] ) + USE SIGNAL ;
- mprj_io_inp_dis\[12\] ( padframe mprj_io_inp_dis[12] ) + USE SIGNAL ;
- mprj_io_inp_dis\[13\] ( padframe mprj_io_inp_dis[13] ) + USE SIGNAL ;
- mprj_io_inp_dis\[14\] ( padframe mprj_io_inp_dis[14] ) + USE SIGNAL ;
- mprj_io_inp_dis\[15\] ( padframe mprj_io_inp_dis[15] ) + USE SIGNAL ;
- mprj_io_inp_dis\[16\] ( padframe mprj_io_inp_dis[16] ) + USE SIGNAL ;
- mprj_io_inp_dis\[17\] ( padframe mprj_io_inp_dis[17] ) + USE SIGNAL ;
- mprj_io_inp_dis\[18\] ( padframe mprj_io_inp_dis[18] ) + USE SIGNAL ;
- mprj_io_inp_dis\[19\] ( padframe mprj_io_inp_dis[19] ) + USE SIGNAL ;
- mprj_io_inp_dis\[1\] ( padframe mprj_io_inp_dis[1] ) + USE SIGNAL ;
- mprj_io_inp_dis\[20\] ( padframe mprj_io_inp_dis[20] ) + USE SIGNAL ;
- mprj_io_inp_dis\[21\] ( padframe mprj_io_inp_dis[21] ) + USE SIGNAL ;
- mprj_io_inp_dis\[22\] ( padframe mprj_io_inp_dis[22] ) + USE SIGNAL ;
- mprj_io_inp_dis\[23\] ( padframe mprj_io_inp_dis[23] ) + USE SIGNAL ;
- mprj_io_inp_dis\[24\] ( padframe mprj_io_inp_dis[24] ) + USE SIGNAL ;
- mprj_io_inp_dis\[25\] ( padframe mprj_io_inp_dis[25] ) + USE SIGNAL ;
- mprj_io_inp_dis\[26\] ( padframe mprj_io_inp_dis[26] ) + USE SIGNAL ;
- mprj_io_inp_dis\[2\] ( padframe mprj_io_inp_dis[2] ) + USE SIGNAL ;
- mprj_io_inp_dis\[3\] ( padframe mprj_io_inp_dis[3] ) + USE SIGNAL ;
- mprj_io_inp_dis\[4\] ( padframe mprj_io_inp_dis[4] ) + USE SIGNAL ;
- mprj_io_inp_dis\[5\] ( padframe mprj_io_inp_dis[5] ) + USE SIGNAL ;
- mprj_io_inp_dis\[6\] ( padframe mprj_io_inp_dis[6] ) + USE SIGNAL ;
- mprj_io_inp_dis\[7\] ( padframe mprj_io_inp_dis[7] ) + USE SIGNAL ;
- mprj_io_inp_dis\[8\] ( padframe mprj_io_inp_dis[8] ) + USE SIGNAL ;
- mprj_io_inp_dis\[9\] ( padframe mprj_io_inp_dis[9] ) + USE SIGNAL ;
- mprj_io_oeb\[0\] ( padframe mprj_io_oeb[0] ) + USE SIGNAL ;
- mprj_io_oeb\[10\] ( padframe mprj_io_oeb[10] ) + USE SIGNAL ;
- mprj_io_oeb\[11\] ( padframe mprj_io_oeb[11] ) + USE SIGNAL ;
- mprj_io_oeb\[12\] ( padframe mprj_io_oeb[12] ) + USE SIGNAL ;
- mprj_io_oeb\[13\] ( padframe mprj_io_oeb[13] ) + USE SIGNAL ;
- mprj_io_oeb\[14\] ( padframe mprj_io_oeb[14] ) + USE SIGNAL ;
- mprj_io_oeb\[15\] ( padframe mprj_io_oeb[15] ) + USE SIGNAL ;
- mprj_io_oeb\[16\] ( padframe mprj_io_oeb[16] ) + USE SIGNAL ;
- mprj_io_oeb\[17\] ( padframe mprj_io_oeb[17] ) + USE SIGNAL ;
- mprj_io_oeb\[18\] ( padframe mprj_io_oeb[18] ) + USE SIGNAL ;
- mprj_io_oeb\[19\] ( padframe mprj_io_oeb[19] ) + USE SIGNAL ;
- mprj_io_oeb\[1\] ( padframe mprj_io_oeb[1] ) + USE SIGNAL ;
- mprj_io_oeb\[20\] ( padframe mprj_io_oeb[20] ) + USE SIGNAL ;
- mprj_io_oeb\[21\] ( padframe mprj_io_oeb[21] ) + USE SIGNAL ;
- mprj_io_oeb\[22\] ( padframe mprj_io_oeb[22] ) + USE SIGNAL ;
- mprj_io_oeb\[23\] ( padframe mprj_io_oeb[23] ) + USE SIGNAL ;
- mprj_io_oeb\[24\] ( padframe mprj_io_oeb[24] ) + USE SIGNAL ;
- mprj_io_oeb\[25\] ( padframe mprj_io_oeb[25] ) + USE SIGNAL ;
- mprj_io_oeb\[26\] ( padframe mprj_io_oeb[26] ) + USE SIGNAL ;
- mprj_io_oeb\[2\] ( padframe mprj_io_oeb[2] ) + USE SIGNAL ;
- mprj_io_oeb\[3\] ( padframe mprj_io_oeb[3] ) + USE SIGNAL ;
- mprj_io_oeb\[4\] ( padframe mprj_io_oeb[4] ) + USE SIGNAL ;
- mprj_io_oeb\[5\] ( padframe mprj_io_oeb[5] ) + USE SIGNAL ;
- mprj_io_oeb\[6\] ( padframe mprj_io_oeb[6] ) + USE SIGNAL ;
- mprj_io_oeb\[7\] ( padframe mprj_io_oeb[7] ) + USE SIGNAL ;
- mprj_io_oeb\[8\] ( padframe mprj_io_oeb[8] ) + USE SIGNAL ;
- mprj_io_oeb\[9\] ( padframe mprj_io_oeb[9] ) + USE SIGNAL ;
- mprj_io_one\[0\] ( padframe mprj_io_one[0] ) + USE SIGNAL ;
- mprj_io_one\[10\] ( padframe mprj_io_one[10] ) + USE SIGNAL ;
- mprj_io_one\[11\] ( padframe mprj_io_one[11] ) + USE SIGNAL ;
- mprj_io_one\[12\] ( padframe mprj_io_one[12] ) + USE SIGNAL ;
- mprj_io_one\[13\] ( padframe mprj_io_one[13] ) + USE SIGNAL ;
- mprj_io_one\[14\] ( padframe mprj_io_one[14] ) + USE SIGNAL ;
- mprj_io_one\[15\] ( padframe mprj_io_one[15] ) + USE SIGNAL ;
- mprj_io_one\[16\] ( padframe mprj_io_one[16] ) + USE SIGNAL ;
- mprj_io_one\[17\] ( padframe mprj_io_one[17] ) + USE SIGNAL ;
- mprj_io_one\[18\] ( padframe mprj_io_one[18] ) + USE SIGNAL ;
- mprj_io_one\[19\] ( padframe mprj_io_one[19] ) + USE SIGNAL ;
- mprj_io_one\[1\] ( padframe mprj_io_one[1] ) + USE SIGNAL ;
- mprj_io_one\[20\] ( padframe mprj_io_one[20] ) + USE SIGNAL ;
- mprj_io_one\[21\] ( padframe mprj_io_one[21] ) + USE SIGNAL ;
- mprj_io_one\[22\] ( padframe mprj_io_one[22] ) + USE SIGNAL ;
- mprj_io_one\[23\] ( padframe mprj_io_one[23] ) + USE SIGNAL ;
- mprj_io_one\[24\] ( padframe mprj_io_one[24] ) + USE SIGNAL ;
- mprj_io_one\[25\] ( padframe mprj_io_one[25] ) + USE SIGNAL ;
- mprj_io_one\[26\] ( padframe mprj_io_one[26] ) + USE SIGNAL ;
- mprj_io_one\[2\] ( padframe mprj_io_one[2] ) + USE SIGNAL ;
- mprj_io_one\[3\] ( padframe mprj_io_one[3] ) + USE SIGNAL ;
- mprj_io_one\[4\] ( padframe mprj_io_one[4] ) + USE SIGNAL ;
- mprj_io_one\[5\] ( padframe mprj_io_one[5] ) + USE SIGNAL ;
- mprj_io_one\[6\] ( padframe mprj_io_one[6] ) + USE SIGNAL ;
- mprj_io_one\[7\] ( padframe mprj_io_one[7] ) + USE SIGNAL ;
- mprj_io_one\[8\] ( padframe mprj_io_one[8] ) + USE SIGNAL ;
- mprj_io_one\[9\] ( padframe mprj_io_one[9] ) + USE SIGNAL ;
- mprj_io_out\[0\] ( padframe mprj_io_out[0] ) + USE SIGNAL ;
- mprj_io_out\[10\] ( padframe mprj_io_out[10] ) + USE SIGNAL ;
- mprj_io_out\[11\] ( padframe mprj_io_out[11] ) + USE SIGNAL ;
- mprj_io_out\[12\] ( padframe mprj_io_out[12] ) + USE SIGNAL ;
- mprj_io_out\[13\] ( padframe mprj_io_out[13] ) + USE SIGNAL ;
- mprj_io_out\[14\] ( padframe mprj_io_out[14] ) + USE SIGNAL ;
- mprj_io_out\[15\] ( padframe mprj_io_out[15] ) + USE SIGNAL ;
- mprj_io_out\[16\] ( padframe mprj_io_out[16] ) + USE SIGNAL ;
- mprj_io_out\[17\] ( padframe mprj_io_out[17] ) + USE SIGNAL ;
- mprj_io_out\[18\] ( padframe mprj_io_out[18] ) + USE SIGNAL ;
- mprj_io_out\[19\] ( padframe mprj_io_out[19] ) + USE SIGNAL ;
- mprj_io_out\[1\] ( padframe mprj_io_out[1] ) + USE SIGNAL ;
- mprj_io_out\[20\] ( padframe mprj_io_out[20] ) + USE SIGNAL ;
- mprj_io_out\[21\] ( padframe mprj_io_out[21] ) + USE SIGNAL ;
- mprj_io_out\[22\] ( padframe mprj_io_out[22] ) + USE SIGNAL ;
- mprj_io_out\[23\] ( padframe mprj_io_out[23] ) + USE SIGNAL ;
- mprj_io_out\[24\] ( padframe mprj_io_out[24] ) + USE SIGNAL ;
- mprj_io_out\[25\] ( padframe mprj_io_out[25] ) + USE SIGNAL ;
- mprj_io_out\[26\] ( padframe mprj_io_out[26] ) + USE SIGNAL ;
- mprj_io_out\[2\] ( padframe mprj_io_out[2] ) + USE SIGNAL ;
- mprj_io_out\[3\] ( padframe mprj_io_out[3] ) + USE SIGNAL ;
- mprj_io_out\[4\] ( padframe mprj_io_out[4] ) + USE SIGNAL ;
- mprj_io_out\[5\] ( padframe mprj_io_out[5] ) + USE SIGNAL ;
- mprj_io_out\[6\] ( padframe mprj_io_out[6] ) + USE SIGNAL ;
- mprj_io_out\[7\] ( padframe mprj_io_out[7] ) + USE SIGNAL ;
- mprj_io_out\[8\] ( padframe mprj_io_out[8] ) + USE SIGNAL ;
- mprj_io_out\[9\] ( padframe mprj_io_out[9] ) + USE SIGNAL ;
- mprj_io_slow_sel\[0\] ( padframe mprj_io_slow_sel[0] ) + USE SIGNAL ;
- mprj_io_slow_sel\[10\] ( padframe mprj_io_slow_sel[10] ) + USE SIGNAL ;
- mprj_io_slow_sel\[11\] ( padframe mprj_io_slow_sel[11] ) + USE SIGNAL ;
- mprj_io_slow_sel\[12\] ( padframe mprj_io_slow_sel[12] ) + USE SIGNAL ;
- mprj_io_slow_sel\[13\] ( padframe mprj_io_slow_sel[13] ) + USE SIGNAL ;
- mprj_io_slow_sel\[14\] ( padframe mprj_io_slow_sel[14] ) + USE SIGNAL ;
- mprj_io_slow_sel\[15\] ( padframe mprj_io_slow_sel[15] ) + USE SIGNAL ;
- mprj_io_slow_sel\[16\] ( padframe mprj_io_slow_sel[16] ) + USE SIGNAL ;
- mprj_io_slow_sel\[17\] ( padframe mprj_io_slow_sel[17] ) + USE SIGNAL ;
- mprj_io_slow_sel\[18\] ( padframe mprj_io_slow_sel[18] ) + USE SIGNAL ;
- mprj_io_slow_sel\[19\] ( padframe mprj_io_slow_sel[19] ) + USE SIGNAL ;
- mprj_io_slow_sel\[1\] ( padframe mprj_io_slow_sel[1] ) + USE SIGNAL ;
- mprj_io_slow_sel\[20\] ( padframe mprj_io_slow_sel[20] ) + USE SIGNAL ;
- mprj_io_slow_sel\[21\] ( padframe mprj_io_slow_sel[21] ) + USE SIGNAL ;
- mprj_io_slow_sel\[22\] ( padframe mprj_io_slow_sel[22] ) + USE SIGNAL ;
- mprj_io_slow_sel\[23\] ( padframe mprj_io_slow_sel[23] ) + USE SIGNAL ;
- mprj_io_slow_sel\[24\] ( padframe mprj_io_slow_sel[24] ) + USE SIGNAL ;
- mprj_io_slow_sel\[25\] ( padframe mprj_io_slow_sel[25] ) + USE SIGNAL ;
- mprj_io_slow_sel\[26\] ( padframe mprj_io_slow_sel[26] ) + USE SIGNAL ;
- mprj_io_slow_sel\[2\] ( padframe mprj_io_slow_sel[2] ) + USE SIGNAL ;
- mprj_io_slow_sel\[3\] ( padframe mprj_io_slow_sel[3] ) + USE SIGNAL ;
- mprj_io_slow_sel\[4\] ( padframe mprj_io_slow_sel[4] ) + USE SIGNAL ;
- mprj_io_slow_sel\[5\] ( padframe mprj_io_slow_sel[5] ) + USE SIGNAL ;
- mprj_io_slow_sel\[6\] ( padframe mprj_io_slow_sel[6] ) + USE SIGNAL ;
- mprj_io_slow_sel\[7\] ( padframe mprj_io_slow_sel[7] ) + USE SIGNAL ;
- mprj_io_slow_sel\[8\] ( padframe mprj_io_slow_sel[8] ) + USE SIGNAL ;
- mprj_io_slow_sel\[9\] ( padframe mprj_io_slow_sel[9] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[0\] ( padframe mprj_io_vtrip_sel[0] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[10\] ( padframe mprj_io_vtrip_sel[10] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[11\] ( padframe mprj_io_vtrip_sel[11] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[12\] ( padframe mprj_io_vtrip_sel[12] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[13\] ( padframe mprj_io_vtrip_sel[13] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[14\] ( padframe mprj_io_vtrip_sel[14] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[15\] ( padframe mprj_io_vtrip_sel[15] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[16\] ( padframe mprj_io_vtrip_sel[16] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[17\] ( padframe mprj_io_vtrip_sel[17] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[18\] ( padframe mprj_io_vtrip_sel[18] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[19\] ( padframe mprj_io_vtrip_sel[19] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[1\] ( padframe mprj_io_vtrip_sel[1] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[20\] ( padframe mprj_io_vtrip_sel[20] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[21\] ( padframe mprj_io_vtrip_sel[21] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[22\] ( padframe mprj_io_vtrip_sel[22] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[23\] ( padframe mprj_io_vtrip_sel[23] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[24\] ( padframe mprj_io_vtrip_sel[24] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[25\] ( padframe mprj_io_vtrip_sel[25] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[26\] ( padframe mprj_io_vtrip_sel[26] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[2\] ( padframe mprj_io_vtrip_sel[2] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[3\] ( padframe mprj_io_vtrip_sel[3] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[4\] ( padframe mprj_io_vtrip_sel[4] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[5\] ( padframe mprj_io_vtrip_sel[5] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[6\] ( padframe mprj_io_vtrip_sel[6] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[7\] ( padframe mprj_io_vtrip_sel[7] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[8\] ( padframe mprj_io_vtrip_sel[8] ) + USE SIGNAL ;
- mprj_io_vtrip_sel\[9\] ( padframe mprj_io_vtrip_sel[9] ) + USE SIGNAL ;
- por_l ( padframe por ) + USE SIGNAL ;
- porb_h ( padframe porb_h ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- resetb ( PIN resetb ) ( padframe resetb ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- rstb_h ( padframe resetb_core_h ) + USE SIGNAL ;
- user_analog\[0\] ( padframe mprj_analog[0] ) + USE SIGNAL ;
- user_analog\[10\] ( padframe mprj_analog[10] ) + USE SIGNAL ;
- user_analog\[1\] ( padframe mprj_analog[1] ) + USE SIGNAL ;
- user_analog\[2\] ( padframe mprj_analog[2] ) + USE SIGNAL ;
- user_analog\[3\] ( padframe mprj_analog[3] ) + USE SIGNAL ;
- user_analog\[4\] ( padframe mprj_analog[4] ) + USE SIGNAL ;
- user_analog\[5\] ( padframe mprj_analog[5] ) + USE SIGNAL ;
- user_analog\[6\] ( padframe mprj_analog[6] ) + USE SIGNAL ;
- user_analog\[7\] ( padframe mprj_analog[7] ) + USE SIGNAL ;
- user_analog\[8\] ( padframe mprj_analog[8] ) + USE SIGNAL ;
- user_analog\[9\] ( padframe mprj_analog[9] ) + USE SIGNAL ;
- user_clamp_high\[0\] ( padframe mprj_clamp_high[0] ) + USE SIGNAL ;
- user_clamp_high\[1\] ( padframe mprj_clamp_high[1] ) + USE SIGNAL ;
- user_clamp_high\[2\] ( padframe mprj_clamp_high[2] ) + USE SIGNAL ;
- user_clamp_low\[0\] ( padframe mprj_clamp_low[0] ) + USE SIGNAL ;
- user_clamp_low\[1\] ( padframe mprj_clamp_low[1] ) + USE SIGNAL ;
- user_clamp_low\[2\] ( padframe mprj_clamp_low[2] ) + USE SIGNAL ;
- user_gpio_analog\[0\] ( padframe mprj_gpio_analog[0] ) + USE SIGNAL ;
- user_gpio_analog\[10\] ( padframe mprj_gpio_analog[10] ) + USE SIGNAL ;
- user_gpio_analog\[11\] ( padframe mprj_gpio_analog[11] ) + USE SIGNAL ;
- user_gpio_analog\[12\] ( padframe mprj_gpio_analog[12] ) + USE SIGNAL ;
- user_gpio_analog\[13\] ( padframe mprj_gpio_analog[13] ) + USE SIGNAL ;
- user_gpio_analog\[14\] ( padframe mprj_gpio_analog[14] ) + USE SIGNAL ;
- user_gpio_analog\[15\] ( padframe mprj_gpio_analog[15] ) + USE SIGNAL ;
- user_gpio_analog\[16\] ( padframe mprj_gpio_analog[16] ) + USE SIGNAL ;
- user_gpio_analog\[17\] ( padframe mprj_gpio_analog[17] ) + USE SIGNAL ;
- user_gpio_analog\[1\] ( padframe mprj_gpio_analog[1] ) + USE SIGNAL ;
- user_gpio_analog\[2\] ( padframe mprj_gpio_analog[2] ) + USE SIGNAL ;
- user_gpio_analog\[3\] ( padframe mprj_gpio_analog[3] ) + USE SIGNAL ;
- user_gpio_analog\[4\] ( padframe mprj_gpio_analog[4] ) + USE SIGNAL ;
- user_gpio_analog\[5\] ( padframe mprj_gpio_analog[5] ) + USE SIGNAL ;
- user_gpio_analog\[6\] ( padframe mprj_gpio_analog[6] ) + USE SIGNAL ;
- user_gpio_analog\[7\] ( padframe mprj_gpio_analog[7] ) + USE SIGNAL ;
- user_gpio_analog\[8\] ( padframe mprj_gpio_analog[8] ) + USE SIGNAL ;
- user_gpio_analog\[9\] ( padframe mprj_gpio_analog[9] ) + USE SIGNAL ;
- user_gpio_noesd\[0\] ( padframe mprj_gpio_noesd[0] ) + USE SIGNAL ;
- user_gpio_noesd\[10\] ( padframe mprj_gpio_noesd[10] ) + USE SIGNAL ;
- user_gpio_noesd\[11\] ( padframe mprj_gpio_noesd[11] ) + USE SIGNAL ;
- user_gpio_noesd\[12\] ( padframe mprj_gpio_noesd[12] ) + USE SIGNAL ;
- user_gpio_noesd\[13\] ( padframe mprj_gpio_noesd[13] ) + USE SIGNAL ;
- user_gpio_noesd\[14\] ( padframe mprj_gpio_noesd[14] ) + USE SIGNAL ;
- user_gpio_noesd\[15\] ( padframe mprj_gpio_noesd[15] ) + USE SIGNAL ;
- user_gpio_noesd\[16\] ( padframe mprj_gpio_noesd[16] ) + USE SIGNAL ;
- user_gpio_noesd\[17\] ( padframe mprj_gpio_noesd[17] ) + USE SIGNAL ;
- user_gpio_noesd\[1\] ( padframe mprj_gpio_noesd[1] ) + USE SIGNAL ;
- user_gpio_noesd\[2\] ( padframe mprj_gpio_noesd[2] ) + USE SIGNAL ;
- user_gpio_noesd\[3\] ( padframe mprj_gpio_noesd[3] ) + USE SIGNAL ;
- user_gpio_noesd\[4\] ( padframe mprj_gpio_noesd[4] ) + USE SIGNAL ;
- user_gpio_noesd\[5\] ( padframe mprj_gpio_noesd[5] ) + USE SIGNAL ;
- user_gpio_noesd\[6\] ( padframe mprj_gpio_noesd[6] ) + USE SIGNAL ;
- user_gpio_noesd\[7\] ( padframe mprj_gpio_noesd[7] ) + USE SIGNAL ;
- user_gpio_noesd\[8\] ( padframe mprj_gpio_noesd[8] ) + USE SIGNAL ;
- user_gpio_noesd\[9\] ( padframe mprj_gpio_noesd[9] ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vccd ( PIN vccd ) ( padframe vccd_pad ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vccd1 ( PIN vccd1 ) ( padframe vccd1_pad ) + USE SIGNAL ;
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
- vccd1_core ( padframe vccd1 ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vccd2 ( PIN vccd2 ) ( padframe vccd2_pad ) + USE SIGNAL ;
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
- vccd2_core ( padframe vccd2 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vccd_core ( padframe vccd ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vdda ( PIN vdda ) ( padframe vdda_pad ) + USE SIGNAL ;
- vdda1 ( PIN vdda1 ) ( padframe vdda1_pad ) + USE SIGNAL ;
- vdda1_2 ( PIN vdda1_2 ) ( padframe vdda1_pad2 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vdda1_core ( padframe vdda1 ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vdda2 ( PIN vdda2 ) ( padframe vdda2_pad ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vdda2_core ( padframe vdda2 ) + USE SIGNAL ;
- vdda_core ( padframe vdda ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vddio ( PIN vddio ) ( padframe vddio_pad ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vddio_2 ( PIN vddio_2 ) ( padframe vddio_pad2 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vddio_core ( padframe vddio ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssa ( PIN vssa ) ( padframe vssa_pad ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vssa1 ( PIN vssa1 ) ( padframe vssa1_pad ) + USE SIGNAL ;
- vssa1_2 ( PIN vssa1_2 ) ( padframe vssa1_pad2 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vssa1_core ( padframe vssa1 ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vssa2 ( PIN vssa2 ) ( padframe vssa2_pad ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vssa2_core ( padframe vssa2 ) + USE SIGNAL ;
- vssa_core ( padframe vssa ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssd ( PIN vssd ) ( padframe vssd_pad ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vssd1 ( PIN vssd1 ) ( padframe vssd1_pad ) + USE SIGNAL ;
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
- vssd1_core ( padframe vssd1 ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vssd2 ( PIN vssd2 ) ( padframe vssd2_pad ) + USE SIGNAL ;
reharden `caravan` to fix outer pins labeling
2023-05-29 08:47:03 -05:00
- vssd2_core ( padframe vssd2 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vssd_core ( padframe vssd ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
- vssio ( PIN vssio ) ( padframe vssio_pad ) + USE SIGNAL ;
Caravan redesign (#321) * Fixed caravan top level power routing and updated views for mag, gds and lef * caravan(rtl): updates ~ typos fix - remove unused pin in chip_io_alt + add caravan_power_routing verilog * Apply automatic changes to Manifest and README.rst * ~ update caravan openlane configs to add extra cell references ~ correct placment and cell names of some macro in caravan interactive script * reharden: caravan + add non functional blocks + add an initial iteration of caravan * Apply automatic changes to Manifest and README.rst * Revert "Fixed caravan top level power routing and updated views for mag, gds and lef" This reverts commit 70628f748af35aaeae06829b05b2c28a49648fc2. * fixed caravan top level power routing * reharden: caravan based on new power routing ~ guard rtl chip_io power pins in the power macro guard * Apply automatic changes to Manifest and README.rst * fixed caravan top level power routing * rehadren: caravan + add caravan signal routing to openlane run ~ change rtl to guard power and analog against routing by openlane by ifndef TOP_ROUTING ~ add pr bounadry for caravan signal routing to fix origin issues * Apply automatic changes to Manifest and README.rst * fix power connection in buffering block and regenerate gl * Apply automatic changes to Manifest and README.rst * updated views for caravan * Added extract unique to lvs-gds-cell target. (#313) * This fixes errors in the top level RTL of caravan that failed to hook up the buffers through the SoC correctly. * Apply automatic changes to Manifest and README.rst * reharden: caravan ~ rtl updated * fixed caravan mag top level * updated views for caravan + signoff * fixed top level cell name * fix syntax error related to signal initialization place in caravan (#319) * fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit * Apply automatic changes to Manifest and README.rst Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> * Apply automatic changes to Manifest and README.rst Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu> Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com> Co-authored-by: Tim Edwards <tim@opencircuitdesign.com> Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com> Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com> Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 09:37:41 -05:00
- vssio_2 ( PIN vssio_2 ) ( padframe vssio_pad2 ) + USE SIGNAL ;
add initial views for `caravan`
2023-05-23 05:05:18 -05:00
- vssio_core ( padframe vssio ) + USE SIGNAL ;
[DATA] Add caravan layout
2021-11-22 15:10:25 -06:00
END NETS
END DESIGN