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caravel/signoff/digital_pll/openlane-signoff/20-rcx_mcsta.nom.log

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reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/digital_pll.odb
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
min_report
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.68 0.68 ^ _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.68 ^ _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 0.19 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.75 0.75 ^ _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.15 0.00 0.75 ^ _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.75 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.08 0.17 library hold time
0.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 data required time
-0.75 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.58 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.72 0.72 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.01 pll_control.prep[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.72 ^ _347_/A_N (sky130_fd_sc_hd__nand2b_2)
0.05 0.19 0.91 ^ _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.05 0.00 0.91 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
-0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.72 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.78 0.78 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tval[0] (net)
0.17 0.00 0.78 ^ _329_/A1 (sky130_fd_sc_hd__o21a_2)
0.06 0.28 1.06 ^ _329_/X (sky130_fd_sc_hd__o21a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.06 0.00 1.06 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
1.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.87 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.70 0.71 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.10 0.00 0.71 ^ _343_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.26 0.96 ^ _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.06 0.00 0.96 ^ _344_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.12 ^ _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.05 0.00 1.12 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
1.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.93 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.84 0.85 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.25 0.00 0.85 ^ _332_/A1 (sky130_fd_sc_hd__o21a_2)
0.05 0.30 1.15 ^ _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.05 0.00 1.15 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
1.15 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.15 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.95 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.72 0.72 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.11 0.00 0.72 ^ _345_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.26 0.98 ^ _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.06 0.00 0.98 ^ _346_/A (sky130_fd_sc_hd__buf_2)
0.06 0.17 1.15 ^ _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 1.15 ^ _456_/D (sky130_fd_sc_hd__dfrtp_2)
1.15 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.19 data required time
-1.15 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.72 0.73 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.tval[1] (net)
0.11 0.00 0.73 ^ _326_/A0 (sky130_fd_sc_hd__mux2_2)
0.07 0.28 1.00 ^ _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.07 0.00 1.00 ^ _327_/A (sky130_fd_sc_hd__buf_2)
0.04 0.16 1.16 ^ _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.04 0.00 1.16 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.16 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.16 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.76 0.76 ^ _475_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[2] (net)
0.15 0.00 0.76 ^ _221_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.28 1.04 ^ _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.06 0.00 1.04 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.04 0.15 1.20 ^ _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.04 0.00 1.20 ^ _475_/D (sky130_fd_sc_hd__dfrtp_2)
1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 data required time
-1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.00 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.23 0.83 0.83 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.03 pll_control.tint[0] (net)
0.23 0.00 0.83 ^ _323_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.07 0.37 1.20 ^ _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.07 0.00 1.20 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.01 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 0.80 0.81 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[3] (net)
0.20 0.00 0.81 ^ _334_/A1 (sky130_fd_sc_hd__o211a_2)
0.07 0.39 1.20 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _029_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 1.20 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 0.19 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.01 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.84 0.85 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.25 0.00 0.85 ^ _336_/A (sky130_fd_sc_hd__nand2_2)
0.16 0.22 1.07 v _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.16 0.00 1.07 v _342_/C (sky130_fd_sc_hd__nand3_2)
0.07 0.13 1.20 ^ _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.07 0.00 1.20 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.02 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.75 0.76 ^ _474_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.15 0.00 0.76 ^ _223_/A1 (sky130_fd_sc_hd__mux2_2)
0.09 0.31 1.07 ^ _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.09 0.00 1.07 ^ _224_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.24 ^ _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.05 0.00 1.24 ^ _474_/D (sky130_fd_sc_hd__dfrtp_2)
1.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
-1.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.05 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.28 0.86 0.86 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.28 0.00 0.86 ^ _340_/A (sky130_fd_sc_hd__xnor2_2)
0.08 0.27 1.14 ^ _340_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _154_ (net)
0.08 0.00 1.14 ^ _341_/A2 (sky130_fd_sc_hd__a21boi_2)
0.06 0.10 1.24 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.06 0.00 1.24 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
1.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.07 0.18 library hold time
0.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.05 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.77 0.78 ^ _476_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[3] (net)
0.17 0.00 0.78 ^ _219_/A1 (sky130_fd_sc_hd__mux2_2)
0.07 0.31 1.08 ^ _219_/X (sky130_fd_sc_hd__mux2_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _047_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 1.08 ^ _220_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.25 ^ _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.05 0.00 1.25 ^ _476_/D (sky130_fd_sc_hd__dfrtp_2)
1.25 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.25 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.06 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.18 0.79 0.79 ^ _477_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.count1[4] (net)
0.18 0.00 0.80 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.07 0.31 1.10 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.07 0.00 1.10 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.27 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.05 0.00 1.27 ^ _477_/D (sky130_fd_sc_hd__dfrtp_2)
1.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
-1.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.08 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.76 0.76 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[1] (net)
0.15 0.00 0.76 ^ _275_/A (sky130_fd_sc_hd__inv_2)
0.20 0.21 0.97 v _275_/Y (sky130_fd_sc_hd__inv_2)
7 0.05 _099_ (net)
0.20 0.00 0.97 v _321_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.29 1.26 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.09 0.00 1.26 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
1.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.08 0.17 library hold time
0.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 data required time
-1.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.09 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.21 0.81 0.81 ^ _468_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[3] (net)
0.21 0.00 0.81 ^ _314_/A0 (sky130_fd_sc_hd__mux2_2)
0.07 0.31 1.12 ^ _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.07 0.00 1.12 ^ _315_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.28 ^ _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.05 0.00 1.28 ^ _468_/D (sky130_fd_sc_hd__dfrtp_2)
1.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
-1.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.09 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.77 0.78 ^ _473_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[0] (net)
0.17 0.00 0.78 ^ _226_/A1 (sky130_fd_sc_hd__mux2_2)
0.09 0.33 1.10 ^ _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.09 0.00 1.10 ^ _227_/A (sky130_fd_sc_hd__buf_2)
0.06 0.19 1.29 ^ _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.06 0.00 1.29 ^ _473_/D (sky130_fd_sc_hd__dfrtp_2)
1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
-1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.10 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 0.80 0.81 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[2] (net)
0.20 0.00 0.81 ^ _335_/B1 (sky130_fd_sc_hd__a21oi_2)
0.06 0.10 0.91 v _335_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _150_ (net)
0.06 0.00 0.91 v _337_/A2 (sky130_fd_sc_hd__o21ai_2)
0.07 0.15 1.06 ^ _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.07 0.00 1.06 ^ _338_/B (sky130_fd_sc_hd__and2_2)
0.10 0.28 1.34 ^ _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.10 0.00 1.34 ^ _339_/A (sky130_fd_sc_hd__buf_2)
0.07 0.19 1.53 ^ _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.07 0.00 1.53 ^ _460_/D (sky130_fd_sc_hd__dfrtp_2)
1.53 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.53 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.34 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 0.80 0.80 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[2] (net)
0.20 0.00 0.80 ^ _273_/A (sky130_fd_sc_hd__buf_2)
0.30 0.40 1.20 ^ _273_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _097_ (net)
0.30 0.00 1.20 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.06 0.34 1.54 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.06 0.00 1.54 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.70 ^ _318_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _035_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.05 0.00 1.70 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
1.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.51 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.29 0.87 0.87 ^ _469_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.04 pll_control.tint[4] (net)
0.29 0.00 0.88 ^ _228_/A (sky130_fd_sc_hd__buf_2)
0.36 0.48 1.35 ^ _228_/X (sky130_fd_sc_hd__buf_2)
7 0.05 _052_ (net)
0.36 0.00 1.36 ^ _311_/A1 (sky130_fd_sc_hd__o22a_2)
0.05 0.37 1.73 ^ _311_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.05 0.00 1.73 ^ _469_/D (sky130_fd_sc_hd__dfrtp_2)
1.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.19 data required time
-----------------------------------------------------------------------------
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.53 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.33 0.34 ^ _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 0.34 ^ _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.38 0.38 ^ _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.08 0.00 0.38 ^ _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.04 0.22 library hold time
0.22 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.22 data required time
-0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.16 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.36 0.36 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.06 0.00 0.36 ^ _347_/A_N (sky130_fd_sc_hd__nand2b_2)
0.03 0.10 0.46 ^ _347_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _023_ (net)
0.03 0.00 0.46 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.46 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.46 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.40 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tval[0] (net)
0.10 0.00 0.40 ^ _329_/A1 (sky130_fd_sc_hd__o21a_2)
0.03 0.13 0.53 ^ _329_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.03 0.00 0.53 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
0.53 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.53 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.30 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.35 0.35 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.05 0.00 0.35 ^ _343_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.12 0.48 ^ _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.03 0.00 0.48 ^ _344_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.56 ^ _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.03 0.00 0.56 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.33 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.16 0.43 0.44 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.16 0.00 0.44 ^ _332_/A1 (sky130_fd_sc_hd__o21a_2)
0.03 0.14 0.58 ^ _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.03 0.00 0.58 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.35 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.36 0.36 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.06 0.00 0.36 ^ _345_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.13 0.49 ^ _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.03 0.00 0.49 ^ _346_/A (sky130_fd_sc_hd__buf_2)
0.04 0.09 0.57 ^ _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.04 0.00 0.58 ^ _456_/D (sky130_fd_sc_hd__dfrtp_2)
0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.03 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.35 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.36 0.37 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.tval[1] (net)
0.07 0.00 0.37 ^ _326_/A0 (sky130_fd_sc_hd__mux2_2)
0.04 0.14 0.50 ^ _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.04 0.00 0.50 ^ _327_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.59 ^ _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.03 0.00 0.59 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.35 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.41 0.41 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[3] (net)
0.12 0.00 0.41 ^ _334_/A1 (sky130_fd_sc_hd__o211a_2)
0.04 0.17 0.59 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.04 0.00 0.59 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.39 ^ _475_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[2] (net)
0.09 0.00 0.39 ^ _221_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.14 0.52 ^ _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.03 0.00 0.52 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.61 ^ _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.03 0.00 0.61 ^ _475_/D (sky130_fd_sc_hd__dfrtp_2)
0.61 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.14 0.42 0.43 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.03 pll_control.tint[0] (net)
0.14 0.00 0.43 ^ _323_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.04 0.18 0.61 ^ _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.04 0.00 0.61 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.38 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.16 0.43 0.44 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.16 0.00 0.44 ^ _336_/A (sky130_fd_sc_hd__nand2_2)
0.07 0.10 0.54 v _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.07 0.00 0.54 v _342_/C (sky130_fd_sc_hd__nand3_2)
0.04 0.07 0.61 ^ _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.04 0.00 0.61 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.39 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.44 0.45 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.17 0.00 0.45 ^ _340_/A (sky130_fd_sc_hd__xnor2_2)
0.05 0.13 0.58 ^ _340_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _154_ (net)
0.05 0.00 0.58 ^ _341_/A2 (sky130_fd_sc_hd__a21boi_2)
0.03 0.04 0.63 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.03 0.00 0.63 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.38 ^ _474_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.09 0.00 0.38 ^ _223_/A1 (sky130_fd_sc_hd__mux2_2)
0.05 0.15 0.54 ^ _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.05 0.00 0.54 ^ _224_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.63 ^ _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.03 0.00 0.63 ^ _474_/D (sky130_fd_sc_hd__dfrtp_2)
0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.39 ^ _476_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[3] (net)
0.10 0.00 0.39 ^ _219_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.15 0.54 ^ _219_/X (sky130_fd_sc_hd__mux2_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _047_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 0.54 ^ _220_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.63 ^ _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.03 0.00 0.63 ^ _476_/D (sky130_fd_sc_hd__dfrtp_2)
0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.40 0.40 ^ _477_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.count1[4] (net)
0.11 0.00 0.40 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.15 0.56 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.04 0.00 0.56 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.65 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.03 0.00 0.65 ^ _477_/D (sky130_fd_sc_hd__dfrtp_2)
0.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.42 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.38 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[1] (net)
0.09 0.00 0.38 ^ _275_/A (sky130_fd_sc_hd__inv_2)
0.10 0.11 0.49 v _275_/Y (sky130_fd_sc_hd__inv_2)
7 0.04 _099_ (net)
0.10 0.00 0.49 v _321_/A (sky130_fd_sc_hd__xnor2_2)
0.04 0.15 0.64 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.04 0.00 0.64 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
0.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.22 library hold time
0.22 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.22 data required time
-0.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.42 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.41 0.41 ^ _468_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[3] (net)
0.13 0.00 0.41 ^ _314_/A0 (sky130_fd_sc_hd__mux2_2)
0.04 0.15 0.57 ^ _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.04 0.00 0.57 ^ _315_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.65 ^ _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.03 0.00 0.65 ^ _468_/D (sky130_fd_sc_hd__dfrtp_2)
0.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.42 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.39 ^ _473_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[0] (net)
0.10 0.00 0.39 ^ _226_/A1 (sky130_fd_sc_hd__mux2_2)
0.05 0.16 0.56 ^ _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.05 0.00 0.56 ^ _227_/A (sky130_fd_sc_hd__buf_2)
0.04 0.10 0.66 ^ _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.04 0.00 0.66 ^ _473_/D (sky130_fd_sc_hd__dfrtp_2)
0.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.43 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.41 0.41 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[2] (net)
0.12 0.00 0.41 ^ _335_/B1 (sky130_fd_sc_hd__a21oi_2)
0.04 0.04 0.46 v _335_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _150_ (net)
0.04 0.00 0.46 v _337_/A2 (sky130_fd_sc_hd__o21ai_2)
0.04 0.09 0.55 ^ _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.04 0.00 0.55 ^ _338_/B (sky130_fd_sc_hd__and2_2)
0.06 0.14 0.68 ^ _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.06 0.00 0.68 ^ _339_/A (sky130_fd_sc_hd__buf_2)
0.04 0.10 0.79 ^ _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.04 0.00 0.79 ^ _460_/D (sky130_fd_sc_hd__dfrtp_2)
0.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.56 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.40 0.41 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[2] (net)
0.12 0.00 0.41 ^ _273_/A (sky130_fd_sc_hd__buf_2)
0.19 0.23 0.64 ^ _273_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _097_ (net)
0.19 0.00 0.64 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.17 0.80 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.03 0.00 0.80 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.89 ^ _318_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _035_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.89 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.66 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.18 0.45 0.45 ^ _469_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.04 pll_control.tint[4] (net)
0.18 0.00 0.46 ^ _228_/A (sky130_fd_sc_hd__buf_2)
0.22 0.27 0.72 ^ _228_/X (sky130_fd_sc_hd__buf_2)
7 0.05 _052_ (net)
0.22 0.00 0.72 ^ _311_/A1 (sky130_fd_sc_hd__o22a_2)
0.03 0.17 0.90 ^ _311_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.03 0.00 0.90 ^ _469_/D (sky130_fd_sc_hd__dfrtp_2)
0.90 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.90 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.67 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.21 0.21 ^ _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.21 ^ _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.21 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.21 data arrival time
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.24 ^ _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.24 ^ _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.01 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.23 0.23 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.05 0.00 0.23 ^ _347_/A_N (sky130_fd_sc_hd__nand2b_2)
0.02 0.06 0.29 ^ _347_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _023_ (net)
0.02 0.00 0.29 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.06 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.25 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tval[0] (net)
0.07 0.00 0.25 ^ _329_/A1 (sky130_fd_sc_hd__o21a_2)
0.02 0.08 0.34 ^ _329_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.02 0.00 0.34 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.22 0.22 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.04 0.00 0.22 ^ _343_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.08 0.30 ^ _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.02 0.00 0.30 ^ _344_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.35 ^ _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 0.35 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.35 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
-0.35 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.12 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.26 0.27 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[3] (net)
0.09 0.00 0.27 ^ _334_/A1 (sky130_fd_sc_hd__o211a_2)
0.02 0.10 0.37 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _029_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 0.37 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.13 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.28 0.28 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.12 0.00 0.28 ^ _332_/A1 (sky130_fd_sc_hd__o21a_2)
0.02 0.08 0.37 ^ _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.02 0.00 0.37 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.13 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.23 0.23 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.04 0.00 0.23 ^ _345_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.08 0.31 ^ _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.02 0.00 0.31 ^ _346_/A (sky130_fd_sc_hd__buf_2)
0.03 0.06 0.37 ^ _346_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _024_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.37 ^ _456_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.13 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.23 0.23 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.tval[1] (net)
0.05 0.00 0.23 ^ _326_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.09 0.32 ^ _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.03 0.00 0.32 ^ _327_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.37 ^ _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 0.37 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.27 0.28 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.03 pll_control.tint[0] (net)
0.11 0.00 0.28 ^ _323_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.03 0.11 0.39 ^ _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.03 0.00 0.39 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _475_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[2] (net)
0.06 0.00 0.25 ^ _221_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.09 0.33 ^ _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.02 0.00 0.33 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.39 ^ _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 0.39 ^ _475_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.28 0.28 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.12 0.00 0.28 ^ _336_/A (sky130_fd_sc_hd__nand2_2)
0.05 0.06 0.34 v _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.05 0.00 0.34 v _342_/C (sky130_fd_sc_hd__nand3_2)
0.03 0.05 0.39 ^ _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.03 0.00 0.39 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.16 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _474_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.06 0.00 0.25 ^ _223_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.10 0.34 ^ _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.03 0.00 0.34 ^ _224_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.40 ^ _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.02 0.00 0.40 ^ _474_/D (sky130_fd_sc_hd__dfrtp_2)
0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.16 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.29 0.29 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.13 0.00 0.29 ^ _340_/A (sky130_fd_sc_hd__xnor2_2)
0.04 0.08 0.37 ^ _340_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _154_ (net)
0.04 0.00 0.37 ^ _341_/A2 (sky130_fd_sc_hd__a21boi_2)
0.02 0.03 0.40 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.02 0.00 0.40 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.25 ^ _476_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[3] (net)
0.07 0.00 0.25 ^ _219_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.09 0.35 ^ _219_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.03 0.00 0.35 ^ _220_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.41 ^ _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.02 0.00 0.41 ^ _476_/D (sky130_fd_sc_hd__dfrtp_2)
0.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.25 0.26 ^ _477_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.count1[4] (net)
0.08 0.00 0.26 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.10 0.35 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.03 0.00 0.36 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.41 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.02 0.00 0.41 ^ _477_/D (sky130_fd_sc_hd__dfrtp_2)
0.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.18 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.25 ^ _473_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[0] (net)
0.07 0.00 0.25 ^ _226_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.10 0.36 ^ _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.04 0.00 0.36 ^ _227_/A (sky130_fd_sc_hd__buf_2)
0.03 0.06 0.42 ^ _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.03 0.00 0.42 ^ _473_/D (sky130_fd_sc_hd__dfrtp_2)
0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.18 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.26 0.27 ^ _468_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[3] (net)
0.09 0.00 0.27 ^ _314_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.10 0.36 ^ _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.03 0.00 0.36 ^ _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.42 ^ _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 0.42 ^ _468_/D (sky130_fd_sc_hd__dfrtp_2)
0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.18 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.24 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[1] (net)
0.06 0.00 0.24 ^ _275_/A (sky130_fd_sc_hd__inv_2)
0.07 0.07 0.31 v _275_/Y (sky130_fd_sc_hd__inv_2)
7 0.04 _099_ (net)
0.07 0.00 0.31 v _321_/A (sky130_fd_sc_hd__xnor2_2)
0.03 0.10 0.42 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.03 0.00 0.42 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.26 0.27 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[2] (net)
0.09 0.00 0.27 ^ _335_/B1 (sky130_fd_sc_hd__a21oi_2)
0.03 0.02 0.29 v _335_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _150_ (net)
0.03 0.00 0.29 v _337_/A2 (sky130_fd_sc_hd__o21ai_2)
0.02 0.06 0.35 ^ _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.02 0.00 0.35 ^ _338_/B (sky130_fd_sc_hd__and2_2)
0.04 0.09 0.43 ^ _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.04 0.00 0.43 ^ _339_/A (sky130_fd_sc_hd__buf_2)
0.03 0.07 0.50 ^ _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.03 0.00 0.50 ^ _460_/D (sky130_fd_sc_hd__dfrtp_2)
0.50 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.50 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.26 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.14 0.29 0.30 ^ _469_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.04 pll_control.tint[4] (net)
0.14 0.00 0.30 ^ _228_/A (sky130_fd_sc_hd__buf_2)
0.17 0.18 0.48 ^ _228_/X (sky130_fd_sc_hd__buf_2)
7 0.05 _052_ (net)
0.17 0.00 0.48 ^ _311_/A1 (sky130_fd_sc_hd__o22a_2)
0.02 0.09 0.57 ^ _311_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.02 0.00 0.57 ^ _469_/D (sky130_fd_sc_hd__dfrtp_2)
0.57 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.57 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.33 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.26 0.26 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[2] (net)
0.09 0.00 0.27 ^ _273_/A (sky130_fd_sc_hd__buf_2)
0.14 0.15 0.42 ^ _273_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _097_ (net)
0.14 0.00 0.42 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.02 0.10 0.52 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.02 0.00 0.52 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.58 ^ _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.02 0.00 0.58 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.34 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
min_report_end
max_report
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.22 0.34 6.27 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.22 0.00 6.27 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.76 7.03 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.09 0.00 7.03 v _315_/A (sky130_fd_sc_hd__buf_2)
0.04 0.25 7.28 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.04 0.00 7.28 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
7.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.10 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.22 0.34 6.27 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.22 0.00 6.27 ^ _326_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 7.03 v _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.09 0.00 7.03 v _327_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 7.27 v _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.04 0.00 7.27 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
7.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.18 data required time
-7.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.10 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.22 0.34 6.27 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.22 0.00 6.27 ^ _317_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.75 7.02 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.08 0.00 7.02 v _318_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 7.27 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.05 0.00 7.27 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
7.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-7.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.09 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _304_/A1 (sky130_fd_sc_hd__a21o_2)
0.12 0.49 5.13 v _304_/X (sky130_fd_sc_hd__a21o_2)
3 0.02 _128_ (net)
0.12 0.00 5.13 v _305_/A3 (sky130_fd_sc_hd__a32o_2)
0.14 0.60 5.73 v _305_/X (sky130_fd_sc_hd__a32o_2)
3 0.02 _129_ (net)
0.14 0.00 5.73 v _307_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.55 6.29 v _307_/X (sky130_fd_sc_hd__a32o_2)
2 0.01 _131_ (net)
0.09 0.00 6.29 v _309_/A (sky130_fd_sc_hd__and2_2)
0.07 0.38 6.66 v _309_/X (sky130_fd_sc_hd__and2_2)
1 0.00 _133_ (net)
0.07 0.00 6.66 v _311_/B1 (sky130_fd_sc_hd__o22a_2)
0.07 0.39 7.05 v _311_/X (sky130_fd_sc_hd__o22a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _037_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 7.05 v _469_/D (sky130_fd_sc_hd__dfrtp_2)
7.05 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.05 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.89 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.22 0.34 6.27 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.22 0.00 6.27 ^ _323_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.08 0.50 6.76 v _323_/X (sky130_fd_sc_hd__o2bb2a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _033_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 6.77 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
6.77 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.26 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.16 data required time
-6.77 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.61 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.22 0.34 6.27 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.22 0.00 6.27 ^ _328_/B (sky130_fd_sc_hd__nand2_2)
0.07 0.16 6.42 v _328_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _146_ (net)
0.07 0.00 6.42 v _329_/B1 (sky130_fd_sc_hd__o21a_2)
0.06 0.22 6.64 v _329_/X (sky130_fd_sc_hd__o21a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.06 0.00 6.64 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
6.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-6.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.47 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _320_/C1 (sky130_fd_sc_hd__o211a_2)
0.13 0.42 6.35 ^ _320_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _141_ (net)
0.13 0.00 6.36 ^ _321_/B (sky130_fd_sc_hd__xnor2_2)
0.12 0.16 6.51 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.12 0.00 6.51 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
6.51 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.28 6.14 library setup time
6.14 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.14 data required time
-6.51 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.37 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.92 0.93 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.93 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.32 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.32 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.57 1.90 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.90 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.39 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.39 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.17 0.21 2.60 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.17 0.00 2.60 ^ _337_/B1 (sky130_fd_sc_hd__o21ai_2)
0.06 0.13 2.73 v _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.06 0.00 2.73 v _338_/B (sky130_fd_sc_hd__and2_2)
0.09 0.44 3.17 v _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.09 0.00 3.17 v _339_/A (sky130_fd_sc_hd__buf_2)
0.06 0.26 3.43 v _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.06 0.00 3.43 v _460_/D (sky130_fd_sc_hd__dfrtp_2)
3.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.74 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.26 0.45 2.11 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.26 0.00 2.11 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.78 2.89 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.09 0.00 2.89 v _218_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 3.14 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.05 0.00 3.14 v _477_/D (sky130_fd_sc_hd__dfrtp_2)
3.14 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.14 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.03 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.92 0.93 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.93 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.32 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.32 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.57 1.90 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.90 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.39 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.39 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.17 0.21 2.60 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.17 0.00 2.60 ^ _342_/C (sky130_fd_sc_hd__nand3_2)
0.11 0.18 2.78 v _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.11 0.00 2.78 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
2.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.27 6.15 library setup time
6.15 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.15 data required time
-2.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.92 0.93 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.93 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.32 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.32 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.57 1.90 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.90 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.39 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.39 v _332_/A2 (sky130_fd_sc_hd__o21a_2)
0.06 0.39 2.78 v _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.06 0.00 2.78 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
2.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-2.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.39 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.92 0.93 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.93 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.32 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.32 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.57 1.90 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.90 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.39 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.39 v _333_/B (sky130_fd_sc_hd__nand2b_2)
0.07 0.12 2.51 ^ _333_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _149_ (net)
0.07 0.00 2.51 ^ _334_/B1 (sky130_fd_sc_hd__o211a_2)
0.07 0.37 2.88 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _029_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 2.88 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
2.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.13 6.29 library setup time
6.29 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.29 data required time
-2.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.41 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _226_/S (sky130_fd_sc_hd__mux2_2)
0.11 0.82 2.48 v _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.11 0.00 2.48 v _227_/A (sky130_fd_sc_hd__buf_2)
0.05 0.27 2.75 v _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.05 0.00 2.75 v _473_/D (sky130_fd_sc_hd__dfrtp_2)
2.75 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-2.75 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.42 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.92 0.93 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.93 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.32 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.32 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.57 1.90 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.90 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.39 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.39 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.17 0.21 2.60 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.17 0.00 2.60 ^ _341_/A1 (sky130_fd_sc_hd__a21boi_2)
0.08 0.13 2.73 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.08 0.00 2.73 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
2.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.26 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.16 data required time
-2.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.43 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _223_/S (sky130_fd_sc_hd__mux2_2)
0.10 0.81 2.47 v _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.10 0.00 2.47 v _224_/A (sky130_fd_sc_hd__buf_2)
0.05 0.26 2.72 v _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.05 0.00 2.73 v _474_/D (sky130_fd_sc_hd__dfrtp_2)
2.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.45 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _219_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.79 2.45 v _219_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.09 0.00 2.45 v _220_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 2.70 v _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.05 0.00 2.70 v _476_/D (sky130_fd_sc_hd__dfrtp_2)
2.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.47 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _345_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.77 2.43 v _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.08 0.00 2.43 v _346_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 2.68 v _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.05 0.00 2.68 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
2.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-2.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _343_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.77 2.43 v _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.08 0.00 2.43 v _344_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 2.67 v _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.04 0.00 2.67 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
2.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.50 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _221_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 2.43 v _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.09 0.00 2.43 v _222_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 2.67 v _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.04 0.00 2.67 v _475_/D (sky130_fd_sc_hd__dfrtp_2)
2.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.18 data required time
-2.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.51 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.18 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.18 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.29 0.43 1.66 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.29 0.00 1.66 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.26 0.45 2.11 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.26 0.00 2.11 ^ _347_/B (sky130_fd_sc_hd__nand2b_2)
0.08 0.16 2.26 v _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 2.26 v _455_/D (sky130_fd_sc_hd__dfrtp_2)
2.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.26 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.16 data required time
-2.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.89 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.94 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.12 0.00 0.95 v _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.95 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.28 6.14 library setup time
6.14 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.14 data required time
-0.95 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.19 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.87 0.87 v _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.87 v _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.26 6.16 library setup time
6.16 data required time
-----------------------------------------------------------------------------
6.16 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.29 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.20 2.58 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.58 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.84 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.84 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.05 0.16 3.00 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.05 0.00 3.00 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.19 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.19 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.36 3.55 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.05 0.00 3.55 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 3.67 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 3.67 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.65 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.20 2.58 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.58 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.84 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.84 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.05 0.16 3.00 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.05 0.00 3.00 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.19 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.19 ^ _326_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.36 3.55 v _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.05 0.00 3.55 v _327_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 3.67 v _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 3.67 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.65 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.20 2.58 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.58 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.84 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.84 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.05 0.16 3.00 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.05 0.00 3.00 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.19 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.19 ^ _317_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.36 3.55 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.04 0.00 3.55 v _318_/A (sky130_fd_sc_hd__buf_2)
0.03 0.12 3.67 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.03 0.00 3.67 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.33 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.66 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _304_/A1 (sky130_fd_sc_hd__a21o_2)
0.06 0.26 2.64 v _304_/X (sky130_fd_sc_hd__a21o_2)
3 0.02 _128_ (net)
0.06 0.00 2.64 v _305_/A3 (sky130_fd_sc_hd__a32o_2)
0.08 0.33 2.97 v _305_/X (sky130_fd_sc_hd__a32o_2)
3 0.02 _129_ (net)
0.08 0.00 2.97 v _307_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.30 3.27 v _307_/X (sky130_fd_sc_hd__a32o_2)
2 0.01 _131_ (net)
0.05 0.00 3.27 v _309_/A (sky130_fd_sc_hd__and2_2)
0.04 0.17 3.44 v _309_/X (sky130_fd_sc_hd__and2_2)
1 0.00 _133_ (net)
0.04 0.00 3.44 v _311_/B1 (sky130_fd_sc_hd__o22a_2)
0.03 0.20 3.64 v _311_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.03 0.00 3.64 v _469_/D (sky130_fd_sc_hd__dfrtp_2)
3.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-3.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.68 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.20 2.58 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.58 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.84 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.84 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.05 0.16 3.00 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.05 0.00 3.00 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.19 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.19 ^ _323_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.04 0.24 3.43 v _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.04 0.00 3.43 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
3.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
6.32 data required time
-----------------------------------------------------------------------------
6.32 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.89 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.20 2.58 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.58 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.84 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.84 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.05 0.16 3.00 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.05 0.00 3.00 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.19 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.19 ^ _328_/B (sky130_fd_sc_hd__nand2_2)
0.04 0.07 3.26 v _328_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _146_ (net)
0.04 0.00 3.26 v _329_/B1 (sky130_fd_sc_hd__o21a_2)
0.04 0.11 3.37 v _329_/X (sky130_fd_sc_hd__o21a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 3.37 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
3.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-3.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.95 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.20 2.58 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.58 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.84 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.84 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.05 0.16 3.00 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.05 0.00 3.00 ^ _320_/C1 (sky130_fd_sc_hd__o211a_2)
0.07 0.20 3.19 ^ _320_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _141_ (net)
0.07 0.00 3.19 ^ _321_/B (sky130_fd_sc_hd__xnor2_2)
0.14 0.12 3.31 ^ _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.14 0.00 3.31 ^ _466_/D (sky130_fd_sc_hd__dfrtp_2)
3.31 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.08 6.34 library setup time
6.34 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.34 data required time
-3.31 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.03 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.45 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.45 v _225_/A (sky130_fd_sc_hd__buf_2)
0.09 0.20 0.65 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.09 0.00 0.65 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.92 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.93 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.16 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.16 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.28 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.11 0.00 1.28 ^ _337_/B1 (sky130_fd_sc_hd__o21ai_2)
0.04 0.06 1.34 v _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.04 0.00 1.34 v _338_/B (sky130_fd_sc_hd__and2_2)
0.05 0.20 1.55 v _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.05 0.00 1.55 v _339_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.68 v _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.03 0.00 1.68 v _460_/D (sky130_fd_sc_hd__dfrtp_2)
1.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.65 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.88 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.16 0.25 1.12 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.16 0.00 1.13 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 1.50 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.05 0.00 1.50 v _218_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.62 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.03 0.00 1.62 v _477_/D (sky130_fd_sc_hd__dfrtp_2)
1.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.33 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.70 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.88 ^ _226_/S (sky130_fd_sc_hd__mux2_2)
0.06 0.39 1.26 v _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.06 0.00 1.27 v _227_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.40 v _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.03 0.00 1.40 v _473_/D (sky130_fd_sc_hd__dfrtp_2)
1.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.01 6.67 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.93 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.88 ^ _223_/S (sky130_fd_sc_hd__mux2_2)
0.06 0.38 1.26 v _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.06 0.00 1.26 v _224_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.39 v _224_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _039_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 1.39 v _474_/D (sky130_fd_sc_hd__dfrtp_2)
1.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.33 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.94 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.88 ^ _219_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.38 1.25 v _219_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.05 0.00 1.25 v _220_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.38 v _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.03 0.00 1.38 v _476_/D (sky130_fd_sc_hd__dfrtp_2)
1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.33 data required time
-1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.95 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.45 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.45 v _225_/A (sky130_fd_sc_hd__buf_2)
0.09 0.20 0.65 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.09 0.00 0.65 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.92 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.93 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.16 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.16 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.28 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.11 0.00 1.28 ^ _342_/C (sky130_fd_sc_hd__nand3_2)
0.06 0.08 1.36 v _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.06 0.00 1.36 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.11 6.31 library setup time
6.31 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.31 data required time
-1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.95 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.88 ^ _345_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.36 1.24 v _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.04 0.00 1.24 v _346_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.37 v _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.03 0.00 1.37 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
1.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.45 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.45 v _225_/A (sky130_fd_sc_hd__buf_2)
0.09 0.20 0.65 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.09 0.00 0.65 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.92 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.93 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.16 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.16 v _332_/A2 (sky130_fd_sc_hd__o21a_2)
0.03 0.20 1.36 v _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.03 0.00 1.36 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.87 ^ _343_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.36 1.24 v _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.04 0.00 1.24 v _344_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.36 v _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 1.36 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.09 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.36 data arrival time
-----------------------------------------------------------------------------
4.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.88 ^ _221_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 1.24 v _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.05 0.00 1.24 v _222_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.36 v _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 1.36 v _475_/D (sky130_fd_sc_hd__dfrtp_2)
1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.33 data required time
-1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.97 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.45 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.45 v _225_/A (sky130_fd_sc_hd__buf_2)
0.09 0.20 0.65 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.09 0.00 0.65 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.92 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.93 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.16 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.16 v _333_/B (sky130_fd_sc_hd__nand2b_2)
0.04 0.07 1.23 ^ _333_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _149_ (net)
0.04 0.00 1.23 ^ _334_/B1 (sky130_fd_sc_hd__o211a_2)
0.04 0.16 1.39 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.04 0.00 1.39 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
1.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.05 6.37 library setup time
6.37 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.37 data required time
-1.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.97 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.45 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.45 v _225_/A (sky130_fd_sc_hd__buf_2)
0.09 0.20 0.65 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.09 0.00 0.65 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.92 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.93 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.16 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.16 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.28 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.11 0.00 1.28 ^ _341_/A1 (sky130_fd_sc_hd__a21boi_2)
0.04 0.06 1.34 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.04 0.00 1.34 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
1.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.98 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.18 0.25 0.87 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.18 0.00 0.88 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.16 0.25 1.12 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.16 0.00 1.12 ^ _347_/B (sky130_fd_sc_hd__nand2b_2)
0.04 0.07 1.19 v _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 1.19 v _455_/D (sky130_fd_sc_hd__dfrtp_2)
1.19 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.19 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.12 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.46 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.46 v _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.46 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.11 6.31 library setup time
6.31 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.31 data required time
-0.46 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.84 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.42 0.42 v _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 0.42 v _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.42 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
6.32 data required time
-----------------------------------------------------------------------------
6.32 data required time
-0.42 data arrival time
-----------------------------------------------------------------------------
5.90 slack (MET)
======================= Fastest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.61 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.61 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.77 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.77 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.85 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.85 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 1.98 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 1.98 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.19 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.03 0.00 2.19 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.27 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 2.27 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.08 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.61 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.61 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.77 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.77 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.85 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.85 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 1.98 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 1.98 ^ _326_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.19 v _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.03 0.00 2.19 v _327_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.27 v _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 2.27 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.09 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.61 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.61 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.77 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.77 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.85 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.85 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 1.98 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 1.98 ^ _317_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.19 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.03 0.00 2.19 v _318_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.27 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.02 0.00 2.27 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.09 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _304_/A1 (sky130_fd_sc_hd__a21o_2)
0.05 0.17 1.65 v _304_/X (sky130_fd_sc_hd__a21o_2)
3 0.02 _128_ (net)
0.05 0.00 1.65 v _305_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.17 1.83 v _305_/X (sky130_fd_sc_hd__a32o_2)
3 0.02 _129_ (net)
0.05 0.00 1.83 v _307_/A3 (sky130_fd_sc_hd__a32o_2)
0.03 0.16 1.98 v _307_/X (sky130_fd_sc_hd__a32o_2)
2 0.01 _131_ (net)
0.03 0.00 1.98 v _309_/A (sky130_fd_sc_hd__and2_2)
0.03 0.11 2.09 v _309_/X (sky130_fd_sc_hd__and2_2)
1 0.00 _133_ (net)
0.03 0.00 2.09 v _311_/B1 (sky130_fd_sc_hd__o22a_2)
0.02 0.12 2.21 v _311_/X (sky130_fd_sc_hd__o22a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _037_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 2.21 v _469_/D (sky130_fd_sc_hd__dfrtp_2)
2.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.61 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.61 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.77 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.77 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.85 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.85 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 1.98 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 1.98 ^ _323_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.03 0.14 2.12 v _323_/X (sky130_fd_sc_hd__o2bb2a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _033_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 2.12 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
2.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.35 data required time
-2.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.23 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.61 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.61 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.77 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.77 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.85 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.85 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 1.98 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 1.98 ^ _328_/B (sky130_fd_sc_hd__nand2_2)
0.03 0.03 2.01 v _328_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _146_ (net)
0.03 0.00 2.01 v _329_/B1 (sky130_fd_sc_hd__o21a_2)
0.03 0.07 2.09 v _329_/X (sky130_fd_sc_hd__o21a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 2.09 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
2.09 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.35 data required time
-2.09 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.27 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _272_/A (sky130_fd_sc_hd__buf_2)
0.08 0.16 1.64 v _272_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _096_ (net)
0.08 0.00 1.64 v _292_/A2 (sky130_fd_sc_hd__o31a_2)
0.04 0.23 1.87 v _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.87 v _320_/C1 (sky130_fd_sc_hd__o211a_2)
0.04 0.09 1.96 v _320_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _141_ (net)
0.04 0.00 1.96 v _321_/B (sky130_fd_sc_hd__xnor2_2)
0.05 0.09 2.05 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.05 0.00 2.05 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
2.05 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.08 6.34 library setup time
6.34 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.34 data required time
-2.05 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.29 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.28 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.42 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.17 0.59 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.59 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.74 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.74 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.83 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.08 0.00 0.83 ^ _337_/B1 (sky130_fd_sc_hd__o21ai_2)
0.02 0.02 0.85 v _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.02 0.00 0.85 v _338_/B (sky130_fd_sc_hd__and2_2)
0.03 0.13 0.98 v _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.03 0.00 0.98 v _339_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 1.06 v _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.02 0.00 1.06 v _460_/D (sky130_fd_sc_hd__dfrtp_2)
1.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.36 data required time
-1.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.29 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.12 0.17 0.75 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.12 0.00 0.75 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.22 0.96 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.03 0.00 0.96 v _218_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 1.04 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.02 0.00 1.04 v _477_/D (sky130_fd_sc_hd__dfrtp_2)
1.04 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.04 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.31 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _226_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.23 0.81 v _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.04 0.00 0.81 v _227_/A (sky130_fd_sc_hd__buf_2)
0.02 0.09 0.89 v _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.02 0.00 0.89 v _473_/D (sky130_fd_sc_hd__dfrtp_2)
0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 6.67 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.36 data required time
-0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.46 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _223_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.22 0.80 v _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.04 0.00 0.81 v _224_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.89 v _224_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _039_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 0.89 v _474_/D (sky130_fd_sc_hd__dfrtp_2)
0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.01 6.67 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.47 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.28 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.42 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.17 0.59 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.59 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.74 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.74 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.83 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.08 0.00 0.83 ^ _342_/C (sky130_fd_sc_hd__nand3_2)
0.04 0.04 0.87 v _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.04 0.00 0.87 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.47 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _219_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.22 0.80 v _219_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.04 0.00 0.80 v _220_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.88 v _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.02 0.00 0.88 v _476_/D (sky130_fd_sc_hd__dfrtp_2)
0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.48 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _345_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.79 v _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.03 0.00 0.79 v _346_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.87 v _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.02 0.00 0.87 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.48 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _343_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.79 v _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.03 0.00 0.79 v _344_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.87 v _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 0.87 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 6.35 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.28 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.42 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.17 0.59 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.59 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.74 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.74 v _332_/A2 (sky130_fd_sc_hd__o21a_2)
0.02 0.12 0.87 v _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.02 0.00 0.87 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.28 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.42 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.17 0.59 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.59 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.74 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.74 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.83 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.08 0.00 0.83 ^ _341_/A1 (sky130_fd_sc_hd__a21boi_2)
0.03 0.03 0.86 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.03 0.00 0.86 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.86 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.86 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _221_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.79 v _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.03 0.00 0.79 v _222_/A (sky130_fd_sc_hd__buf_2)
0.02 0.07 0.87 v _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 0.87 v _475_/D (sky130_fd_sc_hd__dfrtp_2)
0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.28 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.42 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.17 0.59 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.59 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.74 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.74 v _333_/B (sky130_fd_sc_hd__nand2b_2)
0.03 0.05 0.79 ^ _333_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _149_ (net)
0.03 0.00 0.79 ^ _334_/B1 (sky130_fd_sc_hd__o211a_2)
0.03 0.08 0.87 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.03 0.00 0.87 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 6.39 library setup time
6.39 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.39 data required time
-0.87 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.51 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.41 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.14 0.17 0.58 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.14 0.00 0.58 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.12 0.17 0.75 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.12 0.00 0.75 ^ _347_/B (sky130_fd_sc_hd__nand2b_2)
0.03 0.03 0.78 v _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.78 v _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.35 data required time
-0.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.57 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.29 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.29 v _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.08 6.34 library setup time
6.34 data required time
-----------------------------------------------------------------------------
6.34 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.05 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.26 0.26 v _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.26 v _471_/D (sky130_fd_sc_hd__dfrtp_2)
0.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
6.09 slack (MET)
max_report_end
check_report
===========================================================================
report_checks -unconstrained
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.22 0.34 6.27 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.22 0.00 6.27 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.76 7.03 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.09 0.00 7.03 v _315_/A (sky130_fd_sc_hd__buf_2)
0.04 0.25 7.28 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.04 0.00 7.28 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
7.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.10 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.51 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.10 0.24 0.75 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.10 0.00 0.75 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.15 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.15 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.37 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.37 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.77 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.77 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.94 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.94 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.11 0.44 2.38 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.11 0.00 2.38 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.20 2.58 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.58 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.84 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.84 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.05 0.16 3.00 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.05 0.00 3.00 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.19 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.19 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.36 3.55 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.05 0.00 3.55 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 3.67 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 3.67 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 0.00 6.67 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.65 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.32 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.48 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.73 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.73 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.87 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.87 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.10 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.10 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.21 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.21 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.48 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.48 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.61 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.61 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.77 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.77 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.85 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.85 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 1.98 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 1.98 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.19 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.03 0.00 2.19 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.27 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 2.27 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 6.67 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.08 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 0.00 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.04 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.04 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.20 0.45 1.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.20 0.00 1.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.25 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.25 v _240_/B (sky130_fd_sc_hd__and3_2)
0.09 0.48 2.73 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.09 0.00 2.73 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.13 0.76 3.49 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.13 0.00 3.49 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.80 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.80 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.83 4.64 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.64 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.07 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.07 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.53 5.61 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.61 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.09 0.32 5.93 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.09 0.00 5.93 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.22 0.34 6.27 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.22 0.00 6.27 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.76 7.03 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.09 0.00 7.03 v _315_/A (sky130_fd_sc_hd__buf_2)
0.04 0.25 7.28 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.04 0.00 7.28 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
7.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.14 0.00 6.67 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.10 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
No paths found.
======================= Fastest Corner ===================================
No paths found.
check_report_end
check_slew
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= Slowest Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
dco 7 14 -7 (VIOLATED)
div[3] 7 8 (VIOLATED)
_426_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
dco 7 14 -7 (VIOLATED)
div[3] 7 8 (VIOLATED)
_426_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
dco 7 14 -7 (VIOLATED)
div[3] 7 8 (VIOLATED)
_426_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
max slew violation count 0
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
max fanout violation count 4
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
max cap violation count 0
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
============================================================================
check_slew_end
tns_report
===========================================================================
report_tns
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
tns -5.63
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
tns_report_end
wns_report
===========================================================================
report_wns
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
wns -1.10
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
wns_report_end
worst_slack
===========================================================================
report_worst_slack -max (Setup)
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
worst slack -1.10
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
report_worst_slack -min (Hold)
============================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
worst slack -0.02
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
worst_slack_end
power_report
===========================================================================
report_power
============================================================================
======================= Slowest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Sequential 1.15e-04 1.41e-05 3.37e-07 1.29e-04 27.0%
Combinational 1.54e-04 1.94e-04 1.72e-06 3.50e-04 73.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Total 2.69e-04 2.08e-04 2.05e-06 4.80e-04 100.0%
56.2% 43.4% 0.4%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Sequential 1.50e-04 1.79e-05 1.84e-10 1.68e-04 27.8%
Combinational 1.88e-04 2.47e-04 1.37e-09 4.35e-04 72.2%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Total 3.38e-04 2.65e-04 1.55e-09 6.03e-04 100.0%
56.0% 44.0% 0.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Sequential 1.74e-04 2.12e-05 3.12e-10 1.95e-04 28.0%
Combinational 2.10e-04 2.93e-04 3.77e-09 5.02e-04 72.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Total 3.84e-04 3.14e-04 4.08e-09 6.98e-04 100.0%
55.0% 45.0% 0.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
power_report_end
area_report
===========================================================================
report_design_area
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Design area 3727 u^2 93% utilization.
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF files for all corners...
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Writing SDF for the ff corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/mca/process_corner_nom/digital_pll.ff.sdf...
Writing SDF for the ss corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/mca/process_corner_nom/digital_pll.ss.sdf...
Writing SDF for the tt corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/mca/process_corner_nom/digital_pll.tt.sdf...