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caravel/signoff/digital_pll/openlane-signoff/18-rcx_mcsta.max.log

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reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/digital_pll.odb
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
min_report
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.68 0.68 ^ _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 0.68 ^ _471_/D (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.76 0.76 ^ _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.15 0.00 0.76 ^ _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.76 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.08 0.17 library hold time
0.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 data required time
-0.76 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.59 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.72 0.72 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.01 pll_control.prep[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.73 ^ _347_/A_N (sky130_fd_sc_hd__nand2b_2)
0.06 0.19 0.91 ^ _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.06 0.00 0.91 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
-0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.72 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.78 0.79 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tval[0] (net)
0.17 0.00 0.80 ^ _329_/A1 (sky130_fd_sc_hd__o21a_2)
0.06 0.28 1.08 ^ _329_/X (sky130_fd_sc_hd__o21a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.06 0.00 1.08 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.08 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
-----------------------------------------------------------------------------
0.20 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.08 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.88 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.71 0.71 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.10 0.00 0.71 ^ _343_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.26 0.97 ^ _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.06 0.00 0.97 ^ _344_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.12 ^ _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.05 0.00 1.12 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
1.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.93 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.26 0.85 0.86 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.26 0.00 0.86 ^ _332_/A1 (sky130_fd_sc_hd__o21a_2)
0.05 0.30 1.16 ^ _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.05 0.00 1.16 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
1.16 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.16 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.72 0.72 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.11 0.00 0.72 ^ _345_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.26 0.98 ^ _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.06 0.00 0.98 ^ _346_/A (sky130_fd_sc_hd__buf_2)
0.06 0.17 1.15 ^ _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.06 0.00 1.15 ^ _456_/D (sky130_fd_sc_hd__dfrtp_2)
1.15 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.15 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.73 0.74 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.tval[1] (net)
0.12 0.00 0.74 ^ _326_/A0 (sky130_fd_sc_hd__mux2_2)
0.07 0.28 1.01 ^ _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.07 0.00 1.01 ^ _327_/A (sky130_fd_sc_hd__buf_2)
0.04 0.16 1.17 ^ _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.04 0.00 1.17 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.97 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.76 0.77 ^ _475_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[2] (net)
0.15 0.00 0.77 ^ _221_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.28 1.06 ^ _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.06 0.00 1.06 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.04 0.15 1.21 ^ _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.04 0.00 1.21 ^ _475_/D (sky130_fd_sc_hd__dfrtp_2)
1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.01 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.21 0.81 0.82 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[3] (net)
0.21 0.00 0.82 ^ _334_/A1 (sky130_fd_sc_hd__o211a_2)
0.07 0.39 1.21 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _029_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 1.21 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 data required time
-1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.02 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.24 0.83 0.84 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.03 pll_control.tint[0] (net)
0.24 0.00 0.84 ^ _323_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.07 0.37 1.22 ^ _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.07 0.00 1.22 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
1.22 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.22 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.02 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.26 0.85 0.86 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.26 0.00 0.86 ^ _336_/A (sky130_fd_sc_hd__nand2_2)
0.16 0.23 1.09 v _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.16 0.00 1.09 v _342_/C (sky130_fd_sc_hd__nand3_2)
0.07 0.14 1.22 ^ _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.07 0.00 1.22 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
1.22 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 data required time
-1.22 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.03 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.76 0.77 ^ _474_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.15 0.00 0.77 ^ _223_/A1 (sky130_fd_sc_hd__mux2_2)
0.09 0.31 1.08 ^ _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.09 0.00 1.08 ^ _224_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.26 ^ _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.05 0.00 1.26 ^ _474_/D (sky130_fd_sc_hd__dfrtp_2)
1.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.26 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.06 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.29 0.87 0.87 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.29 0.00 0.87 ^ _340_/A (sky130_fd_sc_hd__xnor2_2)
0.08 0.27 1.15 ^ _340_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _154_ (net)
0.08 0.00 1.15 ^ _341_/A2 (sky130_fd_sc_hd__a21boi_2)
0.06 0.10 1.25 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.06 0.00 1.25 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
1.25 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.07 0.19 library hold time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.25 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.06 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.78 0.79 ^ _476_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[3] (net)
0.17 0.00 0.79 ^ _219_/A1 (sky130_fd_sc_hd__mux2_2)
0.08 0.31 1.10 ^ _219_/X (sky130_fd_sc_hd__mux2_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _047_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 1.10 ^ _220_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.27 ^ _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.05 0.00 1.27 ^ _476_/D (sky130_fd_sc_hd__dfrtp_2)
1.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
-----------------------------------------------------------------------------
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.07 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.19 0.80 0.81 ^ _477_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.count1[4] (net)
0.19 0.00 0.81 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.07 0.31 1.12 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.07 0.00 1.12 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.29 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.05 0.00 1.29 ^ _477_/D (sky130_fd_sc_hd__dfrtp_2)
1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.09 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.21 0.81 0.82 ^ _468_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[3] (net)
0.21 0.00 0.82 ^ _314_/A0 (sky130_fd_sc_hd__mux2_2)
0.07 0.31 1.14 ^ _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.07 0.00 1.14 ^ _315_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.30 ^ _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.05 0.00 1.30 ^ _468_/D (sky130_fd_sc_hd__dfrtp_2)
1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.10 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.78 0.79 ^ _473_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[0] (net)
0.17 0.00 0.79 ^ _226_/A1 (sky130_fd_sc_hd__mux2_2)
0.10 0.33 1.12 ^ _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.10 0.00 1.12 ^ _227_/A (sky130_fd_sc_hd__buf_2)
0.07 0.19 1.31 ^ _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.07 0.00 1.31 ^ _473_/D (sky130_fd_sc_hd__dfrtp_2)
1.31 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 data required time
-1.31 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.16 0.77 0.77 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.02 pll_control.tint[1] (net)
0.16 0.00 0.77 ^ _275_/A (sky130_fd_sc_hd__inv_2)
0.20 0.22 0.99 v _275_/Y (sky130_fd_sc_hd__inv_2)
7 0.05 _099_ (net)
0.20 0.00 0.99 v _321_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.30 1.29 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.09 0.00 1.29 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.08 0.17 library hold time
0.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 data required time
-1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.21 0.81 0.82 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[2] (net)
0.21 0.00 0.82 ^ _335_/B1 (sky130_fd_sc_hd__a21oi_2)
0.07 0.10 0.93 v _335_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _150_ (net)
0.07 0.00 0.93 v _337_/A2 (sky130_fd_sc_hd__o21ai_2)
0.07 0.15 1.08 ^ _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.07 0.00 1.08 ^ _338_/B (sky130_fd_sc_hd__and2_2)
0.10 0.28 1.36 ^ _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.10 0.00 1.36 ^ _339_/A (sky130_fd_sc_hd__buf_2)
0.07 0.19 1.55 ^ _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.07 0.00 1.55 ^ _460_/D (sky130_fd_sc_hd__dfrtp_2)
1.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.21 0.81 0.82 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[2] (net)
0.21 0.00 0.82 ^ _273_/A (sky130_fd_sc_hd__buf_2)
0.31 0.41 1.23 ^ _273_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _097_ (net)
0.31 0.00 1.23 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.06 0.34 1.57 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.06 0.00 1.57 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.74 ^ _318_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _035_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.05 0.00 1.74 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
1.74 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.74 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.54 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.31 0.88 0.89 ^ _469_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.04 pll_control.tint[4] (net)
0.31 0.00 0.89 ^ _228_/A (sky130_fd_sc_hd__buf_2)
0.37 0.49 1.38 ^ _228_/X (sky130_fd_sc_hd__buf_2)
7 0.05 _052_ (net)
0.37 0.00 1.38 ^ _311_/A1 (sky130_fd_sc_hd__o22a_2)
0.05 0.37 1.76 ^ _311_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.05 0.00 1.76 ^ _469_/D (sky130_fd_sc_hd__dfrtp_2)
1.76 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.76 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
1.56 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.34 0.34 ^ _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 0.34 ^ _471_/D (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.03 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.23 data required time
-0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
0.11 slack (MET)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.38 ^ _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.09 0.00 0.39 ^ _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.04 0.22 library hold time
0.22 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.22 data required time
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.36 0.36 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.07 0.00 0.36 ^ _347_/A_N (sky130_fd_sc_hd__nand2b_2)
0.03 0.10 0.47 ^ _347_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _023_ (net)
0.03 0.00 0.47 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.47 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.47 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.40 0.40 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tval[0] (net)
0.11 0.00 0.41 ^ _329_/A1 (sky130_fd_sc_hd__o21a_2)
0.03 0.13 0.54 ^ _329_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.03 0.00 0.54 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
0.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.31 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.35 0.35 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.06 0.00 0.35 ^ _343_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.13 0.48 ^ _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.03 0.00 0.48 ^ _344_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.56 ^ _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.03 0.00 0.56 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.33 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.16 0.43 0.44 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.16 0.00 0.45 ^ _332_/A1 (sky130_fd_sc_hd__o21a_2)
0.03 0.14 0.59 ^ _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.03 0.00 0.59 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.35 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.36 0.36 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.06 0.00 0.36 ^ _345_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.13 0.49 ^ _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.03 0.00 0.49 ^ _346_/A (sky130_fd_sc_hd__buf_2)
0.04 0.09 0.58 ^ _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.04 0.00 0.58 ^ _456_/D (sky130_fd_sc_hd__dfrtp_2)
0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.03 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.35 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.36 0.37 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.tval[1] (net)
0.07 0.00 0.37 ^ _326_/A0 (sky130_fd_sc_hd__mux2_2)
0.04 0.14 0.51 ^ _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.04 0.00 0.51 ^ _327_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.59 ^ _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.03 0.00 0.59 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.41 0.42 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[3] (net)
0.13 0.00 0.42 ^ _334_/A1 (sky130_fd_sc_hd__o211a_2)
0.04 0.17 0.60 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.04 0.00 0.60 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.39 ^ _475_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[2] (net)
0.09 0.00 0.39 ^ _221_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.14 0.53 ^ _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.03 0.00 0.53 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.62 ^ _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.03 0.00 0.62 ^ _475_/D (sky130_fd_sc_hd__dfrtp_2)
0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.38 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.43 0.44 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.03 pll_control.tint[0] (net)
0.15 0.00 0.44 ^ _323_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.04 0.18 0.62 ^ _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.04 0.00 0.62 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.38 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.16 0.43 0.44 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.16 0.00 0.45 ^ _336_/A (sky130_fd_sc_hd__nand2_2)
0.08 0.11 0.55 v _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.08 0.00 0.55 v _342_/C (sky130_fd_sc_hd__nand3_2)
0.04 0.07 0.63 ^ _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.04 0.00 0.63 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.03 0.23 library hold time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.18 0.45 0.45 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.18 0.00 0.45 ^ _340_/A (sky130_fd_sc_hd__xnor2_2)
0.05 0.13 0.59 ^ _340_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _154_ (net)
0.05 0.00 0.59 ^ _341_/A2 (sky130_fd_sc_hd__a21boi_2)
0.03 0.04 0.63 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.03 0.00 0.63 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.39 ^ _474_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.09 0.00 0.39 ^ _223_/A1 (sky130_fd_sc_hd__mux2_2)
0.05 0.15 0.55 ^ _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.05 0.00 0.55 ^ _224_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.64 ^ _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.03 0.00 0.64 ^ _474_/D (sky130_fd_sc_hd__dfrtp_2)
0.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.40 ^ _476_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[3] (net)
0.10 0.00 0.40 ^ _219_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.15 0.56 ^ _219_/X (sky130_fd_sc_hd__mux2_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _047_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 0.56 ^ _220_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.65 ^ _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.03 0.00 0.65 ^ _476_/D (sky130_fd_sc_hd__dfrtp_2)
0.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.41 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.40 0.41 ^ _477_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.count1[4] (net)
0.11 0.00 0.41 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.16 0.57 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.04 0.00 0.57 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.66 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.03 0.00 0.66 ^ _477_/D (sky130_fd_sc_hd__dfrtp_2)
0.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.42 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.41 0.42 ^ _468_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[3] (net)
0.13 0.00 0.42 ^ _314_/A0 (sky130_fd_sc_hd__mux2_2)
0.04 0.16 0.58 ^ _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.04 0.00 0.58 ^ _315_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.67 ^ _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.03 0.00 0.67 ^ _468_/D (sky130_fd_sc_hd__dfrtp_2)
0.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.43 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.40 ^ _473_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[0] (net)
0.10 0.00 0.40 ^ _226_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.16 0.57 ^ _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.06 0.00 0.57 ^ _227_/A (sky130_fd_sc_hd__buf_2)
0.04 0.10 0.67 ^ _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.04 0.00 0.67 ^ _473_/D (sky130_fd_sc_hd__dfrtp_2)
0.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.24 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.43 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.39 0.39 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.02 pll_control.tint[1] (net)
0.09 0.00 0.39 ^ _275_/A (sky130_fd_sc_hd__inv_2)
0.11 0.11 0.50 v _275_/Y (sky130_fd_sc_hd__inv_2)
7 0.05 _099_ (net)
0.11 0.00 0.50 v _321_/A (sky130_fd_sc_hd__xnor2_2)
0.05 0.16 0.66 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.05 0.00 0.66 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
0.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.22 library hold time
0.22 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.22 data required time
-0.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.44 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.41 0.42 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[2] (net)
0.13 0.00 0.42 ^ _335_/B1 (sky130_fd_sc_hd__a21oi_2)
0.04 0.04 0.47 v _335_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _150_ (net)
0.04 0.00 0.47 v _337_/A2 (sky130_fd_sc_hd__o21ai_2)
0.04 0.09 0.56 ^ _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.04 0.00 0.56 ^ _338_/B (sky130_fd_sc_hd__and2_2)
0.06 0.14 0.70 ^ _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.06 0.00 0.70 ^ _339_/A (sky130_fd_sc_hd__buf_2)
0.04 0.10 0.80 ^ _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.04 0.00 0.80 ^ _460_/D (sky130_fd_sc_hd__dfrtp_2)
0.80 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.03 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.80 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.57 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.41 0.42 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[2] (net)
0.13 0.00 0.42 ^ _273_/A (sky130_fd_sc_hd__buf_2)
0.19 0.23 0.65 ^ _273_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _097_ (net)
0.19 0.00 0.66 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.17 0.83 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.03 0.00 0.83 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.91 ^ _318_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _035_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.91 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.68 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.19 0.46 0.47 ^ _469_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.04 pll_control.tint[4] (net)
0.19 0.00 0.47 ^ _228_/A (sky130_fd_sc_hd__buf_2)
0.23 0.27 0.74 ^ _228_/X (sky130_fd_sc_hd__buf_2)
7 0.05 _052_ (net)
0.23 0.00 0.74 ^ _311_/A1 (sky130_fd_sc_hd__o22a_2)
0.03 0.18 0.92 ^ _311_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.03 0.00 0.92 ^ _469_/D (sky130_fd_sc_hd__dfrtp_2)
0.92 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.92 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.68 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.21 0.21 ^ _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.21 ^ _471_/D (sky130_fd_sc_hd__dfrtp_2)
0.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.25 ^ _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.25 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.25 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.01 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.23 0.23 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.05 0.00 0.23 ^ _347_/A_N (sky130_fd_sc_hd__nand2b_2)
0.02 0.07 0.30 ^ _347_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _023_ (net)
0.02 0.00 0.30 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.06 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.25 0.26 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tval[0] (net)
0.08 0.00 0.26 ^ _329_/A1 (sky130_fd_sc_hd__o21a_2)
0.02 0.08 0.34 ^ _329_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.02 0.00 0.34 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.10 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.22 0.22 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.04 0.00 0.22 ^ _343_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.08 0.30 ^ _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.02 0.00 0.30 ^ _344_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.36 ^ _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 0.36 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
0.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
-0.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.12 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.26 0.27 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[3] (net)
0.09 0.00 0.27 ^ _334_/A1 (sky130_fd_sc_hd__o211a_2)
0.02 0.10 0.37 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _029_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 0.37 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.13 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.28 0.29 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.12 0.00 0.29 ^ _332_/A1 (sky130_fd_sc_hd__o21a_2)
0.02 0.09 0.38 ^ _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.02 0.00 0.38 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.38 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.38 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.13 slack (MET)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.23 0.23 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.05 0.00 0.23 ^ _345_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.08 0.31 ^ _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.02 0.00 0.31 ^ _346_/A (sky130_fd_sc_hd__buf_2)
0.03 0.06 0.37 ^ _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.03 0.00 0.37 ^ _456_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.13 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.23 0.24 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.tval[1] (net)
0.05 0.00 0.24 ^ _326_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.09 0.33 ^ _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.03 0.00 0.33 ^ _327_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.38 ^ _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 0.38 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _475_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[2] (net)
0.06 0.00 0.26 ^ _221_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.09 0.34 ^ _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.02 0.00 0.34 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.40 ^ _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 0.40 ^ _475_/D (sky130_fd_sc_hd__dfrtp_2)
0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.27 0.28 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.03 pll_control.tint[0] (net)
0.11 0.00 0.29 ^ _323_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.03 0.11 0.40 ^ _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.03 0.00 0.40 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.28 0.29 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[4] (net)
0.12 0.00 0.29 ^ _336_/A (sky130_fd_sc_hd__nand2_2)
0.05 0.06 0.35 v _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.05 0.00 0.35 v _342_/C (sky130_fd_sc_hd__nand3_2)
0.03 0.05 0.41 ^ _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.03 0.00 0.41 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _474_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.06 0.00 0.25 ^ _223_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.10 0.35 ^ _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.03 0.00 0.35 ^ _224_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.41 ^ _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.02 0.00 0.41 ^ _474_/D (sky130_fd_sc_hd__dfrtp_2)
0.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.24 data required time
-0.41 data arrival time
-----------------------------------------------------------------------------
0.17 slack (MET)
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.29 0.29 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.04 pll_control.count0[1] (net)
0.13 0.00 0.30 ^ _340_/A (sky130_fd_sc_hd__xnor2_2)
0.04 0.08 0.38 ^ _340_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _154_ (net)
0.04 0.00 0.38 ^ _341_/A2 (sky130_fd_sc_hd__a21boi_2)
0.02 0.03 0.40 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.02 0.00 0.40 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.40 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.26 ^ _476_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[3] (net)
0.07 0.00 0.26 ^ _219_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.10 0.36 ^ _219_/X (sky130_fd_sc_hd__mux2_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _047_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.36 ^ _220_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.42 ^ _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.02 0.00 0.42 ^ _476_/D (sky130_fd_sc_hd__dfrtp_2)
0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.26 0.27 ^ _477_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.count1[4] (net)
0.08 0.00 0.27 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.10 0.36 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.03 0.00 0.36 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.42 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.02 0.00 0.42 ^ _477_/D (sky130_fd_sc_hd__dfrtp_2)
0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.18 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.26 0.27 ^ _468_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[3] (net)
0.10 0.00 0.28 ^ _314_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.10 0.37 ^ _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.03 0.00 0.37 ^ _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.43 ^ _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 0.43 ^ _468_/D (sky130_fd_sc_hd__dfrtp_2)
0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.26 ^ _473_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.count1[0] (net)
0.07 0.00 0.26 ^ _226_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.10 0.37 ^ _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.04 0.00 0.37 ^ _227_/A (sky130_fd_sc_hd__buf_2)
0.03 0.07 0.43 ^ _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.03 0.00 0.43 ^ _473_/D (sky130_fd_sc_hd__dfrtp_2)
0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.19 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.24 0.25 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.02 pll_control.tint[1] (net)
0.07 0.00 0.25 ^ _275_/A (sky130_fd_sc_hd__inv_2)
0.07 0.07 0.32 v _275_/Y (sky130_fd_sc_hd__inv_2)
7 0.05 _099_ (net)
0.08 0.00 0.32 v _321_/A (sky130_fd_sc_hd__xnor2_2)
0.03 0.11 0.43 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.03 0.00 0.43 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.27 0.27 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[2] (net)
0.10 0.00 0.28 ^ _335_/B1 (sky130_fd_sc_hd__a21oi_2)
0.03 0.02 0.30 v _335_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _150_ (net)
0.03 0.00 0.30 v _337_/A2 (sky130_fd_sc_hd__o21ai_2)
0.02 0.06 0.36 ^ _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.02 0.00 0.36 ^ _338_/B (sky130_fd_sc_hd__and2_2)
0.04 0.09 0.44 ^ _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.04 0.00 0.44 ^ _339_/A (sky130_fd_sc_hd__buf_2)
0.03 0.07 0.51 ^ _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.03 0.00 0.51 ^ _460_/D (sky130_fd_sc_hd__dfrtp_2)
0.51 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.51 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.27 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.14 0.30 0.30 ^ _469_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.04 pll_control.tint[4] (net)
0.14 0.00 0.31 ^ _228_/A (sky130_fd_sc_hd__buf_2)
0.17 0.18 0.49 ^ _228_/X (sky130_fd_sc_hd__buf_2)
7 0.05 _052_ (net)
0.17 0.00 0.49 ^ _311_/A1 (sky130_fd_sc_hd__o22a_2)
0.02 0.09 0.58 ^ _311_/X (sky130_fd_sc_hd__o22a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _037_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 0.58 ^ _469_/D (sky130_fd_sc_hd__dfrtp_2)
0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.58 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.34 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.26 0.27 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[2] (net)
0.09 0.00 0.28 ^ _273_/A (sky130_fd_sc_hd__buf_2)
0.15 0.16 0.43 ^ _273_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _097_ (net)
0.15 0.00 0.44 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.02 0.10 0.54 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.02 0.00 0.54 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.60 ^ _318_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _035_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 0.60 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.35 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
min_report_end
max_report
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.23 0.34 6.31 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.23 0.00 6.31 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 7.08 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.09 0.00 7.08 v _315_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 7.32 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.05 0.00 7.32 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.14 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.23 0.34 6.31 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.23 0.00 6.31 ^ _326_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 7.08 v _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.09 0.00 7.08 v _327_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 7.32 v _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.04 0.00 7.32 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.14 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.23 0.34 6.31 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.23 0.00 6.31 ^ _317_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.75 7.06 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.08 0.00 7.06 v _318_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 7.31 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.05 0.00 7.31 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
7.31 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.25 6.18 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-----------------------------------------------------------------------------
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.31 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.13 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _304_/A1 (sky130_fd_sc_hd__a21o_2)
0.12 0.50 5.17 v _304_/X (sky130_fd_sc_hd__a21o_2)
3 0.02 _128_ (net)
0.12 0.00 5.17 v _305_/A3 (sky130_fd_sc_hd__a32o_2)
0.14 0.60 5.77 v _305_/X (sky130_fd_sc_hd__a32o_2)
3 0.02 _129_ (net)
0.14 0.00 5.77 v _307_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.55 6.32 v _307_/X (sky130_fd_sc_hd__a32o_2)
2 0.01 _131_ (net)
0.09 0.00 6.33 v _309_/A (sky130_fd_sc_hd__and2_2)
0.07 0.38 6.70 v _309_/X (sky130_fd_sc_hd__and2_2)
1 0.00 _133_ (net)
0.07 0.00 6.70 v _311_/B1 (sky130_fd_sc_hd__o22a_2)
0.07 0.39 7.09 v _311_/X (sky130_fd_sc_hd__o22a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _037_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 7.09 v _469_/D (sky130_fd_sc_hd__dfrtp_2)
7.09 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.09 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.92 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.23 0.34 6.31 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.23 0.00 6.31 ^ _323_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.08 0.50 6.81 v _323_/X (sky130_fd_sc_hd__o2bb2a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _033_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 6.81 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
6.81 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.26 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-6.81 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.64 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.23 0.34 6.31 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.23 0.00 6.31 ^ _328_/B (sky130_fd_sc_hd__nand2_2)
0.07 0.16 6.47 v _328_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _146_ (net)
0.07 0.00 6.47 v _329_/B1 (sky130_fd_sc_hd__o21a_2)
0.06 0.22 6.69 v _329_/X (sky130_fd_sc_hd__o21a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.06 0.00 6.69 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
6.69 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-6.69 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.51 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _320_/C1 (sky130_fd_sc_hd__o211a_2)
0.13 0.43 6.40 ^ _320_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _141_ (net)
0.13 0.00 6.40 ^ _321_/B (sky130_fd_sc_hd__xnor2_2)
0.13 0.16 6.56 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.13 0.00 6.56 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
6.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.28 6.14 library setup time
6.14 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.14 data required time
-6.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.42 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.93 0.94 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.94 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.33 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.34 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.58 1.91 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.92 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.41 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.42 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.17 0.21 2.63 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.17 0.00 2.63 ^ _337_/B1 (sky130_fd_sc_hd__o21ai_2)
0.07 0.13 2.76 v _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.07 0.00 2.76 v _338_/B (sky130_fd_sc_hd__and2_2)
0.09 0.44 3.20 v _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.09 0.00 3.20 v _339_/A (sky130_fd_sc_hd__buf_2)
0.06 0.26 3.47 v _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.06 0.00 3.47 v _460_/D (sky130_fd_sc_hd__dfrtp_2)
3.47 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.25 6.18 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.47 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.71 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.26 0.46 2.13 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.26 0.00 2.13 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.79 2.92 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.09 0.00 2.92 v _218_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 3.17 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.05 0.00 3.17 v _477_/D (sky130_fd_sc_hd__dfrtp_2)
3.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.25 6.18 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.01 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.93 0.94 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.94 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.33 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.34 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.58 1.91 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.92 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.41 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.42 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.17 0.21 2.63 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.17 0.00 2.63 ^ _342_/C (sky130_fd_sc_hd__nand3_2)
0.11 0.18 2.81 v _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.11 0.00 2.81 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
2.81 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.67 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.27 6.15 library setup time
6.15 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.15 data required time
-2.81 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.34 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.93 0.94 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.94 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.33 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.34 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.58 1.91 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.92 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.41 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.42 v _332_/A2 (sky130_fd_sc_hd__o21a_2)
0.06 0.39 2.80 v _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.06 0.00 2.80 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
2.80 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.18 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.80 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.93 0.94 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.94 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.33 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.34 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.58 1.91 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.92 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.41 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.42 v _333_/B (sky130_fd_sc_hd__nand2b_2)
0.07 0.12 2.54 ^ _333_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _149_ (net)
0.07 0.00 2.54 ^ _334_/B1 (sky130_fd_sc_hd__o211a_2)
0.07 0.37 2.91 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _029_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.07 0.00 2.91 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
2.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.13 6.30 library setup time
6.30 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.30 data required time
-2.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.39 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.93 0.94 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.11 0.00 0.94 v _225_/A (sky130_fd_sc_hd__buf_2)
0.18 0.39 1.33 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.18 0.00 1.34 v _330_/C (sky130_fd_sc_hd__and3_2)
0.12 0.58 1.91 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.12 0.00 1.92 v _331_/B (sky130_fd_sc_hd__and2_2)
0.11 0.50 2.41 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.11 0.00 2.42 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.17 0.21 2.63 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.17 0.00 2.63 ^ _341_/A1 (sky130_fd_sc_hd__a21boi_2)
0.08 0.14 2.76 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.08 0.00 2.76 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
2.76 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.67 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.26 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.16 data required time
-2.76 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _226_/S (sky130_fd_sc_hd__mux2_2)
0.11 0.83 2.50 v _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.11 0.00 2.50 v _227_/A (sky130_fd_sc_hd__buf_2)
0.06 0.27 2.77 v _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.06 0.00 2.77 v _473_/D (sky130_fd_sc_hd__dfrtp_2)
2.77 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.18 data required time
-2.77 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.40 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _223_/S (sky130_fd_sc_hd__mux2_2)
0.11 0.82 2.49 v _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.11 0.00 2.49 v _224_/A (sky130_fd_sc_hd__buf_2)
0.05 0.26 2.75 v _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.05 0.00 2.75 v _474_/D (sky130_fd_sc_hd__dfrtp_2)
2.75 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.75 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.43 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _219_/S (sky130_fd_sc_hd__mux2_2)
0.10 0.80 2.47 v _219_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.10 0.00 2.47 v _220_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 2.73 v _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.05 0.00 2.73 v _476_/D (sky130_fd_sc_hd__dfrtp_2)
2.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.25 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.18 data required time
-2.73 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.45 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _345_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.77 2.45 v _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.08 0.00 2.45 v _346_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 2.70 v _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.05 0.00 2.70 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
2.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-2.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.47 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _343_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.77 2.45 v _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.08 0.00 2.45 v _344_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 2.69 v _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.04 0.00 2.69 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
2.69 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 6.67 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.24 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.17 data required time
-2.69 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _221_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.78 2.45 v _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.09 0.00 2.45 v _222_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 2.69 v _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.04 0.00 2.69 v _475_/D (sky130_fd_sc_hd__dfrtp_2)
2.69 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.69 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.28 1.23 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.19 0.00 1.23 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.30 0.44 1.67 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.30 0.00 1.67 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.26 0.46 2.13 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.26 0.00 2.13 ^ _347_/B (sky130_fd_sc_hd__nand2b_2)
0.08 0.16 2.29 v _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 2.29 v _455_/D (sky130_fd_sc_hd__dfrtp_2)
2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.26 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.16 data required time
-2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.87 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.95 0.95 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.13 0.00 0.95 v _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.95 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 6.67 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.28 6.14 library setup time
6.14 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.14 data required time
-0.95 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.19 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.87 0.88 v _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.88 v _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.00 6.67 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.26 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.16 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.28 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.21 2.60 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.60 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.86 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.86 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.16 3.02 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.06 0.00 3.02 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.21 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.22 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 3.58 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.05 0.00 3.58 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 3.70 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 3.70 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.63 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.21 2.60 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.60 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.86 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.86 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.16 3.02 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.06 0.00 3.02 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.21 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.22 ^ _326_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 3.58 v _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.05 0.00 3.58 v _327_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 3.70 v _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 3.70 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.63 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.21 2.60 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.60 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.86 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.86 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.16 3.02 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.06 0.00 3.02 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.21 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.22 ^ _317_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.36 3.57 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.05 0.00 3.57 v _318_/A (sky130_fd_sc_hd__buf_2)
0.03 0.12 3.70 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.03 0.00 3.70 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.63 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _304_/A1 (sky130_fd_sc_hd__a21o_2)
0.06 0.26 2.66 v _304_/X (sky130_fd_sc_hd__a21o_2)
3 0.02 _128_ (net)
0.06 0.00 2.66 v _305_/A3 (sky130_fd_sc_hd__a32o_2)
0.08 0.33 2.99 v _305_/X (sky130_fd_sc_hd__a32o_2)
3 0.02 _129_ (net)
0.08 0.00 2.99 v _307_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.30 3.29 v _307_/X (sky130_fd_sc_hd__a32o_2)
2 0.01 _131_ (net)
0.05 0.00 3.29 v _309_/A (sky130_fd_sc_hd__and2_2)
0.04 0.18 3.47 v _309_/X (sky130_fd_sc_hd__and2_2)
1 0.00 _133_ (net)
0.04 0.00 3.47 v _311_/B1 (sky130_fd_sc_hd__o22a_2)
0.03 0.20 3.67 v _311_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.03 0.00 3.67 v _469_/D (sky130_fd_sc_hd__dfrtp_2)
3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.10 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.33 data required time
-3.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.66 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.21 2.60 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.60 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.86 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.86 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.16 3.02 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.06 0.00 3.02 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.21 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.22 ^ _323_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.04 0.24 3.45 v _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.04 0.00 3.45 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
3.45 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-3.45 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.87 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.21 2.60 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.60 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.86 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.86 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.16 3.02 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.06 0.00 3.02 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.21 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.22 ^ _328_/B (sky130_fd_sc_hd__nand2_2)
0.04 0.07 3.28 v _328_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _146_ (net)
0.04 0.00 3.28 v _329_/B1 (sky130_fd_sc_hd__o21a_2)
0.04 0.11 3.40 v _329_/X (sky130_fd_sc_hd__o21a_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 3.40 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
3.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.10 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.33 data required time
-3.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.93 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.21 2.60 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.60 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.86 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.86 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.16 3.02 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.06 0.00 3.02 ^ _320_/C1 (sky130_fd_sc_hd__o211a_2)
0.07 0.20 3.22 ^ _320_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _141_ (net)
0.07 0.00 3.22 ^ _321_/B (sky130_fd_sc_hd__xnor2_2)
0.15 0.12 3.34 ^ _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.15 0.00 3.34 ^ _466_/D (sky130_fd_sc_hd__dfrtp_2)
3.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.08 6.34 library setup time
6.34 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.34 data required time
-3.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
3.00 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.46 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.46 v _225_/A (sky130_fd_sc_hd__buf_2)
0.10 0.20 0.66 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.10 0.00 0.66 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.94 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.94 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.17 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.17 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.30 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.11 0.00 1.30 ^ _337_/B1 (sky130_fd_sc_hd__o21ai_2)
0.04 0.06 1.36 v _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.04 0.00 1.36 v _338_/B (sky130_fd_sc_hd__and2_2)
0.05 0.21 1.57 v _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.05 0.00 1.57 v _339_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.70 v _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.03 0.00 1.70 v _460_/D (sky130_fd_sc_hd__dfrtp_2)
1.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.10 6.33 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.63 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.17 0.25 1.14 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.17 0.00 1.14 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 1.52 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.05 0.00 1.52 v _218_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.64 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.03 0.00 1.64 v _477_/D (sky130_fd_sc_hd__dfrtp_2)
1.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.64 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.69 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _226_/S (sky130_fd_sc_hd__mux2_2)
0.06 0.39 1.28 v _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.06 0.00 1.28 v _227_/A (sky130_fd_sc_hd__buf_2)
0.03 0.14 1.42 v _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.03 0.00 1.42 v _473_/D (sky130_fd_sc_hd__dfrtp_2)
1.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.10 6.33 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.92 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _223_/S (sky130_fd_sc_hd__mux2_2)
0.06 0.39 1.27 v _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.06 0.00 1.27 v _224_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.40 v _224_/X (sky130_fd_sc_hd__buf_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _039_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 1.40 v _474_/D (sky130_fd_sc_hd__dfrtp_2)
1.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.93 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.46 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.46 v _225_/A (sky130_fd_sc_hd__buf_2)
0.10 0.20 0.66 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.10 0.00 0.66 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.94 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.94 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.17 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.17 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.30 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.11 0.00 1.30 ^ _342_/C (sky130_fd_sc_hd__nand3_2)
0.06 0.08 1.38 v _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.06 0.00 1.38 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.67 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.11 6.31 library setup time
6.31 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.31 data required time
-1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.94 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _219_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.38 1.27 v _219_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.05 0.00 1.27 v _220_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.39 v _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.03 0.00 1.39 v _476_/D (sky130_fd_sc_hd__dfrtp_2)
1.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.94 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _345_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.37 1.25 v _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.04 0.00 1.25 v _346_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.38 v _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.03 0.00 1.38 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.94 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.46 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.46 v _225_/A (sky130_fd_sc_hd__buf_2)
0.10 0.20 0.66 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.10 0.00 0.66 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.94 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.94 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.17 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.17 v _332_/A2 (sky130_fd_sc_hd__o21a_2)
0.03 0.20 1.38 v _332_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.03 0.00 1.38 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.10 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.33 data required time
-1.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.95 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _343_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.36 1.25 v _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.04 0.00 1.25 v _344_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.37 v _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 1.37 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
1.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 6.67 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.09 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.95 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _221_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 1.26 v _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.05 0.00 1.26 v _222_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.37 v _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 1.37 v _475_/D (sky130_fd_sc_hd__dfrtp_2)
1.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.46 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.46 v _225_/A (sky130_fd_sc_hd__buf_2)
0.10 0.20 0.66 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.10 0.00 0.66 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.94 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.94 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.17 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.17 v _333_/B (sky130_fd_sc_hd__nand2b_2)
0.04 0.07 1.24 ^ _333_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _149_ (net)
0.04 0.00 1.25 ^ _334_/B1 (sky130_fd_sc_hd__o211a_2)
0.04 0.17 1.41 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.04 0.00 1.41 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
1.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.05 6.37 library setup time
6.37 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.37 data required time
-1.41 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.45 0.46 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.06 0.00 0.46 v _225_/A (sky130_fd_sc_hd__buf_2)
0.10 0.20 0.66 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.10 0.00 0.66 v _330_/C (sky130_fd_sc_hd__and3_2)
0.06 0.27 0.94 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.06 0.00 0.94 v _331_/B (sky130_fd_sc_hd__and2_2)
0.06 0.23 1.17 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.06 0.00 1.17 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.30 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.11 0.00 1.30 ^ _341_/A1 (sky130_fd_sc_hd__a21boi_2)
0.04 0.06 1.36 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.04 0.00 1.36 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.67 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.12 0.17 0.63 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.12 0.00 0.63 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.19 0.25 0.88 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.19 0.00 0.89 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.17 0.25 1.14 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.17 0.00 1.14 ^ _347_/B (sky130_fd_sc_hd__nand2b_2)
0.04 0.07 1.21 v _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 1.21 v _455_/D (sky130_fd_sc_hd__dfrtp_2)
1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
-1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.46 0.47 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.06 0.00 0.47 v _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.47 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 6.67 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.31 data required time
-0.47 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.84 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Corner: tt
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.42 0.43 v _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 0.43 v _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.00 6.67 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.32 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.89 slack (MET)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
======================= Fastest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.63 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.63 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.79 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.79 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.87 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.87 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 2.00 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 2.00 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.22 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.03 0.00 2.22 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.29 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 2.29 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.07 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.63 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.63 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.79 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.79 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.87 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.87 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 2.00 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 2.00 ^ _326_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.22 v _326_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _145_ (net)
0.03 0.00 2.22 v _327_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.29 v _327_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 2.29 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.07 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.63 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.63 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.79 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.79 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.87 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.87 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 2.00 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 2.00 ^ _317_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.21 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _139_ (net)
0.03 0.00 2.21 v _318_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.29 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.02 0.00 2.29 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.07 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _469_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _304_/A1 (sky130_fd_sc_hd__a21o_2)
0.05 0.17 1.67 v _304_/X (sky130_fd_sc_hd__a21o_2)
3 0.02 _128_ (net)
0.05 0.00 1.67 v _305_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.18 1.84 v _305_/X (sky130_fd_sc_hd__a32o_2)
3 0.02 _129_ (net)
0.05 0.00 1.84 v _307_/A3 (sky130_fd_sc_hd__a32o_2)
0.03 0.16 2.00 v _307_/X (sky130_fd_sc_hd__a32o_2)
2 0.01 _131_ (net)
0.03 0.00 2.00 v _309_/A (sky130_fd_sc_hd__and2_2)
0.03 0.11 2.11 v _309_/X (sky130_fd_sc_hd__and2_2)
1 0.00 _133_ (net)
0.03 0.00 2.11 v _311_/B1 (sky130_fd_sc_hd__o22a_2)
0.02 0.12 2.23 v _311_/X (sky130_fd_sc_hd__o22a_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _037_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 2.23 v _469_/D (sky130_fd_sc_hd__dfrtp_2)
2.23 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _469_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.07 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.23 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.13 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.63 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.63 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.79 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.79 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.87 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.87 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 2.00 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 2.00 ^ _323_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.03 0.14 2.14 v _323_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.03 0.00 2.14 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
2.14 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.07 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.36 data required time
-2.14 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.21 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.63 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.63 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.79 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.79 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.87 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.87 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 2.00 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 2.00 ^ _328_/B (sky130_fd_sc_hd__nand2_2)
0.03 0.03 2.04 v _328_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _146_ (net)
0.03 0.00 2.04 v _329_/B1 (sky130_fd_sc_hd__o21a_2)
0.03 0.07 2.11 v _329_/X (sky130_fd_sc_hd__o21a_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 2.11 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
2.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.07 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.36 data required time
-2.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.25 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _272_/A (sky130_fd_sc_hd__buf_2)
0.08 0.16 1.66 v _272_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _096_ (net)
0.08 0.00 1.66 v _292_/A2 (sky130_fd_sc_hd__o31a_2)
0.04 0.23 1.89 v _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.89 v _320_/C1 (sky130_fd_sc_hd__o211a_2)
0.04 0.09 1.98 v _320_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _141_ (net)
0.04 0.00 1.98 v _321_/B (sky130_fd_sc_hd__xnor2_2)
0.05 0.09 2.07 v _321_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.01 _034_ (net)
0.05 0.00 2.07 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
2.07 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.08 6.34 library setup time
6.34 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.34 data required time
-2.07 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.27 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.29 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.43 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.18 0.60 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.60 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.75 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.75 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.84 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.08 0.00 0.84 ^ _337_/B1 (sky130_fd_sc_hd__o21ai_2)
0.02 0.02 0.86 v _337_/Y (sky130_fd_sc_hd__o21ai_2)
1 0.00 _152_ (net)
0.02 0.00 0.86 v _338_/B (sky130_fd_sc_hd__and2_2)
0.03 0.13 0.99 v _338_/X (sky130_fd_sc_hd__and2_2)
1 0.01 _153_ (net)
0.03 0.00 0.99 v _339_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 1.08 v _339_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _028_ (net)
0.02 0.00 1.08 v _460_/D (sky130_fd_sc_hd__dfrtp_2)
1.08 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.07 6.36 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.08 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.28 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _477_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.13 0.17 0.76 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.13 0.00 0.76 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.22 0.98 v _217_/X (sky130_fd_sc_hd__mux2_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _046_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.04 0.00 0.98 v _218_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 1.06 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.02 0.00 1.06 v _477_/D (sky130_fd_sc_hd__dfrtp_2)
1.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _477_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.30 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _473_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _226_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.23 0.82 v _226_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _051_ (net)
0.04 0.00 0.82 v _227_/A (sky130_fd_sc_hd__buf_2)
0.02 0.09 0.91 v _227_/X (sky130_fd_sc_hd__buf_2)
1 0.01 _038_ (net)
0.02 0.00 0.91 v _473_/D (sky130_fd_sc_hd__dfrtp_2)
0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _473_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 6.36 library setup time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.46 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.29 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.43 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.18 0.60 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.60 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.75 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.75 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.84 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.08 0.00 0.85 ^ _342_/C (sky130_fd_sc_hd__nand3_2)
0.04 0.04 0.89 v _342_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.04 0.00 0.89 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.67 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.46 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _474_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _223_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.23 0.82 v _223_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _049_ (net)
0.04 0.00 0.82 v _224_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.90 v _224_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.02 0.00 0.90 v _474_/D (sky130_fd_sc_hd__dfrtp_2)
0.90 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _474_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.90 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.47 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _476_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _219_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.22 0.81 v _219_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.04 0.00 0.81 v _220_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.89 v _220_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.02 0.00 0.89 v _476_/D (sky130_fd_sc_hd__dfrtp_2)
0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _476_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.36 data required time
-0.89 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.47 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _345_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.80 v _345_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _156_ (net)
0.03 0.00 0.80 v _346_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.88 v _346_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.02 0.00 0.88 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.88 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.47 slack (MET)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.29 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.43 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.18 0.60 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.60 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.75 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.75 v _336_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.84 ^ _336_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _151_ (net)
0.08 0.00 0.84 ^ _341_/A1 (sky130_fd_sc_hd__a21boi_2)
0.03 0.03 0.88 v _341_/Y (sky130_fd_sc_hd__a21boi_2)
1 0.00 _027_ (net)
0.03 0.00 0.88 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.88 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.67 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.48 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.29 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.43 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.18 0.60 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.60 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.75 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.75 v _332_/A2 (sky130_fd_sc_hd__o21a_2)
0.02 0.13 0.88 v _332_/X (sky130_fd_sc_hd__o21a_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1 0.00 _030_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.02 0.00 0.88 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.88 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.07 6.36 library setup time
6.36 data required time
-----------------------------------------------------------------------------
6.36 data required time
-0.88 data arrival time
-----------------------------------------------------------------------------
5.48 slack (MET)
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _343_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.80 v _343_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _155_ (net)
0.03 0.00 0.80 v _344_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.87 v _344_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 0.88 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 6.67 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.06 6.35 library setup time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.48 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _475_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _221_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.80 v _221_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.03 0.00 0.80 v _222_/A (sky130_fd_sc_hd__buf_2)
0.02 0.07 0.88 v _222_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 0.88 v _475_/D (sky130_fd_sc_hd__dfrtp_2)
0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _475_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.28 0.29 v _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.count0[0] (net)
0.04 0.00 0.29 v _225_/A (sky130_fd_sc_hd__buf_2)
0.07 0.13 0.42 v _225_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _050_ (net)
0.07 0.00 0.43 v _330_/C (sky130_fd_sc_hd__and3_2)
0.05 0.18 0.60 v _330_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _147_ (net)
0.05 0.00 0.60 v _331_/B (sky130_fd_sc_hd__and2_2)
0.04 0.15 0.75 v _331_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _148_ (net)
0.04 0.00 0.75 v _333_/B (sky130_fd_sc_hd__nand2b_2)
0.03 0.05 0.80 ^ _333_/Y (sky130_fd_sc_hd__nand2b_2)
1 0.00 _149_ (net)
0.03 0.00 0.80 ^ _334_/B1 (sky130_fd_sc_hd__o211a_2)
0.03 0.08 0.89 ^ _334_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.03 0.00 0.89 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.89 data arrival time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.03 6.39 library setup time
6.39 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.39 data required time
-0.89 data arrival time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.50 slack (MET)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _214_/A (sky130_fd_sc_hd__xnor2_2)
0.09 0.12 0.41 ^ _214_/Y (sky130_fd_sc_hd__xnor2_2)
2 0.00 _043_ (net)
0.09 0.00 0.42 ^ _215_/A (sky130_fd_sc_hd__buf_2)
0.15 0.17 0.59 ^ _215_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _044_ (net)
0.15 0.00 0.59 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.13 0.17 0.76 ^ _216_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _045_ (net)
0.13 0.00 0.76 ^ _347_/B (sky130_fd_sc_hd__nand2b_2)
0.03 0.03 0.79 v _347_/Y (sky130_fd_sc_hd__nand2b_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.79 v _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.35 data required time
-0.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
5.56 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _472_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.29 0.30 v _471_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.oscbuf[1] (net)
0.05 0.00 0.30 v _472_/D (sky130_fd_sc_hd__dfrtp_2)
0.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 6.67 ^ _472_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.08 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-0.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.05 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _470_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _471_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 0.00 ^ _470_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.26 0.27 v _470_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.03 0.00 0.27 v _471_/D (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.27 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.00 6.67 ^ _471_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.27 data arrival time
-----------------------------------------------------------------------------
6.09 slack (MET)
max_report_end
check_report
===========================================================================
report_checks -unconstrained
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.23 0.34 6.31 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.23 0.00 6.31 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 7.08 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.09 0.00 7.08 v _315_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 7.32 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.05 0.00 7.32 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.14 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.51 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.11 0.00 0.52 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.76 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.11 0.00 0.76 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.40 1.16 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.07 0.00 1.16 v _240_/B (sky130_fd_sc_hd__and3_2)
0.05 0.23 1.39 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.05 0.00 1.39 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.07 0.40 1.79 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.07 0.00 1.79 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.04 0.17 1.96 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.04 0.00 1.96 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.12 0.44 2.39 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.12 0.00 2.40 v _285_/A (sky130_fd_sc_hd__and3_2)
0.04 0.21 2.60 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.04 0.00 2.60 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.07 0.26 2.86 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.07 0.00 2.86 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.16 3.02 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.06 0.00 3.02 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.14 0.19 3.21 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.14 0.00 3.22 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 3.58 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.05 0.00 3.58 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 3.70 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 3.70 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.10 0.01 6.68 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
2.63 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.08 0.00 0.33 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.49 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.07 0.00 0.49 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.25 0.74 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.05 0.00 0.74 v _240_/B (sky130_fd_sc_hd__and3_2)
0.04 0.14 0.88 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.04 0.00 0.88 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.05 0.23 1.11 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.05 0.00 1.11 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.03 0.11 1.22 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.03 0.00 1.22 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.08 0.27 1.49 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.08 0.00 1.50 v _285_/A (sky130_fd_sc_hd__and3_2)
0.03 0.13 1.63 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.03 0.00 1.63 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.05 0.16 1.79 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.05 0.00 1.79 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 1.87 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.04 0.00 1.87 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.11 0.13 2.00 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.11 0.00 2.00 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 2.22 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.03 0.00 2.22 v _315_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.29 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 2.29 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
24 0.08 pll_control.clock (net)
0.08 0.01 6.68 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-2.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
4.07 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _468_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _459_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.20 0.00 1.05 v _233_/A (sky130_fd_sc_hd__xor2_2)
0.21 0.45 1.50 v _233_/X (sky130_fd_sc_hd__xor2_2)
3 0.02 _057_ (net)
0.21 0.00 1.50 v _236_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.76 2.26 v _236_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _060_ (net)
0.12 0.00 2.26 v _240_/B (sky130_fd_sc_hd__and3_2)
0.10 0.48 2.74 v _240_/X (sky130_fd_sc_hd__and3_2)
2 0.01 _064_ (net)
0.10 0.00 2.75 v _249_/A2 (sky130_fd_sc_hd__o32a_2)
0.14 0.76 3.51 v _249_/X (sky130_fd_sc_hd__o32a_2)
3 0.01 _073_ (net)
0.14 0.00 3.51 v _260_/B1 (sky130_fd_sc_hd__o2111a_2)
0.07 0.32 3.83 v _260_/X (sky130_fd_sc_hd__o2111a_2)
1 0.00 _084_ (net)
0.07 0.00 3.83 v _271_/A1 (sky130_fd_sc_hd__o31a_2)
0.20 0.84 4.67 v _271_/X (sky130_fd_sc_hd__o31a_2)
6 0.03 _095_ (net)
0.20 0.00 4.67 v _285_/A (sky130_fd_sc_hd__and3_2)
0.07 0.43 5.10 v _285_/X (sky130_fd_sc_hd__and3_2)
1 0.00 _109_ (net)
0.07 0.00 5.10 v _291_/A_N (sky130_fd_sc_hd__and3b_2)
0.13 0.54 5.64 ^ _291_/X (sky130_fd_sc_hd__and3b_2)
3 0.01 _115_ (net)
0.13 0.00 5.64 ^ _292_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.33 5.97 ^ _292_/X (sky130_fd_sc_hd__o31a_2)
2 0.01 _116_ (net)
0.10 0.00 5.97 ^ _293_/A (sky130_fd_sc_hd__buf_2)
0.23 0.34 6.31 ^ _293_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _117_ (net)
0.23 0.00 6.31 ^ _314_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 7.08 v _314_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _137_ (net)
0.09 0.00 7.08 v _315_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 7.32 v _315_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.05 0.00 7.32 v _468_/D (sky130_fd_sc_hd__dfrtp_2)
7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
0.15 0.01 6.68 ^ _468_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-7.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
-1.14 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
No paths found.
======================= Fastest Corner ===================================
No paths found.
check_report_end
check_slew
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= Slowest Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
dco 7 14 -7 (VIOLATED)
div[3] 7 8 (VIOLATED)
_426_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
dco 7 14 -7 (VIOLATED)
div[3] 7 8 (VIOLATED)
_426_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
dco 7 14 -7 (VIOLATED)
div[3] 7 8 (VIOLATED)
_426_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
max slew violation count 0
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
max fanout violation count 4
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
max cap violation count 0
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
============================================================================
check_slew_end
tns_report
===========================================================================
report_tns
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
tns -5.91
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
tns_report_end
wns_report
===========================================================================
report_wns
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
wns -1.14
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
wns_report_end
worst_slack
===========================================================================
report_worst_slack -max (Setup)
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
worst slack -1.14
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
report_worst_slack -min (Hold)
============================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
worst slack -0.02
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
worst_slack_end
power_report
===========================================================================
report_power
============================================================================
======================= Slowest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Sequential 1.15e-04 1.46e-05 3.37e-07 1.30e-04 26.7%
Combinational 1.54e-04 2.00e-04 1.72e-06 3.56e-04 73.3%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Total 2.69e-04 2.15e-04 2.05e-06 4.86e-04 100.0%
55.4% 44.2% 0.4%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Sequential 1.50e-04 1.86e-05 1.84e-10 1.68e-04 27.5%
Combinational 1.88e-04 2.55e-04 1.37e-09 4.43e-04 72.5%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Total 3.38e-04 2.74e-04 1.55e-09 6.12e-04 100.0%
55.3% 44.7% 0.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Sequential 1.74e-04 2.21e-05 3.12e-10 1.96e-04 27.7%
Combinational 2.10e-04 3.02e-04 3.77e-09 5.12e-04 72.3%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Total 3.84e-04 3.24e-04 4.08e-09 7.08e-04 100.0%
54.3% 45.7% 0.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
power_report_end
area_report
===========================================================================
report_design_area
============================================================================
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Design area 3727 u^2 93% utilization.
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF files for all corners...
reharden!: digital_pll ~ disable or gate + add nosynth list file
2022-10-17 14:33:25 -05:00
Writing SDF for the ff corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/mca/process_corner_max/digital_pll.ff.sdf...
Writing SDF for the ss corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/mca/process_corner_max/digital_pll.ss.sdf...
Writing SDF for the tt corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_12_25/results/routing/mca/process_corner_max/digital_pll.tt.sdf...