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caravel/def/gpio_control_block.def

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157 KiB
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harden gpio_control_block
2021-11-04 09:19:12 -05:00
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN gpio_control_block ;
UNITS DISTANCE MICRONS 1000 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
DIEAREA ( 0 0 ) ( 170000 65000 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
ROW ROW_0 unithd 4600 2720 N DO 102 BY 1 STEP 460 0 ;
ROW ROW_2_2 unithd 15180 8160 N DO 79 BY 1 STEP 460 0 ;
ROW ROW_3_2 unithd 15180 10880 FS DO 79 BY 1 STEP 460 0 ;
ROW ROW_4_2 unithd 15180 13600 N DO 79 BY 1 STEP 460 0 ;
ROW ROW_5_2 unithd 15180 16320 FS DO 79 BY 1 STEP 460 0 ;
ROW ROW_6_2 unithd 15180 19040 N DO 79 BY 1 STEP 460 0 ;
ROW ROW_7_2 unithd 15180 21760 FS DO 79 BY 1 STEP 460 0 ;
ROW ROW_8_2 unithd 15180 24480 N DO 79 BY 1 STEP 460 0 ;
ROW ROW_9 unithd 4600 27200 FS DO 102 BY 1 STEP 460 0 ;
ROW ROW_10 unithd 4600 29920 N DO 102 BY 1 STEP 460 0 ;
ROW ROW_11 unithd 4600 32640 FS DO 102 BY 1 STEP 460 0 ;
ROW ROW_12 unithd 4600 35360 N DO 102 BY 1 STEP 460 0 ;
ROW ROW_13 unithd 4600 38080 FS DO 102 BY 1 STEP 460 0 ;
ROW ROW_14 unithd 4600 40800 N DO 102 BY 1 STEP 460 0 ;
ROW ROW_15 unithd 4600 43520 FS DO 102 BY 1 STEP 460 0 ;
ROW ROW_16 unithd 4600 46240 N DO 102 BY 1 STEP 460 0 ;
ROW ROW_17 unithd 4600 48960 FS DO 102 BY 1 STEP 460 0 ;
ROW ROW_18 unithd 4600 51680 N DO 102 BY 1 STEP 460 0 ;
ROW ROW_19 unithd 4600 54400 FS DO 102 BY 1 STEP 460 0 ;
ROW ROW_20 unithd 4600 57120 N DO 102 BY 1 STEP 460 0 ;
ROW ROW_1_2 unithd 15180 5440 FS DO 79 BY 1 STEP 460 0 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
TRACKS X 230 DO 370 STEP 460 LAYER li1 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
TRACKS Y 170 DO 191 STEP 340 LAYER li1 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
TRACKS X 170 DO 500 STEP 340 LAYER met1 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
TRACKS Y 170 DO 191 STEP 340 LAYER met1 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
TRACKS X 230 DO 370 STEP 460 LAYER met2 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
TRACKS Y 230 DO 141 STEP 460 LAYER met2 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
TRACKS X 340 DO 250 STEP 680 LAYER met3 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
TRACKS Y 340 DO 96 STEP 680 LAYER met3 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
TRACKS X 460 DO 185 STEP 920 LAYER met4 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
TRACKS Y 460 DO 71 STEP 920 LAYER met4 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
TRACKS X 1700 DO 50 STEP 3400 LAYER met5 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
TRACKS Y 1700 DO 19 STEP 3400 LAYER met5 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
GCELLGRID X 0 DO 24 STEP 6900 ;
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
GCELLGRID Y 0 DO 9 STEP 6900 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
VIAS 5 ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- via2_3_1600_480_1_5_320_320 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 85 165 55 85 + ROWCOL 1 5 ;
- via3_4_1600_480_1_4_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 85 65 65 + ROWCOL 1 4 ;
- via4_5_1600_480_1_4_400_400 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 90 60 100 65 + ROWCOL 1 4 ;
- via5_6_1600_1600_1_1_1600_1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 190 310 400 ;
- via5_6_1400_1600_1_1_1600_1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 300 400 310 400 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
END VIAS
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
COMPONENTS 270 ;
- ANTENNA__065__A0 sky130_fd_sc_hd__diode_2 + PLACED ( 5980 35360 ) FN ;
- ANTENNA__066__B sky130_fd_sc_hd__diode_2 + PLACED ( 44620 2720 ) FN ;
- ANTENNA__071__B sky130_fd_sc_hd__diode_2 + PLACED ( 5980 48960 ) FS ;
- ANTENNA__072__B sky130_fd_sc_hd__diode_2 + PLACED ( 49220 27200 ) S ;
- ANTENNA__073__A sky130_fd_sc_hd__diode_2 + PLACED ( 6440 2720 ) N ;
- ANTENNA__073__B sky130_fd_sc_hd__diode_2 + PLACED ( 14720 2720 ) N ;
- ANTENNA__074__A_N sky130_fd_sc_hd__diode_2 + PLACED ( 15640 2720 ) N ;
- ANTENNA__074__B sky130_fd_sc_hd__diode_2 + PLACED ( 17940 2720 ) FN ;
- ANTENNA__075__B sky130_fd_sc_hd__diode_2 + PLACED ( 43700 35360 ) FN ;
- ANTENNA__076__B sky130_fd_sc_hd__diode_2 + PLACED ( 49220 51680 ) FN ;
- ANTENNA__077__B sky130_fd_sc_hd__diode_2 + PLACED ( 5980 46240 ) FN ;
- ANTENNA__078__B sky130_fd_sc_hd__diode_2 + PLACED ( 41400 5440 ) S ;
- ANTENNA__079__A sky130_fd_sc_hd__diode_2 + PLACED ( 29900 10880 ) FS ;
- ANTENNA__079__B sky130_fd_sc_hd__diode_2 + PLACED ( 28980 10880 ) FS ;
- ANTENNA__080__A_N sky130_fd_sc_hd__diode_2 + PLACED ( 13800 2720 ) N ;
- ANTENNA__080__B sky130_fd_sc_hd__diode_2 + PLACED ( 16560 5440 ) S ;
- ANTENNA__081__B sky130_fd_sc_hd__diode_2 + PLACED ( 49220 43520 ) S ;
- ANTENNA__082__B sky130_fd_sc_hd__diode_2 + PLACED ( 16560 2720 ) N ;
- ANTENNA__083__A sky130_fd_sc_hd__diode_2 + PLACED ( 22080 8160 ) N ;
- ANTENNA__083__B sky130_fd_sc_hd__diode_2 + PLACED ( 17480 5440 ) S ;
- ANTENNA__084__A_N sky130_fd_sc_hd__diode_2 + PLACED ( 23000 8160 ) N ;
- ANTENNA__084__B sky130_fd_sc_hd__diode_2 + PLACED ( 18400 5440 ) S ;
- ANTENNA__085__B sky130_fd_sc_hd__diode_2 + PLACED ( 31280 2720 ) FN ;
- ANTENNA__086__B sky130_fd_sc_hd__diode_2 + PLACED ( 49220 32640 ) S ;
- ANTENNA__087__B sky130_fd_sc_hd__diode_2 + PLACED ( 28980 8160 ) FN ;
- ANTENNA__088__B sky130_fd_sc_hd__diode_2 + PLACED ( 43700 2720 ) FN ;
- ANTENNA__089__B sky130_fd_sc_hd__diode_2 + PLACED ( 28060 10880 ) S ;
- ANTENNA__090__B sky130_fd_sc_hd__diode_2 + PLACED ( 27140 10880 ) S ;
- ANTENNA__091__B sky130_fd_sc_hd__diode_2 + PLACED ( 27140 13600 ) FN ;
- ANTENNA__092__B sky130_fd_sc_hd__diode_2 + PLACED ( 16560 16320 ) FS ;
- ANTENNA__093__B sky130_fd_sc_hd__diode_2 + PLACED ( 29440 38080 ) FS ;
- ANTENNA__094__B sky130_fd_sc_hd__diode_2 + PLACED ( 21160 8160 ) FN ;
- ANTENNA__095__B sky130_fd_sc_hd__diode_2 + PLACED ( 40020 21760 ) S ;
- ANTENNA__096__B sky130_fd_sc_hd__diode_2 + PLACED ( 16560 21760 ) S ;
- ANTENNA__125__RESET_B sky130_fd_sc_hd__diode_2 + PLACED ( 5980 43520 ) S ;
- ANTENNA_clkbuf_0_serial_clock_A sky130_fd_sc_hd__diode_2 + PLACED ( 25760 10880 ) S ;
- ANTENNA_clkbuf_0_serial_load_A sky130_fd_sc_hd__diode_2 + PLACED ( 5980 29920 ) FN ;
- ANTENNA_input1_A sky130_fd_sc_hd__diode_2 + PLACED ( 32200 2720 ) FN ;
- ANTENNA_input2_A sky130_fd_sc_hd__diode_2 + PLACED ( 19320 2720 ) FN ;
- ANTENNA_input3_A sky130_fd_sc_hd__diode_2 + PLACED ( 45540 2720 ) FN ;
- ANTENNA_input4_A sky130_fd_sc_hd__diode_2 + PLACED ( 5980 27200 ) S ;
- ANTENNA_input5_A sky130_fd_sc_hd__diode_2 + PLACED ( 27140 8160 ) FN ;
- FILLER_0_3 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5980 2720 ) N ;
- FILLER_0_31 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 18860 2720 ) N ;
- FILLER_0_57 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 30820 2720 ) N ;
- FILLER_0_91 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 46460 2720 ) N ;
- FILLER_10_85 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 43700 29920 ) N ;
- FILLER_14_98 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 49680 40800 ) N ;
- FILLER_17_98 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 49680 48960 ) FS ;
- FILLER_19_55 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 29900 54400 ) FS ;
- FILLER_19_70 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 36800 54400 ) FS ;
- FILLER_1_32 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 19320 5440 ) FS ;
- FILLER_1_98 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 49680 5440 ) FS ;
- FILLER_20_98 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 49680 57120 ) N ;
- FILLER_2_42 sky130_fd_sc_hd__decap_6 + SOURCE DIST + PLACED ( 23920 8160 ) N ;
- FILLER_2_48 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 26680 8160 ) N ;
- FILLER_2_52 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 28520 8160 ) N ;
- FILLER_3_48 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 26680 10880 ) FS ;
- FILLER_3_80 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 41400 10880 ) FS ;
- FILLER_5_56 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 30360 16320 ) FS ;
- FILLER_5_98 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 49680 16320 ) FS ;
- FILLER_7_98 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 49680 21760 ) FS ;
- FILLER_8_52 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 28520 24480 ) N ;
- FILLER_8_98 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 49680 24480 ) N ;
- PHY_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 2720 ) N ;
- PHY_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 2720 ) FN ;
- PHY_10 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 16320 ) FS ;
- PHY_11 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 16320 ) S ;
- PHY_12 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 19040 ) N ;
- PHY_13 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 19040 ) FN ;
- PHY_14 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 21760 ) FS ;
- PHY_15 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 21760 ) S ;
- PHY_16 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 24480 ) N ;
- PHY_17 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 24480 ) FN ;
- PHY_18 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 27200 ) FS ;
- PHY_19 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 27200 ) S ;
- PHY_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 5440 ) FS ;
- PHY_20 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 29920 ) N ;
- PHY_21 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 29920 ) FN ;
- PHY_22 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 32640 ) FS ;
- PHY_23 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 32640 ) S ;
- PHY_24 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 35360 ) N ;
- PHY_25 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 35360 ) FN ;
- PHY_26 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 38080 ) FS ;
- PHY_27 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 38080 ) S ;
- PHY_28 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 40800 ) N ;
- PHY_29 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 40800 ) FN ;
- PHY_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 5440 ) S ;
- PHY_30 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 43520 ) FS ;
- PHY_31 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 43520 ) S ;
- PHY_32 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 46240 ) N ;
- PHY_33 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 46240 ) FN ;
- PHY_34 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 48960 ) FS ;
- PHY_35 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 48960 ) S ;
- PHY_36 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 51680 ) N ;
- PHY_37 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 51680 ) FN ;
- PHY_38 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 54400 ) FS ;
- PHY_39 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 54400 ) S ;
- PHY_4 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 8160 ) N ;
- PHY_40 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 4600 57120 ) N ;
- PHY_41 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 57120 ) FN ;
- PHY_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 8160 ) FN ;
- PHY_6 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 10880 ) FS ;
- PHY_7 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 10880 ) S ;
- PHY_8 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 15180 13600 ) N ;
- PHY_9 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 50140 13600 ) FN ;
- TAP_42 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 2720 ) N ;
- TAP_43 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 2720 ) N ;
- TAP_44 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 2720 ) N ;
- TAP_45 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 40940 5440 ) FS ;
- TAP_46 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28060 8160 ) N ;
- TAP_47 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 40940 10880 ) FS ;
- TAP_48 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28060 13600 ) N ;
- TAP_49 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 40940 16320 ) FS ;
- TAP_50 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28060 19040 ) N ;
- TAP_51 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 40940 21760 ) FS ;
- TAP_52 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28060 24480 ) N ;
- TAP_53 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 27200 ) FS ;
- TAP_54 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 27200 ) FS ;
- TAP_55 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 27200 ) FS ;
- TAP_56 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 29920 ) N ;
- TAP_57 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 29920 ) N ;
- TAP_58 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 32640 ) FS ;
- TAP_59 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 35360 ) N ;
- TAP_60 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 35360 ) N ;
- TAP_61 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 38080 ) FS ;
- TAP_62 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 40800 ) N ;
- TAP_63 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 40800 ) N ;
- TAP_64 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 43520 ) FS ;
- TAP_65 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 46240 ) N ;
- TAP_66 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 46240 ) N ;
- TAP_67 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 48960 ) FS ;
- TAP_68 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 51680 ) N ;
- TAP_69 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 51680 ) N ;
- TAP_70 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 54400 ) FS ;
- TAP_71 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 17480 57120 ) N ;
- TAP_72 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 30360 57120 ) N ;
- TAP_73 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 43240 57120 ) N ;
- _060_ sky130_fd_sc_hd__inv_2 + PLACED ( 46920 2720 ) N ;
- _061__1 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 44620 43520 ) FS ;
- _062__14 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 19780 8160 ) N ;
- _063_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 46920 46240 ) N ;
- _064_ sky130_fd_sc_hd__and2_0 + PLACED ( 47380 24480 ) FN ;
- _065_ sky130_fd_sc_hd__mux2_4 + PLACED ( 44620 35360 ) FN ;
- _066_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 46000 43520 ) S ;
- _067_ sky130_fd_sc_hd__and3b_2 + PLACED ( 45540 27200 ) S ;
- _068_ sky130_fd_sc_hd__and2b_2 + PLACED ( 45080 10880 ) FS ;
- _069_ sky130_fd_sc_hd__o21ai_2 + PLACED ( 46460 16320 ) S ;
- _070_ sky130_fd_sc_hd__o21ai_4 + PLACED ( 44160 29920 ) FN ;
- _071_ sky130_fd_sc_hd__or2_0 + PLACED ( 34500 54400 ) FS ;
- _072_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 36800 21760 ) S ;
- _073_ sky130_fd_sc_hd__or2_0 + PLACED ( 5980 57120 ) FN ;
- _074_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 10580 2720 ) N ;
- _075_ sky130_fd_sc_hd__or2_0 + PLACED ( 28520 40800 ) N ;
- _076_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 41400 43520 ) S ;
- _077_ sky130_fd_sc_hd__or2_0 + PLACED ( 47380 40800 ) N ;
- _078_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 43700 46240 ) FN ;
- _079_ sky130_fd_sc_hd__or2_0 + PLACED ( 30820 57120 ) N ;
- _080_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 6900 43520 ) FS ;
- _081_ sky130_fd_sc_hd__or2_0 + PLACED ( 28060 43520 ) S ;
- _082_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 7360 2720 ) N ;
- _083_ sky130_fd_sc_hd__or2_0 + PLACED ( 17940 57120 ) N ;
- _084_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 16560 8160 ) N ;
- _085_ sky130_fd_sc_hd__or2_0 + PLACED ( 47380 5440 ) S ;
- _086_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 46000 32640 ) S ;
- _087_ sky130_fd_sc_hd__or2_0 + PLACED ( 47380 57120 ) N ;
- _088_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 43240 16320 ) S ;
- _089_ sky130_fd_sc_hd__or2_0 + PLACED ( 47380 48960 ) FS ;
- _090_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 41860 10880 ) FS ;
- _091_ sky130_fd_sc_hd__or2_0 + PLACED ( 25760 19040 ) N ;
- _092_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 7360 32640 ) FS ;
- _093_ sky130_fd_sc_hd__or2_0 + PLACED ( 30820 32640 ) FS ;
- _094_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 17480 21760 ) FS ;
- _095_ sky130_fd_sc_hd__or2_0 + PLACED ( 30820 27200 ) FS ;
- _096_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 33580 21760 ) FS ;
- _097__2 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 5980 40800 ) N ;
- _098__3 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 30820 38080 ) FS ;
- _099__4 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 5980 51680 ) N ;
- _100__5 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 5980 54400 ) FS ;
- _101__6 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 6900 27200 ) FS ;
- _102__7 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 5980 32640 ) FS ;
- _103__8 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 28520 19040 ) N ;
- _104__9 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 35880 38080 ) S ;
- _105__10 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 28520 13600 ) N ;
- _106__11 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 25760 13600 ) FN ;
- _107__12 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 6900 29920 ) N ;
- _108__13 sky130_fd_sc_hd__inv_2 + SOURCE TIMING + PLACED ( 21620 29920 ) N ;
- _109_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 28520 51680 ) N ;
- _110_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 17020 54400 ) FS ;
- _111_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 33120 32640 ) FS ;
- _112_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 37260 38080 ) FS ;
- _113_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 17940 46240 ) N ;
- _114_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 17940 35360 ) N ;
- _115_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 17480 48960 ) FS ;
- _116_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 34500 24480 ) N ;
- _117_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 34500 48960 ) FS ;
- _118_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 37260 54400 ) FS ;
- _119_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 17480 16320 ) FS ;
- _120_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 20700 21760 ) FS ;
- _121_ sky130_fd_sc_hd__dfbbn_2 + PLACED ( 26680 29920 ) N ;
- _122_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 17940 51680 ) N ;
- _123_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 6900 46240 ) FN ;
- _124_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 6900 48960 ) FS ;
- _125_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 13800 43520 ) FS ;
- _126_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 17940 40800 ) N ;
- _127_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 6900 35360 ) N ;
- _128_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 15180 38080 ) FS ;
- _129_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 19780 27200 ) FS ;
- _130_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 19780 32640 ) FS ;
- _131_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 30820 40800 ) N ;
- _132_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 32660 35360 ) N ;
- _133_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 30820 43520 ) S ;
- _134_ sky130_fd_sc_hd__dfrtp_4 + PLACED ( 32660 46240 ) N ;
- _135_ sky130_fd_sc_hd__dfrtp_2 + PLACED ( 7360 54400 ) S ;
- _136_ sky130_fd_sc_hd__buf_2 + PLACED ( 16560 24480 ) N ;
- _139_ sky130_fd_sc_hd__ebufn_8 + PLACED ( 18400 24480 ) FN ;
- clkbuf_0_serial_clock sky130_fd_sc_hd__clkbuf_16 + SOURCE TIMING + PLACED ( 8280 57120 ) FN ;
- clkbuf_0_serial_load sky130_fd_sc_hd__clkbuf_16 + SOURCE TIMING + PLACED ( 5980 38080 ) S ;
- clkbuf_1_0__f_serial_clock sky130_fd_sc_hd__clkbuf_16 + SOURCE TIMING + PLACED ( 8280 27200 ) FS ;
- clkbuf_1_0__f_serial_load sky130_fd_sc_hd__clkbuf_16 + SOURCE TIMING + PLACED ( 16560 19040 ) N ;
- clkbuf_1_1__f_serial_clock sky130_fd_sc_hd__clkbuf_16 + SOURCE TIMING + PLACED ( 10580 32640 ) FS ;
- clkbuf_1_1__f_serial_load sky130_fd_sc_hd__clkbuf_16 + SOURCE TIMING + PLACED ( 8280 29920 ) FN ;
- const_source sky130_fd_sc_hd__conb_1 + PLACED ( 42320 5440 ) S ;
- fanout21 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 30820 46240 ) FN ;
- fanout22 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 30820 35360 ) FN ;
- fanout23 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 47380 51680 ) N ;
- fanout24 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 41400 51680 ) FN ;
- fanout25 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 48300 10880 ) FS ;
- fanout26 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 41400 16320 ) S ;
- fanout27 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 41400 40800 ) N ;
- fanout28 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 32660 24480 ) N ;
- gpio_in_buf sky130_fd_sc_hd__einvp_8 + PLACED ( 41400 21760 ) FS ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
- gpio_logic_high gpio_logic_high + FIXED ( 5980 8400 ) N ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- hold1 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 43700 40800 ) FN ;
- hold10 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 39560 29920 ) FN ;
- hold11 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 17940 29920 ) N ;
- hold12 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 32200 38080 ) FS ;
- hold13 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 25760 38080 ) S ;
- hold2 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 30820 48960 ) FS ;
- hold3 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 30820 54400 ) S ;
- hold4 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 43700 57120 ) FN ;
- hold5 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 10120 43520 ) FS ;
- hold6 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 24380 43520 ) S ;
- hold7 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 43700 51680 ) FN ;
- hold8 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 28980 24480 ) FN ;
- hold9 sky130_fd_sc_hd__dlygate4sd3_1 + SOURCE TIMING + PLACED ( 23000 29920 ) FN ;
- input1 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 43700 5440 ) FS ;
- input2 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 48300 2720 ) FN ;
- input3 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 43700 27200 ) S ;
- input4 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 17940 27200 ) FS ;
- input5 sky130_fd_sc_hd__buf_2 + SOURCE TIMING + PLACED ( 45540 5440 ) S ;
- one_buffer sky130_fd_sc_hd__buf_16 + PLACED ( 20700 5440 ) S ;
- output10 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 29900 13600 ) FN ;
- output11 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 40020 8160 ) FN ;
- output12 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 30820 16320 ) FS ;
- output13 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 29900 19040 ) N ;
- output14 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 40020 13600 ) N ;
- output15 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 33120 27200 ) S ;
- output16 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 40020 19040 ) N ;
- output17 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 33120 57120 ) FN ;
- output18 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 7360 40800 ) FN ;
- output19 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 20240 57120 ) N ;
- output20 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 7360 51680 ) FN ;
- output6 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 33120 2720 ) N ;
- output7 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 30820 5440 ) S ;
- output8 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 29900 8160 ) N ;
- output9 sky130_fd_sc_hd__buf_16 + SOURCE TIMING + PLACED ( 30820 10880 ) S ;
- serial_clock_out_buffer sky130_fd_sc_hd__clkbuf_16 + PLACED ( 16560 10880 ) FS ;
- serial_load_out_buffer sky130_fd_sc_hd__clkbuf_16 + PLACED ( 16560 13600 ) N ;
- zero_buffer sky130_fd_sc_hd__buf_16 + PLACED ( 20240 2720 ) FN ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
END COMPONENTS
PINS 47 ;
- gpio_defaults[0] + NET gpio_defaults[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 4830 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[10] + NET gpio_defaults[10] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 27830 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[11] + NET gpio_defaults[11] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 30130 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[12] + NET gpio_defaults[12] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 32430 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[1] + NET gpio_defaults[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 7130 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[2] + NET gpio_defaults[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 9430 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[3] + NET gpio_defaults[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 11730 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[4] + NET gpio_defaults[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 14030 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[5] + NET gpio_defaults[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 16330 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[6] + NET gpio_defaults[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 18630 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[7] + NET gpio_defaults[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 20930 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[8] + NET gpio_defaults[8] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 23230 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- gpio_defaults[9] + NET gpio_defaults[9] + DIRECTION INPUT + USE SIGNAL
+ PORT
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ PLACED ( 25530 63000 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- mgmt_gpio_in + NET mgmt_gpio_in + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 4420 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- mgmt_gpio_oeb + NET mgmt_gpio_oeb + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 8500 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- mgmt_gpio_out + NET mgmt_gpio_out + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 10540 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- one + NET one + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 6460 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_ana_en + NET pad_gpio_ana_en + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 12580 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_ana_pol + NET pad_gpio_ana_pol + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 14620 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_ana_sel + NET pad_gpio_ana_sel + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 16660 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_dm[0] + NET pad_gpio_dm[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 18700 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_dm[1] + NET pad_gpio_dm[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 20740 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_dm[2] + NET pad_gpio_dm[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 22780 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_holdover + NET pad_gpio_holdover + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 24820 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_ib_mode_sel + NET pad_gpio_ib_mode_sel + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 26860 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_in + NET pad_gpio_in + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 28900 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_inenb + NET pad_gpio_inenb + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 30940 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_out + NET pad_gpio_out + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 32980 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_outenb + NET pad_gpio_outenb + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 35020 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_slow_sel + NET pad_gpio_slow_sel + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 37060 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- pad_gpio_vtrip_sel + NET pad_gpio_vtrip_sel + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 39100 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- resetn + NET resetn + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 41140 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- resetn_out + NET resetn_out + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 43180 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- serial_clock + NET serial_clock + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 45220 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- serial_clock_out + NET serial_clock_out + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 47260 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- serial_data_in + NET serial_data_in + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 49300 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- serial_data_out + NET serial_data_out + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 51340 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- serial_load + NET serial_load + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 53380 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- serial_load_out + NET serial_load_out + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 55420 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- user_gpio_in + NET user_gpio_in + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 57460 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- user_gpio_oeb + NET user_gpio_oeb + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 59500 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- user_gpio_out + NET user_gpio_out + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 61540 ) N ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- vccd + NET vccd + SPECIAL + DIRECTION INOUT + USE POWER
harden gpio_control_block
2021-11-04 09:19:12 -05:00
+ PORT
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ LAYER met5 ( -22820 -800 ) ( 22820 800 )
+ LAYER met5 ( -22820 -17700 ) ( 22820 -16100 )
+ LAYER met5 ( -22820 -34600 ) ( 22820 -33000 )
+ LAYER met5 ( -22820 -51500 ) ( 22820 -49900 )
+ LAYER met4 ( 10620 -54920 ) ( 12220 2680 )
+ LAYER met4 ( -14380 -54920 ) ( -12780 2680 )
+ FIXED ( 27180 57400 ) N ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- vccd1 + NET vccd1 + SPECIAL + DIRECTION INOUT + USE POWER
harden gpio_control_block
2021-11-04 09:19:12 -05:00
+ PORT
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ LAYER met5 ( -22820 -800 ) ( 22820 800 )
+ LAYER met5 ( -22820 -17700 ) ( 22820 -16100 )
+ LAYER met5 ( -22820 -34600 ) ( 22820 -33000 )
+ LAYER met4 ( 15620 -43260 ) ( 17220 14340 )
+ LAYER met4 ( -9380 -43260 ) ( -7780 14340 )
+ FIXED ( 27180 45740 ) N ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- vssd + NET vssd + SPECIAL + DIRECTION INOUT + USE GROUND
harden gpio_control_block
2021-11-04 09:19:12 -05:00
+ PORT
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ LAYER met5 ( -22820 -800 ) ( 22820 800 )
+ LAYER met5 ( -22820 -17700 ) ( 22820 -16100 )
+ LAYER met5 ( -22820 -34600 ) ( 22820 -33000 )
+ LAYER met4 ( -1880 -46470 ) ( -280 11130 )
+ FIXED ( 27180 48950 ) N ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- vssd1 + NET vssd1 + SPECIAL + DIRECTION INOUT + USE GROUND
harden gpio_control_block
2021-11-04 09:19:12 -05:00
+ PORT
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ LAYER met5 ( -22820 -800 ) ( 22820 800 )
+ LAYER met5 ( -22820 -17700 ) ( 22820 -16100 )
+ LAYER met5 ( -22820 -34600 ) ( 22820 -33000 )
+ LAYER met4 ( 3120 -51710 ) ( 4720 5890 )
+ FIXED ( 27180 54190 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
- zero + NET zero + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met3 ( -50000 -300 ) ( 50000 300 )
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
+ PLACED ( 120000 2380 ) N ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
END PINS
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
BLOCKAGES 9 ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
- LAYER li1 RECT ( 0 0 ) ( 16795 30025 ) ;
- LAYER li1 RECT ( 0 29965 ) ( 4265 65069 ) ;
- LAYER li1 RECT ( 4215 57405 ) ( 49815 64930 ) ;
- LAYER li1 RECT ( 16830 0 ) ( 49410 5240 ) ;
- LAYER li1 RECT ( 49000 0 ) ( 169810 64845 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- LAYER met4 RECT ( 49000 0 ) ( 170000 65000 ) ;
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
- LAYER met5 RECT ( 50000 0 ) ( 170000 65000 ) ;
[DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks
2021-12-05 11:48:02 -06:00
- LAYER met2 RECT ( 120000 0 ) ( 170000 65000 ) ;
- LAYER met1 RECT ( 120000 0 ) ( 170000 65000 ) ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
END BLOCKAGES
SPECIALNETS 4 ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- vccd ( PIN vccd ) ( gpio_in_buf VPB ) ( const_source VPB ) ( _139_ VPB ) ( _136_ VPB ) ( _135_ VPB ) ( _134_ VPB )
( _133_ VPB ) ( _132_ VPB ) ( _131_ VPB ) ( _130_ VPB ) ( _129_ VPB ) ( _128_ VPB ) ( _127_ VPB ) ( _126_ VPB )
( _125_ VPB ) ( _124_ VPB ) ( _123_ VPB ) ( _122_ VPB ) ( _121_ VPB ) ( _120_ VPB ) ( _119_ VPB ) ( _118_ VPB )
( _117_ VPB ) ( _116_ VPB ) ( _115_ VPB ) ( _114_ VPB ) ( _113_ VPB ) ( _112_ VPB ) ( _111_ VPB ) ( _110_ VPB )
( _109_ VPB ) ( _096_ VPB ) ( _095_ VPB ) ( _094_ VPB ) ( _093_ VPB ) ( _092_ VPB ) ( _091_ VPB ) ( _090_ VPB )
( _089_ VPB ) ( _088_ VPB ) ( _087_ VPB ) ( _086_ VPB ) ( _085_ VPB ) ( _084_ VPB ) ( _083_ VPB ) ( _082_ VPB )
( _081_ VPB ) ( _080_ VPB ) ( _079_ VPB ) ( _078_ VPB ) ( _077_ VPB ) ( _076_ VPB ) ( _075_ VPB ) ( _074_ VPB )
( _073_ VPB ) ( _072_ VPB ) ( _071_ VPB ) ( _070_ VPB ) ( _069_ VPB ) ( _068_ VPB ) ( _067_ VPB ) ( _066_ VPB )
( _065_ VPB ) ( _064_ VPB ) ( _063_ VPB ) ( _060_ VPB ) ( PHY_9 VPB ) ( PHY_8 VPB ) ( PHY_7 VPB ) ( PHY_6 VPB )
( PHY_5 VPB ) ( PHY_41 VPB ) ( PHY_40 VPB ) ( PHY_4 VPB ) ( PHY_39 VPB ) ( PHY_38 VPB ) ( PHY_37 VPB ) ( PHY_36 VPB )
( PHY_35 VPB ) ( PHY_34 VPB ) ( PHY_33 VPB ) ( PHY_32 VPB ) ( PHY_31 VPB ) ( PHY_30 VPB ) ( PHY_3 VPB ) ( PHY_29 VPB )
( PHY_28 VPB ) ( PHY_27 VPB ) ( PHY_26 VPB ) ( PHY_25 VPB ) ( PHY_24 VPB ) ( PHY_23 VPB ) ( PHY_22 VPB ) ( PHY_21 VPB )
( PHY_20 VPB ) ( PHY_2 VPB ) ( PHY_19 VPB ) ( PHY_18 VPB ) ( PHY_17 VPB ) ( PHY_16 VPB ) ( PHY_15 VPB ) ( PHY_14 VPB )
( PHY_13 VPB ) ( PHY_12 VPB ) ( PHY_11 VPB ) ( PHY_10 VPB ) ( PHY_1 VPB ) ( PHY_0 VPB ) ( gpio_in_buf VPWR ) ( const_source VPWR )
( _139_ VPWR ) ( _136_ VPWR ) ( _135_ VPWR ) ( _134_ VPWR ) ( _133_ VPWR ) ( _132_ VPWR ) ( _131_ VPWR ) ( _130_ VPWR )
( _129_ VPWR ) ( _128_ VPWR ) ( _127_ VPWR ) ( _126_ VPWR ) ( _125_ VPWR ) ( _124_ VPWR ) ( _123_ VPWR ) ( _122_ VPWR )
( _121_ VPWR ) ( _120_ VPWR ) ( _119_ VPWR ) ( _118_ VPWR ) ( _117_ VPWR ) ( _116_ VPWR ) ( _115_ VPWR ) ( _114_ VPWR )
( _113_ VPWR ) ( _112_ VPWR ) ( _111_ VPWR ) ( _110_ VPWR ) ( _109_ VPWR ) ( _096_ VPWR ) ( _095_ VPWR ) ( _094_ VPWR )
( _093_ VPWR ) ( _092_ VPWR ) ( _091_ VPWR ) ( _090_ VPWR ) ( _089_ VPWR ) ( _088_ VPWR ) ( _087_ VPWR ) ( _086_ VPWR )
( _085_ VPWR ) ( _084_ VPWR ) ( _083_ VPWR ) ( _082_ VPWR ) ( _081_ VPWR ) ( _080_ VPWR ) ( _079_ VPWR ) ( _078_ VPWR )
( _077_ VPWR ) ( _076_ VPWR ) ( _075_ VPWR ) ( _074_ VPWR ) ( _073_ VPWR ) ( _072_ VPWR ) ( _071_ VPWR ) ( _070_ VPWR )
( _069_ VPWR ) ( _068_ VPWR ) ( _067_ VPWR ) ( _066_ VPWR ) ( _065_ VPWR ) ( _064_ VPWR ) ( _063_ VPWR ) ( _060_ VPWR )
( TAP_73 VPWR ) ( TAP_72 VPWR ) ( TAP_71 VPWR ) ( TAP_70 VPWR ) ( TAP_69 VPWR ) ( TAP_68 VPWR ) ( TAP_67 VPWR ) ( TAP_66 VPWR )
( TAP_65 VPWR ) ( TAP_64 VPWR ) ( TAP_63 VPWR ) ( TAP_62 VPWR ) ( TAP_61 VPWR ) ( TAP_60 VPWR ) ( TAP_59 VPWR ) ( TAP_58 VPWR )
( TAP_57 VPWR ) ( TAP_56 VPWR ) ( TAP_55 VPWR ) ( TAP_54 VPWR ) ( TAP_53 VPWR ) ( TAP_52 VPWR ) ( TAP_51 VPWR ) ( TAP_50 VPWR )
( TAP_49 VPWR ) ( TAP_48 VPWR ) ( TAP_47 VPWR ) ( TAP_46 VPWR ) ( TAP_45 VPWR ) ( TAP_44 VPWR ) ( TAP_43 VPWR ) ( TAP_42 VPWR )
( PHY_9 VPWR ) ( PHY_8 VPWR ) ( PHY_7 VPWR ) ( PHY_6 VPWR ) ( PHY_5 VPWR ) ( PHY_41 VPWR ) ( PHY_40 VPWR ) ( PHY_4 VPWR )
( PHY_39 VPWR ) ( PHY_38 VPWR ) ( PHY_37 VPWR ) ( PHY_36 VPWR ) ( PHY_35 VPWR ) ( PHY_34 VPWR ) ( PHY_33 VPWR ) ( PHY_32 VPWR )
( PHY_31 VPWR ) ( PHY_30 VPWR ) ( PHY_3 VPWR ) ( PHY_29 VPWR ) ( PHY_28 VPWR ) ( PHY_27 VPWR ) ( PHY_26 VPWR ) ( PHY_25 VPWR )
( PHY_24 VPWR ) ( PHY_23 VPWR ) ( PHY_22 VPWR ) ( PHY_21 VPWR ) ( PHY_20 VPWR ) ( PHY_2 VPWR ) ( PHY_19 VPWR ) ( PHY_18 VPWR )
( PHY_17 VPWR ) ( PHY_16 VPWR ) ( PHY_15 VPWR ) ( PHY_14 VPWR ) ( PHY_13 VPWR ) ( PHY_12 VPWR ) ( PHY_11 VPWR ) ( PHY_10 VPWR )
( PHY_1 VPWR ) ( PHY_0 VPWR ) + USE POWER
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
+ ROUTED met4 0 + SHAPE STRIPE ( 13600 23600 ) via5_6_1600_1600_1_1_1600_1600
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 480 + SHAPE FOLLOWPIN ( 15180 21760 ) ( 51520 21760 )
NEW met1 480 + SHAPE FOLLOWPIN ( 15180 16320 ) ( 51520 16320 )
NEW met1 480 + SHAPE FOLLOWPIN ( 15180 10880 ) ( 51520 10880 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 59840 ) ( 51520 59840 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 54400 ) ( 51520 54400 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 48960 ) ( 51520 48960 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 43520 ) ( 51520 43520 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 38080 ) ( 51520 38080 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 32640 ) ( 51520 32640 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 27200 ) ( 51520 27200 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 5440 ) ( 51520 5440 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met5 1600 + SHAPE STRIPE ( 4360 57400 ) ( 50000 57400 )
NEW met5 1600 + SHAPE STRIPE ( 4360 40500 ) ( 50000 40500 )
NEW met5 1600 + SHAPE STRIPE ( 4360 23600 ) ( 50000 23600 )
NEW met5 1600 + SHAPE STRIPE ( 4360 6700 ) ( 50000 6700 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met4 1600 + SHAPE STRIPE ( 38600 2480 ) ( 38600 60080 )
NEW met4 1600 + SHAPE STRIPE ( 13600 2480 ) ( 13600 60080 )
NEW met4 0 + SHAPE STRIPE ( 38600 57400 ) via5_6_1600_1600_1_1_1600_1600
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met4 0 + SHAPE STRIPE ( 38600 40500 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 38600 23600 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 38600 6700 ) via5_6_1600_1600_1_1_1600_1600
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met4 0 + SHAPE STRIPE ( 13600 57400 ) via5_6_1600_1600_1_1_1600_1600
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met4 0 + SHAPE STRIPE ( 13600 40500 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 13600 23600 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 13600 6700 ) via5_6_1600_1600_1_1_1600_1600
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met3 330 + SHAPE STRIPE ( 37810 59840 ) ( 39390 59840 )
NEW met3 0 + SHAPE STRIPE ( 38600 59840 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 59840 ) ( 39370 59840 )
NEW met2 0 + SHAPE STRIPE ( 38600 59840 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 59840 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 54400 ) ( 39390 54400 )
NEW met3 0 + SHAPE STRIPE ( 38600 54400 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 54400 ) ( 39370 54400 )
NEW met2 0 + SHAPE STRIPE ( 38600 54400 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 54400 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 48960 ) ( 39390 48960 )
NEW met3 0 + SHAPE STRIPE ( 38600 48960 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 48960 ) ( 39370 48960 )
NEW met2 0 + SHAPE STRIPE ( 38600 48960 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 48960 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 43520 ) ( 39390 43520 )
NEW met3 0 + SHAPE STRIPE ( 38600 43520 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 43520 ) ( 39370 43520 )
NEW met2 0 + SHAPE STRIPE ( 38600 43520 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 43520 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 38080 ) ( 39390 38080 )
NEW met3 0 + SHAPE STRIPE ( 38600 38080 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 38080 ) ( 39370 38080 )
NEW met2 0 + SHAPE STRIPE ( 38600 38080 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 38080 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 32640 ) ( 39390 32640 )
NEW met3 0 + SHAPE STRIPE ( 38600 32640 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 32640 ) ( 39370 32640 )
NEW met2 0 + SHAPE STRIPE ( 38600 32640 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 32640 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 27200 ) ( 39390 27200 )
NEW met3 0 + SHAPE STRIPE ( 38600 27200 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 27200 ) ( 39370 27200 )
NEW met2 0 + SHAPE STRIPE ( 38600 27200 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 27200 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 21760 ) ( 39390 21760 )
NEW met3 0 + SHAPE STRIPE ( 38600 21760 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 21760 ) ( 39370 21760 )
NEW met2 0 + SHAPE STRIPE ( 38600 21760 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 21760 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 16320 ) ( 39390 16320 )
NEW met3 0 + SHAPE STRIPE ( 38600 16320 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 16320 ) ( 39370 16320 )
NEW met2 0 + SHAPE STRIPE ( 38600 16320 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 16320 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 10880 ) ( 39390 10880 )
NEW met3 0 + SHAPE STRIPE ( 38600 10880 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 10880 ) ( 39370 10880 )
NEW met2 0 + SHAPE STRIPE ( 38600 10880 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 10880 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 37810 5440 ) ( 39390 5440 )
NEW met3 0 + SHAPE STRIPE ( 38600 5440 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 37830 5440 ) ( 39370 5440 )
NEW met2 0 + SHAPE STRIPE ( 38600 5440 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 38600 5440 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 59840 ) ( 14390 59840 )
NEW met3 0 + SHAPE STRIPE ( 13600 59840 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 59840 ) ( 14370 59840 )
NEW met2 0 + SHAPE STRIPE ( 13600 59840 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 59840 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 54400 ) ( 14390 54400 )
NEW met3 0 + SHAPE STRIPE ( 13600 54400 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 54400 ) ( 14370 54400 )
NEW met2 0 + SHAPE STRIPE ( 13600 54400 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 54400 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 48960 ) ( 14390 48960 )
NEW met3 0 + SHAPE STRIPE ( 13600 48960 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 48960 ) ( 14370 48960 )
NEW met2 0 + SHAPE STRIPE ( 13600 48960 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 48960 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 43520 ) ( 14390 43520 )
NEW met3 0 + SHAPE STRIPE ( 13600 43520 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 43520 ) ( 14370 43520 )
NEW met2 0 + SHAPE STRIPE ( 13600 43520 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 43520 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 38080 ) ( 14390 38080 )
NEW met3 0 + SHAPE STRIPE ( 13600 38080 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 38080 ) ( 14370 38080 )
NEW met2 0 + SHAPE STRIPE ( 13600 38080 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 38080 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 32640 ) ( 14390 32640 )
NEW met3 0 + SHAPE STRIPE ( 13600 32640 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 32640 ) ( 14370 32640 )
NEW met2 0 + SHAPE STRIPE ( 13600 32640 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 32640 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 27200 ) ( 14390 27200 )
NEW met3 0 + SHAPE STRIPE ( 13600 27200 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 27200 ) ( 14370 27200 )
NEW met2 0 + SHAPE STRIPE ( 13600 27200 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 27200 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 12810 5440 ) ( 14390 5440 )
NEW met3 0 + SHAPE STRIPE ( 13600 5440 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 12830 5440 ) ( 14370 5440 )
NEW met2 0 + SHAPE STRIPE ( 13600 5440 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 13600 5440 ) via2_3_1600_480_1_5_320_320 ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- vccd1 ( PIN vccd1 ) ( * vccd1 ) + USE POWER
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
+ ROUTED met4 0 + SHAPE STRIPE ( 6980 11940 ) via5_6_1400_1600_1_1_1600_1600
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met5 1600 + SHAPE STRIPE ( 4360 45740 ) ( 50000 45740 )
NEW met5 1600 + SHAPE STRIPE ( 4360 28840 ) ( 50000 28840 )
NEW met5 1600 + SHAPE STRIPE ( 4360 11940 ) ( 50000 11940 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met4 1600 + SHAPE STRIPE ( 43600 2480 ) ( 43600 60080 )
NEW met4 1600 + SHAPE STRIPE ( 18600 2480 ) ( 18600 60080 )
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met4 0 + SHAPE STRIPE ( 43600 45740 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 43600 28840 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 43600 11940 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 18600 45740 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 18600 28840 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 18600 11940 ) via5_6_1600_1600_1_1_1600_1600 ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- vssd ( PIN vssd ) ( gpio_in_buf VNB ) ( const_source VNB ) ( _139_ VNB ) ( _136_ VNB ) ( _135_ VNB ) ( _134_ VNB )
( _133_ VNB ) ( _132_ VNB ) ( _131_ VNB ) ( _130_ VNB ) ( _129_ VNB ) ( _128_ VNB ) ( _127_ VNB ) ( _126_ VNB )
( _125_ VNB ) ( _124_ VNB ) ( _123_ VNB ) ( _122_ VNB ) ( _121_ VNB ) ( _120_ VNB ) ( _119_ VNB ) ( _118_ VNB )
( _117_ VNB ) ( _116_ VNB ) ( _115_ VNB ) ( _114_ VNB ) ( _113_ VNB ) ( _112_ VNB ) ( _111_ VNB ) ( _110_ VNB )
( _109_ VNB ) ( _096_ VNB ) ( _095_ VNB ) ( _094_ VNB ) ( _093_ VNB ) ( _092_ VNB ) ( _091_ VNB ) ( _090_ VNB )
( _089_ VNB ) ( _088_ VNB ) ( _087_ VNB ) ( _086_ VNB ) ( _085_ VNB ) ( _084_ VNB ) ( _083_ VNB ) ( _082_ VNB )
( _081_ VNB ) ( _080_ VNB ) ( _079_ VNB ) ( _078_ VNB ) ( _077_ VNB ) ( _076_ VNB ) ( _075_ VNB ) ( _074_ VNB )
( _073_ VNB ) ( _072_ VNB ) ( _071_ VNB ) ( _070_ VNB ) ( _069_ VNB ) ( _068_ VNB ) ( _067_ VNB ) ( _066_ VNB )
( _065_ VNB ) ( _064_ VNB ) ( _063_ VNB ) ( _060_ VNB ) ( PHY_9 VNB ) ( PHY_8 VNB ) ( PHY_7 VNB ) ( PHY_6 VNB )
( PHY_5 VNB ) ( PHY_41 VNB ) ( PHY_40 VNB ) ( PHY_4 VNB ) ( PHY_39 VNB ) ( PHY_38 VNB ) ( PHY_37 VNB ) ( PHY_36 VNB )
( PHY_35 VNB ) ( PHY_34 VNB ) ( PHY_33 VNB ) ( PHY_32 VNB ) ( PHY_31 VNB ) ( PHY_30 VNB ) ( PHY_3 VNB ) ( PHY_29 VNB )
( PHY_28 VNB ) ( PHY_27 VNB ) ( PHY_26 VNB ) ( PHY_25 VNB ) ( PHY_24 VNB ) ( PHY_23 VNB ) ( PHY_22 VNB ) ( PHY_21 VNB )
( PHY_20 VNB ) ( PHY_2 VNB ) ( PHY_19 VNB ) ( PHY_18 VNB ) ( PHY_17 VNB ) ( PHY_16 VNB ) ( PHY_15 VNB ) ( PHY_14 VNB )
( PHY_13 VNB ) ( PHY_12 VNB ) ( PHY_11 VNB ) ( PHY_10 VNB ) ( PHY_1 VNB ) ( PHY_0 VNB ) ( gpio_in_buf VGND ) ( const_source VGND )
( _139_ VGND ) ( _136_ VGND ) ( _135_ VGND ) ( _134_ VGND ) ( _133_ VGND ) ( _132_ VGND ) ( _131_ VGND ) ( _130_ VGND )
( _129_ VGND ) ( _128_ VGND ) ( _127_ VGND ) ( _126_ VGND ) ( _125_ VGND ) ( _124_ VGND ) ( _123_ VGND ) ( _122_ VGND )
( _121_ VGND ) ( _120_ VGND ) ( _119_ VGND ) ( _118_ VGND ) ( _117_ VGND ) ( _116_ VGND ) ( _115_ VGND ) ( _114_ VGND )
( _113_ VGND ) ( _112_ VGND ) ( _111_ VGND ) ( _110_ VGND ) ( _109_ VGND ) ( _096_ VGND ) ( _095_ VGND ) ( _094_ VGND )
( _093_ VGND ) ( _092_ VGND ) ( _091_ VGND ) ( _090_ VGND ) ( _089_ VGND ) ( _088_ VGND ) ( _087_ VGND ) ( _086_ VGND )
( _085_ VGND ) ( _084_ VGND ) ( _083_ VGND ) ( _082_ VGND ) ( _081_ VGND ) ( _080_ VGND ) ( _079_ VGND ) ( _078_ VGND )
( _077_ VGND ) ( _076_ VGND ) ( _075_ VGND ) ( _074_ VGND ) ( _073_ VGND ) ( _072_ VGND ) ( _071_ VGND ) ( _070_ VGND )
( _069_ VGND ) ( _068_ VGND ) ( _067_ VGND ) ( _066_ VGND ) ( _065_ VGND ) ( _064_ VGND ) ( _063_ VGND ) ( _060_ VGND )
( TAP_73 VGND ) ( TAP_72 VGND ) ( TAP_71 VGND ) ( TAP_70 VGND ) ( TAP_69 VGND ) ( TAP_68 VGND ) ( TAP_67 VGND ) ( TAP_66 VGND )
( TAP_65 VGND ) ( TAP_64 VGND ) ( TAP_63 VGND ) ( TAP_62 VGND ) ( TAP_61 VGND ) ( TAP_60 VGND ) ( TAP_59 VGND ) ( TAP_58 VGND )
( TAP_57 VGND ) ( TAP_56 VGND ) ( TAP_55 VGND ) ( TAP_54 VGND ) ( TAP_53 VGND ) ( TAP_52 VGND ) ( TAP_51 VGND ) ( TAP_50 VGND )
( TAP_49 VGND ) ( TAP_48 VGND ) ( TAP_47 VGND ) ( TAP_46 VGND ) ( TAP_45 VGND ) ( TAP_44 VGND ) ( TAP_43 VGND ) ( TAP_42 VGND )
( PHY_9 VGND ) ( PHY_8 VGND ) ( PHY_7 VGND ) ( PHY_6 VGND ) ( PHY_5 VGND ) ( PHY_41 VGND ) ( PHY_40 VGND ) ( PHY_4 VGND )
( PHY_39 VGND ) ( PHY_38 VGND ) ( PHY_37 VGND ) ( PHY_36 VGND ) ( PHY_35 VGND ) ( PHY_34 VGND ) ( PHY_33 VGND ) ( PHY_32 VGND )
( PHY_31 VGND ) ( PHY_30 VGND ) ( PHY_3 VGND ) ( PHY_29 VGND ) ( PHY_28 VGND ) ( PHY_27 VGND ) ( PHY_26 VGND ) ( PHY_25 VGND )
( PHY_24 VGND ) ( PHY_23 VGND ) ( PHY_22 VGND ) ( PHY_21 VGND ) ( PHY_20 VGND ) ( PHY_2 VGND ) ( PHY_19 VGND ) ( PHY_18 VGND )
( PHY_17 VGND ) ( PHY_16 VGND ) ( PHY_15 VGND ) ( PHY_14 VGND ) ( PHY_13 VGND ) ( PHY_12 VGND ) ( PHY_11 VGND ) ( PHY_10 VGND )
( PHY_1 VGND ) ( PHY_0 VGND ) + USE GROUND
+ ROUTED met1 480 + SHAPE FOLLOWPIN ( 15180 24480 ) ( 51520 24480 )
NEW met1 480 + SHAPE FOLLOWPIN ( 15180 19040 ) ( 51520 19040 )
NEW met1 480 + SHAPE FOLLOWPIN ( 15180 13600 ) ( 51520 13600 )
NEW met1 480 + SHAPE FOLLOWPIN ( 15180 8160 ) ( 51520 8160 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 57120 ) ( 51520 57120 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 51680 ) ( 51520 51680 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 46240 ) ( 51520 46240 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 40800 ) ( 51520 40800 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 35360 ) ( 51520 35360 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 29920 ) ( 51520 29920 )
NEW met1 480 + SHAPE FOLLOWPIN ( 4600 2720 ) ( 51520 2720 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met5 1600 + SHAPE STRIPE ( 4360 48950 ) ( 50000 48950 )
NEW met5 1600 + SHAPE STRIPE ( 4360 32050 ) ( 50000 32050 )
NEW met5 1600 + SHAPE STRIPE ( 4360 15150 ) ( 50000 15150 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met4 1600 + SHAPE STRIPE ( 26100 2480 ) ( 26100 60080 )
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met4 0 + SHAPE STRIPE ( 26100 48950 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 26100 32050 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 26100 15150 ) via5_6_1600_1600_1_1_1600_1600
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met3 330 + SHAPE STRIPE ( 25310 57120 ) ( 26890 57120 )
NEW met3 0 + SHAPE STRIPE ( 26100 57120 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 57120 ) ( 26870 57120 )
NEW met2 0 + SHAPE STRIPE ( 26100 57120 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 57120 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 51680 ) ( 26890 51680 )
NEW met3 0 + SHAPE STRIPE ( 26100 51680 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 51680 ) ( 26870 51680 )
NEW met2 0 + SHAPE STRIPE ( 26100 51680 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 51680 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 46240 ) ( 26890 46240 )
NEW met3 0 + SHAPE STRIPE ( 26100 46240 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 46240 ) ( 26870 46240 )
NEW met2 0 + SHAPE STRIPE ( 26100 46240 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 46240 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 40800 ) ( 26890 40800 )
NEW met3 0 + SHAPE STRIPE ( 26100 40800 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 40800 ) ( 26870 40800 )
NEW met2 0 + SHAPE STRIPE ( 26100 40800 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 40800 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 35360 ) ( 26890 35360 )
NEW met3 0 + SHAPE STRIPE ( 26100 35360 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 35360 ) ( 26870 35360 )
NEW met2 0 + SHAPE STRIPE ( 26100 35360 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 35360 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 29920 ) ( 26890 29920 )
NEW met3 0 + SHAPE STRIPE ( 26100 29920 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 29920 ) ( 26870 29920 )
NEW met2 0 + SHAPE STRIPE ( 26100 29920 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 29920 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 24480 ) ( 26890 24480 )
NEW met3 0 + SHAPE STRIPE ( 26100 24480 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 24480 ) ( 26870 24480 )
NEW met2 0 + SHAPE STRIPE ( 26100 24480 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 24480 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 19040 ) ( 26890 19040 )
NEW met3 0 + SHAPE STRIPE ( 26100 19040 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 19040 ) ( 26870 19040 )
NEW met2 0 + SHAPE STRIPE ( 26100 19040 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 19040 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 13600 ) ( 26890 13600 )
NEW met3 0 + SHAPE STRIPE ( 26100 13600 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 13600 ) ( 26870 13600 )
NEW met2 0 + SHAPE STRIPE ( 26100 13600 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 13600 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 8160 ) ( 26890 8160 )
NEW met3 0 + SHAPE STRIPE ( 26100 8160 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 8160 ) ( 26870 8160 )
NEW met2 0 + SHAPE STRIPE ( 26100 8160 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 8160 ) via2_3_1600_480_1_5_320_320
NEW met3 330 + SHAPE STRIPE ( 25310 2720 ) ( 26890 2720 )
NEW met3 0 + SHAPE STRIPE ( 26100 2720 ) via4_5_1600_480_1_4_400_400
NEW met2 370 + SHAPE STRIPE ( 25330 2720 ) ( 26870 2720 )
NEW met2 0 + SHAPE STRIPE ( 26100 2720 ) via3_4_1600_480_1_4_400_400
NEW met1 0 + SHAPE STRIPE ( 26100 2720 ) via2_3_1600_480_1_5_320_320 ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- vssd1 ( PIN vssd1 ) ( * vssd1 ) + USE GROUND
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
+ ROUTED met4 0 + SHAPE STRIPE ( 10680 20390 ) via5_6_1400_1600_1_1_1600_1600
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met5 1600 + SHAPE STRIPE ( 4360 54190 ) ( 50000 54190 )
NEW met5 1600 + SHAPE STRIPE ( 4360 37290 ) ( 50000 37290 )
NEW met5 1600 + SHAPE STRIPE ( 4360 20390 ) ( 50000 20390 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met4 1600 + SHAPE STRIPE ( 31100 2480 ) ( 31100 60080 )
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met4 0 + SHAPE STRIPE ( 31100 54190 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 31100 37290 ) via5_6_1600_1600_1_1_1600_1600
NEW met4 0 + SHAPE STRIPE ( 31100 20390 ) via5_6_1600_1600_1_1_1600_1600 ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
END SPECIALNETS
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NETS 168 ;
- _000_ ( _116_ Q_N ) ( _068_ A_N ) + USE SIGNAL
+ ROUTED met1 ( 44850 12750 ) ( 45310 * )
NEW met2 ( 44850 12750 ) ( * 24990 )
NEW li1 ( 45310 12750 ) L1M1_PR_MR
NEW met1 ( 44850 12750 ) M1M2_PR
NEW li1 ( 44850 24990 ) L1M1_PR_MR
NEW met1 ( 44850 24990 ) M1M2_PR
NEW met1 ( 44850 24990 ) RECT ( -355 -70 0 70 ) ;
- _001_ ( gpio_in_buf A ) ( _060_ Y ) + USE SIGNAL
+ ROUTED met2 ( 47610 4930 ) ( * 23290 )
NEW li1 ( 47610 4930 ) L1M1_PR_MR
NEW met1 ( 47610 4930 ) M1M2_PR
NEW li1 ( 47610 23290 ) L1M1_PR_MR
NEW met1 ( 47610 23290 ) M1M2_PR
NEW met1 ( 47610 4930 ) RECT ( -355 -70 0 70 )
NEW met1 ( 47610 23290 ) RECT ( -355 -70 0 70 ) ;
- _002_ ( _109_ RESET_B ) ( _071_ X ) + USE SIGNAL
+ ROUTED met1 ( 36570 52870 ) ( 37950 * )
NEW met2 ( 36570 52870 ) ( * 54910 )
NEW li1 ( 37950 52870 ) L1M1_PR_MR
NEW met1 ( 36570 52870 ) M1M2_PR
NEW li1 ( 36570 54910 ) L1M1_PR_MR
NEW met1 ( 36570 54910 ) M1M2_PR
NEW met1 ( 36570 54910 ) RECT ( -355 -70 0 70 ) ;
- _003_ ( _109_ SET_B ) ( _072_ Y ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 33810 22270 ) ( 36110 * )
NEW met1 ( 36110 22270 ) ( * 22610 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 36110 22610 ) ( 37490 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 33810 22270 ) ( * 52530 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 33810 52530 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 33810 22270 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 37490 22610 ) L1M1_PR_MR ;
- _004_ ( _110_ RESET_B ) ( _073_ X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 4370 59330 ) ( 6210 * )
NEW met1 ( 4370 59330 ) ( * 60350 )
NEW met2 ( 23690 55930 ) ( * 60350 )
NEW met1 ( 23690 55930 ) ( 26450 * )
NEW met1 ( 4370 60350 ) ( 23690 * )
NEW li1 ( 6210 59330 ) L1M1_PR_MR
NEW met1 ( 23690 60350 ) M1M2_PR
NEW met1 ( 23690 55930 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 26450 55930 ) L1M1_PR_MR ;
- _005_ ( _110_ SET_B ) ( _074_ Y ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 13110 4590 ) ( 24150 * )
NEW met2 ( 23690 35020 ) ( 24150 * )
NEW met2 ( 23690 35020 ) ( * 51340 )
NEW met2 ( 22770 51340 ) ( 23690 * )
NEW met2 ( 22770 51340 ) ( * 56270 )
NEW met2 ( 24150 4590 ) ( * 35020 )
NEW met1 ( 24150 4590 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 13110 4590 ) L1M1_PR_MR
NEW met1 ( 22770 56270 ) M1M2_PR ;
- _006_ ( _111_ RESET_B ) ( _075_ X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 42550 34170 ) ( * 42500 )
NEW met3 ( 39330 42500 ) ( 42550 * )
NEW met2 ( 39330 42500 ) ( * 43010 )
NEW met1 ( 30590 43010 ) ( 39330 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 42550 34170 ) L1M1_PR_MR
NEW met1 ( 42550 34170 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 42550 42500 ) M2M3_PR
NEW met2 ( 39330 42500 ) M2M3_PR
NEW met1 ( 39330 43010 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 30590 43010 ) L1M1_PR_MR
NEW met1 ( 42550 34170 ) RECT ( -355 -70 0 70 ) ;
- _007_ ( _111_ SET_B ) ( _076_ Y ) + USE SIGNAL
+ ROUTED met1 ( 40710 34510 0 ) ( 42090 * )
NEW met2 ( 42090 34510 ) ( * 44030 )
NEW met1 ( 42090 34510 ) M1M2_PR
NEW li1 ( 42090 44030 ) L1M1_PR_MR
NEW met1 ( 42090 44030 ) M1M2_PR
NEW met1 ( 42090 44030 ) RECT ( -355 -70 0 70 ) ;
- _008_ ( _112_ RESET_B ) ( _077_ X ) + USE SIGNAL
+ ROUTED met1 ( 46690 39610 ) ( 49450 * )
NEW met2 ( 49450 39610 ) ( * 41650 )
NEW li1 ( 46690 39610 ) L1M1_PR_MR
NEW met1 ( 49450 39610 ) M1M2_PR
NEW li1 ( 49450 41650 ) L1M1_PR_MR
NEW met1 ( 49450 41650 ) M1M2_PR
NEW met1 ( 49450 41650 ) RECT ( -355 -70 0 70 ) ;
- _009_ ( _112_ SET_B ) ( _078_ Y ) + USE SIGNAL
+ ROUTED met2 ( 44390 39950 ) ( * 47770 )
NEW met1 ( 44390 39950 ) M1M2_PR
NEW li1 ( 44390 47770 ) L1M1_PR_MR
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met1 ( 44390 47770 ) M1M2_PR
NEW met1 ( 44390 47770 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- _010_ ( _113_ RESET_B ) ( _079_ X ) + USE SIGNAL
+ ROUTED met2 ( 27370 47430 ) ( * 57970 )
NEW met1 ( 27370 57970 ) ( 32890 * )
NEW li1 ( 27370 47430 ) L1M1_PR_MR
NEW met1 ( 27370 47430 ) M1M2_PR
NEW met1 ( 27370 57970 ) M1M2_PR
NEW li1 ( 32890 57970 ) L1M1_PR_MR
NEW met1 ( 27370 47430 ) RECT ( -355 -70 0 70 ) ;
- _011_ ( _113_ SET_B ) ( _080_ Y ) + USE SIGNAL
+ ROUTED met1 ( 8510 45390 ) ( * 45730 )
NEW met2 ( 21850 45730 ) ( * 47090 )
NEW met1 ( 8510 45730 ) ( 21850 * )
NEW li1 ( 8510 45390 ) L1M1_PR_MR
NEW met1 ( 21850 45730 ) M1M2_PR
NEW met1 ( 21850 47090 ) M1M2_PR ;
- _012_ ( _114_ RESET_B ) ( _081_ X ) + USE SIGNAL
+ ROUTED met1 ( 27370 36550 ) ( 27830 * )
NEW met2 ( 27830 36550 ) ( * 44030 )
NEW met1 ( 27830 44030 ) ( 28290 * )
NEW li1 ( 27370 36550 ) L1M1_PR_MR
NEW met1 ( 27830 36550 ) M1M2_PR
NEW met1 ( 27830 44030 ) M1M2_PR
NEW li1 ( 28290 44030 ) L1M1_PR_MR ;
- _013_ ( _114_ SET_B ) ( _082_ Y ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 9890 4930 ) ( * 7310 )
NEW met1 ( 9890 7310 ) ( 22310 * )
NEW met2 ( 22310 7310 ) ( * 36210 )
NEW li1 ( 9890 4930 ) L1M1_PR_MR
NEW met1 ( 9890 4930 ) M1M2_PR
NEW met1 ( 9890 7310 ) M1M2_PR
NEW met1 ( 22310 7310 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 22310 36210 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 9890 4930 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- _014_ ( _115_ RESET_B ) ( _083_ X ) + USE SIGNAL
+ ROUTED met1 ( 24150 50490 ) ( 26910 * )
NEW met2 ( 24150 50490 ) ( * 57970 )
NEW met1 ( 20010 57970 ) ( 24150 * )
NEW li1 ( 26910 50490 ) L1M1_PR_MR
NEW met1 ( 24150 50490 ) M1M2_PR
NEW met1 ( 24150 57970 ) M1M2_PR
NEW li1 ( 20010 57970 ) L1M1_PR_MR ;
- _015_ ( _115_ SET_B ) ( _084_ Y ) + USE SIGNAL
+ ROUTED met1 ( 19090 10030 ) ( 23690 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 23690 10030 ) ( * 13800 )
NEW met2 ( 23230 13800 ) ( 23690 * )
NEW met2 ( 23230 13800 ) ( * 50830 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 19090 10030 ) L1M1_PR_MR
NEW met1 ( 23690 10030 ) M1M2_PR
NEW met1 ( 23230 50830 ) M1M2_PR ;
- _016_ ( _116_ RESET_B ) ( _085_ X ) + USE SIGNAL
+ ROUTED met1 ( 46690 6630 ) ( 47610 * )
NEW met1 ( 43930 25670 ) ( 46690 * )
NEW met2 ( 46690 6630 ) ( * 25670 )
NEW li1 ( 47610 6630 ) L1M1_PR_MR
NEW met1 ( 46690 6630 ) M1M2_PR
NEW met1 ( 46690 25670 ) M1M2_PR
NEW li1 ( 43930 25670 ) L1M1_PR_MR ;
- _017_ ( _116_ SET_B ) ( _086_ Y ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 42090 25330 0 ) ( 46230 * )
NEW met2 ( 46230 25330 ) ( * 33150 )
NEW met1 ( 46230 33150 ) ( 46690 * )
NEW met1 ( 46230 25330 ) M1M2_PR
NEW met1 ( 46230 33150 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 46690 33150 ) L1M1_PR_MR ;
- _018_ ( _117_ RESET_B ) ( _087_ X ) + USE SIGNAL
+ ROUTED met1 ( 43930 50490 ) ( 48990 * )
NEW met2 ( 48990 50490 ) ( * 57970 )
NEW met1 ( 48990 57970 ) ( 49450 * )
NEW li1 ( 43930 50490 ) L1M1_PR_MR
NEW met1 ( 48990 50490 ) M1M2_PR
NEW met1 ( 48990 57970 ) M1M2_PR
NEW li1 ( 49450 57970 ) L1M1_PR_MR ;
- _019_ ( _117_ SET_B ) ( _088_ Y ) + USE SIGNAL
+ ROUTED met1 ( 42090 50830 0 ) ( 43470 * )
NEW met2 ( 43470 17510 ) ( * 50830 )
NEW met1 ( 43470 17510 ) ( 43930 * )
NEW met1 ( 43470 50830 ) M1M2_PR
NEW met1 ( 43470 17510 ) M1M2_PR
NEW li1 ( 43930 17510 ) L1M1_PR_MR ;
- _020_ ( _118_ RESET_B ) ( _089_ X ) + USE SIGNAL
+ ROUTED met2 ( 49450 50830 ) ( * 55930 )
NEW met1 ( 46690 55930 ) ( 49450 * )
NEW li1 ( 49450 50830 ) L1M1_PR_MR
NEW met1 ( 49450 50830 ) M1M2_PR
NEW met1 ( 49450 55930 ) M1M2_PR
NEW li1 ( 46690 55930 ) L1M1_PR_MR
NEW met1 ( 49450 50830 ) RECT ( -355 -70 0 70 ) ;
- _021_ ( _118_ SET_B ) ( _090_ Y ) + USE SIGNAL
+ ROUTED met2 ( 43470 12750 ) ( * 13800 )
NEW met2 ( 43470 13800 ) ( 43930 * )
NEW met2 ( 43930 13800 ) ( * 56270 )
NEW li1 ( 43470 12750 ) L1M1_PR_MR
NEW met1 ( 43470 12750 ) M1M2_PR
NEW met1 ( 43930 56270 ) M1M2_PR
NEW met1 ( 43470 12750 ) RECT ( -355 -70 0 70 ) ;
- _022_ ( _119_ RESET_B ) ( _091_ X ) + USE SIGNAL
+ ROUTED met1 ( 26910 17850 ) ( 29670 * )
NEW met2 ( 29670 17850 ) ( * 19890 )
NEW met1 ( 27830 19890 ) ( 29670 * )
NEW li1 ( 26910 17850 ) L1M1_PR_MR
NEW met1 ( 29670 17850 ) M1M2_PR
NEW met1 ( 29670 19890 ) M1M2_PR
NEW li1 ( 27830 19890 ) L1M1_PR_MR ;
- _023_ ( _119_ SET_B ) ( _092_ Y ) + USE SIGNAL
+ ROUTED met1 ( 9890 33150 ) ( 13800 * )
NEW met1 ( 13800 33150 ) ( * 33490 )
NEW met1 ( 13800 33490 ) ( 18630 * )
NEW met1 ( 18630 33150 ) ( * 33490 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 18630 33150 ) ( 23690 * )
NEW met2 ( 23690 18530 ) ( * 33150 )
NEW met1 ( 23690 18530 ) ( 25530 * )
NEW met1 ( 25530 18190 ) ( * 18530 )
NEW met1 ( 25070 18190 0 ) ( 25530 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 9890 33150 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 23690 33150 ) M1M2_PR
NEW met1 ( 23690 18530 ) M1M2_PR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- _024_ ( _120_ RESET_B ) ( _093_ X ) + USE SIGNAL
+ ROUTED met1 ( 30130 23290 ) ( 31510 * )
NEW met2 ( 31510 23290 ) ( * 33150 )
NEW met1 ( 31510 33150 ) ( 32890 * )
NEW li1 ( 30130 23290 ) L1M1_PR_MR
NEW met1 ( 31510 23290 ) M1M2_PR
NEW met1 ( 31510 33150 ) M1M2_PR
NEW li1 ( 32890 33150 ) L1M1_PR_MR ;
- _025_ ( _120_ SET_B ) ( _094_ Y ) + USE SIGNAL
+ ROUTED met1 ( 19090 23630 ) ( * 23970 )
NEW met1 ( 19090 23970 ) ( 24150 * )
NEW met1 ( 24150 23630 ) ( * 23970 )
NEW met1 ( 24150 23630 ) ( 24610 * 0 )
NEW li1 ( 19090 23630 ) L1M1_PR_MR ;
- _026_ ( _121_ RESET_B ) ( _095_ X ) + USE SIGNAL
+ ROUTED met1 ( 32890 29070 ) ( 36110 * )
NEW met2 ( 36110 29070 ) ( * 31110 )
NEW li1 ( 32890 29070 ) L1M1_PR_MR
NEW met1 ( 36110 29070 ) M1M2_PR
NEW li1 ( 36110 31110 ) L1M1_PR_MR
NEW met1 ( 36110 31110 ) M1M2_PR
NEW met1 ( 36110 31110 ) RECT ( -355 -70 0 70 ) ;
- _027_ ( _121_ SET_B ) ( _096_ Y ) + USE SIGNAL
+ ROUTED met1 ( 34270 30770 0 ) ( 35190 * )
NEW met2 ( 35190 23630 ) ( * 30770 )
NEW met1 ( 35190 30770 ) M1M2_PR
NEW li1 ( 35190 23630 ) L1M1_PR_MR
NEW met1 ( 35190 23630 ) M1M2_PR
NEW met1 ( 35190 23630 ) RECT ( -355 -70 0 70 ) ;
- _042_ ( _065_ A1 ) ( _064_ X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 47610 26010 ) ( * 26180 )
NEW met3 ( 47380 26180 ) ( 47610 * )
NEW met4 ( 47380 26180 ) ( * 29580 )
NEW met3 ( 47380 29580 ) ( 47610 * )
NEW met2 ( 47610 29580 ) ( * 36550 )
NEW met1 ( 47610 36550 ) ( 48070 * )
NEW li1 ( 47610 26010 ) L1M1_PR_MR
NEW met1 ( 47610 26010 ) M1M2_PR
NEW met2 ( 47610 26180 ) M2M3_PR
NEW met3 ( 47380 26180 ) M3M4_PR
NEW met3 ( 47380 29580 ) M3M4_PR
NEW met2 ( 47610 29580 ) M2M3_PR
NEW met1 ( 47610 36550 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 48070 36550 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 47610 26010 ) RECT ( -355 -70 0 70 )
NEW met3 ( 47610 26180 ) RECT ( 0 -150 390 150 )
NEW met3 ( 47380 29580 ) RECT ( -390 -150 0 150 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- _043_ ( _070_ B1 ) ( _066_ Y ) + USE SIGNAL
+ ROUTED met2 ( 45770 31110 ) ( * 44030 )
NEW met1 ( 45770 44030 ) ( 46690 * )
NEW li1 ( 45770 31110 ) L1M1_PR_MR
NEW met1 ( 45770 31110 ) M1M2_PR
NEW met1 ( 45770 44030 ) M1M2_PR
NEW li1 ( 46690 44030 ) L1M1_PR_MR
NEW met1 ( 45770 31110 ) RECT ( -355 -70 0 70 ) ;
- _044_ ( _069_ A2 ) ( _068_ B ) ( _067_ X ) + USE SIGNAL
+ ROUTED met2 ( 48530 17850 ) ( * 28050 )
NEW met2 ( 48530 11730 ) ( * 17850 )
NEW met1 ( 47150 11730 ) ( 48530 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 46230 28050 ) ( 48530 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 48530 11730 ) M1M2_PR
NEW li1 ( 48530 17850 ) L1M1_PR_MR
NEW met1 ( 48530 17850 ) M1M2_PR
NEW met1 ( 48530 28050 ) M1M2_PR
NEW li1 ( 47150 11730 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 46230 28050 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 48530 17850 ) RECT ( -355 -70 0 70 ) ;
- _045_ ( _070_ A1 ) ( _068_ X ) + USE SIGNAL
+ ROUTED met1 ( 47610 13090 ) ( 48070 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 48070 13090 ) ( * 26860 )
NEW met3 ( 48070 26860 ) ( 48300 * )
NEW met3 ( 48300 26860 ) ( * 28220 )
NEW met3 ( 48070 28220 ) ( 48300 * )
NEW met2 ( 48070 28220 ) ( * 31110 )
NEW met1 ( 48070 31110 ) ( 48990 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 48990 31110 ) L1M1_PR_MR
NEW li1 ( 47610 13090 ) L1M1_PR_MR
NEW met1 ( 48070 13090 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 48070 26860 ) M2M3_PR
NEW met2 ( 48070 28220 ) M2M3_PR
NEW met1 ( 48070 31110 ) M1M2_PR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- _046_ ( _070_ A2 ) ( _069_ Y ) + USE SIGNAL
+ ROUTED met2 ( 47150 18190 ) ( * 18700 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met3 ( 46460 18700 ) ( 47150 * )
NEW met4 ( 46460 18700 ) ( * 30260 )
NEW met3 ( 46460 30260 ) ( 47150 * )
NEW met2 ( 47150 30260 ) ( * 31110 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47150 18190 ) L1M1_PR_MR
NEW met1 ( 47150 18190 ) M1M2_PR
NEW met2 ( 47150 18700 ) M2M3_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met3 ( 46460 18700 ) M3M4_PR
NEW met3 ( 46460 30260 ) M3M4_PR
NEW met2 ( 47150 30260 ) M2M3_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47150 31110 ) L1M1_PR_MR
NEW met1 ( 47150 31110 ) M1M2_PR
NEW met1 ( 47150 18190 ) RECT ( -355 -70 0 70 )
NEW met1 ( 47150 31110 ) RECT ( -355 -70 0 70 ) ;
- _047_ ( _139_ TE_B ) ( _063_ Y ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 26910 24990 ) ( * 25330 )
NEW met1 ( 26910 24990 ) ( 31050 * )
NEW met2 ( 31050 22950 ) ( * 24990 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 31050 22950 ) ( 34730 * )
NEW met1 ( 34730 22950 ) ( * 23290 )
NEW met1 ( 34730 23290 ) ( 35650 * )
NEW met1 ( 35650 23290 ) ( * 23630 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 35650 23630 ) ( 39790 * )
NEW met1 ( 39790 23290 ) ( * 23630 )
NEW met1 ( 39790 23290 ) ( 46690 * )
NEW met1 ( 46690 23290 ) ( * 23630 )
NEW met1 ( 46690 23630 ) ( 50370 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 50370 23630 ) ( * 47090 )
NEW met1 ( 48530 47090 ) ( 50370 * )
NEW li1 ( 26910 25330 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 31050 24990 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 31050 22950 ) M1M2_PR
NEW met1 ( 50370 23630 ) M1M2_PR
NEW met1 ( 50370 47090 ) M1M2_PR
NEW li1 ( 48530 47090 ) L1M1_PR_MR ;
- _048_ ( _120_ Q_N ) + USE SIGNAL ;
- _049_ ( _119_ Q_N ) + USE SIGNAL ;
- _050_ ( _118_ Q_N ) + USE SIGNAL ;
- _051_ ( _117_ Q_N ) + USE SIGNAL ;
- _052_ ( _115_ Q_N ) + USE SIGNAL ;
- _053_ ( _114_ Q_N ) + USE SIGNAL ;
- _054_ ( _113_ Q_N ) + USE SIGNAL ;
- _055_ ( _112_ Q_N ) + USE SIGNAL ;
- _056_ ( _111_ Q_N ) + USE SIGNAL ;
- _057_ ( _110_ Q_N ) + USE SIGNAL ;
- _058_ ( _109_ Q_N ) + USE SIGNAL ;
- _059_ ( _121_ Q_N ) + USE SIGNAL ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- clknet_0_serial_clock ( clkbuf_1_1__f_serial_clock A ) ( clkbuf_1_0__f_serial_clock A ) ( clkbuf_0_serial_clock X ) + USE CLOCK
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 10810 34170 ) ( 11270 * )
NEW met2 ( 11270 34170 ) ( * 57630 )
NEW met1 ( 10810 57630 ) ( 11270 * )
NEW met1 ( 8510 29070 ) ( 11270 * )
NEW met2 ( 11270 29070 ) ( * 34170 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 10810 34170 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 11270 34170 ) M1M2_PR
NEW met1 ( 11270 57630 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 10810 57630 ) L1M1_PR_MR
NEW li1 ( 8510 29070 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 11270 29070 ) M1M2_PR ;
harden: gpio_control_block with updated rtl TODO: run full verification
2022-08-15 04:28:54 -05:00
- clknet_0_serial_load ( clkbuf_1_1__f_serial_load A ) ( clkbuf_1_0__f_serial_load A ) ( clkbuf_0_serial_load X ) + USE CLOCK
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 10350 35870 ) ( * 38590 )
NEW met1 ( 8510 38590 ) ( 10350 * )
NEW met1 ( 16790 30770 ) ( 17250 * )
NEW met2 ( 16790 20230 ) ( * 30770 )
NEW met2 ( 16790 30770 ) ( * 35870 )
NEW met1 ( 10350 35870 ) ( 16790 * )
NEW met1 ( 10350 35870 ) M1M2_PR
NEW met1 ( 10350 38590 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 8510 38590 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 17250 30770 ) L1M1_PR_MR
NEW met1 ( 16790 30770 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 16790 20230 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 16790 20230 ) M1M2_PR
NEW met1 ( 16790 35870 ) M1M2_PR
NEW met1 ( 16790 20230 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- clknet_1_0__leaf_serial_clock ( _123_ CLK ) ( _124_ CLK ) ( _125_ CLK ) ( _126_ CLK ) ( _127_ CLK ) ( _128_ CLK ) ( _129_ CLK )
( _130_ CLK ) ( _062__14 A ) ( clkbuf_1_0__f_serial_clock X ) + USE CLOCK
+ ROUTED met1 ( 19550 9350 ) ( 20010 * )
NEW met1 ( 7130 49470 ) ( * 50150 )
NEW met1 ( 19550 28390 ) ( 20010 * )
NEW met1 ( 17250 28390 ) ( 19550 * )
NEW met1 ( 19550 33830 ) ( 20010 * )
NEW met2 ( 19550 28390 ) ( * 33830 )
NEW met2 ( 15410 34170 ) ( * 36890 )
NEW met1 ( 15410 34170 ) ( 19550 * )
NEW met1 ( 19550 33830 ) ( * 34170 )
NEW met2 ( 15410 36890 ) ( * 39270 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 18170 41310 ) ( * 41990 )
NEW met1 ( 15410 41310 ) ( 18170 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 15410 39270 ) ( * 41310 )
NEW met1 ( 14030 44030 ) ( * 44710 )
NEW met1 ( 14030 44030 ) ( 15410 * )
NEW met2 ( 15410 41310 ) ( * 44030 )
NEW met2 ( 17250 44030 ) ( * 47430 )
NEW met1 ( 15410 44030 ) ( 17250 * )
NEW met2 ( 17250 47430 ) ( * 49470 )
NEW met1 ( 7130 36890 ) ( 15410 * )
NEW met1 ( 7130 49470 ) ( 17250 * )
NEW met2 ( 19550 9350 ) ( * 28390 )
NEW met1 ( 19550 9350 ) M1M2_PR
NEW li1 ( 20010 9350 ) L1M1_PR_MR
NEW li1 ( 7130 36890 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 7130 50150 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 20010 28390 ) L1M1_PR_MR
NEW met1 ( 19550 28390 ) M1M2_PR
NEW li1 ( 17250 28390 ) L1M1_PR_MR
NEW li1 ( 20010 33830 ) L1M1_PR_MR
NEW met1 ( 19550 33830 ) M1M2_PR
NEW met1 ( 15410 36890 ) M1M2_PR
NEW met1 ( 15410 34170 ) M1M2_PR
NEW li1 ( 15410 39270 ) L1M1_PR_MR
NEW met1 ( 15410 39270 ) M1M2_PR
NEW li1 ( 18170 41990 ) L1M1_PR_MR
NEW met1 ( 15410 41310 ) M1M2_PR
NEW li1 ( 14030 44710 ) L1M1_PR_MR
NEW met1 ( 15410 44030 ) M1M2_PR
NEW li1 ( 17250 47430 ) L1M1_PR_MR
NEW met1 ( 17250 47430 ) M1M2_PR
NEW met1 ( 17250 44030 ) M1M2_PR
NEW met1 ( 17250 49470 ) M1M2_PR
NEW met1 ( 15410 39270 ) RECT ( -355 -70 0 70 )
NEW met1 ( 17250 47430 ) RECT ( 0 -70 355 70 ) ;
- clknet_1_0__leaf_serial_load ( _098__3 A ) ( _101__6 A ) ( _103__8 A ) ( _106__11 A ) ( _107__12 A ) ( _108__13 A ) ( clkbuf_1_0__f_serial_load X ) + USE CLOCK
+ ROUTED met1 ( 7130 31110 ) ( * 31450 )
NEW met2 ( 7130 28730 ) ( * 31110 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 21850 31110 ) ( * 32130 )
NEW met1 ( 21850 32130 ) ( 31050 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 31050 32130 ) ( * 39610 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 16790 31450 ) ( * 32130 )
NEW met1 ( 16790 32130 ) ( 18630 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 18630 31790 ) ( * 32130 )
NEW met1 ( 18630 31790 ) ( 21850 * )
NEW met1 ( 25530 20570 ) ( 28290 * )
NEW met2 ( 28290 20570 ) ( * 32130 )
NEW met1 ( 28750 20230 ) ( * 20570 )
NEW met1 ( 28290 20570 ) ( 28750 * )
NEW met1 ( 26910 14790 ) ( 28290 * )
NEW met2 ( 28290 14790 ) ( * 20570 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 7130 31450 ) ( 16790 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 7130 31110 ) L1M1_PR_MR
NEW li1 ( 7130 28730 ) L1M1_PR_MR
NEW met1 ( 7130 28730 ) M1M2_PR
NEW met1 ( 7130 31110 ) M1M2_PR
NEW li1 ( 21850 31110 ) L1M1_PR_MR
NEW met1 ( 31050 32130 ) M1M2_PR
NEW li1 ( 31050 39610 ) L1M1_PR_MR
NEW met1 ( 31050 39610 ) M1M2_PR
NEW li1 ( 25530 20570 ) L1M1_PR_MR
NEW met1 ( 28290 20570 ) M1M2_PR
NEW met1 ( 28290 32130 ) M1M2_PR
NEW li1 ( 28750 20230 ) L1M1_PR_MR
NEW li1 ( 26910 14790 ) L1M1_PR_MR
NEW met1 ( 28290 14790 ) M1M2_PR
NEW met1 ( 7130 28730 ) RECT ( -355 -70 0 70 )
NEW met1 ( 7130 31110 ) RECT ( -595 -70 0 70 )
NEW met1 ( 31050 39610 ) RECT ( -355 -70 0 70 )
NEW met1 ( 28290 32130 ) RECT ( -595 -70 0 70 ) ;
- gpio_defaults[0] ( PIN gpio_defaults[0] ) ( ANTENNA__071__B DIODE ) ( ANTENNA__072__B DIODE ) ( _072_ B ) ( _071_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 35650 22950 ) ( 37950 * )
NEW met2 ( 35650 22950 ) ( * 31620 )
NEW met2 ( 35650 31620 ) ( 36110 * )
NEW met2 ( 47610 27540 ) ( * 27710 )
NEW met3 ( 41860 27540 ) ( 47610 * )
NEW met3 ( 41860 27540 ) ( * 28220 )
NEW met3 ( 35650 28220 ) ( 41860 * )
NEW met1 ( 47610 27710 ) ( 49450 * )
NEW met1 ( 4830 51170 ) ( 6210 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 4830 51170 ) ( * 61540 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 34730 55420 ) ( * 55590 )
NEW met3 ( 4830 55420 ) ( 34730 * )
NEW met3 ( 34730 55420 ) ( 36110 * )
NEW met2 ( 36110 31620 ) ( * 55420 )
NEW li1 ( 49450 27710 ) L1M1_PR_MR
NEW li1 ( 37950 22950 ) L1M1_PR_MR
NEW met1 ( 35650 22950 ) M1M2_PR
NEW met1 ( 47610 27710 ) M1M2_PR
NEW met2 ( 47610 27540 ) M2M3_PR
NEW met2 ( 35650 28220 ) M2M3_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 6210 51170 ) L1M1_PR_MR
NEW met1 ( 4830 51170 ) M1M2_PR
NEW li1 ( 34730 55590 ) L1M1_PR_MR
NEW met1 ( 34730 55590 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 34730 55420 ) M2M3_PR
NEW met2 ( 4830 55420 ) M2M3_PR
NEW met2 ( 36110 55420 ) M2M3_PR
NEW met2 ( 35650 28220 ) RECT ( -70 -485 70 0 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 34730 55590 ) RECT ( -355 -70 0 70 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 4830 55420 ) RECT ( -70 -485 70 0 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- gpio_defaults[10] ( PIN gpio_defaults[10] ) ( ANTENNA__085__B DIODE ) ( ANTENNA__086__B DIODE ) ( _086_ B ) ( _085_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 49450 3230 ) ( * 6630 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 49450 6630 ) ( 51750 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29670 48450 ) ( 31970 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 27830 53380 ) ( 28750 * )
NEW met2 ( 27830 53380 ) ( * 61540 0 )
NEW met1 ( 49450 33830 ) ( 51750 * )
NEW met2 ( 51750 6630 ) ( * 33830 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 39790 3230 ) ( * 4590 )
NEW met1 ( 31970 4590 ) ( 39790 * )
NEW met2 ( 47150 33830 ) ( * 44370 )
NEW met1 ( 45370 44370 ) ( 47150 * )
NEW met1 ( 45370 44030 ) ( * 44370 )
NEW met1 ( 42550 44030 ) ( 45370 * )
NEW met2 ( 42550 44030 ) ( * 47940 )
NEW met3 ( 32430 47940 ) ( 42550 * )
NEW met2 ( 32430 47940 ) ( * 48110 )
NEW met1 ( 31970 48110 ) ( 32430 * )
NEW met1 ( 28750 48110 ) ( 29670 * )
NEW met2 ( 28750 48110 ) ( * 53380 )
NEW met1 ( 29670 48110 ) ( * 48450 )
NEW met1 ( 31970 48110 ) ( * 48450 )
NEW met1 ( 39790 3230 ) ( 49450 * )
NEW met1 ( 47150 33830 ) ( 49450 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 49450 6630 ) L1M1_PR_MR
NEW met1 ( 49450 6630 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 49450 3230 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 51750 6630 ) M1M2_PR
NEW li1 ( 49450 33830 ) L1M1_PR_MR
NEW met1 ( 51750 33830 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 39790 3230 ) M1M2_PR
NEW met1 ( 39790 4590 ) M1M2_PR
NEW li1 ( 31970 4590 ) L1M1_PR_MR
NEW li1 ( 47150 33830 ) L1M1_PR_MR
NEW met1 ( 47150 33830 ) M1M2_PR
NEW met1 ( 47150 44370 ) M1M2_PR
NEW met1 ( 42550 44030 ) M1M2_PR
NEW met2 ( 42550 47940 ) M2M3_PR
NEW met2 ( 32430 47940 ) M2M3_PR
NEW met1 ( 32430 48110 ) M1M2_PR
NEW met1 ( 28750 48110 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 49450 6630 ) RECT ( -355 -70 0 70 )
NEW met1 ( 47150 33830 ) RECT ( -355 -70 0 70 ) ;
- gpio_defaults[11] ( PIN gpio_defaults[11] ) ( ANTENNA__087__B DIODE ) ( ANTENNA__088__B DIODE ) ( _088_ B ) ( _087_ B ) + USE SIGNAL
+ ROUTED met1 ( 29670 10370 ) ( 30590 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 30590 3230 ) ( * 10370 )
NEW met1 ( 30590 3230 ) ( 34500 * )
NEW met1 ( 34500 3230 ) ( * 3570 )
NEW met1 ( 34500 3570 ) ( 43930 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 30590 10370 ) ( * 13800 )
NEW met2 ( 47610 58650 ) ( * 60350 )
NEW met1 ( 30130 60350 ) ( 47610 * )
NEW met2 ( 30130 60350 ) ( * 61540 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 44390 17850 ) ( * 18190 )
NEW met1 ( 30130 18190 ) ( 44390 * )
NEW met2 ( 30130 18190 ) ( * 25500 )
NEW met3 ( 30130 25500 ) ( 31050 * )
NEW met2 ( 31050 25500 ) ( * 30770 )
NEW met2 ( 30590 30770 ) ( 31050 * )
NEW met2 ( 30590 30770 ) ( * 36380 )
NEW met2 ( 30130 36380 ) ( 30590 * )
NEW met2 ( 30130 36380 ) ( * 39270 )
NEW met1 ( 30130 39270 ) ( 31510 * )
NEW met2 ( 31510 39270 ) ( * 50660 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 30130 50660 ) ( 31510 * )
NEW met2 ( 30130 50660 ) ( * 60350 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 30130 13800 ) ( 30590 * )
NEW met2 ( 30130 13800 ) ( * 18190 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 29670 10370 ) L1M1_PR_MR
NEW met1 ( 30590 10370 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 30590 3230 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 43930 3570 ) L1M1_PR_MR
NEW li1 ( 47610 58650 ) L1M1_PR_MR
NEW met1 ( 47610 58650 ) M1M2_PR
NEW met1 ( 47610 60350 ) M1M2_PR
NEW met1 ( 30130 60350 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 44390 17850 ) L1M1_PR_MR
NEW met1 ( 30130 18190 ) M1M2_PR
NEW met2 ( 30130 25500 ) M2M3_PR
NEW met2 ( 31050 25500 ) M2M3_PR
NEW met1 ( 30130 39270 ) M1M2_PR
NEW met1 ( 31510 39270 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 47610 58650 ) RECT ( -355 -70 0 70 ) ;
- gpio_defaults[12] ( PIN gpio_defaults[12] ) ( ANTENNA__089__B DIODE ) ( ANTENNA__090__B DIODE ) ( _090_ B ) ( _089_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 28750 11730 ) ( 32890 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 27830 11730 ) ( 28750 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 32890 11730 ) ( 34500 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 34500 11730 ) ( * 12070 )
NEW met1 ( 34500 12070 ) ( 43930 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 32890 11730 ) ( * 13800 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 47610 48450 ) ( * 50150 )
NEW met1 ( 32890 48450 ) ( 47610 * )
NEW met2 ( 32890 33830 ) ( * 48450 )
NEW met2 ( 32430 33830 ) ( 32890 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 32430 13800 ) ( * 33830 )
NEW met2 ( 32430 13800 ) ( 32890 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 32430 48620 ) ( * 61540 0 )
NEW met2 ( 32430 48620 ) ( 32890 * )
NEW met2 ( 32890 48450 ) ( * 48620 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 32890 11730 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 28750 11730 ) L1M1_PR_MR
NEW li1 ( 27830 11730 ) L1M1_PR_MR
NEW li1 ( 43930 12070 ) L1M1_PR_MR
NEW li1 ( 47610 50150 ) L1M1_PR_MR
NEW met1 ( 47610 50150 ) M1M2_PR
NEW met1 ( 47610 48450 ) M1M2_PR
NEW met1 ( 32890 48450 ) M1M2_PR
NEW met1 ( 47610 50150 ) RECT ( -355 -70 0 70 ) ;
- gpio_defaults[1] ( PIN gpio_defaults[1] ) ( ANTENNA__083__B DIODE ) ( ANTENNA__084__B DIODE ) ( _084_ B ) ( _083_ B ) + USE SIGNAL
+ ROUTED met2 ( 19090 7650 ) ( * 9350 )
NEW met1 ( 18170 7650 ) ( 19090 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 7130 58990 ) ( * 61540 0 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 18170 58310 ) ( 18630 * )
NEW met2 ( 18630 43180 ) ( * 58310 )
NEW met2 ( 18630 43180 ) ( 19090 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 18630 58310 ) ( * 58990 )
NEW met1 ( 7130 58990 ) ( 18630 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 19090 9350 ) ( * 43180 )
NEW li1 ( 19090 9350 ) L1M1_PR_MR
NEW met1 ( 19090 9350 ) M1M2_PR
NEW li1 ( 19090 7650 ) L1M1_PR_MR
NEW met1 ( 19090 7650 ) M1M2_PR
NEW li1 ( 18170 7650 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 7130 58990 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 18170 58310 ) L1M1_PR_MR
NEW met1 ( 18630 58310 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 18630 58990 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 19090 9350 ) RECT ( -355 -70 0 70 )
NEW met1 ( 19090 7650 ) RECT ( -355 -70 0 70 ) ;
- gpio_defaults[2] ( PIN gpio_defaults[2] ) ( ANTENNA__073__B DIODE ) ( ANTENNA__074__B DIODE ) ( _074_ B ) ( _073_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 8050 58310 ) ( 10810 * )
NEW met2 ( 9430 61540 0 ) ( 10810 * )
NEW met2 ( 10810 58310 ) ( * 61540 )
NEW met1 ( 12650 4250 ) ( 14950 * )
NEW met1 ( 12650 4250 ) ( * 4590 )
NEW met1 ( 11730 4590 ) ( 12650 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 11730 4590 ) ( * 22610 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 10810 22610 ) ( 11730 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 14950 4250 ) ( 18170 * )
NEW met1 ( 13570 3910 ) ( * 4250 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 10810 22610 ) ( * 58310 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 8050 58310 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 10810 58310 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 14950 4250 ) L1M1_PR_MR
NEW met1 ( 11730 4590 ) M1M2_PR
NEW li1 ( 18170 4250 ) L1M1_PR_MR
NEW li1 ( 13570 3910 ) L1M1_PR_MR
NEW met1 ( 13570 4250 ) RECT ( 0 -70 255 70 ) ;
- gpio_defaults[3] ( PIN gpio_defaults[3] ) ( ANTENNA__079__B DIODE ) ( ANTENNA__080__B DIODE ) ( _080_ B ) ( _079_ B ) + USE SIGNAL
+ ROUTED met1 ( 14950 6630 ) ( 16790 * )
NEW met1 ( 14950 12410 ) ( 29210 * )
NEW met2 ( 8970 22950 ) ( * 44710 )
NEW met2 ( 8970 44710 ) ( * 59330 )
NEW met2 ( 11730 59330 ) ( * 61540 0 )
NEW met1 ( 31050 58650 ) ( * 59330 )
NEW met1 ( 8970 22950 ) ( 14950 * )
NEW met1 ( 8970 59330 ) ( 31050 * )
NEW met2 ( 14950 6630 ) ( * 22950 )
NEW li1 ( 16790 6630 ) L1M1_PR_MR
NEW met1 ( 14950 6630 ) M1M2_PR
NEW li1 ( 29210 12410 ) L1M1_PR_MR
NEW met1 ( 14950 12410 ) M1M2_PR
NEW li1 ( 8970 44710 ) L1M1_PR_MR
NEW met1 ( 8970 44710 ) M1M2_PR
NEW met1 ( 8970 22950 ) M1M2_PR
NEW met1 ( 8970 59330 ) M1M2_PR
NEW met1 ( 11730 59330 ) M1M2_PR
NEW li1 ( 31050 58650 ) L1M1_PR_MR
NEW met1 ( 14950 22950 ) M1M2_PR
NEW met2 ( 14950 12410 ) RECT ( -70 -485 70 0 )
NEW met1 ( 8970 44710 ) RECT ( -355 -70 0 70 )
NEW met1 ( 11730 59330 ) RECT ( -595 -70 0 70 ) ;
- gpio_defaults[4] ( PIN gpio_defaults[4] ) ( ANTENNA__081__B DIODE ) ( ANTENNA__082__B DIODE ) ( _082_ B ) ( _081_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 10350 4930 ) ( 16790 * )
NEW met1 ( 10350 3910 ) ( * 4930 )
NEW met2 ( 15410 26860 ) ( 16330 * )
NEW met2 ( 15410 4930 ) ( * 26860 )
NEW met1 ( 28290 45050 ) ( 30130 * )
NEW met2 ( 28290 45050 ) ( * 45220 )
NEW met3 ( 16330 45220 ) ( 28290 * )
NEW met2 ( 45770 44540 ) ( * 44710 )
NEW met3 ( 40940 44540 ) ( 45770 * )
NEW met3 ( 40940 44540 ) ( * 45220 )
NEW met3 ( 28290 45220 ) ( 40940 * )
NEW met1 ( 45770 44710 ) ( 49450 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 15870 56780 ) ( 16330 * )
NEW met2 ( 15870 56780 ) ( * 61540 )
NEW met2 ( 14030 61540 0 ) ( 15870 * )
NEW met2 ( 16330 26860 ) ( * 56780 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 49450 44710 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 16790 4930 ) L1M1_PR_MR
NEW li1 ( 10350 3910 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15410 4930 ) M1M2_PR
NEW li1 ( 30130 45050 ) L1M1_PR_MR
NEW met1 ( 28290 45050 ) M1M2_PR
NEW met2 ( 28290 45220 ) M2M3_PR
NEW met2 ( 16330 45220 ) M2M3_PR
NEW met1 ( 45770 44710 ) M1M2_PR
NEW met2 ( 45770 44540 ) M2M3_PR
NEW met1 ( 15410 4930 ) RECT ( -595 -70 0 70 )
NEW met2 ( 16330 45220 ) RECT ( -70 -485 70 0 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- gpio_defaults[5] ( PIN gpio_defaults[5] ) ( ANTENNA__091__B DIODE ) ( ANTENNA__092__B DIODE ) ( _092_ B ) ( _091_ B ) + USE SIGNAL
+ ROUTED met2 ( 12190 30770 ) ( * 33830 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 17250 18530 ) ( * 27710 )
NEW met1 ( 15870 27710 ) ( 17250 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 15870 27710 ) ( * 30770 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17250 20230 ) ( 25990 * )
NEW met1 ( 17250 15470 ) ( 27370 * )
NEW met2 ( 17250 15470 ) ( * 18530 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 18630 33830 ) ( * 37060 )
NEW met2 ( 18170 37060 ) ( 18630 * )
NEW met2 ( 18170 37060 ) ( * 61540 )
NEW met2 ( 16330 61540 0 ) ( 18170 * )
NEW met1 ( 12190 30770 ) ( 15870 * )
NEW met1 ( 9430 33830 ) ( 18630 * )
NEW li1 ( 9430 33830 ) L1M1_PR_MR
NEW met1 ( 12190 30770 ) M1M2_PR
NEW met1 ( 12190 33830 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 17250 18530 ) L1M1_PR_MR
NEW met1 ( 17250 18530 ) M1M2_PR
NEW met1 ( 17250 27710 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 15870 27710 ) M1M2_PR
NEW met1 ( 15870 30770 ) M1M2_PR
NEW li1 ( 25990 20230 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17250 20230 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 27370 15470 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17250 15470 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 18630 33830 ) M1M2_PR
NEW met1 ( 12190 33830 ) RECT ( -595 -70 0 70 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17250 18530 ) RECT ( -355 -70 0 70 )
NEW met2 ( 17250 20230 ) RECT ( -70 -485 70 0 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- gpio_defaults[6] ( PIN gpio_defaults[6] ) ( ANTENNA__093__B DIODE ) ( ANTENNA__094__B DIODE ) ( _094_ B ) ( _093_ B ) + USE SIGNAL
+ ROUTED met1 ( 18630 9690 ) ( 21390 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 29670 39610 ) ( * 39780 )
NEW met3 ( 20010 39780 ) ( 29670 * )
NEW met2 ( 20010 39780 ) ( * 61540 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 18630 61540 0 ) ( 20010 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29670 33830 ) ( 31050 * )
NEW met2 ( 29670 33830 ) ( * 39610 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 19550 22950 ) ( 20010 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 20010 22950 ) ( * 34340 )
NEW met2 ( 19550 34340 ) ( 20010 * )
NEW met2 ( 19550 34340 ) ( * 39780 )
NEW met2 ( 19550 39780 ) ( 20010 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 18630 22610 ) ( * 22950 )
NEW met1 ( 18630 22950 ) ( 19550 * )
NEW met2 ( 18630 9690 ) ( * 22610 )
NEW li1 ( 21390 9690 ) L1M1_PR_MR
NEW met1 ( 18630 9690 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 29670 39610 ) L1M1_PR_MR
NEW met1 ( 29670 39610 ) M1M2_PR
NEW met2 ( 29670 39780 ) M2M3_PR
NEW met2 ( 20010 39780 ) M2M3_PR
NEW li1 ( 31050 33830 ) L1M1_PR_MR
NEW met1 ( 29670 33830 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 19550 22950 ) L1M1_PR_MR
NEW met1 ( 20010 22950 ) M1M2_PR
NEW met1 ( 18630 22610 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29670 39610 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- gpio_defaults[7] ( PIN gpio_defaults[7] ) ( ANTENNA__095__B DIODE ) ( ANTENNA__096__B DIODE ) ( _096_ B ) ( _095_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 17250 22270 ) ( 22770 * )
NEW met2 ( 22770 22270 ) ( * 41310 )
NEW met1 ( 20930 41310 ) ( 22770 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 31050 28050 ) ( * 28390 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 26910 28050 ) ( 31050 * )
NEW met2 ( 26910 26690 ) ( * 28050 )
NEW met1 ( 22770 26690 ) ( 26910 * )
NEW met2 ( 36570 23290 ) ( * 25500 )
NEW met2 ( 36110 25500 ) ( 36570 * )
NEW met2 ( 36110 25500 ) ( * 28050 )
NEW met1 ( 31050 28050 ) ( 36110 * )
NEW met1 ( 36570 22270 ) ( 40250 * )
NEW met2 ( 36570 22270 ) ( * 23290 )
NEW met2 ( 20930 41310 ) ( * 61540 0 )
NEW li1 ( 17250 22270 ) L1M1_PR_MR
NEW met1 ( 22770 22270 ) M1M2_PR
NEW met1 ( 22770 41310 ) M1M2_PR
NEW met1 ( 20930 41310 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31050 28390 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 26910 28050 ) M1M2_PR
NEW met1 ( 26910 26690 ) M1M2_PR
NEW met1 ( 22770 26690 ) M1M2_PR
NEW li1 ( 36570 23290 ) L1M1_PR_MR
NEW met1 ( 36570 23290 ) M1M2_PR
NEW met1 ( 36110 28050 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 40250 22270 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 36570 22270 ) M1M2_PR
NEW met2 ( 22770 26690 ) RECT ( -70 -485 70 0 )
NEW met1 ( 36570 23290 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- gpio_defaults[8] ( PIN gpio_defaults[8] ) ( ANTENNA__075__B DIODE ) ( ANTENNA__076__B DIODE ) ( _076_ B ) ( _075_ B ) + USE SIGNAL
+ ROUTED met2 ( 22310 61540 ) ( 23230 * 0 )
NEW met1 ( 48070 52190 ) ( 49450 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 26910 42330 ) ( 28750 * )
NEW met2 ( 26910 42330 ) ( * 44370 )
NEW met1 ( 22310 44370 ) ( 26910 * )
NEW met1 ( 42550 45050 ) ( 43010 * )
NEW met2 ( 43010 45050 ) ( * 45900 )
NEW met3 ( 27370 45900 ) ( 43010 * )
NEW met2 ( 27370 45730 ) ( * 45900 )
NEW met2 ( 26910 45730 ) ( 27370 * )
NEW met2 ( 26910 44370 ) ( * 45730 )
NEW met3 ( 43010 45900 ) ( 48070 * )
NEW met1 ( 44390 37570 ) ( 46230 * )
NEW met2 ( 46230 37570 ) ( * 42670 )
NEW met1 ( 46230 42670 ) ( 48070 * )
NEW met2 ( 48070 42670 ) ( * 45900 )
NEW met2 ( 22310 44370 ) ( * 61540 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 48070 45900 ) ( * 52190 )
NEW li1 ( 49450 52190 ) L1M1_PR_MR
NEW met1 ( 48070 52190 ) M1M2_PR
NEW li1 ( 28750 42330 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 26910 42330 ) M1M2_PR
NEW met1 ( 26910 44370 ) M1M2_PR
NEW met1 ( 22310 44370 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 42550 45050 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 43010 45050 ) M1M2_PR
NEW met2 ( 43010 45900 ) M2M3_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 27370 45900 ) M2M3_PR
NEW met2 ( 48070 45900 ) M2M3_PR
NEW li1 ( 44390 37570 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 46230 37570 ) M1M2_PR
NEW met1 ( 46230 42670 ) M1M2_PR
NEW met1 ( 48070 42670 ) M1M2_PR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- gpio_defaults[9] ( PIN gpio_defaults[9] ) ( ANTENNA__077__B DIODE ) ( ANTENNA__078__B DIODE ) ( _078_ B ) ( _077_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 42090 6290 ) ( 42550 * )
NEW met1 ( 42550 5950 ) ( * 6290 )
NEW met1 ( 42550 5950 ) ( 46690 * )
NEW met2 ( 46690 5780 ) ( * 5950 )
NEW met2 ( 46230 5780 ) ( 46690 * )
NEW met1 ( 47610 41990 ) ( 48070 * )
NEW met2 ( 48070 33490 ) ( * 41990 )
NEW met1 ( 44850 33490 ) ( 48070 * )
NEW met2 ( 44850 25500 ) ( * 33490 )
NEW met3 ( 44850 25500 ) ( 45540 * )
NEW met3 ( 45540 22780 ) ( * 25500 )
NEW met3 ( 45540 22780 ) ( 46230 * )
NEW met1 ( 44850 47770 ) ( 48070 * )
NEW met1 ( 48070 46750 ) ( * 47770 )
NEW met1 ( 47610 46750 ) ( 48070 * )
NEW met2 ( 47610 41820 ) ( * 46750 )
NEW met2 ( 47610 41820 ) ( 48070 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 14030 46580 ) ( * 46750 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met3 ( 14030 46580 ) ( 15180 * )
NEW met3 ( 15180 46580 ) ( * 47260 )
NEW met3 ( 15180 47260 ) ( 43010 * )
NEW met2 ( 43010 46750 ) ( * 47260 )
NEW met1 ( 43010 46750 ) ( 47610 * )
NEW met2 ( 24150 61540 ) ( 25530 * 0 )
NEW met2 ( 24150 60690 ) ( * 61540 )
NEW met1 ( 21850 60690 ) ( 24150 * )
NEW met2 ( 21850 47940 ) ( * 60690 )
NEW met3 ( 21620 47940 ) ( 21850 * )
NEW met3 ( 21620 47260 ) ( * 47940 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 6670 46750 ) ( 14030 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 46230 5780 ) ( * 22780 )
NEW li1 ( 42090 6290 ) L1M1_PR_MR
NEW met1 ( 46690 5950 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 6670 46750 ) L1M1_PR_MR
NEW li1 ( 47610 41990 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 48070 41990 ) M1M2_PR
NEW met1 ( 48070 33490 ) M1M2_PR
NEW met1 ( 44850 33490 ) M1M2_PR
NEW met2 ( 44850 25500 ) M2M3_PR
NEW met2 ( 46230 22780 ) M2M3_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 44850 47770 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 47610 46750 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 14030 46750 ) M1M2_PR
NEW met2 ( 14030 46580 ) M2M3_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 43010 47260 ) M2M3_PR
NEW met1 ( 43010 46750 ) M1M2_PR
NEW met1 ( 24150 60690 ) M1M2_PR
NEW met1 ( 21850 60690 ) M1M2_PR
NEW met2 ( 21850 47940 ) M2M3_PR ;
- update gpio_control_block config (#57) - update gpio_control_block views - gitignore gds/*gds
2022-04-08 11:27:51 -05:00
- gpio_logic1 ( gpio_logic_high gpio_logic1 ) ( gpio_in_buf TE ) + USE SIGNAL
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
+ ROUTED met2 ( 13570 17000 ) ( * 19550 )
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met3 ( 12420 17000 0 ) ( 13570 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 40250 19550 ) ( * 22950 )
NEW met1 ( 40250 22950 ) ( 41630 * )
NEW met1 ( 13570 19550 ) ( 40250 * )
NEW met1 ( 13570 19550 ) M1M2_PR
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met2 ( 13570 17000 ) M2M3_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 40250 19550 ) M1M2_PR
NEW met1 ( 40250 22950 ) M1M2_PR
NEW li1 ( 41630 22950 ) L1M1_PR_MR ;
- gpio_outenb ( _115_ Q ) ( _064_ A ) ( _063_ B ) + USE SIGNAL
+ ROUTED met2 ( 49450 47430 ) ( * 49470 )
NEW met1 ( 49450 49470 ) ( * 49810 )
NEW met1 ( 45770 49810 ) ( 49450 * )
NEW met1 ( 45770 49470 ) ( * 49810 )
NEW met1 ( 29730 49470 ) ( 45770 * )
NEW met1 ( 49450 26350 ) ( 49910 * )
NEW met2 ( 49910 26350 ) ( * 42330 )
NEW met2 ( 49450 42330 ) ( 49910 * )
NEW met2 ( 49450 42330 ) ( * 47430 )
NEW li1 ( 49450 47430 ) L1M1_PR_MR
NEW met1 ( 49450 47430 ) M1M2_PR
NEW met1 ( 49450 49470 ) M1M2_PR
NEW li1 ( 29730 49470 ) L1M1_PR_MR
NEW li1 ( 49450 26350 ) L1M1_PR_MR
NEW met1 ( 49910 26350 ) M1M2_PR
NEW met1 ( 49450 47430 ) RECT ( -355 -70 0 70 ) ;
- mgmt_ena ( _109_ Q ) ( _069_ B1 ) ( _066_ A_N ) ( _065_ S ) + USE SIGNAL
+ ROUTED met1 ( 47150 36210 ) ( * 36550 )
NEW met1 ( 47150 36210 ) ( 48990 * )
NEW met2 ( 48990 18190 ) ( * 36210 )
NEW met1 ( 47610 18190 ) ( 48990 * )
NEW met1 ( 47610 17850 ) ( * 18190 )
NEW met1 ( 46690 17850 ) ( 47610 * )
NEW met1 ( 48530 45050 ) ( 48990 * )
NEW met2 ( 48990 36210 ) ( * 45050 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 49910 49980 ) ( * 53550 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 48990 49980 ) ( 49910 * )
NEW met2 ( 48990 45050 ) ( * 49980 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45310 52870 ) ( * 53550 )
NEW met1 ( 44390 52870 ) ( 45310 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 44390 52870 ) ( * 53550 )
NEW met1 ( 40770 53550 ) ( 44390 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45310 53550 ) ( 49910 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47150 36550 ) L1M1_PR_MR
NEW met1 ( 48990 36210 ) M1M2_PR
NEW met1 ( 48990 18190 ) M1M2_PR
NEW li1 ( 46690 17850 ) L1M1_PR_MR
NEW li1 ( 48530 45050 ) L1M1_PR_MR
NEW met1 ( 48990 45050 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 49910 53550 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 44390 52870 ) M1M2_PR
NEW met1 ( 44390 53550 ) M1M2_PR
NEW li1 ( 40770 53550 ) L1M1_PR_MR ;
- mgmt_gpio_in ( PIN mgmt_gpio_in ) ( _139_ Z ) + USE SIGNAL
+ ROUTED met3 ( 56350 4420 ) ( 70380 * 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29670 23970 ) ( 56350 * )
NEW met2 ( 29670 23970 ) ( * 25670 )
NEW met1 ( 29670 25670 ) ( * 26010 )
NEW met1 ( 25530 26010 ) ( 29670 * )
NEW met2 ( 56350 4420 ) ( * 23970 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 56350 4420 ) M2M3_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 56350 23970 ) M1M2_PR
NEW met1 ( 29670 23970 ) M1M2_PR
NEW met1 ( 29670 25670 ) M1M2_PR
NEW li1 ( 25530 26010 ) L1M1_PR_MR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- mgmt_gpio_oeb ( PIN mgmt_gpio_oeb ) ( ANTENNA_input1_A DIODE ) ( input1 A ) + USE SIGNAL
+ ROUTED met2 ( 43930 6970 ) ( * 8500 )
NEW met3 ( 43930 8500 ) ( 70380 * 0 )
NEW met2 ( 43930 4930 ) ( * 6970 )
NEW met1 ( 32890 4930 ) ( 43930 * )
NEW li1 ( 32890 4930 ) L1M1_PR_MR
NEW li1 ( 43930 6970 ) L1M1_PR_MR
NEW met1 ( 43930 6970 ) M1M2_PR
NEW met2 ( 43930 8500 ) M2M3_PR
NEW met1 ( 43930 4930 ) M1M2_PR
NEW met1 ( 43930 6970 ) RECT ( -355 -70 0 70 ) ;
- mgmt_gpio_out ( PIN mgmt_gpio_out ) ( ANTENNA_input2_A DIODE ) ( input2 A ) + USE SIGNAL
+ ROUTED met2 ( 20010 2210 ) ( * 3230 )
NEW met2 ( 83490 3910 ) ( * 10540 )
NEW met3 ( 83260 10540 0 ) ( 83490 * )
NEW met1 ( 51750 2210 ) ( * 3910 )
NEW met1 ( 20010 2210 ) ( 51750 * )
NEW met1 ( 49910 3910 ) ( 83490 * )
NEW met1 ( 20010 2210 ) M1M2_PR
NEW li1 ( 20010 3230 ) L1M1_PR_MR
NEW met1 ( 20010 3230 ) M1M2_PR
NEW met1 ( 83490 3910 ) M1M2_PR
NEW met2 ( 83490 10540 ) M2M3_PR
NEW li1 ( 49910 3910 ) L1M1_PR_MR
NEW met1 ( 20010 3230 ) RECT ( -355 -70 0 70 ) ;
- net1 ( input1 X ) ( _067_ C ) ( _064_ B ) + USE SIGNAL
+ ROUTED met1 ( 48530 25670 ) ( 50830 * )
NEW met2 ( 50830 25670 ) ( * 28730 )
NEW met2 ( 50830 7650 ) ( * 25670 )
NEW met1 ( 48070 28730 ) ( * 29070 )
NEW met1 ( 47105 29070 ) ( 48070 * )
NEW met1 ( 44850 7650 ) ( 50830 * )
NEW met1 ( 48070 28730 ) ( 50830 * )
NEW met1 ( 50830 7650 ) M1M2_PR
NEW li1 ( 48530 25670 ) L1M1_PR_MR
NEW met1 ( 50830 25670 ) M1M2_PR
NEW met1 ( 50830 28730 ) M1M2_PR
NEW li1 ( 44850 7650 ) L1M1_PR_MR
NEW li1 ( 47105 29070 ) L1M1_PR_MR ;
- net10 ( output10 A ) ( _117_ Q ) ( _067_ B ) + USE SIGNAL
+ ROUTED met1 ( 46690 49470 ) ( 46730 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 44850 27710 ) ( 47150 * )
NEW met1 ( 44850 27710 ) ( * 28050 )
NEW met1 ( 43010 28050 ) ( 44850 * )
NEW met2 ( 43010 28050 ) ( * 28220 )
NEW met3 ( 43010 28220 ) ( 46690 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 39790 14790 ) ( * 15130 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 39790 15130 ) ( 43010 * )
NEW met2 ( 43010 15130 ) ( * 28050 )
NEW met2 ( 46690 28220 ) ( * 49470 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 46690 49470 ) M1M2_PR
NEW li1 ( 46730 49470 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 47150 27710 ) L1M1_PR_MR
NEW met1 ( 43010 28050 ) M1M2_PR
NEW met2 ( 43010 28220 ) M2M3_PR
NEW met2 ( 46690 28220 ) M2M3_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 39790 14790 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 43010 15130 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 46690 49470 ) RECT ( -315 -70 0 70 ) ;
- net11 ( output11 A ) ( _118_ Q ) ( _067_ A_N ) + USE SIGNAL
+ ROUTED met1 ( 48530 29070 ) ( 48990 * )
NEW met2 ( 48530 29070 ) ( * 55250 )
NEW met1 ( 48530 55250 ) ( 49490 * )
NEW met1 ( 48990 29070 ) ( 49450 * )
NEW met2 ( 49450 9350 ) ( * 29070 )
NEW li1 ( 49450 9350 ) L1M1_PR_MR
NEW met1 ( 49450 9350 ) M1M2_PR
NEW li1 ( 48990 29070 ) L1M1_PR_MR
NEW met1 ( 48530 29070 ) M1M2_PR
NEW met1 ( 48530 55250 ) M1M2_PR
NEW li1 ( 49490 55250 ) L1M1_PR_MR
NEW met1 ( 49450 29070 ) M1M2_PR
NEW met1 ( 49450 9350 ) RECT ( -355 -70 0 70 ) ;
- net12 ( output12 A ) ( _110_ Q ) + USE SIGNAL
+ ROUTED met1 ( 29250 55250 ) ( 33350 * )
NEW met2 ( 33350 17850 ) ( * 55250 )
NEW met1 ( 32890 17850 ) ( 33350 * )
NEW li1 ( 29250 55250 ) L1M1_PR_MR
NEW met1 ( 33350 55250 ) M1M2_PR
NEW met1 ( 33350 17850 ) M1M2_PR
NEW li1 ( 32890 17850 ) L1M1_PR_MR ;
- net13 ( output13 A ) ( _114_ Q ) + USE SIGNAL
+ ROUTED met1 ( 30130 35870 ) ( 30170 * )
NEW met2 ( 30130 30260 ) ( * 35870 )
NEW met2 ( 30130 30260 ) ( 30590 * )
NEW met2 ( 30590 20230 ) ( * 30260 )
NEW li1 ( 30170 35870 ) L1M1_PR_MR
NEW met1 ( 30130 35870 ) M1M2_PR
NEW li1 ( 30590 20230 ) L1M1_PR_MR
NEW met1 ( 30590 20230 ) M1M2_PR
NEW met1 ( 30170 35870 ) RECT ( 0 -70 315 70 )
NEW met1 ( 30590 20230 ) RECT ( -355 -70 0 70 ) ;
- net14 ( output14 A ) ( _113_ Q ) ( _063_ A_N ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 47610 47090 ) ( * 47430 )
NEW met1 ( 40710 47090 ) ( 47610 * )
NEW met2 ( 40710 14790 ) ( * 47090 )
NEW met1 ( 30190 47090 ) ( 33810 * )
NEW met1 ( 33810 46750 ) ( * 47090 )
NEW met1 ( 33810 46750 ) ( 40710 * )
NEW met1 ( 40710 46750 ) ( * 47090 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47610 47430 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 40710 47090 ) M1M2_PR
NEW li1 ( 40710 14790 ) L1M1_PR_MR
NEW met1 ( 40710 14790 ) M1M2_PR
NEW li1 ( 30190 47090 ) L1M1_PR_MR
NEW met1 ( 40710 14790 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net15 ( output15 A ) ( _070_ Y ) + USE SIGNAL
+ ROUTED met2 ( 43010 28730 ) ( * 30770 )
NEW met1 ( 43010 30770 ) ( 44390 * )
NEW li1 ( 43010 28730 ) L1M1_PR_MR
NEW met1 ( 43010 28730 ) M1M2_PR
NEW met1 ( 43010 30770 ) M1M2_PR
NEW li1 ( 44390 30770 ) L1M1_PR_MR
NEW met1 ( 43010 28730 ) RECT ( -355 -70 0 70 ) ;
- net16 ( output16 A ) ( _065_ X ) + USE SIGNAL
+ ROUTED met2 ( 41170 20230 ) ( * 36550 )
NEW met1 ( 41170 36550 ) ( 44850 * )
NEW li1 ( 41170 20230 ) L1M1_PR_MR
NEW met1 ( 41170 20230 ) M1M2_PR
NEW met1 ( 41170 36550 ) M1M2_PR
NEW li1 ( 44850 36550 ) L1M1_PR_MR
NEW met1 ( 41170 20230 ) RECT ( -355 -70 0 70 ) ;
- net17 ( output17 A ) ( _111_ Q ) + USE SIGNAL
+ ROUTED met1 ( 44850 34170 ) ( 45370 * )
NEW met2 ( 44850 34170 ) ( * 58310 )
NEW met1 ( 43010 58310 ) ( 44850 * )
NEW li1 ( 45370 34170 ) L1M1_PR_MR
NEW met1 ( 44850 34170 ) M1M2_PR
NEW met1 ( 44850 58310 ) M1M2_PR
NEW li1 ( 43010 58310 ) L1M1_PR_MR ;
- net18 ( output18 A ) ( _112_ Q ) + USE SIGNAL
+ ROUTED met1 ( 41630 40290 ) ( 49490 * )
NEW met2 ( 41630 40290 ) ( * 41310 )
NEW met1 ( 34270 41310 ) ( 41630 * )
NEW met1 ( 34270 41310 ) ( * 41650 )
NEW met1 ( 30130 41650 ) ( 34270 * )
NEW met1 ( 30130 41650 ) ( * 43010 )
NEW met1 ( 15410 43010 ) ( 30130 * )
NEW met1 ( 15410 41990 ) ( * 43010 )
NEW li1 ( 49490 40290 ) L1M1_PR_MR
NEW met1 ( 41630 40290 ) M1M2_PR
NEW met1 ( 41630 41310 ) M1M2_PR
NEW li1 ( 15410 41990 ) L1M1_PR_MR ;
- net19 ( output19 A ) ( _136_ X ) + USE SIGNAL
+ ROUTED met1 ( 17710 26690 ) ( 21390 * )
NEW met2 ( 21390 26690 ) ( * 58310 )
NEW li1 ( 17710 26690 ) L1M1_PR_MR
NEW met1 ( 21390 26690 ) M1M2_PR
NEW li1 ( 21390 58310 ) L1M1_PR_MR
NEW met1 ( 21390 58310 ) M1M2_PR
NEW met1 ( 21390 58310 ) RECT ( -355 -70 0 70 ) ;
- net2 ( input2 X ) ( _069_ A1 ) + USE SIGNAL
+ ROUTED met2 ( 48990 4930 ) ( * 17510 )
NEW li1 ( 48990 4930 ) L1M1_PR_MR
NEW met1 ( 48990 4930 ) M1M2_PR
NEW li1 ( 48990 17510 ) L1M1_PR_MR
NEW met1 ( 48990 17510 ) M1M2_PR
NEW met1 ( 48990 4930 ) RECT ( -355 -70 0 70 )
NEW met1 ( 48990 17510 ) RECT ( -355 -70 0 70 ) ;
- net20 ( output20 A ) ( _135_ Q ) + USE SIGNAL
+ ROUTED met2 ( 8050 52870 ) ( * 54910 )
NEW met1 ( 8050 52870 ) ( 15410 * )
NEW met1 ( 8050 52870 ) M1M2_PR
NEW li1 ( 8050 54910 ) L1M1_PR_MR
NEW met1 ( 8050 54910 ) M1M2_PR
NEW li1 ( 15410 52870 ) L1M1_PR_MR
NEW met1 ( 8050 54910 ) RECT ( -355 -70 0 70 ) ;
- net21 ( fanout21 X ) ( _127_ RESET_B ) ( _126_ RESET_B ) ( _082_ A_N ) ( _081_ A ) ( _094_ A_N ) ( _092_ A_N )
( _091_ A ) + USE SIGNAL
+ ROUTED met2 ( 11730 3570 ) ( * 3740 )
NEW met2 ( 10810 3740 ) ( 11730 * )
NEW met2 ( 10810 3570 ) ( * 3740 )
NEW met1 ( 8050 3570 ) ( 10810 * )
NEW met1 ( 8050 3570 ) ( * 3910 )
NEW met1 ( 11730 3570 ) ( 17250 * )
NEW met2 ( 11730 31790 ) ( * 36210 )
NEW met1 ( 8050 33490 ) ( * 34170 )
NEW met1 ( 8050 33490 ) ( 11730 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29210 44710 ) ( 29670 * )
NEW met2 ( 29670 44710 ) ( * 45220 )
NEW met2 ( 29670 45220 ) ( 30130 * )
NEW met2 ( 30130 45220 ) ( * 48110 )
NEW met1 ( 30130 48110 ) ( 31510 * )
NEW met1 ( 25070 41990 0 ) ( * 42670 )
NEW met1 ( 25070 42670 ) ( 29670 * )
NEW met2 ( 29670 42670 ) ( * 44710 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 26910 20230 ) ( 27370 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 27370 20230 ) ( * 42670 )
NEW met1 ( 17710 23290 ) ( 18170 * )
NEW met2 ( 17710 19890 ) ( * 23290 )
NEW met1 ( 17710 19890 ) ( 26910 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 26910 19890 ) ( * 20230 )
NEW met2 ( 14030 28050 ) ( * 31790 )
NEW met1 ( 14030 28050 ) ( 17710 * )
NEW met2 ( 17710 23290 ) ( * 28050 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 16330 14620 ) ( 17250 * )
NEW met2 ( 16330 14620 ) ( * 19890 )
NEW met1 ( 16330 19890 ) ( 17710 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 11730 31790 ) ( 14030 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 17250 3570 ) ( * 14620 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 17250 3570 ) M1M2_PR
NEW met1 ( 11730 3570 ) M1M2_PR
NEW met1 ( 10810 3570 ) M1M2_PR
NEW li1 ( 8050 3910 ) L1M1_PR_MR
NEW met1 ( 11730 36210 ) M1M2_PR
NEW met1 ( 11730 31790 ) M1M2_PR
NEW li1 ( 8050 34170 ) L1M1_PR_MR
NEW met1 ( 11730 33490 ) M1M2_PR
NEW li1 ( 29210 44710 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29670 44710 ) M1M2_PR
NEW met1 ( 30130 48110 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31510 48110 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29670 42670 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 26910 20230 ) L1M1_PR_MR
NEW met1 ( 27370 20230 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 27370 42670 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 18170 23290 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17710 23290 ) M1M2_PR
NEW met1 ( 17710 19890 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 14030 31790 ) M1M2_PR
NEW met1 ( 14030 28050 ) M1M2_PR
NEW met1 ( 17710 28050 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 16330 19890 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 11730 33490 ) RECT ( -70 -485 70 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 27370 42670 ) RECT ( -595 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net22 ( fanout22 X ) ( _130_ RESET_B ) ( _096_ A_N ) ( _095_ A ) ( _093_ A ) ( _128_ RESET_B ) ( _129_ RESET_B )
( fanout21 A ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 27370 34510 0 ) ( 28750 * )
NEW met2 ( 28750 34510 ) ( * 40290 )
NEW met1 ( 24150 40290 ) ( 28750 * )
NEW met1 ( 24150 39950 ) ( * 40290 )
NEW met1 ( 22770 39950 0 ) ( 24150 * )
NEW met1 ( 28750 37230 ) ( 31510 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 31970 33490 ) ( * 33830 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29210 33490 ) ( 31970 * )
NEW met1 ( 29210 33490 ) ( * 34170 )
NEW met1 ( 28750 34170 ) ( 29210 * )
NEW met1 ( 28750 34170 ) ( * 34510 )
NEW met1 ( 27370 29070 0 ) ( 27830 * )
NEW met2 ( 27830 29070 ) ( * 34510 )
NEW met1 ( 31970 28730 ) ( * 29070 )
NEW met1 ( 27830 29070 ) ( 31970 * )
NEW met1 ( 28750 47430 ) ( 32430 * )
NEW met2 ( 28750 40290 ) ( * 47430 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 34270 23290 ) ( * 28730 )
NEW met1 ( 31970 28730 ) ( 34270 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 28750 34510 ) M1M2_PR
NEW met1 ( 28750 40290 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31510 37230 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 28750 37230 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31970 33830 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 27830 29070 ) M1M2_PR
NEW met1 ( 27830 34510 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31970 28730 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 32430 47430 ) L1M1_PR_MR
NEW met1 ( 28750 47430 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 34270 23290 ) L1M1_PR_MR
NEW met1 ( 34270 23290 ) M1M2_PR
NEW met1 ( 34270 28730 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 28750 37230 ) RECT ( -70 -485 70 0 )
NEW met1 ( 27830 34510 ) RECT ( -595 -70 0 70 )
NEW met1 ( 34270 23290 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net23 ( ANTENNA__079__A DIODE ) ( ANTENNA__080__A_N DIODE ) ( ANTENNA__125__RESET_B DIODE ) ( ANTENNA__073__A DIODE ) ( ANTENNA__074__A_N DIODE ) ( ANTENNA__083__A DIODE ) ( ANTENNA__084__A_N DIODE )
( fanout23 X ) ( _084_ A_N ) ( _083_ A ) ( _074_ A_N ) ( _073_ A ) ( _125_ RESET_B ) ( _080_ A_N ) ( _079_ A ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 5750 45730 ) ( 6210 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 6210 45050 ) ( 7590 * )
NEW met1 ( 6210 45050 ) ( * 45730 )
NEW met1 ( 5750 4930 ) ( 6670 * )
NEW met2 ( 5750 4930 ) ( * 45730 )
NEW met1 ( 11270 3230 ) ( * 3910 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 5750 3230 ) ( 11270 * )
NEW met2 ( 5750 3230 ) ( * 4930 )
NEW met1 ( 11270 3230 ) ( 14030 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 14030 3230 ) ( 15870 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15870 9350 ) ( 17250 * )
NEW met2 ( 15870 3230 ) ( * 9350 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 17250 9010 ) ( 22310 * )
NEW met1 ( 17250 9010 ) ( * 9350 )
NEW met1 ( 22310 9010 ) ( 23230 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 23230 11390 ) ( 30130 * )
NEW met2 ( 23230 9010 ) ( * 11390 )
NEW met1 ( 30590 45050 ) ( 31970 * )
NEW met1 ( 30590 45050 ) ( * 45390 )
NEW met1 ( 21390 45390 0 ) ( 30590 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 5750 58310 ) ( 7130 * )
NEW met1 ( 7130 58650 ) ( 19090 * )
NEW met1 ( 7130 58310 ) ( * 58650 )
NEW met2 ( 31970 58310 ) ( * 58990 )
NEW met2 ( 30590 58990 ) ( 31970 * )
NEW met1 ( 19090 58990 ) ( 30590 * )
NEW met1 ( 19090 58650 ) ( * 58990 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 45770 52700 ) ( * 53890 )
NEW met3 ( 31970 52700 ) ( 45770 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 5750 45730 ) ( * 58310 )
NEW met2 ( 31970 45050 ) ( * 58310 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45770 53890 ) ( 48530 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 48530 53890 ) L1M1_PR_MR
NEW li1 ( 6210 45730 ) L1M1_PR_MR
NEW met1 ( 5750 45730 ) M1M2_PR
NEW li1 ( 7590 45050 ) L1M1_PR_MR
NEW li1 ( 6670 4930 ) L1M1_PR_MR
NEW met1 ( 5750 4930 ) M1M2_PR
NEW li1 ( 11270 3910 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 5750 3230 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 14030 3230 ) L1M1_PR_MR
NEW li1 ( 15870 3230 ) L1M1_PR_MR
NEW li1 ( 17250 9350 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15870 9350 ) M1M2_PR
NEW met1 ( 15870 3230 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 22310 9010 ) L1M1_PR_MR
NEW li1 ( 23230 9010 ) L1M1_PR_MR
NEW li1 ( 30130 11390 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 23230 11390 ) M1M2_PR
NEW met1 ( 23230 9010 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 31970 45050 ) M1M2_PR
NEW li1 ( 7130 58310 ) L1M1_PR_MR
NEW met1 ( 5750 58310 ) M1M2_PR
NEW li1 ( 19090 58650 ) L1M1_PR_MR
NEW li1 ( 31970 58310 ) L1M1_PR_MR
NEW met1 ( 31970 58310 ) M1M2_PR
NEW met1 ( 30590 58990 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45770 53890 ) M1M2_PR
NEW met2 ( 45770 52700 ) M2M3_PR
NEW met2 ( 31970 52700 ) M2M3_PR
NEW met1 ( 15870 3230 ) RECT ( -595 -70 0 70 )
NEW met1 ( 23230 9010 ) RECT ( -595 -70 0 70 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 31970 58310 ) RECT ( 0 -70 355 70 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 31970 52700 ) RECT ( -70 -485 70 0 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net24 ( fanout24 X ) ( _122_ RESET_B ) ( _072_ A_N ) ( _123_ RESET_B ) ( _124_ RESET_B ) ( fanout23 A ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 37030 38590 ) ( 41170 * )
NEW met2 ( 37030 23290 ) ( * 38590 )
NEW met1 ( 37030 23290 ) ( 39330 * )
NEW met1 ( 13570 47090 0 ) ( 15410 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 42090 52190 ) ( 47610 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 47610 52190 ) ( * 52870 )
NEW met1 ( 41170 52190 ) ( 42090 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 25530 52530 0 ) ( 27830 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 27830 52020 ) ( * 52530 )
NEW met3 ( 27830 52020 ) ( 41170 * )
NEW met1 ( 15410 48450 ) ( 27830 * )
NEW met2 ( 27830 48450 ) ( * 52020 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 14490 50830 0 ) ( 15410 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 15410 48450 ) ( * 50830 )
NEW met2 ( 15410 47090 ) ( * 48450 )
NEW met2 ( 41170 38590 ) ( * 52190 )
NEW met1 ( 41170 38590 ) M1M2_PR
NEW met1 ( 37030 38590 ) M1M2_PR
NEW met1 ( 37030 23290 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 39330 23290 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15410 47090 ) M1M2_PR
NEW li1 ( 42090 52190 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47610 52870 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 41170 52190 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 27830 52530 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 27830 52020 ) M2M3_PR
NEW met2 ( 41170 52020 ) M2M3_PR
NEW met1 ( 15410 48450 ) M1M2_PR
NEW met1 ( 27830 48450 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 15410 50830 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 41170 52020 ) RECT ( -70 -485 70 0 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net25 ( fanout25 X ) ( _089_ A ) ( _087_ A ) ( _077_ A ) ( _134_ RESET_B ) ( _133_ RESET_B ) ( _088_ A_N )
( _071_ A ) + USE SIGNAL
+ ROUTED met1 ( 49450 13090 ) ( 52210 * )
NEW met1 ( 48530 41990 ) ( 52210 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 52210 16830 ) ( * 41990 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 48530 50150 ) ( 52210 * )
NEW met2 ( 52210 41990 ) ( * 50150 )
NEW met1 ( 35650 55590 ) ( 38870 * )
NEW met1 ( 38870 55590 ) ( * 55930 )
NEW met1 ( 38870 55930 ) ( 39790 * )
NEW met1 ( 48530 58310 ) ( 52210 * )
NEW met2 ( 52210 50150 ) ( * 58310 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 52210 13090 ) ( * 16830 )
NEW met2 ( 39790 48300 ) ( * 55930 )
NEW met2 ( 47150 16830 ) ( * 17510 )
NEW met1 ( 45770 17510 ) ( 47150 * )
NEW met1 ( 45770 17510 ) ( * 17850 )
NEW met1 ( 39790 47430 0 ) ( * 48110 )
NEW met2 ( 39790 48110 ) ( * 48300 )
NEW met1 ( 37490 45390 0 ) ( 38410 * )
NEW met2 ( 38410 45390 ) ( * 48300 )
NEW met2 ( 38410 48300 ) ( 39790 * )
NEW met1 ( 47150 16830 ) ( 52210 * )
NEW met1 ( 39790 48110 ) ( 52210 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 49450 13090 ) L1M1_PR_MR
NEW met1 ( 52210 13090 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 52210 16830 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 48530 41990 ) L1M1_PR_MR
NEW met1 ( 52210 41990 ) M1M2_PR
NEW li1 ( 48530 50150 ) L1M1_PR_MR
NEW met1 ( 52210 50150 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 52210 48110 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 35650 55590 ) L1M1_PR_MR
NEW met1 ( 39790 55930 ) M1M2_PR
NEW li1 ( 48530 58310 ) L1M1_PR_MR
NEW met1 ( 52210 58310 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 47150 16830 ) M1M2_PR
NEW met1 ( 47150 17510 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 45770 17850 ) L1M1_PR_MR
NEW met1 ( 39790 48110 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 38410 45390 ) M1M2_PR
NEW met2 ( 52210 48110 ) RECT ( -70 -485 70 0 )
NEW met1 ( 39790 48110 ) RECT ( 0 -70 595 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net26 ( fanout26 X ) ( _136_ A ) ( _135_ RESET_B ) ( _090_ A_N ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 14950 25670 ) ( 16790 * )
NEW met2 ( 14950 25670 ) ( * 31620 )
NEW met2 ( 14950 31620 ) ( 15870 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 15870 31620 ) ( * 56270 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 33810 16830 ) ( 42090 * )
NEW met1 ( 33810 16830 ) ( * 17170 )
NEW met1 ( 28750 17170 ) ( 33810 * )
NEW met1 ( 28750 16830 ) ( * 17170 )
NEW met1 ( 15870 16830 ) ( 28750 * )
NEW met2 ( 15870 16830 ) ( * 25670 )
NEW met1 ( 42090 16830 ) ( 42550 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 13110 56270 0 ) ( 15870 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 42550 12410 ) ( * 16830 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 42550 12410 ) L1M1_PR_MR
NEW met1 ( 42550 12410 ) M1M2_PR
NEW li1 ( 16790 25670 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 14950 25670 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 15870 56270 ) M1M2_PR
NEW li1 ( 42090 16830 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15870 16830 ) M1M2_PR
NEW met1 ( 15870 25670 ) M1M2_PR
NEW met1 ( 42550 16830 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 42550 12410 ) RECT ( -355 -70 0 70 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15870 25670 ) RECT ( -595 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net27 ( fanout27 X ) ( _132_ RESET_B ) ( _131_ RESET_B ) ( _086_ A_N ) ( _085_ A ) ( _078_ A_N ) ( _076_ A_N )
( _075_ A ) + USE SIGNAL
+ ROUTED met1 ( 48530 6290 ) ( 49910 * )
NEW met1 ( 48530 6290 ) ( * 6630 )
NEW met1 ( 48530 34170 ) ( 51290 * )
NEW met2 ( 51290 25330 ) ( * 34170 )
NEW met1 ( 49910 25330 ) ( 51290 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 49910 6290 ) ( * 25330 )
NEW met1 ( 40250 36210 0 ) ( 40710 * )
NEW met1 ( 40710 35870 ) ( * 36210 )
NEW met1 ( 40710 35870 ) ( 46230 * )
NEW met2 ( 46230 34170 ) ( * 35870 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 40250 42670 ) ( 42550 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 40250 36890 ) ( * 42670 )
NEW met1 ( 40250 36210 0 ) ( * 36890 )
NEW met1 ( 37950 41990 0 ) ( 40250 * )
NEW met1 ( 43930 45050 ) ( * 45730 )
NEW met1 ( 40710 45730 ) ( 43930 * )
NEW met1 ( 40710 45390 ) ( * 45730 )
NEW met1 ( 40250 45390 ) ( 40710 * )
NEW met2 ( 40250 42670 ) ( * 45390 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 45770 47430 ) ( 46230 * )
NEW met2 ( 45770 45390 ) ( * 47430 )
NEW met1 ( 43930 45390 ) ( 45770 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 29670 41820 ) ( * 41990 )
NEW met3 ( 29670 41820 ) ( 37950 * )
NEW met2 ( 37950 41820 ) ( * 41990 )
NEW met1 ( 46230 34170 ) ( 48530 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 49910 6290 ) M1M2_PR
NEW li1 ( 48530 6630 ) L1M1_PR_MR
NEW li1 ( 48530 34170 ) L1M1_PR_MR
NEW met1 ( 51290 34170 ) M1M2_PR
NEW met1 ( 51290 25330 ) M1M2_PR
NEW met1 ( 49910 25330 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 46230 35870 ) M1M2_PR
NEW met1 ( 46230 34170 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 42550 42670 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 40250 42670 ) M1M2_PR
NEW met1 ( 40250 36890 ) M1M2_PR
NEW met1 ( 40250 41990 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 43930 45050 ) L1M1_PR_MR
NEW met1 ( 40250 45390 ) M1M2_PR
NEW li1 ( 46230 47430 ) L1M1_PR_MR
NEW met1 ( 45770 47430 ) M1M2_PR
NEW met1 ( 45770 45390 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 29670 41990 ) L1M1_PR_MR
NEW met1 ( 29670 41990 ) M1M2_PR
NEW met2 ( 29670 41820 ) M2M3_PR
NEW met2 ( 37950 41820 ) M2M3_PR
NEW met1 ( 37950 41990 ) M1M2_PR
NEW met2 ( 40250 41990 ) RECT ( -70 -485 70 0 )
NEW met1 ( 29670 41990 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net28 ( fanout28 X ) ( fanout26 A ) ( fanout25 A ) ( fanout27 A ) ( fanout22 A ) ( fanout24 A ) + USE SIGNAL
+ ROUTED met1 ( 43010 12410 ) ( 48530 * )
NEW met2 ( 41630 41990 ) ( * 44540 )
NEW met2 ( 41630 44540 ) ( 42090 * )
NEW met2 ( 42090 44540 ) ( * 52870 )
NEW met1 ( 42090 52870 ) ( 43010 * )
NEW met1 ( 32430 36550 ) ( * 37570 )
NEW met1 ( 32430 37570 ) ( 43010 * )
NEW met2 ( 43010 37570 ) ( * 41990 )
NEW met1 ( 41630 41990 ) ( 43010 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 33810 26350 ) ( 34730 * )
NEW met2 ( 34730 26350 ) ( * 29580 )
NEW met2 ( 34270 29580 ) ( 34730 * )
NEW met2 ( 34270 29580 ) ( * 37570 )
NEW met1 ( 42090 17850 ) ( 43010 * )
NEW met2 ( 42090 17850 ) ( * 26860 )
NEW met2 ( 41630 26860 ) ( 42090 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 41630 26860 ) ( * 37570 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 42090 14450 ) ( 43010 * )
NEW met2 ( 42090 14450 ) ( * 17850 )
NEW met2 ( 43010 12410 ) ( * 14450 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 48530 12410 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 43010 12410 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 41630 41990 ) L1M1_PR_MR
NEW met1 ( 41630 41990 ) M1M2_PR
NEW met1 ( 42090 52870 ) M1M2_PR
NEW li1 ( 43010 52870 ) L1M1_PR_MR
NEW li1 ( 32430 36550 ) L1M1_PR_MR
NEW met1 ( 43010 37570 ) M1M2_PR
NEW met1 ( 43010 41990 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 33810 26350 ) L1M1_PR_MR
NEW met1 ( 34730 26350 ) M1M2_PR
NEW met1 ( 34270 37570 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 43010 17850 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 42090 17850 ) M1M2_PR
NEW met1 ( 41630 37570 ) M1M2_PR
NEW met1 ( 43010 14450 ) M1M2_PR
NEW met1 ( 42090 14450 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 41630 41990 ) RECT ( -355 -70 0 70 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 34270 37570 ) RECT ( -595 -70 0 70 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 41630 37570 ) RECT ( -595 -70 0 70 ) ;
- net29 ( _109_ CLK_N ) ( _061__1 Y ) + USE CLOCK
+ ROUTED met2 ( 45310 45730 ) ( * 52530 )
NEW met1 ( 40250 52530 ) ( 45310 * )
NEW met1 ( 40250 52190 ) ( * 52530 )
NEW met1 ( 28750 52190 ) ( 40250 * )
NEW met1 ( 28750 52190 ) ( * 52870 )
NEW li1 ( 45310 45730 ) L1M1_PR_MR
NEW met1 ( 45310 45730 ) M1M2_PR
NEW met1 ( 45310 52530 ) M1M2_PR
NEW li1 ( 28750 52870 ) L1M1_PR_MR
NEW met1 ( 45310 45730 ) RECT ( -355 -70 0 70 ) ;
- net3 ( input3 X ) ( _139_ A ) ( _060_ A ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 44390 3910 ) ( 47150 * )
NEW met1 ( 27830 25330 ) ( * 25670 )
NEW met1 ( 27830 25330 ) ( 34270 * )
NEW met1 ( 34270 24990 ) ( * 25330 )
NEW met1 ( 34270 24990 ) ( 42550 * )
NEW met2 ( 42550 24990 ) ( * 27710 )
NEW met1 ( 42550 27710 ) ( 44390 * )
NEW met2 ( 44390 3910 ) ( * 27710 )
NEW met1 ( 44390 3910 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47150 3910 ) L1M1_PR_MR
NEW li1 ( 44390 27710 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 44390 27710 ) M1M2_PR
NEW li1 ( 27830 25670 ) L1M1_PR_MR
NEW met1 ( 42550 24990 ) M1M2_PR
NEW met1 ( 42550 27710 ) M1M2_PR
NEW met1 ( 44390 27710 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net30 ( _110_ CLK_N ) ( _097__2 Y ) + USE CLOCK
+ ROUTED met1 ( 6670 43010 ) ( 7130 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 7130 43010 ) ( * 56610 )
NEW met1 ( 17250 55930 ) ( * 56610 )
NEW met1 ( 7130 56610 ) ( 17250 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 6670 43010 ) L1M1_PR_MR
NEW met1 ( 7130 43010 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 7130 56610 ) M1M2_PR
NEW li1 ( 17250 55930 ) L1M1_PR_MR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net31 ( _111_ CLK_N ) ( _098__3 Y ) + USE CLOCK
+ ROUTED met1 ( 31510 34170 ) ( 33350 * )
NEW met2 ( 31510 34170 ) ( * 38590 )
NEW li1 ( 33350 34170 ) L1M1_PR_MR
NEW met1 ( 31510 34170 ) M1M2_PR
NEW li1 ( 31510 38590 ) L1M1_PR_MR
NEW met1 ( 31510 38590 ) M1M2_PR
NEW met1 ( 31510 38590 ) RECT ( -355 -70 0 70 ) ;
- net32 ( _112_ CLK_N ) ( _099__4 Y ) + USE CLOCK
+ ROUTED met2 ( 24610 39950 ) ( * 53210 )
NEW met1 ( 24610 39950 ) ( 37490 * )
NEW met1 ( 37490 39610 ) ( * 39950 )
NEW met1 ( 6670 53210 ) ( 24610 * )
NEW li1 ( 6670 53210 ) L1M1_PR_MR
NEW met1 ( 24610 53210 ) M1M2_PR
NEW met1 ( 24610 39950 ) M1M2_PR
NEW li1 ( 37490 39610 ) L1M1_PR_MR ;
- net33 ( _113_ CLK_N ) ( _100__5 Y ) + USE CLOCK
+ ROUTED met2 ( 6670 47770 ) ( * 55250 )
NEW met1 ( 6670 47770 ) ( 18170 * )
NEW met1 ( 6670 47770 ) M1M2_PR
NEW li1 ( 6670 55250 ) L1M1_PR_MR
NEW met1 ( 6670 55250 ) M1M2_PR
NEW li1 ( 18170 47770 ) L1M1_PR_MR
NEW met1 ( 6670 55250 ) RECT ( -355 -70 0 70 ) ;
- net34 ( _114_ CLK_N ) ( _101__6 Y ) + USE CLOCK
+ ROUTED met2 ( 18170 29410 ) ( * 36550 )
NEW met1 ( 7590 29410 ) ( 18170 * )
NEW li1 ( 7590 29410 ) L1M1_PR_MR
NEW met1 ( 18170 29410 ) M1M2_PR
NEW li1 ( 18170 36550 ) L1M1_PR_MR
NEW met1 ( 18170 36550 ) M1M2_PR
NEW met1 ( 18170 36550 ) RECT ( -355 -70 0 70 ) ;
- net35 ( _115_ CLK_N ) ( _102__7 Y ) + USE CLOCK
+ ROUTED met1 ( 6670 34170 ) ( 7590 * )
NEW met2 ( 7590 34170 ) ( * 51170 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15870 50490 ) ( * 51170 )
NEW met1 ( 15870 50490 ) ( 17710 * )
NEW met1 ( 7590 51170 ) ( 15870 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 6670 34170 ) L1M1_PR_MR
NEW met1 ( 7590 34170 ) M1M2_PR
NEW met1 ( 7590 51170 ) M1M2_PR
NEW li1 ( 17710 50490 ) L1M1_PR_MR ;
- net36 ( _116_ CLK_N ) ( _103__8 Y ) + USE CLOCK
+ ROUTED met1 ( 29210 20570 ) ( 34730 * )
NEW met2 ( 34730 20570 ) ( * 25670 )
NEW li1 ( 29210 20570 ) L1M1_PR_MR
NEW met1 ( 34730 20570 ) M1M2_PR
NEW li1 ( 34730 25670 ) L1M1_PR_MR
NEW met1 ( 34730 25670 ) M1M2_PR
NEW met1 ( 34730 25670 ) RECT ( -355 -70 0 70 ) ;
- net37 ( _117_ CLK_N ) ( _104__9 Y ) + USE CLOCK
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 34730 40290 ) ( 36570 * )
NEW met2 ( 34730 40290 ) ( * 50150 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 36570 40290 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 34730 40290 ) M1M2_PR
NEW li1 ( 34730 50150 ) L1M1_PR_MR
NEW met1 ( 34730 50150 ) M1M2_PR
NEW met1 ( 34730 50150 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net38 ( _118_ CLK_N ) ( _105__10 Y ) + USE CLOCK
+ ROUTED met2 ( 29210 15810 ) ( * 55930 )
NEW met1 ( 29210 55930 ) ( 37490 * )
NEW li1 ( 29210 15810 ) L1M1_PR_MR
NEW met1 ( 29210 15810 ) M1M2_PR
NEW met1 ( 29210 55930 ) M1M2_PR
NEW li1 ( 37490 55930 ) L1M1_PR_MR
NEW met1 ( 29210 15810 ) RECT ( -355 -70 0 70 ) ;
- net39 ( _119_ CLK_N ) ( _106__11 Y ) + USE CLOCK
+ ROUTED met1 ( 17710 15810 ) ( 26450 * )
NEW met2 ( 17710 15810 ) ( * 17510 )
NEW li1 ( 26450 15810 ) L1M1_PR_MR
NEW met1 ( 17710 15810 ) M1M2_PR
NEW li1 ( 17710 17510 ) L1M1_PR_MR
NEW met1 ( 17710 17510 ) M1M2_PR
NEW met1 ( 17710 17510 ) RECT ( -355 -70 0 70 ) ;
- net4 ( fanout28 A ) ( input4 X ) + USE SIGNAL
+ ROUTED met2 ( 32890 25670 ) ( * 27710 )
NEW met1 ( 19090 27710 ) ( 32890 * )
NEW li1 ( 32890 25670 ) L1M1_PR_MR
NEW met1 ( 32890 25670 ) M1M2_PR
NEW met1 ( 32890 27710 ) M1M2_PR
NEW li1 ( 19090 27710 ) L1M1_PR_MR
NEW met1 ( 32890 25670 ) RECT ( -355 -70 0 70 ) ;
- net40 ( _120_ CLK_N ) ( _107__12 Y ) + USE CLOCK
+ ROUTED met2 ( 18630 23290 ) ( * 30430 )
NEW met1 ( 18630 23290 ) ( 20930 * )
NEW met1 ( 7590 30430 ) ( 18630 * )
NEW li1 ( 7590 30430 ) L1M1_PR_MR
NEW met1 ( 18630 30430 ) M1M2_PR
NEW met1 ( 18630 23290 ) M1M2_PR
NEW li1 ( 20930 23290 ) L1M1_PR_MR ;
- net41 ( _121_ CLK_N ) ( _108__13 Y ) + USE CLOCK
+ ROUTED met1 ( 22310 31450 ) ( 26910 * )
NEW li1 ( 26910 31450 ) L1M1_PR_MR
NEW li1 ( 22310 31450 ) L1M1_PR_MR ;
- net42 ( _135_ CLK ) ( _062__14 Y ) + USE CLOCK
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 16790 55590 ) ( 20470 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 20470 10370 ) ( * 55590 )
NEW li1 ( 20470 10370 ) L1M1_PR_MR
NEW met1 ( 20470 10370 ) M1M2_PR
NEW met1 ( 20470 55590 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 16790 55590 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 20470 10370 ) RECT ( -355 -70 0 70 ) ;
- net43 ( _132_ D ) ( _112_ D ) ( hold1 X ) + USE SIGNAL
+ ROUTED met2 ( 39330 39610 ) ( * 41650 )
NEW met1 ( 39330 41650 ) ( 43930 * )
NEW met1 ( 34270 36890 ) ( 34730 * )
NEW met2 ( 34730 36890 ) ( * 39270 )
NEW met1 ( 34730 39270 ) ( 39330 * )
NEW met1 ( 39330 39270 ) ( * 39610 )
NEW li1 ( 39330 39610 ) L1M1_PR_MR
NEW met1 ( 39330 39610 ) M1M2_PR
NEW met1 ( 39330 41650 ) M1M2_PR
NEW li1 ( 43930 41650 ) L1M1_PR_MR
NEW li1 ( 34270 36890 ) L1M1_PR_MR
NEW met1 ( 34730 36890 ) M1M2_PR
NEW met1 ( 34730 39270 ) M1M2_PR
NEW met1 ( 39330 39610 ) RECT ( -355 -70 0 70 ) ;
- net44 ( _134_ D ) ( _117_ D ) ( hold2 X ) + USE SIGNAL
+ ROUTED met1 ( 34270 50490 ) ( 36570 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 34270 47090 ) ( 34305 * )
NEW met2 ( 34270 47090 ) ( * 50490 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 34270 50490 ) L1M1_PR_MR
NEW li1 ( 36570 50490 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 34305 47090 ) L1M1_PR_MR
NEW met1 ( 34270 47090 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 34270 50490 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 34305 47090 ) RECT ( 0 -70 320 70 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 34270 50490 ) RECT ( -595 -70 0 70 ) ;
- net45 ( _123_ D ) ( _109_ D ) ( hold3 X ) + USE SIGNAL
+ ROUTED met1 ( 29670 52870 ) ( 30590 * )
NEW met2 ( 29670 46750 ) ( * 52870 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 15870 46750 ) ( 29670 * )
NEW met1 ( 15870 46750 ) ( * 47090 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 29670 55590 ) ( 31050 * )
NEW met2 ( 29670 52870 ) ( * 55590 )
NEW li1 ( 30590 52870 ) L1M1_PR_MR
NEW met1 ( 29670 52870 ) M1M2_PR
NEW met1 ( 29670 46750 ) M1M2_PR
NEW li1 ( 15870 47090 ) L1M1_PR_MR
NEW li1 ( 31050 55590 ) L1M1_PR_MR
NEW met1 ( 29670 55590 ) M1M2_PR ;
- net46 ( _125_ D ) ( _110_ D ) ( hold4 X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 18985 55930 ) ( 19550 * )
NEW met2 ( 19550 55930 ) ( * 58650 )
NEW met1 ( 19550 58650 ) ( 25070 * )
NEW met1 ( 25070 57630 ) ( * 58650 )
NEW met1 ( 25070 57630 ) ( 43930 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 15410 44710 ) ( 19090 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 19090 44710 ) ( * 47940 )
NEW met2 ( 19090 47940 ) ( 19550 * )
NEW met2 ( 19550 47940 ) ( * 55930 )
NEW li1 ( 18985 55930 ) L1M1_PR_MR
NEW met1 ( 19550 55930 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 19550 58650 ) M1M2_PR
NEW li1 ( 43930 57630 ) L1M1_PR_MR
NEW li1 ( 15410 44710 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 19090 44710 ) M1M2_PR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net47 ( _124_ D ) ( _115_ D ) ( hold5 X ) + USE SIGNAL
+ ROUTED met1 ( 12190 45390 ) ( 13570 * )
NEW met2 ( 12190 45390 ) ( * 50150 )
NEW met1 ( 8510 50150 ) ( 13800 * )
NEW met1 ( 13800 49810 ) ( * 50150 )
NEW met1 ( 13800 49810 ) ( 17710 * )
NEW met1 ( 17710 49810 ) ( * 50150 )
NEW met1 ( 17710 50150 ) ( 19550 * )
NEW li1 ( 8510 50150 ) L1M1_PR_MR
NEW li1 ( 13570 45390 ) L1M1_PR_MR
NEW met1 ( 12190 45390 ) M1M2_PR
NEW met1 ( 12190 50150 ) M1M2_PR
NEW li1 ( 19550 50150 ) L1M1_PR_MR
NEW met1 ( 12190 50150 ) RECT ( -595 -70 0 70 ) ;
- net48 ( _126_ D ) ( _113_ D ) ( hold6 X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 19550 41650 ) ( * 47430 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 19550 47430 ) ( 20010 * )
NEW met1 ( 19090 44030 ) ( 24610 * )
NEW met2 ( 19090 43860 ) ( * 44030 )
NEW met2 ( 19090 43860 ) ( 19550 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 19550 41650 ) L1M1_PR_MR
NEW met1 ( 19550 41650 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 19550 47430 ) M1M2_PR
NEW li1 ( 20010 47430 ) L1M1_PR_MR
NEW li1 ( 24610 44030 ) L1M1_PR_MR
NEW met1 ( 19090 44030 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 19550 41650 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net49 ( _118_ D ) ( hold7 X ) + USE SIGNAL
+ ROUTED met1 ( 42550 53890 ) ( 43930 * )
NEW met2 ( 42550 53890 ) ( * 55590 )
NEW met1 ( 39330 55590 ) ( 42550 * )
NEW li1 ( 43930 53890 ) L1M1_PR_MR
NEW met1 ( 42550 53890 ) M1M2_PR
NEW met1 ( 42550 55590 ) M1M2_PR
NEW li1 ( 39330 55590 ) L1M1_PR_MR ;
- net5 ( input5 X ) ( _122_ D ) + USE SIGNAL
+ ROUTED met1 ( 43010 6290 ) ( 46230 * )
NEW met1 ( 43010 6290 ) ( * 6970 )
NEW met1 ( 41170 6970 ) ( 43010 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 41170 6970 ) ( * 9350 )
NEW met1 ( 37490 9350 ) ( 41170 * )
NEW met1 ( 35190 33150 ) ( 37490 * )
NEW met2 ( 35190 33150 ) ( * 49810 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 28290 49810 ) ( 35190 * )
NEW met2 ( 28290 49810 ) ( * 52190 )
NEW met1 ( 19550 52190 ) ( 28290 * )
NEW met1 ( 19550 52190 ) ( * 52530 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 37490 9350 ) ( * 33150 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 46230 6290 ) L1M1_PR_MR
NEW met1 ( 41170 6970 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 41170 9350 ) M1M2_PR
NEW met1 ( 37490 9350 ) M1M2_PR
NEW met1 ( 37490 33150 ) M1M2_PR
NEW met1 ( 35190 33150 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 35190 49810 ) M1M2_PR
NEW met1 ( 28290 49810 ) M1M2_PR
NEW met1 ( 28290 52190 ) M1M2_PR
NEW li1 ( 19550 52530 ) L1M1_PR_MR ;
- net50 ( _130_ D ) ( _121_ D ) ( hold8 X ) + USE SIGNAL
+ ROUTED met2 ( 28750 31450 ) ( * 33830 )
NEW met1 ( 21390 33830 ) ( 28750 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 29210 26350 ) ( 29670 * )
NEW met2 ( 29670 26350 ) ( * 31450 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 28750 31450 ) ( 29670 * )
NEW li1 ( 28750 31450 ) L1M1_PR_MR
NEW met1 ( 28750 31450 ) M1M2_PR
NEW met1 ( 28750 33830 ) M1M2_PR
NEW li1 ( 21390 33830 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 29210 26350 ) L1M1_PR_MR
NEW met1 ( 29670 26350 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 29670 31450 ) M1M2_PR
NEW met1 ( 28750 31450 ) RECT ( -355 -70 0 70 ) ;
- net51 ( _129_ D ) ( _120_ D ) ( hold9 X ) + USE SIGNAL
+ ROUTED met1 ( 21390 29070 ) ( 21850 * )
NEW met2 ( 21850 29070 ) ( * 30430 )
NEW met1 ( 21850 30430 ) ( 23230 * )
NEW met1 ( 21850 23290 ) ( 22770 * )
NEW met2 ( 21850 23290 ) ( * 29070 )
NEW li1 ( 21390 29070 ) L1M1_PR_MR
NEW met1 ( 21850 29070 ) M1M2_PR
NEW met1 ( 21850 30430 ) M1M2_PR
NEW li1 ( 23230 30430 ) L1M1_PR_MR
NEW li1 ( 22770 23290 ) L1M1_PR_MR
NEW met1 ( 21850 23290 ) M1M2_PR ;
- net52 ( _133_ D ) ( _116_ D ) ( hold10 X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 39790 32130 ) ( * 44030 )
NEW met2 ( 38870 44030 ) ( 39790 * )
NEW met2 ( 38870 44030 ) ( * 45730 )
NEW met1 ( 38870 45390 ) ( * 45730 )
NEW met1 ( 38870 45390 ) ( 39755 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 36570 26010 ) ( * 32130 )
NEW met1 ( 36570 32130 ) ( 39790 * )
NEW li1 ( 39790 32130 ) L1M1_PR_MR
openlane!: reharden gpio_control_block update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
2022-09-14 12:42:23 -05:00
NEW met1 ( 39790 32130 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 38870 45730 ) M1M2_PR
NEW li1 ( 39755 45390 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 36570 26010 ) L1M1_PR_MR
NEW met1 ( 36570 26010 ) M1M2_PR
NEW met1 ( 36570 32130 ) M1M2_PR
NEW met1 ( 39790 32130 ) RECT ( -355 -70 0 70 )
NEW met1 ( 36570 26010 ) RECT ( -355 -70 0 70 ) ;
- net53 ( _128_ D ) ( _119_ D ) ( hold11 X ) + USE SIGNAL
+ ROUTED met1 ( 20930 32130 ) ( 21390 * )
NEW met2 ( 20930 32130 ) ( * 40290 )
NEW met1 ( 16790 40290 ) ( 20930 * )
NEW met1 ( 16790 39950 ) ( * 40290 )
NEW met1 ( 19550 17510 ) ( 20930 * )
NEW met2 ( 20930 17510 ) ( * 32130 )
NEW li1 ( 21390 32130 ) L1M1_PR_MR
NEW met1 ( 20930 32130 ) M1M2_PR
NEW met1 ( 20930 40290 ) M1M2_PR
NEW li1 ( 16790 39950 ) L1M1_PR_MR
NEW li1 ( 19550 17510 ) L1M1_PR_MR
NEW met1 ( 20930 17510 ) M1M2_PR ;
- net54 ( _131_ D ) ( _111_ D ) ( hold12 X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 35650 38590 ) ( * 42330 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 32430 42330 ) ( 35650 * )
NEW met1 ( 35190 34170 ) ( 35650 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 35650 34170 ) ( * 38590 )
NEW li1 ( 35650 38590 ) L1M1_PR_MR
NEW met1 ( 35650 38590 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 35650 42330 ) M1M2_PR
NEW li1 ( 32430 42330 ) L1M1_PR_MR
NEW li1 ( 35190 34170 ) L1M1_PR_MR
NEW met1 ( 35650 34170 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 35650 38590 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net55 ( _127_ D ) ( _114_ D ) ( hold13 X ) + USE SIGNAL
+ ROUTED met2 ( 20010 36890 ) ( * 38590 )
NEW met1 ( 20010 38590 ) ( 25990 * )
NEW met1 ( 8445 37570 ) ( 20010 * )
NEW li1 ( 8445 37570 ) L1M1_PR_MR
NEW li1 ( 20010 36890 ) L1M1_PR_MR
NEW met1 ( 20010 36890 ) M1M2_PR
NEW met1 ( 20010 38590 ) M1M2_PR
NEW li1 ( 25990 38590 ) L1M1_PR_MR
NEW met1 ( 20010 37570 ) M1M2_PR
NEW met1 ( 20010 36890 ) RECT ( 0 -70 355 70 )
NEW met2 ( 20010 37570 ) RECT ( -70 -485 70 0 ) ;
- net6 ( output6 A ) ( _119_ Q ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 29730 16830 ) ( 33350 * )
NEW met2 ( 33350 3910 ) ( * 16830 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 33350 3910 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 33350 3910 ) M1M2_PR
NEW met1 ( 33350 16830 ) M1M2_PR
NEW li1 ( 29730 16830 ) L1M1_PR_MR
NEW met1 ( 33350 3910 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- net7 ( output7 A ) ( _121_ Q ) + USE SIGNAL
+ ROUTED met1 ( 38930 31110 ) ( 39790 * )
NEW met2 ( 39790 6970 ) ( * 31110 )
NEW li1 ( 39790 6970 ) L1M1_PR_MR
NEW met1 ( 39790 6970 ) M1M2_PR
NEW met1 ( 39790 31110 ) M1M2_PR
NEW li1 ( 38930 31110 ) L1M1_PR_MR
NEW met1 ( 39790 6970 ) RECT ( -355 -70 0 70 ) ;
- net8 ( output8 A ) ( _120_ Q ) + USE SIGNAL
+ ROUTED met1 ( 31970 22270 ) ( 32930 * )
NEW met2 ( 31970 9350 ) ( * 22270 )
NEW li1 ( 31970 9350 ) L1M1_PR_MR
NEW met1 ( 31970 9350 ) M1M2_PR
NEW met1 ( 31970 22270 ) M1M2_PR
NEW li1 ( 32930 22270 ) L1M1_PR_MR
NEW met1 ( 31970 9350 ) RECT ( -355 -70 0 70 ) ;
- net9 ( output9 A ) ( _116_ Q ) + USE SIGNAL
+ ROUTED met1 ( 40710 12410 ) ( 41630 * )
NEW met1 ( 41630 26350 ) ( 46730 * )
NEW met2 ( 41630 12410 ) ( * 26350 )
NEW li1 ( 40710 12410 ) L1M1_PR_MR
NEW met1 ( 41630 12410 ) M1M2_PR
NEW met1 ( 41630 26350 ) M1M2_PR
NEW li1 ( 46730 26350 ) L1M1_PR_MR ;
- one ( PIN one ) ( one_buffer X ) + USE SIGNAL
+ ROUTED met2 ( 25070 340 ) ( * 5950 )
NEW met2 ( 52210 340 ) ( * 6460 )
NEW met3 ( 52210 6460 ) ( 70380 * 0 )
NEW met3 ( 25070 340 ) ( 52210 * )
NEW met2 ( 25070 340 ) M2M3_PR
NEW li1 ( 25070 5950 ) L1M1_PR_MR
NEW met1 ( 25070 5950 ) M1M2_PR
NEW met2 ( 52210 340 ) M2M3_PR
NEW met2 ( 52210 6460 ) M2M3_PR
NEW met1 ( 25070 5950 ) RECT ( -355 -70 0 70 ) ;
- one_buffered ( one_buffer A ) ( const_source HI ) + USE SIGNAL
+ ROUTED met1 ( 30590 6970 ) ( * 7310 )
NEW met1 ( 30590 7310 ) ( 43470 * )
NEW li1 ( 30590 6970 ) L1M1_PR_MR
NEW li1 ( 43470 7310 ) L1M1_PR_MR ;
- pad_gpio_ana_en ( PIN pad_gpio_ana_en ) ( output6 X ) + USE SIGNAL
+ ROUTED met2 ( 83950 4590 ) ( * 12580 )
NEW met3 ( 83950 12580 ) ( 84180 * 0 )
NEW met1 ( 43010 4590 ) ( 83950 * )
NEW met1 ( 83950 4590 ) M1M2_PR
NEW met2 ( 83950 12580 ) M2M3_PR
NEW li1 ( 43010 4590 ) L1M1_PR_MR ;
- pad_gpio_ana_pol ( PIN pad_gpio_ana_pol ) ( output7 X ) + USE SIGNAL
+ ROUTED met1 ( 36110 7650 ) ( 44390 * )
NEW met1 ( 44390 7310 ) ( * 7650 )
NEW met1 ( 44390 7310 ) ( 55890 * )
NEW met2 ( 55890 7310 ) ( * 14620 )
NEW met3 ( 55890 14620 ) ( 70380 * 0 )
NEW li1 ( 36110 7650 ) L1M1_PR_MR
NEW met1 ( 55890 7310 ) M1M2_PR
NEW met2 ( 55890 14620 ) M2M3_PR ;
- pad_gpio_ana_sel ( PIN pad_gpio_ana_sel ) ( output8 X ) + USE SIGNAL
+ ROUTED met1 ( 58650 8670 ) ( * 9010 )
NEW met1 ( 39790 9010 ) ( 58650 * )
NEW met1 ( 58650 8670 ) ( 83030 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 69230 15130 ) ( 83030 * )
NEW met2 ( 69230 15130 ) ( * 16660 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met3 ( 69230 16660 ) ( 70380 * 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 83030 8670 ) ( * 15130 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 83030 8670 ) M1M2_PR
NEW li1 ( 39790 9010 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 83030 15130 ) M1M2_PR
NEW met1 ( 69230 15130 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 69230 16660 ) M2M3_PR ;
- pad_gpio_dm[0] ( PIN pad_gpio_dm[0] ) ( output9 X ) + USE SIGNAL
+ ROUTED met1 ( 36110 13090 ) ( 47150 * )
NEW met1 ( 47150 12750 ) ( * 13090 )
NEW met1 ( 47150 12750 ) ( 55430 * )
NEW met2 ( 55430 12750 ) ( * 18700 )
NEW met3 ( 55430 18700 ) ( 70380 * 0 )
NEW li1 ( 36110 13090 ) L1M1_PR_MR
NEW met1 ( 55430 12750 ) M1M2_PR
NEW met2 ( 55430 18700 ) M2M3_PR ;
- pad_gpio_dm[1] ( PIN pad_gpio_dm[1] ) ( output10 X ) + USE SIGNAL
+ ROUTED met2 ( 34270 15810 ) ( * 20740 )
NEW met3 ( 34270 20740 ) ( 70380 * 0 )
NEW met2 ( 34270 20740 ) M2M3_PR
NEW li1 ( 34270 15810 ) L1M1_PR_MR
NEW met1 ( 34270 15810 ) M1M2_PR
NEW met1 ( 34270 15810 ) RECT ( -355 -70 0 70 ) ;
- pad_gpio_dm[2] ( PIN pad_gpio_dm[2] ) ( output11 X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 82800 9010 ) ( 84410 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 82800 9010 ) ( * 9690 )
NEW met1 ( 46690 9690 ) ( 82800 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 68310 15810 ) ( 84410 * )
NEW met2 ( 68310 15810 ) ( * 22780 )
NEW met3 ( 68310 22780 ) ( 70380 * 0 )
NEW met2 ( 84410 9010 ) ( * 15810 )
NEW met1 ( 84410 9010 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 46690 9690 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 84410 15810 ) M1M2_PR
NEW met1 ( 68310 15810 ) M1M2_PR
NEW met2 ( 68310 22780 ) M2M3_PR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- pad_gpio_holdover ( PIN pad_gpio_holdover ) ( output12 X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 67850 16830 ) ( * 24820 )
NEW met3 ( 67850 24820 ) ( 70380 * 0 )
NEW met1 ( 62100 16830 ) ( 67850 * )
NEW met1 ( 62100 16830 ) ( * 17170 )
NEW met1 ( 40710 17170 ) ( 62100 * )
NEW met1 ( 67850 16830 ) M1M2_PR
NEW met2 ( 67850 24820 ) M2M3_PR
NEW li1 ( 40710 17170 ) L1M1_PR_MR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- pad_gpio_ib_mode_sel ( PIN pad_gpio_ib_mode_sel ) ( output13 X ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 68770 20570 ) ( * 26860 )
NEW met3 ( 68770 26860 ) ( 70380 * 0 )
NEW met1 ( 39790 20570 ) ( 68770 * )
NEW met1 ( 68770 20570 ) M1M2_PR
NEW met2 ( 68770 26860 ) M2M3_PR
NEW li1 ( 39790 20570 ) L1M1_PR_MR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- pad_gpio_in ( PIN pad_gpio_in ) ( ANTENNA_input3_A DIODE ) ( input3 A ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 45310 28730 ) ( * 28900 )
NEW met2 ( 45310 24140 ) ( 45770 * )
NEW met2 ( 45310 24140 ) ( * 28730 )
NEW met2 ( 45770 4930 ) ( * 24140 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met3 ( 45310 28900 ) ( 70380 * 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 45770 4930 ) L1M1_PR_MR
NEW met1 ( 45770 4930 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 45310 28730 ) L1M1_PR_MR
NEW met1 ( 45310 28730 ) M1M2_PR
NEW met2 ( 45310 28900 ) M2M3_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45770 4930 ) RECT ( 0 -70 355 70 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 45310 28730 ) RECT ( -355 -70 0 70 ) ;
- pad_gpio_inenb ( PIN pad_gpio_inenb ) ( output14 X ) + USE SIGNAL
+ ROUTED met2 ( 56810 15810 ) ( * 30940 )
NEW met1 ( 49910 15810 ) ( 56810 * )
NEW met3 ( 56810 30940 ) ( 70380 * 0 )
NEW met2 ( 56810 30940 ) M2M3_PR
NEW met1 ( 56810 15810 ) M1M2_PR
NEW li1 ( 49910 15810 ) L1M1_PR_MR ;
- pad_gpio_out ( PIN pad_gpio_out ) ( output15 X ) + USE SIGNAL
+ ROUTED met2 ( 68770 28390 ) ( * 32980 )
NEW met3 ( 68770 32980 ) ( 70380 * 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 47150 28390 ) ( * 28680 )
NEW met1 ( 46690 28680 ) ( 47150 * )
NEW met1 ( 46690 28390 ) ( * 28680 )
NEW met1 ( 39790 28390 ) ( 46690 * )
NEW met1 ( 47150 28390 ) ( 68770 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 68770 28390 ) M1M2_PR
NEW met2 ( 68770 32980 ) M2M3_PR
NEW li1 ( 39790 28390 ) L1M1_PR_MR ;
- pad_gpio_outenb ( PIN pad_gpio_outenb ) ( output16 X ) + USE SIGNAL
+ ROUTED met2 ( 55890 20230 ) ( * 35020 )
NEW met1 ( 49910 20230 ) ( 55890 * )
NEW met3 ( 55890 35020 ) ( 70380 * 0 )
NEW met2 ( 55890 35020 ) M2M3_PR
NEW met1 ( 55890 20230 ) M1M2_PR
NEW li1 ( 49910 20230 ) L1M1_PR_MR ;
- pad_gpio_slow_sel ( PIN pad_gpio_slow_sel ) ( output17 X ) + USE SIGNAL
+ ROUTED met2 ( 55890 37060 ) ( * 58990 )
NEW met1 ( 38410 58990 ) ( 55890 * )
NEW met3 ( 55890 37060 ) ( 70380 * 0 )
NEW met2 ( 55890 37060 ) M2M3_PR
NEW met1 ( 55890 58990 ) M1M2_PR
NEW li1 ( 38410 58990 ) L1M1_PR_MR ;
- pad_gpio_vtrip_sel ( PIN pad_gpio_vtrip_sel ) ( output18 X ) + USE SIGNAL
+ ROUTED met2 ( 13570 39100 ) ( * 42330 )
NEW met3 ( 13570 39100 ) ( 70380 * 0 )
NEW met2 ( 13570 39100 ) M2M3_PR
NEW li1 ( 13570 42330 ) L1M1_PR_MR
NEW met1 ( 13570 42330 ) M1M2_PR
NEW met1 ( 13570 42330 ) RECT ( -355 -70 0 70 ) ;
- resetn ( PIN resetn ) ( ANTENNA_input4_A DIODE ) ( input4 A ) + USE SIGNAL
+ ROUTED met2 ( 68310 29410 ) ( * 41140 )
NEW met3 ( 68310 41140 ) ( 70380 * 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 6670 28390 ) ( 13800 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 18170 28730 ) ( 20010 * )
NEW met1 ( 20010 28730 ) ( * 29410 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 13800 28390 ) ( * 28730 )
NEW met1 ( 13800 28730 ) ( 18170 * )
NEW met1 ( 20010 29410 ) ( 68310 * )
NEW li1 ( 6670 28390 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 68310 29410 ) M1M2_PR
NEW met2 ( 68310 41140 ) M2M3_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 18170 28730 ) L1M1_PR_MR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- resetn_out ( PIN resetn_out ) ( output19 X ) + USE SIGNAL
+ ROUTED met2 ( 46230 43180 ) ( * 57970 )
NEW met1 ( 34270 57970 ) ( 46230 * )
NEW met1 ( 34270 57970 ) ( * 58650 )
NEW met1 ( 31510 58650 ) ( 34270 * )
NEW met1 ( 31510 58310 ) ( * 58650 )
NEW met1 ( 30130 58310 ) ( 31510 * )
NEW met3 ( 46230 43180 ) ( 70380 * 0 )
NEW met2 ( 46230 43180 ) M2M3_PR
NEW met1 ( 46230 57970 ) M1M2_PR
NEW li1 ( 30130 58310 ) L1M1_PR_MR ;
- serial_clock ( PIN serial_clock ) ( ANTENNA_clkbuf_0_serial_clock_A DIODE ) ( clkbuf_0_serial_clock A ) + USE CLOCK
+ ROUTED met1 ( 25070 13090 ) ( 25990 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 24610 54060 ) ( 25070 * )
NEW met2 ( 24610 54060 ) ( * 57630 )
NEW met1 ( 17250 57630 ) ( 24610 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 17250 57630 ) ( * 57970 )
NEW met2 ( 41630 45220 ) ( * 56610 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 25070 56610 ) ( 41630 * )
NEW met2 ( 25070 56610 ) ( * 56780 )
NEW met2 ( 24610 56780 ) ( 25070 * )
NEW met2 ( 25070 13090 ) ( * 54060 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met3 ( 41630 45220 ) ( 70380 * 0 )
NEW met1 ( 25070 13090 ) M1M2_PR
NEW li1 ( 25990 13090 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 24610 57630 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 17250 57970 ) L1M1_PR_MR
NEW met2 ( 41630 45220 ) M2M3_PR
NEW met1 ( 41630 56610 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 25070 56610 ) M1M2_PR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- serial_clock_out ( PIN serial_clock_out ) ( serial_clock_out_buffer X ) + USE CLOCK
+ ROUTED met1 ( 25530 12750 ) ( 27370 * )
NEW met2 ( 69230 18530 ) ( * 41140 )
NEW met2 ( 68770 41140 ) ( 69230 * )
NEW met2 ( 68770 41140 ) ( * 47260 )
NEW met3 ( 68770 47260 ) ( 70380 * 0 )
NEW met2 ( 27370 12750 ) ( * 18530 )
NEW met1 ( 27370 18530 ) ( 69230 * )
NEW li1 ( 25530 12750 ) L1M1_PR_MR
NEW met1 ( 27370 12750 ) M1M2_PR
NEW met1 ( 69230 18530 ) M1M2_PR
NEW met2 ( 68770 47260 ) M2M3_PR
NEW met1 ( 27370 18530 ) M1M2_PR ;
- serial_clock_out_buffered ( _134_ CLK ) ( _133_ CLK ) ( _132_ CLK ) ( _131_ CLK ) ( _122_ CLK ) ( clkbuf_1_1__f_serial_clock X ) ( serial_clock_out_buffer A ) + USE CLOCK
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 17710 52870 ) ( 18170 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 17710 33150 ) ( 18170 * )
NEW met2 ( 17710 28900 ) ( * 33150 )
NEW met2 ( 17710 28900 ) ( 18170 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 18170 12750 ) ( * 28900 )
NEW met1 ( 16790 12750 ) ( 18170 * )
NEW met2 ( 31050 42330 ) ( * 42500 )
NEW met3 ( 17710 42500 ) ( 31050 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 32890 36210 ) ( * 36550 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 30590 36210 ) ( 32890 * )
NEW met1 ( 30590 36210 ) ( * 36890 )
NEW met2 ( 30590 36890 ) ( * 42330 )
NEW met2 ( 30590 42330 ) ( 31050 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 30590 47770 ) ( 32890 * )
NEW met2 ( 30590 42330 ) ( * 47770 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 39790 44710 ) ( 41170 * )
NEW met2 ( 39330 44710 ) ( 39790 * )
NEW met2 ( 39330 44710 ) ( * 47770 )
NEW met1 ( 32890 47770 ) ( 39330 * )
NEW met2 ( 17710 33150 ) ( * 52870 )
NEW li1 ( 18170 52870 ) L1M1_PR_MR
NEW met1 ( 17710 52870 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 18170 33150 ) L1M1_PR_MR
NEW met1 ( 17710 33150 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 18170 12750 ) M1M2_PR
NEW li1 ( 16790 12750 ) L1M1_PR_MR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31050 42330 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 31050 42330 ) M1M2_PR
NEW met2 ( 31050 42500 ) M2M3_PR
NEW met2 ( 17710 42500 ) M2M3_PR
NEW li1 ( 32890 36550 ) L1M1_PR_MR
NEW met1 ( 30590 36890 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 32890 47770 ) L1M1_PR_MR
NEW met1 ( 30590 47770 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW li1 ( 41170 44710 ) L1M1_PR_MR
NEW met1 ( 39790 44710 ) M1M2_PR
NEW met1 ( 39330 47770 ) M1M2_PR
NEW met1 ( 31050 42330 ) RECT ( -355 -70 0 70 )
NEW met2 ( 17710 42500 ) RECT ( -70 -485 70 0 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- serial_data_in ( PIN serial_data_in ) ( ANTENNA_input5_A DIODE ) ( input5 A ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met3 ( 110860 49300 0 ) ( 111090 * )
NEW met2 ( 111090 6970 ) ( * 49300 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 27830 9010 ) ( 34500 * )
NEW met1 ( 34500 8670 ) ( * 9010 )
NEW met1 ( 34500 8670 ) ( 47150 * )
NEW met2 ( 47150 6970 ) ( * 8670 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 47150 6970 ) ( 111090 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 27830 9010 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 111090 6970 ) M1M2_PR
NEW met2 ( 111090 49300 ) M2M3_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47150 6970 ) L1M1_PR_MR
NEW met1 ( 47150 8670 ) M1M2_PR
NEW met1 ( 47150 6970 ) M1M2_PR
NEW met1 ( 47150 6970 ) RECT ( -595 -70 0 70 ) ;
- serial_data_out ( PIN serial_data_out ) ( output20 X ) + USE SIGNAL
+ ROUTED met2 ( 12650 50660 ) ( * 52190 )
NEW met3 ( 62100 51340 ) ( 70380 * 0 )
NEW met3 ( 62100 50660 ) ( * 51340 )
NEW met3 ( 12650 50660 ) ( 62100 * )
NEW met2 ( 12650 50660 ) M2M3_PR
NEW li1 ( 12650 52190 ) L1M1_PR_MR
NEW met1 ( 12650 52190 ) M1M2_PR
NEW met1 ( 12650 52190 ) RECT ( -355 -70 0 70 ) ;
- serial_load ( PIN serial_load ) ( ANTENNA_clkbuf_0_serial_load_A DIODE ) ( clkbuf_0_serial_load A ) + USE CLOCK
+ ROUTED met2 ( 14950 39950 ) ( * 53380 )
NEW met2 ( 14950 32130 ) ( * 39950 )
NEW met1 ( 6670 32130 ) ( 14950 * )
NEW met3 ( 14950 53380 ) ( 70380 * 0 )
NEW li1 ( 6670 32130 ) L1M1_PR_MR
NEW li1 ( 14950 39950 ) L1M1_PR_MR
NEW met1 ( 14950 39950 ) M1M2_PR
NEW met2 ( 14950 53380 ) M2M3_PR
NEW met1 ( 14950 32130 ) M1M2_PR
NEW met1 ( 14950 39950 ) RECT ( -355 -70 0 70 ) ;
- serial_load_out ( PIN serial_load_out ) ( serial_load_out_buffer X ) + USE CLOCK
+ ROUTED met2 ( 69230 41650 ) ( * 55420 )
NEW met3 ( 69230 55420 ) ( 70380 * 0 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 55430 26690 ) ( * 41650 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 55430 41650 ) ( 69230 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 48300 26690 ) ( 55430 * )
NEW met1 ( 25530 15130 ) ( 27830 * )
NEW met2 ( 27830 15130 ) ( * 26690 )
NEW met1 ( 27830 26690 ) ( 47610 * )
NEW met1 ( 47610 26350 ) ( * 26690 )
NEW met1 ( 47610 26350 ) ( 48300 * )
NEW met1 ( 48300 26350 ) ( * 26690 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 69230 41650 ) M1M2_PR
NEW met2 ( 69230 55420 ) M2M3_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 55430 26690 ) M1M2_PR
NEW met1 ( 55430 41650 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 25530 15130 ) L1M1_PR_MR
NEW met1 ( 27830 15130 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 27830 26690 ) M1M2_PR ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- serial_load_out_buffered ( _105__10 A ) ( _104__9 A ) ( _102__7 A ) ( _100__5 A ) ( _099__4 A ) ( _097__2 A ) ( _061__1 A )
( clkbuf_1_1__f_serial_load X ) ( serial_load_out_buffer A ) + USE CLOCK
+ ROUTED met2 ( 6210 30770 ) ( * 34170 )
NEW met1 ( 6210 30770 ) ( 9430 * )
NEW met1 ( 9430 30770 ) ( * 31110 )
NEW met2 ( 6210 34170 ) ( * 41990 )
NEW met2 ( 6210 41990 ) ( * 52870 )
NEW met2 ( 6210 52870 ) ( * 55930 )
NEW met2 ( 37030 39610 ) ( * 44030 )
NEW met1 ( 37030 44030 ) ( 40710 * )
NEW met1 ( 40710 44030 ) ( * 44370 )
NEW met1 ( 40710 44370 ) ( 44850 * )
NEW met1 ( 44850 44370 ) ( * 45050 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17710 30770 ) ( * 31110 )
NEW met1 ( 17710 30770 ) ( 23690 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 23690 30430 ) ( * 30770 )
NEW met1 ( 23690 30430 ) ( 31970 * )
NEW met2 ( 31970 30430 ) ( * 39610 )
NEW met1 ( 31970 39610 ) ( 37030 * )
NEW met2 ( 28750 14790 ) ( * 30430 )
NEW met1 ( 16790 14450 ) ( 28750 * )
NEW met1 ( 28750 14450 ) ( * 14790 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 9430 31110 ) ( 17710 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 9430 31110 ) L1M1_PR_MR
NEW li1 ( 6210 34170 ) L1M1_PR_MR
NEW met1 ( 6210 34170 ) M1M2_PR
NEW met1 ( 6210 30770 ) M1M2_PR
NEW li1 ( 6210 41990 ) L1M1_PR_MR
NEW met1 ( 6210 41990 ) M1M2_PR
NEW li1 ( 6210 52870 ) L1M1_PR_MR
NEW met1 ( 6210 52870 ) M1M2_PR
NEW li1 ( 6210 55930 ) L1M1_PR_MR
NEW met1 ( 6210 55930 ) M1M2_PR
NEW li1 ( 37030 39610 ) L1M1_PR_MR
NEW met1 ( 37030 39610 ) M1M2_PR
NEW met1 ( 37030 44030 ) M1M2_PR
NEW li1 ( 44850 45050 ) L1M1_PR_MR
NEW met1 ( 31970 30430 ) M1M2_PR
NEW met1 ( 31970 39610 ) M1M2_PR
NEW li1 ( 28750 14790 ) L1M1_PR_MR
NEW met1 ( 28750 14790 ) M1M2_PR
NEW met1 ( 28750 30430 ) M1M2_PR
NEW li1 ( 16790 14450 ) L1M1_PR_MR
NEW met1 ( 6210 34170 ) RECT ( -355 -70 0 70 )
NEW met1 ( 6210 41990 ) RECT ( -355 -70 0 70 )
NEW met1 ( 6210 52870 ) RECT ( -355 -70 0 70 )
NEW met1 ( 6210 55930 ) RECT ( -355 -70 0 70 )
NEW met1 ( 37030 39610 ) RECT ( -355 -70 0 70 )
NEW met1 ( 28750 14790 ) RECT ( 0 -70 355 70 )
NEW met1 ( 28750 30430 ) RECT ( -595 -70 0 70 ) ;
- shift_register\[0\] ( hold3 A ) ( _122_ Q ) + USE SIGNAL
+ ROUTED met1 ( 28290 53210 ) ( 33810 * )
NEW met2 ( 33810 53210 ) ( * 55590 )
NEW li1 ( 28290 53210 ) L1M1_PR_MR
NEW met1 ( 33810 53210 ) M1M2_PR
NEW li1 ( 33810 55590 ) L1M1_PR_MR
NEW met1 ( 33810 55590 ) M1M2_PR
NEW met1 ( 33810 55590 ) RECT ( -355 -70 0 70 ) ;
- shift_register\[10\] ( hold10 A ) ( _132_ Q ) + USE SIGNAL
+ ROUTED met2 ( 43010 31450 ) ( * 36210 )
NEW li1 ( 43010 31450 ) L1M1_PR_MR
NEW met1 ( 43010 31450 ) M1M2_PR
NEW li1 ( 43010 36210 ) L1M1_PR_MR
NEW met1 ( 43010 36210 ) M1M2_PR
NEW met1 ( 43010 31450 ) RECT ( -355 -70 0 70 )
NEW met1 ( 43010 36210 ) RECT ( -355 -70 0 70 ) ;
- shift_register\[11\] ( hold2 A ) ( _133_ Q ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met1 ( 31050 45390 ) ( 32430 * )
NEW met2 ( 32430 45390 ) ( * 46750 )
NEW met1 ( 31050 46750 ) ( 32430 * )
NEW met2 ( 31050 46750 ) ( * 50150 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31050 45390 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 32430 45390 ) M1M2_PR
NEW met1 ( 32430 46750 ) M1M2_PR
NEW met1 ( 31050 46750 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 31050 50150 ) L1M1_PR_MR
NEW met1 ( 31050 50150 ) M1M2_PR
NEW met1 ( 31050 50150 ) RECT ( -355 -70 0 70 ) ;
- shift_register\[12\] ( hold7 A ) ( _135_ D ) ( _134_ Q ) + USE SIGNAL
+ ROUTED met2 ( 46690 53210 ) ( * 54910 )
NEW met1 ( 37030 54910 ) ( 46690 * )
NEW met1 ( 37030 54910 ) ( * 55250 )
NEW met1 ( 35650 55250 ) ( 37030 * )
NEW met1 ( 35650 54910 ) ( * 55250 )
NEW met1 ( 15500 54910 ) ( 35650 * )
NEW met2 ( 43010 47770 ) ( * 54910 )
NEW li1 ( 46690 53210 ) L1M1_PR_MR
NEW met1 ( 46690 53210 ) M1M2_PR
NEW met1 ( 46690 54910 ) M1M2_PR
NEW li1 ( 15500 54910 ) L1M1_PR_MR
NEW li1 ( 43010 47770 ) L1M1_PR_MR
NEW met1 ( 43010 47770 ) M1M2_PR
NEW met1 ( 43010 54910 ) M1M2_PR
NEW met1 ( 46690 53210 ) RECT ( -355 -70 0 70 )
NEW met1 ( 43010 47770 ) RECT ( -355 -70 0 70 )
NEW met1 ( 43010 54910 ) RECT ( -595 -70 0 70 ) ;
- shift_register\[1\] ( hold5 A ) ( _123_ Q ) + USE SIGNAL
+ ROUTED met1 ( 9430 45050 ) ( 10350 * )
NEW met2 ( 9430 45050 ) ( * 47090 )
NEW met1 ( 7130 47090 ) ( 9430 * )
NEW li1 ( 10350 45050 ) L1M1_PR_MR
NEW met1 ( 9430 45050 ) M1M2_PR
NEW met1 ( 9430 47090 ) M1M2_PR
NEW li1 ( 7130 47090 ) L1M1_PR_MR ;
- shift_register\[2\] ( hold4 A ) ( _124_ Q ) + USE SIGNAL
+ ROUTED met1 ( 17250 50830 ) ( * 51170 )
NEW met1 ( 17250 51170 ) ( 32890 * )
NEW met2 ( 32890 51170 ) ( * 56100 )
NEW met2 ( 32890 56100 ) ( 34730 * )
NEW met2 ( 34730 56100 ) ( * 58650 )
NEW met1 ( 34730 58650 ) ( 46690 * )
NEW li1 ( 17250 50830 ) L1M1_PR_MR
NEW met1 ( 32890 51170 ) M1M2_PR
NEW met1 ( 34730 58650 ) M1M2_PR
NEW li1 ( 46690 58650 ) L1M1_PR_MR ;
- shift_register\[3\] ( hold6 A ) ( _125_ Q ) + USE SIGNAL
+ ROUTED met1 ( 24150 44710 ) ( 27370 * )
NEW li1 ( 24150 44710 ) L1M1_PR_MR
NEW li1 ( 27370 44710 ) L1M1_PR_MR ;
- shift_register\[4\] ( hold13 A ) ( _126_ Q ) + USE SIGNAL
+ ROUTED met1 ( 28290 39610 ) ( 28750 * )
NEW met2 ( 28290 39610 ) ( * 41650 )
NEW li1 ( 28750 39610 ) L1M1_PR_MR
NEW met1 ( 28290 39610 ) M1M2_PR
NEW li1 ( 28290 41650 ) L1M1_PR_MR
NEW met1 ( 28290 41650 ) M1M2_PR
NEW met1 ( 28290 41650 ) RECT ( -355 -70 0 70 ) ;
- shift_register\[5\] ( hold11 A ) ( _127_ Q ) + USE SIGNAL
+ ROUTED met1 ( 18170 31110 ) ( * 31790 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17250 31790 ) ( 18170 * )
NEW met2 ( 17250 31790 ) ( * 36210 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 18170 31110 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 17250 31790 ) M1M2_PR
NEW li1 ( 17250 36210 ) L1M1_PR_MR
NEW met1 ( 17250 36210 ) M1M2_PR
NEW met1 ( 17250 36210 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- shift_register\[6\] ( hold9 A ) ( _128_ Q ) + USE SIGNAL
+ ROUTED met1 ( 24610 31110 ) ( 25990 * )
NEW met2 ( 24610 31110 ) ( * 39270 )
NEW met1 ( 24610 39270 ) ( 25530 * )
NEW li1 ( 25990 31110 ) L1M1_PR_MR
NEW met1 ( 24610 31110 ) M1M2_PR
NEW met1 ( 24610 39270 ) M1M2_PR
NEW li1 ( 25530 39270 ) L1M1_PR_MR ;
- shift_register\[7\] ( hold8 A ) ( _129_ Q ) + USE SIGNAL
+ ROUTED met1 ( 30130 26010 ) ( 31970 * )
NEW met2 ( 30130 26010 ) ( * 28390 )
NEW li1 ( 31970 26010 ) L1M1_PR_MR
NEW met1 ( 30130 26010 ) M1M2_PR
NEW li1 ( 30130 28390 ) L1M1_PR_MR
NEW met1 ( 30130 28390 ) M1M2_PR
NEW met1 ( 30130 28390 ) RECT ( -355 -70 0 70 ) ;
- shift_register\[8\] ( hold12 A ) ( _130_ Q ) + USE SIGNAL
+ ROUTED met1 ( 30130 34510 ) ( 32430 * )
NEW met2 ( 32430 34510 ) ( * 39270 )
NEW li1 ( 30130 34510 ) L1M1_PR_MR
NEW met1 ( 32430 34510 ) M1M2_PR
NEW li1 ( 32430 39270 ) L1M1_PR_MR
NEW met1 ( 32430 39270 ) M1M2_PR
NEW met1 ( 32430 39270 ) RECT ( -355 -70 0 70 ) ;
- shift_register\[9\] ( hold1 A ) ( _131_ Q ) + USE SIGNAL
+ ROUTED met1 ( 41170 42330 ) ( 46690 * )
NEW li1 ( 41170 42330 ) L1M1_PR_MR
NEW li1 ( 46690 42330 ) L1M1_PR_MR ;
[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells
2021-12-24 13:06:58 -06:00
- user_gpio_in ( PIN user_gpio_in ) ( gpio_in_buf Z ) + USE SIGNAL
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
+ ROUTED met2 ( 67390 22610 ) ( * 57460 )
NEW met3 ( 67390 57460 ) ( 70380 * 0 )
NEW met1 ( 48990 22610 ) ( 67390 * )
NEW met1 ( 67390 22610 ) M1M2_PR
NEW met2 ( 67390 57460 ) M2M3_PR
NEW li1 ( 48990 22610 ) L1M1_PR_MR ;
- user_gpio_oeb ( PIN user_gpio_oeb ) ( ANTENNA__065__A0 DIODE ) ( _065_ A0 ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 67850 36550 ) ( * 59500 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met3 ( 67850 59500 ) ( 70380 * 0 )
NEW met1 ( 62100 36550 ) ( 67850 * )
NEW met1 ( 62100 36550 ) ( * 36890 )
NEW met1 ( 48530 36890 ) ( 62100 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 43010 36890 ) ( * 37060 )
NEW met3 ( 6670 37060 ) ( 43010 * )
NEW met2 ( 6670 37060 ) ( * 37230 )
NEW met1 ( 43010 36890 ) ( 48530 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 67850 36550 ) M1M2_PR
NEW met2 ( 67850 59500 ) M2M3_PR
NEW li1 ( 48530 36890 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 43010 36890 ) M1M2_PR
NEW met2 ( 43010 37060 ) M2M3_PR
NEW met2 ( 6670 37060 ) M2M3_PR
NEW li1 ( 6670 37230 ) L1M1_PR_MR
NEW met1 ( 6670 37230 ) M1M2_PR
NEW met1 ( 6670 37230 ) RECT ( -355 -70 0 70 ) ;
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
- user_gpio_out ( PIN user_gpio_out ) ( ANTENNA__066__B DIODE ) ( _066_ B ) + USE SIGNAL
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
+ ROUTED met2 ( 47150 45050 ) ( * 61540 )
NEW met1 ( 45310 23630 ) ( 46230 * )
NEW met2 ( 46230 23630 ) ( * 24820 )
NEW met2 ( 45770 24820 ) ( 46230 * )
NEW met2 ( 45770 24820 ) ( * 29580 )
NEW met2 ( 45310 29580 ) ( 45770 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met2 ( 45310 29580 ) ( * 45050 )
NEW met1 ( 45310 45050 ) ( 47150 * )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 45310 4930 ) ( * 23630 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met3 ( 47150 61540 ) ( 70380 * 0 )
NEW li1 ( 45310 4930 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45310 4930 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 47150 45050 ) L1M1_PR_MR
NEW met1 ( 47150 45050 ) M1M2_PR
NEW met2 ( 47150 61540 ) M2M3_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45310 23630 ) M1M2_PR
NEW met1 ( 46230 23630 ) M1M2_PR
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 45310 45050 ) M1M2_PR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 45310 4930 ) RECT ( -355 -70 0 70 )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW met1 ( 47150 45050 ) RECT ( -355 -70 0 70 ) ;
- zero ( PIN zero ) ( zero_buffer X ) + USE SIGNAL
+ ROUTED met2 ( 27370 1700 ) ( * 4250 )
NEW met1 ( 26910 4250 ) ( 27370 * )
NEW met3 ( 27370 1700 ) ( 34500 * )
NEW met3 ( 34500 1700 ) ( * 2380 )
NEW met3 ( 34500 2380 ) ( 70380 * 0 )
NEW met2 ( 27370 1700 ) M2M3_PR
NEW met1 ( 27370 4250 ) M1M2_PR
NEW li1 ( 26910 4250 ) L1M1_PR_MR ;
- zero_buffered ( zero_buffer A ) ( const_source LO ) + USE SIGNAL
+ ROUTED met1 ( 30130 3910 ) ( * 4250 )
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met2 ( 42550 4250 ) ( * 6630 )
NEW met1 ( 30130 4250 ) ( 42550 * )
reharden!: gpio_control_block - high level changes: * add larger buffers on output ports * add buffers on input ports * adjust sdc file increasing output load and setting a high transition - detailed changes: * add interactive script for openlane where the order of events is a bit shuffled - to add obstruction before pdn - to manually insert buffers on some ports - to manually remove buffers inserted by synthesis on for example serial_clock_out * change openlane config adding extra row and columns to increase the space and fit the added buffers * change config to enable buffering * increase density for better placement? * change the cell exclude list. some excluded cells didn't make sense * ef decap cells break dynamic sims? * add custom pdn script for to duplicate the old pdn - misc changes: * fix openlane makefile to properly detect interactive script !important still need to run dynamic simulations !important depends on some updates to openlane
2022-09-27 09:09:26 -05:00
NEW li1 ( 30130 3910 ) L1M1_PR_MR
reharden!: gpio_control_clock - add met5 obs to avoid drc with the top level pdn !important: still need to use the latest openlane to replicate
2022-10-05 09:00:34 -05:00
NEW met1 ( 42550 4250 ) M1M2_PR
NEW li1 ( 42550 6630 ) L1M1_PR_MR
NEW met1 ( 42550 6630 ) M1M2_PR
NEW met1 ( 42550 6630 ) RECT ( -355 -70 0 70 ) ;
harden gpio_control_block
2021-11-04 09:19:12 -05:00
END NETS
END DESIGN