2023-04-10 09:13:48 -05:00
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_MAX_FANOUT,SYNTH_STRATEGY
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/home/hosni/caravel-redesign-2/caravel/openlane/housekeeping,housekeeping,23_04_09_06_22,flow completed,0h41m38s0ms,0h35m40s0ms,67464.18509784952,0.2260162185,33732.09254892476,25.12,54.0,2396.73,4058,0,0,0,0,0,0,0,2,2,0,-1,-1,543975,74091,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,292116401.0,0.0,50.14,58.19,22.51,35.17,-1,8372,9432,193,1200,0,0,0,9096,164,1,141,326,4526,44,5,170,943,889,21,10055,2940,4901,7467,7624,32987,210449.33759999997,-1,-1,-1,-1,-1,-1,-1,-1,-1,9.25,10.0,100.0,10.0,1,50,78.2,76.8,0.2,1,0.31,1,sky130_fd_sc_hd,20,AREA 0
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