mirror of https://github.com/efabless/caravel.git
94 lines
2.6 KiB
Tcl
94 lines
2.6 KiB
Tcl
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set ::env(DESIGN_NAME) caravel_clocking
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set ::env(DESIGN_IS_CORE) 0
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set ::env(VERILOG_FILES) "\
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$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
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$::env(DESIGN_DIR)/../../verilog/rtl/clock_div.v\
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$::env(DESIGN_DIR)/../../verilog/rtl/caravel_clocking.v"
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set ::env(CLOCK_PORT) "ext_clk"
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set ::env(CLOCK_NET) "ext_clk core_clk pll_clk pll_clk90"
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set ::env(ROUTING_CORES) "6"
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set ::env(RUN_KLAYOUT) 0
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## Synthesis
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set ::env(SYNTH_STRATEGY) "DELAY 0"
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set ::env(CLOCK_TREE_SYNTH) 1
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set ::env(SYNTH_SIZING) 0
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set ::env(SYNTH_BUFFERING) 0
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set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
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set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
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set ::env(NO_SYNTH_CELL_LIST) $::env(DESIGN_DIR)/no_synth.list
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 100 100"
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# set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/caravel_clocking.def
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set ::env(FP_TAPCELL_DIST) 6
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set ::env(LEFT_MARGIN_MULT) 2
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set ::env(BOTTOM_MARGIN_MULT) 2
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set ::env(TOP_MARGIN_MULT) "2"
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set ::env(BOTTOM_MARGIN_MULT) "1"
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set ::env(DPL_CELL_PADDING) 2
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set ::env(GPL_CELL_PADDING) 4
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set ::env(DIODE_PADDING) 0
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## PDN
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set ::env(FP_PDN_HPITCH) 16.9
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set ::env(FP_PDN_VPITCH) 15.5
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set ::env(FP_PDN_HSPACING) 6.85
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set ::env(FP_PDN_VSPACING) 6.15
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set ::env(FP_PDN_HOFFSET) 5.73
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set ::env(FP_PDN_VOFFSET) 7.63
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# vertical 21.29 15.61
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.63
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
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# set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
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set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.25
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## Routing
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set ::env(GRT_ADJUSTMENT) 0
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) 4
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set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(SYNTH_MUX_MAP)
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set ::env(RSZ_DONT_TOUCH_RX) "core_clk|user_clk"
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set ::env(RSZ_USE_OLD_REMOVER) 1
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set ::env(FP_PDN_SKIP_TRIM) 1
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set ::env(CTS_MAX_CAP) 0.25
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#set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/drc_exclude.list
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set ::env(SYNTH_MAX_FANOUT) 12
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set ::env(FP_PDN_IRDROP) 0
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