riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/manifest

34 lines
2.3 KiB
Plaintext
Raw Normal View History

add manifest
2021-12-16 16:26:20 -06:00
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
Apply automatic changes to Manifest and README.rst
2022-09-28 14:39:43 -05:00
0e2cda74281c33da2f4e23d0ff5af91adcbcf32a verilog/rtl/caravan.v
Apply automatic changes to Manifest and README.rst
2021-12-24 10:48:26 -06:00
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v
add manifest
2021-12-16 16:26:20 -06:00
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
Corrected the issue reported on the github issue tracker (#34) (#50) * Corrected the issue reported on the github issue tracker (#34) in which the use of "clocking" as an instance name in caravel and caravan conflicts with the system verilog keyword of the same name. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-07 09:44:57 -05:00
cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v
add manifest
2021-12-16 16:26:20 -06:00
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v
Caravan top lvs (#67) * - update caravan configuration * change correct gpio_default blocks instance names * implement powerrouting work around * place spare logic blocks * keep the history of runs and sym link last/final one * - update caravan mag, def and gl views - add fake power routing cell in the rtl as a placeholder for openlane to prevent routing on that cell - fix some syntax errors in chip_io_alt - match simple_por lef pins with mag by regenerating it * Apply automatic changes to Manifest and README.rst * add caravan power routing lef * - update mag and def view of caravan - add_macro_placement for fake cell * Added back the power routing to Caravan, fixed DRC errors, ran LVS, corrected placement of isolated substrate regions, and replaced the signal routing for the analog lines. Be aware that merging with main may cause issues with the mgmt_protect.mag file and its subcells mprj2_logic_high.mag and mprj_logic_high.mag. It may be worth cherry-picking the files to merge and exclude those layouts. Co-authored-by: kareem <kareem.farid@efabless.com> Co-authored-by: kareefardi <kareefardi@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-04-14 17:05:16 -05:00
54de41c59139783d39654e1f0a86e2880cb7b076 verilog/rtl/chip_io_alt.v
add manifest
2021-12-16 16:26:20 -06:00
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
Apply automatic changes to Manifest and README.rst
2022-07-24 15:21:58 -05:00
60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v
add manifest
2021-12-16 16:26:20 -06:00
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
Apply automatic changes to Manifest and README.rst
2022-09-29 13:11:39 -05:00
8dafb824eae7173e43f4e2f31c7470a6a1272c79 verilog/rtl/housekeeping.v
add manifest
2021-12-16 16:26:20 -06:00
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
Apply automatic changes to Manifest and README.rst
2022-10-05 05:29:42 -05:00
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
add manifest
2021-12-16 16:26:20 -06:00
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
6f490c83d6064c380a3f475823ef97f325d7f6c1 verilog/rtl/pads.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
6f802b6ab7e6502160adfe41e313958b86d2c277 verilog/rtl/simple_por.v
1b1705d41992b318c791a5703e0d43d0bcda8f12 verilog/rtl/spare_logic_block.v
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
Modified the set_user_id.py script so that mode "-report" returns a valid value. (#93) * Modified the set_user_id.py script so that mode "-report" returns a valid value, instead of throwing an error, because the "info.yaml" file was removed without due consideration of the side effects. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-05-09 00:50:48 -05:00
c94f7ed5aa311f005513ace344991c8e6d3d19f5 scripts/set_user_id.py
add manifest
2021-12-16 16:26:20 -06:00
98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py
3210e724c6dc99563af780ff1778fada5b432604 scripts/compositor.py