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caravel/signoff/caravan/standalone_pvr/caravan.lvs.report

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add caravan signoff reports (LVS, DRC, and STA)
2022-10-31 12:58:57 -05:00
Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
Circuit 1 cell sky130_fd_pr__pfet_g5v0d10v5 and Circuit 2 cell sky130_fd_pr__pfet_g5v0d10v5 are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__pfet_g5v0d10v5 |Circuit 2: sky130_fd_pr__pfet_g5v0d10v5
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__pfet_g5v0d10v5 and sky130_fd_pr__pfet_g5v0d10v5 are equivalent.
Circuit 1 cell sky130_fd_pr__nfet_g5v0d10v5 and Circuit 2 cell sky130_fd_pr__nfet_g5v0d10v5 are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_g5v0d10v5 |Circuit 2: sky130_fd_pr__nfet_g5v0d10v5
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_g5v0d10v5 and sky130_fd_pr__nfet_g5v0d10v5 are equivalent.
Class sky130_fd_sc_hd__nand2_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__nand2_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2)
sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
A |A
VNB |VNB
B |B
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand2_2 and sky130_fd_sc_hd__nand2_2 are equivalent.
Class sky130_fd_sc_hd__inv_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__inv_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (2->1) |sky130_fd_pr__pfet_01v8_hvt (2->1)
sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
Y |Y
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent.
Class sky130_fd_sc_hd__nor2_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__nor2_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor2_2 |Circuit 2: sky130_fd_sc_hd__nor2_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2)
sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor2_2 |Circuit 2: sky130_fd_sc_hd__nor2_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
B |B
VGND |VGND
VNB |VNB
A |A
VPB |VPB
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor2_2 and sky130_fd_sc_hd__nor2_2 are equivalent.
Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB
Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB
Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB
Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
-------------------------------------------|-------------------------------------------
VGND |VGND
LO |LO
HI |HI
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
Circuit 1 cell sky130_fd_pr__esd_nfet_g5v0d10v5 and Circuit 2 cell sky130_fd_pr__esd_nfet_g5v0d10v5 are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__esd_nfet_g5v0d10v |Circuit 2: sky130_fd_pr__esd_nfet_g5v0d10v
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__esd_nfet_g5v0d10v5 and sky130_fd_pr__esd_nfet_g5v0d10v5 are equivalent.
Circuit 1 cell sky130_fd_pr__nfet_01v8_lvt and Circuit 2 cell sky130_fd_pr__nfet_01v8_lvt are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_01v8_lvt |Circuit 2: sky130_fd_pr__nfet_01v8_lvt
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8_lvt and sky130_fd_pr__nfet_01v8_lvt are equivalent.
Circuit 1 cell sky130_fd_pr__nfet_05v0_nvt and Circuit 2 cell sky130_fd_pr__nfet_05v0_nvt are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__nfet_05v0_nvt |Circuit 2: sky130_fd_pr__nfet_05v0_nvt
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_05v0_nvt and sky130_fd_pr__nfet_05v0_nvt are equivalent.
Circuit 1 cell sky130_fd_pr__pfet_01v8 and Circuit 2 cell sky130_fd_pr__pfet_01v8 are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
4 |4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent.
Class sky130_fd_sc_hd__buf_16 (0): Merged 40 parallel devices.
Class sky130_fd_sc_hd__buf_16 (1): Merged 40 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__buf_16 |Circuit 2: sky130_fd_sc_hd__buf_16
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (22->2) |sky130_fd_pr__nfet_01v8 (22->2)
sky130_fd_pr__pfet_01v8_hvt (22->2) |sky130_fd_pr__pfet_01v8_hvt (22->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_16 |Circuit 2: sky130_fd_sc_hd__buf_16
-------------------------------------------|-------------------------------------------
X |X
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__buf_16 and sky130_fd_sc_hd__buf_16 are equivalent.
Circuit 1 cell sky130_fd_pr__res_generic_nd and Circuit 2 cell sky130_fd_pr__res_generic_nd are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__res_generic_nd |Circuit 2: sky130_fd_pr__res_generic_nd
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__res_generic_nd and sky130_fd_pr__res_generic_nd are equivalent.
Circuit 1 cell sky130_fd_pr__res_generic_nd__hv and Circuit 2 cell sky130_fd_pr__res_generic_nd__hv are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__res_generic_nd__h |Circuit 2: sky130_fd_pr__res_generic_nd__h
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__res_generic_nd__hv and sky130_fd_pr__res_generic_nd__hv are equivalent.
Class QI_sky130_fd_sc_hd__ebufn_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__ebufn_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->4) |sky130_fd_pr__pfet_01v8_hvt (6->4)
sky130_fd_pr__nfet_01v8 (6->4) |sky130_fd_pr__nfet_01v8 (6->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__ebufn_2 |Circuit 2: sky130_fd_sc_hd__ebufn_2
-------------------------------------------|-------------------------------------------
VGND |VGND
TE_B |TE_B
VPWR |VPWR
VNB |VNB
VPB |VPB
Z |Z
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__ebufn_2 and sky130_fd_sc_hd__ebufn_2 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10) |sky130_fd_pr__pfet_01v8_hvt (10)
sky130_fd_pr__nfet_01v8 (10) |sky130_fd_pr__nfet_01v8 (10)
Number of devices: 20 |Number of devices: 20
Number of nets: 17 |Number of nets: 17
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__dlclkp_1 |Circuit 2: sky130_fd_sc_hd__dlclkp_1
-------------------------------------------|-------------------------------------------
VGND |VGND
CLK |CLK
VPB |VPB
VNB |VNB
VPWR |VPWR
GCLK |GCLK
GATE |GATE
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__dlclkp_1 and sky130_fd_sc_hd__dlclkp_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (9) |sky130_fd_pr__nfet_01v8 (9)
sky130_fd_pr__pfet_01v8_hvt (9) |sky130_fd_pr__pfet_01v8_hvt (9)
Number of devices: 18 |Number of devices: 18
Number of nets: 16 |Number of nets: 16
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__dlxtp_1 |Circuit 2: sky130_fd_sc_hd__dlxtp_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
D |D
Q |Q
GATE |GATE
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__dlxtp_1 and sky130_fd_sc_hd__dlxtp_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__inv_1 |Circuit 2: sky130_fd_sc_hd__inv_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
A |A
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__inv_1 and sky130_fd_sc_hd__inv_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
A |A
B |B
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (13) |sky130_fd_pr__pfet_01v8_hvt (13)
sky130_fd_pr__nfet_01v8 (13) |sky130_fd_pr__nfet_01v8 (13)
Number of devices: 26 |Number of devices: 26
Number of nets: 24 |Number of nets: 24
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__mux4_1 |Circuit 2: sky130_fd_sc_hd__mux4_1
-------------------------------------------|-------------------------------------------
S1 |S1
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
X |X
A1 |A1
A3 |A3
A0 |A0
A2 |A2
S0 |S0
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__mux4_1 and sky130_fd_sc_hd__mux4_1 are equivalent.
Class QI_sky130_fd_sc_hd__nor4b_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__nor4b_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (9->5) |sky130_fd_pr__pfet_01v8_hvt (9->5)
sky130_fd_pr__nfet_01v8 (9->5) |sky130_fd_pr__nfet_01v8 (9->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__nor4b_2 |Circuit 2: sky130_fd_sc_hd__nor4b_2
-------------------------------------------|-------------------------------------------
VPB |VPB
Y |Y
VGND |VGND
VNB |VNB
D_N |D_N
VPWR |VPWR
A |A
C |C
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__nor4b_2 and sky130_fd_sc_hd__nor4b_2 are equivalent.
Circuit 1 cell sky130_fd_pr__res_generic_pd__hv and Circuit 2 cell sky130_fd_pr__res_generic_pd__hv are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__res_generic_pd__h |Circuit 2: sky130_fd_pr__res_generic_pd__h
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__res_generic_pd__hv and sky130_fd_pr__res_generic_pd__hv are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__decap_12 |Circuit 2: sky130_fd_sc_hd__decap_12
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__decap_12 and sky130_fd_sc_hd__decap_12 are equivalent.
Cell sky130_fd_sc_hvl__conb_1 (0) disconnected node: VNB
Cell sky130_fd_sc_hvl__conb_1 (0) disconnected node: VPB
Cell sky130_fd_sc_hvl__conb_1 (1) disconnected node: VNB
Cell sky130_fd_sc_hvl__conb_1 (1) disconnected node: VPB
Subcircuit summary:
Circuit 1: sky130_fd_sc_hvl__conb_1 |Circuit 2: sky130_fd_sc_hvl__conb_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hvl__conb_1 |Circuit 2: sky130_fd_sc_hvl__conb_1
-------------------------------------------|-------------------------------------------
HI |HI
VPWR |VPWR
VGND |VGND
LO |LO
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hvl__conb_1 and sky130_fd_sc_hvl__conb_1 are equivalent.
Class sky130_fd_sc_hvl__lsbufhv2lv_1 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hvl__lsbufhv2lv_1 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1 |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (2) |sky130_fd_pr__pfet_g5v0d10v5 (2)
sky130_fd_pr__nfet_g5v0d10v5 (10->4) |sky130_fd_pr__nfet_g5v0d10v5 (10->4)
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 **Mismatch** |Number of nets: 11 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1 |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1
---------------------------------------------------------------------------------------
Net: a_30_1337# |Net: a_30_1337#
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__nfet_g5v0d10v5/2 = 2 | sky130_fd_pr__nfet_g5v0d10v5/2 = 2
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 | sky130_fd_pr__pfet_g5v0d10v5/2 = 1
|
Net: VGND_uq0 |Net: VGND
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 2 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
|
Net: VNB |Net: VNB
sky130_fd_pr__nfet_g5v0d10v5/4 = 4 | sky130_fd_pr__nfet_g5v0d10v5/4 = 4
sky130_fd_pr__nfet_01v8/4 = 1 | sky130_fd_pr__nfet_01v8/4 = 1
|
Net: a_30_207# |Net: a_30_207#
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__nfet_g5v0d10v5/2 = 1 | sky130_fd_pr__nfet_g5v0d10v5/2 = 1
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1
|
Net: a_389_1337# |Net: a_389_1337#
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__pfet_01v8_hvt/2 = 1 | sky130_fd_pr__pfet_01v8_hvt/2 = 1
sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1 | sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VPWR_uq0 |(no matching net)
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 |
|
Net: VPWR |(no matching net)
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: A |Net: A
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 | sky130_fd_pr__pfet_g5v0d10v5/2 = 1
sky130_fd_pr__nfet_g5v0d10v5/2 = 1 | sky130_fd_pr__nfet_g5v0d10v5/2 = 1
|
Net: VPB |Net: VPB
sky130_fd_pr__pfet_g5v0d10v5/4 = 2 | sky130_fd_pr__pfet_g5v0d10v5/4 = 2
|
Net: VGND |Net: VPWR
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 2 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 2
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1 |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__nfet_g5v0d10v5:1 |Instance: sky130_fd_pr__nfet_g5v0d10v5:11
(1,3) = (3,3) | (1,3) = (5,5)
2 = 5 | 2 = 2
4 = 5 | 4 = 5
|
Instance: sky130_fd_pr__nfet_g5v0d10v5:6 |Instance: sky130_fd_pr__nfet_g5v0d10v5:3
(1,3) = (5,2) | (1,3) = (5,3)
2 = 2 | 2 = 5
4 = 5 | 4 = 5
|
Instance: sky130_fd_pr__nfet_g5v0d10v5:4 |Instance: sky130_fd_pr__nfet_g5v0d10v5:0
(1,3) = (3,2) | (1,3) = (5,3)
2 = 5 | 2 = 5
4 = 5 | 4 = 5
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__pfet_g5v0d10v5:14 |Instance: sky130_fd_pr__pfet_g5v0d10v5:10
(1,3) = (3,1) | (1,3) = (5,2)
2 = 5 | 2 = 2
4 = 2 | 4 = 2
|
Instance: sky130_fd_pr__pfet_g5v0d10v5:0 |Instance: sky130_fd_pr__pfet_g5v0d10v5:1
(1,3) = (5,1) | (1,3) = (3,2)
2 = 2 | 2 = 5
4 = 2 | 4 = 2
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_fd_sc_hvl__lsbufhv2lv_1 sky130_fd_sc_hvl__lsbufhv2lv_1
Class sky130_fd_sc_hd__clkbuf_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__clkbuf_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
-------------------------------------------|-------------------------------------------
A |A
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
Class sky130_fd_sc_hd__clkbuf_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
X |X
VPB |VPB
A |A
VGND |VGND
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
Class sky130_fd_sc_hd__nor3b_2 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__nor3b_2 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor3b_2 |Circuit 2: sky130_fd_sc_hd__nor3b_2
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
A |A
B |B
C_N |C_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor3b_2 and sky130_fd_sc_hd__nor3b_2 are equivalent.
Class sky130_fd_sc_hd__and3b_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__and3b_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and3b_2 |Circuit 2: sky130_fd_sc_hd__and3b_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
C |C
X |X
B |B
A_N |A_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and3b_2 and sky130_fd_sc_hd__and3b_2 are equivalent.
Class sky130_fd_sc_hd__and3_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__and3_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and3_2 |Circuit 2: sky130_fd_sc_hd__and3_2
-------------------------------------------|-------------------------------------------
X |X
VGND |VGND
A |A
C |C
B |B
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and3_2 and sky130_fd_sc_hd__and3_2 are equivalent.
Class sky130_fd_sc_hd__clkbuf_16 (0): Merged 36 parallel devices.
Class sky130_fd_sc_hd__clkbuf_16 (1): Merged 36 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2)
sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
-------------------------------------------|-------------------------------------------
VPWR |VPWR
X |X
VPB |VPB
VGND |VGND
VNB |VNB
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1)
Number of devices: 1 |Number of devices: 1
Number of nets: 2 |Number of nets: 2
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
-------------------------------------------|-------------------------------------------
VNB |VNB
DIODE |DIODE
VGND |VGND
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (12) |sky130_fd_pr__nfet_01v8 (12)
sky130_fd_pr__pfet_01v8_hvt (12) |sky130_fd_pr__pfet_01v8_hvt (12)
Number of devices: 24 |Number of devices: 24
Number of nets: 18 |Number of nets: 18
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfxtp_1 |Circuit 2: sky130_fd_sc_hd__dfxtp_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VGND |VGND
VPWR |VPWR
D |D
Q |Q
CLK |CLK
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfxtp_1 and sky130_fd_sc_hd__dfxtp_1 are equivalent.
Class sky130_fd_sc_hd__and4bb_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__and4bb_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->7) |sky130_fd_pr__pfet_01v8_hvt (8->7)
sky130_fd_pr__nfet_01v8 (8->7) |sky130_fd_pr__nfet_01v8 (8->7)
Number of devices: 14 |Number of devices: 14
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and4bb_2 |Circuit 2: sky130_fd_sc_hd__and4bb_2
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
D |D
C |C
B_N |B_N
A_N |A_N
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and4bb_2 and sky130_fd_sc_hd__and4bb_2 are equivalent.
Class sky130_fd_sc_hd__and4b_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__and4b_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and4b_2 |Circuit 2: sky130_fd_sc_hd__and4b_2
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
D |D
A_N |A_N
C |C
B |B
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and4b_2 and sky130_fd_sc_hd__and4b_2 are equivalent.
Class sky130_fd_sc_hd__and4_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__and4_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and4_2 |Circuit 2: sky130_fd_sc_hd__and4_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
VGND |VGND
X |X
A |A
C |C
B |B
D |D
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and4_2 and sky130_fd_sc_hd__and4_2 are equivalent.
Class sky130_fd_sc_hd__and2b_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__and2b_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and2b_2 |Circuit 2: sky130_fd_sc_hd__and2b_2
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
B |B
A_N |A_N
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and2b_2 and sky130_fd_sc_hd__and2b_2 are equivalent.
Class sky130_fd_sc_hd__and2_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__and2_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3)
sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
X |X
A |A
B |B
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and2_2 and sky130_fd_sc_hd__and2_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
A0 |A0
A1 |A1
X |X
VPWR |VPWR
S |S
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__mux2_1 and sky130_fd_sc_hd__mux2_1 are equivalent.
Class sky130_fd_sc_hd__dfrtp_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__dfrtp_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfrtp_4 |Circuit 2: sky130_fd_sc_hd__dfrtp_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (17->14) |sky130_fd_pr__nfet_01v8 (17->14)
sky130_fd_pr__pfet_01v8_hvt (17->14) |sky130_fd_pr__pfet_01v8_hvt (17->14)
Number of devices: 28 |Number of devices: 28
Number of nets: 21 |Number of nets: 21
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfrtp_4 |Circuit 2: sky130_fd_sc_hd__dfrtp_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
RESET_B |RESET_B
VPB |VPB
VNB |VNB
VGND |VGND
D |D
Q |Q
CLK |CLK
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfrtp_4 and sky130_fd_sc_hd__dfrtp_4 are equivalent.
Class sky130_fd_sc_hd__nand2b_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__nand2b_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand2b_2 |Circuit 2: sky130_fd_sc_hd__nand2b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->3) |sky130_fd_pr__pfet_01v8_hvt (5->3)
sky130_fd_pr__nfet_01v8 (5->3) |sky130_fd_pr__nfet_01v8 (5->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand2b_2 |Circuit 2: sky130_fd_sc_hd__nand2b_2
-------------------------------------------|-------------------------------------------
B |B
VGND |VGND
A_N |A_N
VNB |VNB
VPWR |VPWR
Y |Y
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand2b_2 and sky130_fd_sc_hd__nand2b_2 are equivalent.
Class sky130_fd_sc_hd__dfbbn_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__dfbbn_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfbbn_2 |Circuit 2: sky130_fd_sc_hd__dfbbn_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (22->20) |sky130_fd_pr__nfet_01v8 (22->20)
sky130_fd_pr__pfet_01v8_hvt (22->20) |sky130_fd_pr__pfet_01v8_hvt (22->20)
Number of devices: 40 |Number of devices: 40
Number of nets: 29 |Number of nets: 29
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfbbn_2 |Circuit 2: sky130_fd_sc_hd__dfbbn_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
RESET_B |RESET_B
Q_N |Q_N
Q |Q
D |D
CLK_N |CLK_N
VPB |VPB
VNB |VNB
VGND |VGND
SET_B |SET_B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfbbn_2 and sky130_fd_sc_hd__dfbbn_2 are equivalent.
Class sky130_fd_sc_hd__mux2_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__mux2_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__mux2_4 |Circuit 2: sky130_fd_sc_hd__mux2_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (9->6) |sky130_fd_pr__pfet_01v8_hvt (9->6)
sky130_fd_pr__nfet_01v8 (9->6) |sky130_fd_pr__nfet_01v8 (9->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__mux2_4 |Circuit 2: sky130_fd_sc_hd__mux2_4
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
S |S
VNB |VNB
VPB |VPB
X |X
A0 |A0
A1 |A1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__mux2_4 and sky130_fd_sc_hd__mux2_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and2_0 |Circuit 2: sky130_fd_sc_hd__and2_0
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and2_0 |Circuit 2: sky130_fd_sc_hd__and2_0
-------------------------------------------|-------------------------------------------
B |B
VGND |VGND
A |A
X |X
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and2_0 and sky130_fd_sc_hd__and2_0 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1
-------------------------------------------|-------------------------------------------
A |A
X |X
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dlygate4sd3_1 and sky130_fd_sc_hd__dlygate4sd3_1 are equivalent.
Class sky130_fd_sc_hd__buf_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__buf_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
-------------------------------------------|-------------------------------------------
X |X
VGND |VGND
VNB |VNB
A |A
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__buf_2 and sky130_fd_sc_hd__buf_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__or2_0 |Circuit 2: sky130_fd_sc_hd__or2_0
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__or2_0 |Circuit 2: sky130_fd_sc_hd__or2_0
-------------------------------------------|-------------------------------------------
X |X
A |A
VPWR |VPWR
B |B
VGND |VGND
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__or2_0 and sky130_fd_sc_hd__or2_0 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__macro_sparecel |Circuit 2: sky130_fd_sc_hd__macro_sparecel
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__nand2_2 (2) |sky130_fd_sc_hd__nand2_2 (2)
sky130_fd_sc_hd__inv_2 (2) |sky130_fd_sc_hd__inv_2 (2)
sky130_fd_sc_hd__nor2_2 (2) |sky130_fd_sc_hd__nor2_2 (2)
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
Number of devices: 7 |Number of devices: 7
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_fd_sc_hd__macro_sparecel |Circuit 2: sky130_fd_sc_hd__macro_sparecel
---------------------------------------------------------------------------------------
Net: sky130_fd_sc_hd__conb_1_0/HI |Net: sky130_fd_sc_hd__conb_1_0/HI
sky130_fd_sc_hd__conb_1/HI = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VPWR |Net: VPWR
sky130_fd_sc_hd__nand2_2/VPWR = 2 | sky130_fd_sc_hd__nand2_2/Y = 2
sky130_fd_sc_hd__inv_2/VPWR = 2 | sky130_fd_sc_hd__inv_2/VPWR = 2
sky130_fd_sc_hd__nor2_2/VPWR = 2 | sky130_fd_sc_hd__nor2_2/Y = 2
sky130_fd_sc_hd__conb_1/VPWR = 1 | sky130_fd_sc_hd__conb_1/LO = 1
|
Net: VGND |Net: VGND
sky130_fd_sc_hd__nand2_2/VGND = 2 | sky130_fd_sc_hd__nand2_2/VPWR = 2
sky130_fd_sc_hd__inv_2/VGND = 2 | sky130_fd_sc_hd__inv_2/Y = 2
sky130_fd_sc_hd__nor2_2/VGND = 2 | sky130_fd_sc_hd__nor2_2/VPWR = 2
sky130_fd_sc_hd__conb_1/VGND = 1 | sky130_fd_sc_hd__conb_1/HI = 1
|
Net: VNB |Net: VNB
sky130_fd_sc_hd__nand2_2/VNB = 2 | sky130_fd_sc_hd__nand2_2/VPB = 2
sky130_fd_sc_hd__inv_2/VNB = 2 | sky130_fd_sc_hd__inv_2/VPB = 2
sky130_fd_sc_hd__nor2_2/VNB = 2 | sky130_fd_sc_hd__nor2_2/VPB = 2
sky130_fd_sc_hd__conb_1/VNB = 1 | sky130_fd_sc_hd__conb_1/VPWR = 1
|
Net: VPB |Net: VPB
sky130_fd_sc_hd__nand2_2/VPB = 2 | sky130_fd_sc_hd__nand2_2/VNB = 2
sky130_fd_sc_hd__inv_2/VPB = 2 | sky130_fd_sc_hd__inv_2/VNB = 2
sky130_fd_sc_hd__nor2_2/VPB = 2 | sky130_fd_sc_hd__nor2_2/VNB = 2
sky130_fd_sc_hd__conb_1/VPB = 1 | sky130_fd_sc_hd__conb_1/VPB = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: LO |Net: LO
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_fd_sc_hd__macro_sparecel |Circuit 2: sky130_fd_sc_hd__macro_sparecel
---------------------------------------------------------------------------------------
Instance: sky130_fd_sc_hd__conb_1_0 |Instance: sky130_fd_sc_hd__conb_1_0
LO = 5 | LO = 7
HI = 1 | HI = 7
VPB = 7 | VPB = 7
VNB = 7 | VNB = 1
VGND = 7 | VGND = 5
VPWR = 7 | VPWR = 7
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_fd_sc_hd__macro_sparecell sky130_fd_sc_hd__macro_sparecell
Class gpio_logic_high (0): Merged 14 parallel devices.
Class gpio_logic_high (1): Merged 14 parallel devices.
Subcircuit summary:
Circuit 1: gpio_logic_high |Circuit 2: gpio_logic_high
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_6 (1) |sky130_fd_sc_hd__decap_6 (1)
sky130_fd_sc_hd__decap_8 (1) |sky130_fd_sc_hd__decap_8 (1)
sky130_fd_sc_hd__decap_3 (13->1) |sky130_fd_sc_hd__decap_3 (13->1)
sky130_fd_sc_hd__decap_4 (3->1) |sky130_fd_sc_hd__decap_4 (3->1)
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
Number of devices: 5 |Number of devices: 5
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: gpio_logic_high |Circuit 2: gpio_logic_high
-------------------------------------------|-------------------------------------------
gpio_logic1 |gpio_logic1
vssd1 |vssd1
vccd1 |vccd1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes gpio_logic_high and gpio_logic_high are equivalent.
Class sky130_fd_sc_hd__o21ai_4 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__o21ai_4 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21ai_4 |Circuit 2: sky130_fd_sc_hd__o21ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21ai_4 |Circuit 2: sky130_fd_sc_hd__o21ai_4
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
A2 |A2
VGND |VGND
A1 |A1
B1 |B1
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21ai_4 and sky130_fd_sc_hd__o21ai_4 are equivalent.
Class sky130_fd_sc_hd__o21ai_2 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__o21ai_2 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21ai_2 |Circuit 2: sky130_fd_sc_hd__o21ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21ai_2 |Circuit 2: sky130_fd_sc_hd__o21ai_2
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
A2 |A2
VGND |VGND
VPWR |VPWR
B1 |B1
A1 |A1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21ai_2 and sky130_fd_sc_hd__o21ai_2 are equivalent.
Class sky130_fd_sc_hd__dfrtp_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__dfrtp_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfrtp_2 |Circuit 2: sky130_fd_sc_hd__dfrtp_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (15->14) |sky130_fd_pr__nfet_01v8 (15->14)
sky130_fd_pr__pfet_01v8_hvt (15->14) |sky130_fd_pr__pfet_01v8_hvt (15->14)
Number of devices: 28 |Number of devices: 28
Number of nets: 21 |Number of nets: 21
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfrtp_2 |Circuit 2: sky130_fd_sc_hd__dfrtp_2
-------------------------------------------|-------------------------------------------
RESET_B |RESET_B
VPWR |VPWR
VPB |VPB
VNB |VNB
VGND |VGND
Q |Q
D |D
CLK |CLK
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfrtp_2 and sky130_fd_sc_hd__dfrtp_2 are equivalent.
Class sky130_fd_sc_hd__xnor2_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__xnor2_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__xnor2_2 |Circuit 2: sky130_fd_sc_hd__xnor2_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__xnor2_2 |Circuit 2: sky130_fd_sc_hd__xnor2_2
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VPWR |VPWR
B |B
A |A
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__xnor2_2 and sky130_fd_sc_hd__xnor2_2 are equivalent.
Class sky130_fd_sc_hd__a211o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a211o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a211o_2 |Circuit 2: sky130_fd_sc_hd__a211o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a211o_2 |Circuit 2: sky130_fd_sc_hd__a211o_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
A1 |A1
B1 |B1
C1 |C1
X |X
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a211o_2 and sky130_fd_sc_hd__a211o_2 are equivalent.
Class sky130_fd_sc_hd__clkinv_1 (0): Merged 1 parallel devices.
Class sky130_fd_sc_hd__clkinv_1 (1): Merged 1 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkinv_1 |Circuit 2: sky130_fd_sc_hd__clkinv_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (2->1) |sky130_fd_pr__pfet_01v8_hvt (2->1)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkinv_1 |Circuit 2: sky130_fd_sc_hd__clkinv_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
Y |Y
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkinv_1 and sky130_fd_sc_hd__clkinv_1 are equivalent.
Class sky130_fd_sc_hd__o21a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o21a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21a_2 |Circuit 2: sky130_fd_sc_hd__o21a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21a_2 |Circuit 2: sky130_fd_sc_hd__o21a_2
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
A2 |A2
X |X
A1 |A1
B1 |B1
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21a_2 and sky130_fd_sc_hd__o21a_2 are equivalent.
Class sky130_fd_sc_hd__einvp_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__einvp_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__einvp_2 |Circuit 2: sky130_fd_sc_hd__einvp_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->3) |sky130_fd_pr__pfet_01v8_hvt (5->3)
sky130_fd_pr__nfet_01v8 (5->3) |sky130_fd_pr__nfet_01v8 (5->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__einvp_2 |Circuit 2: sky130_fd_sc_hd__einvp_2
-------------------------------------------|-------------------------------------------
VPB |VPB
TE |TE
VNB |VNB
VPWR |VPWR
VGND |VGND
A |A
Z |Z
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__einvp_2 and sky130_fd_sc_hd__einvp_2 are equivalent.
Class sky130_fd_sc_hd__einvn_8 (0): Merged 28 parallel devices.
Class sky130_fd_sc_hd__einvn_8 (1): Merged 28 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__einvn_8 |Circuit 2: sky130_fd_sc_hd__einvn_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (17->3) |sky130_fd_pr__pfet_01v8_hvt (17->3)
sky130_fd_pr__nfet_01v8 (17->3) |sky130_fd_pr__nfet_01v8 (17->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__einvn_8 |Circuit 2: sky130_fd_sc_hd__einvn_8
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
TE_B |TE_B
VGND |VGND
Z |Z
A |A
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__einvn_8 and sky130_fd_sc_hd__einvn_8 are equivalent.
Class sky130_fd_sc_hd__o2111a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o2111a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o2111a_2 |Circuit 2: sky130_fd_sc_hd__o2111a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o2111a_2 |Circuit 2: sky130_fd_sc_hd__o2111a_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
C1 |C1
X |X
B1 |B1
A2 |A2
A1 |A1
D1 |D1
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o2111a_2 and sky130_fd_sc_hd__o2111a_2 are equivalent.
Class sky130_fd_sc_hd__mux2_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__mux2_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__mux2_2 |Circuit 2: sky130_fd_sc_hd__mux2_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__mux2_2 |Circuit 2: sky130_fd_sc_hd__mux2_2
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
A1 |A1
A0 |A0
X |X
VGND |VGND
VPWR |VPWR
S |S
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__mux2_2 and sky130_fd_sc_hd__mux2_2 are equivalent.
Class sky130_fd_sc_hd__a21o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a21o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21o_2 |Circuit 2: sky130_fd_sc_hd__a21o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->4) |sky130_fd_pr__pfet_01v8_hvt (5->4)
sky130_fd_pr__nfet_01v8 (5->4) |sky130_fd_pr__nfet_01v8 (5->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21o_2 |Circuit 2: sky130_fd_sc_hd__a21o_2
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
A1 |A1
X |X
B1 |B1
A2 |A2
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21o_2 and sky130_fd_sc_hd__a21o_2 are equivalent.
Class sky130_fd_sc_hd__einvn_4 (0): Merged 12 parallel devices.
Class sky130_fd_sc_hd__einvn_4 (1): Merged 12 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__einvn_4 |Circuit 2: sky130_fd_sc_hd__einvn_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (9->3) |sky130_fd_pr__nfet_01v8 (9->3)
sky130_fd_pr__pfet_01v8_hvt (9->3) |sky130_fd_pr__pfet_01v8_hvt (9->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__einvn_4 |Circuit 2: sky130_fd_sc_hd__einvn_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
TE_B |TE_B
Z |Z
A |A
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__einvn_4 and sky130_fd_sc_hd__einvn_4 are equivalent.
Class sky130_fd_sc_hd__o31a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o31a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o31a_2 |Circuit 2: sky130_fd_sc_hd__o31a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o31a_2 |Circuit 2: sky130_fd_sc_hd__o31a_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
A3 |A3
X |X
B1 |B1
A1 |A1
A2 |A2
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o31a_2 and sky130_fd_sc_hd__o31a_2 are equivalent.
Class sky130_fd_sc_hd__o211a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o211a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o211a_2 |Circuit 2: sky130_fd_sc_hd__o211a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o211a_2 |Circuit 2: sky130_fd_sc_hd__o211a_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VPB |VPB
VNB |VNB
VPWR |VPWR
B1 |B1
C1 |C1
X |X
A2 |A2
A1 |A1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o211a_2 and sky130_fd_sc_hd__o211a_2 are equivalent.
Class sky130_fd_sc_hd__o22a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o22a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o22a_2 |Circuit 2: sky130_fd_sc_hd__o22a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o22a_2 |Circuit 2: sky130_fd_sc_hd__o22a_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
X |X
B2 |B2
B1 |B1
A2 |A2
A1 |A1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o22a_2 and sky130_fd_sc_hd__o22a_2 are equivalent.
Class sky130_fd_sc_hd__nand3b_2 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__nand3b_2 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand3b_2 |Circuit 2: sky130_fd_sc_hd__nand3b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand3b_2 |Circuit 2: sky130_fd_sc_hd__nand3b_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
Y |Y
VPB |VPB
VNB |VNB
C |C
B |B
VGND |VGND
A_N |A_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand3b_2 and sky130_fd_sc_hd__nand3b_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
-------------------------------------------|-------------------------------------------
VGND |VGND
A |A
VNB |VNB
X |X
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkbuf_1 and sky130_fd_sc_hd__clkbuf_1 are equivalent.
Class sky130_fd_sc_hd__nand4b_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__nand4b_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand4b_2 |Circuit 2: sky130_fd_sc_hd__nand4b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (9->5) |sky130_fd_pr__nfet_01v8 (9->5)
sky130_fd_pr__pfet_01v8_hvt (9->5) |sky130_fd_pr__pfet_01v8_hvt (9->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand4b_2 |Circuit 2: sky130_fd_sc_hd__nand4b_2
-------------------------------------------|-------------------------------------------
C |C
D |D
B |B
A_N |A_N
VGND |VGND
VPWR |VPWR
Y |Y
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand4b_2 and sky130_fd_sc_hd__nand4b_2 are equivalent.
Class sky130_fd_sc_hd__nand3_2 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__nand3_2 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand3_2 |Circuit 2: sky130_fd_sc_hd__nand3_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand3_2 |Circuit 2: sky130_fd_sc_hd__nand3_2
-------------------------------------------|-------------------------------------------
Y |Y
VNB |VNB
VPWR |VPWR
VPB |VPB
C |C
B |B
A |A
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand3_2 and sky130_fd_sc_hd__nand3_2 are equivalent.
Class sky130_fd_sc_hd__a22o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a22o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a22o_2 |Circuit 2: sky130_fd_sc_hd__a22o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a22o_2 |Circuit 2: sky130_fd_sc_hd__a22o_2
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
X |X
A2 |A2
B1 |B1
A1 |A1
B2 |B2
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a22o_2 and sky130_fd_sc_hd__a22o_2 are equivalent.
Class sky130_fd_sc_hd__xor2_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__xor2_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__xor2_2 |Circuit 2: sky130_fd_sc_hd__xor2_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__xor2_2 |Circuit 2: sky130_fd_sc_hd__xor2_2
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VPWR |VPWR
X |X
A |A
B |B
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__xor2_2 and sky130_fd_sc_hd__xor2_2 are equivalent.
Class sky130_fd_sc_hd__a21boi_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__a21boi_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21boi_2 |Circuit 2: sky130_fd_sc_hd__a21boi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21boi_2 |Circuit 2: sky130_fd_sc_hd__a21boi_2
-------------------------------------------|-------------------------------------------
B1_N |B1_N
VPWR |VPWR
A1 |A1
A2 |A2
VNB |VNB
Y |Y
VGND |VGND
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21boi_2 and sky130_fd_sc_hd__a21boi_2 are equivalent.
Class sky130_fd_sc_hd__a32o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a32o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a32o_2 |Circuit 2: sky130_fd_sc_hd__a32o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a32o_2 |Circuit 2: sky130_fd_sc_hd__a32o_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
A2 |A2
B2 |B2
A1 |A1
B1 |B1
A3 |A3
X |X
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a32o_2 and sky130_fd_sc_hd__a32o_2 are equivalent.
Class sky130_fd_sc_hd__o2bb2a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o2bb2a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o2bb2a_2 |Circuit 2: sky130_fd_sc_hd__o2bb2a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o2bb2a_2 |Circuit 2: sky130_fd_sc_hd__o2bb2a_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
VGND |VGND
A1_N |A1_N
A2_N |A2_N
X |X
B2 |B2
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o2bb2a_2 and sky130_fd_sc_hd__o2bb2a_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__einvp_1 |Circuit 2: sky130_fd_sc_hd__einvp_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__einvp_1 |Circuit 2: sky130_fd_sc_hd__einvp_1
-------------------------------------------|-------------------------------------------
VPB |VPB
TE |TE
VNB |VNB
A |A
Z |Z
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__einvp_1 and sky130_fd_sc_hd__einvp_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_ef_sc_hd__decap_12 and sky130_ef_sc_hd__decap_12 are equivalent.
Class sky130_fd_sc_hd__a21oi_2 (0): Merged 4 parallel devices.
Class sky130_fd_sc_hd__a21oi_2 (1): Merged 4 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21oi_2 |Circuit 2: sky130_fd_sc_hd__a21oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21oi_2 |Circuit 2: sky130_fd_sc_hd__a21oi_2
-------------------------------------------|-------------------------------------------
Y |Y
VNB |VNB
VPWR |VPWR
B1 |B1
VGND |VGND
A2 |A2
A1 |A1
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21oi_2 and sky130_fd_sc_hd__a21oi_2 are equivalent.
Class sky130_fd_sc_hd__o221a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o221a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o221a_2 |Circuit 2: sky130_fd_sc_hd__o221a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o221a_2 |Circuit 2: sky130_fd_sc_hd__o221a_2
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
C1 |C1
A2 |A2
B2 |B2
B1 |B1
A1 |A1
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o221a_2 and sky130_fd_sc_hd__o221a_2 are equivalent.
Class sky130_fd_sc_hd__o21ba_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o21ba_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21ba_2 |Circuit 2: sky130_fd_sc_hd__o21ba_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21ba_2 |Circuit 2: sky130_fd_sc_hd__o21ba_2
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
X |X
A2 |A2
A1 |A1
B1_N |B1_N
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21ba_2 and sky130_fd_sc_hd__o21ba_2 are equivalent.
Class sky130_fd_sc_hd__o32a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o32a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o32a_2 |Circuit 2: sky130_fd_sc_hd__o32a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o32a_2 |Circuit 2: sky130_fd_sc_hd__o32a_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
A3 |A3
B2 |B2
B1 |B1
A1 |A1
X |X
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o32a_2 and sky130_fd_sc_hd__o32a_2 are equivalent.
Class sky130_fd_sc_hd__a31o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a31o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a31o_2 |Circuit 2: sky130_fd_sc_hd__a31o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a31o_2 |Circuit 2: sky130_fd_sc_hd__a31o_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
A2 |A2
A1 |A1
B1 |B1
A3 |A3
X |X
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a31o_2 and sky130_fd_sc_hd__a31o_2 are equivalent.
Class sky130_fd_sc_hd__clkinv_2 (0): Merged 3 parallel devices.
Class sky130_fd_sc_hd__clkinv_2 (1): Merged 3 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkinv_2 |Circuit 2: sky130_fd_sc_hd__clkinv_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1)
sky130_fd_pr__pfet_01v8_hvt (3->1) |sky130_fd_pr__pfet_01v8_hvt (3->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkinv_2 |Circuit 2: sky130_fd_sc_hd__clkinv_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
Y |Y
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkinv_2 and sky130_fd_sc_hd__clkinv_2 are equivalent.
Class sky130_fd_sc_hd__clkinv_8 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__clkinv_8 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (8->1) |sky130_fd_pr__nfet_01v8 (8->1)
sky130_fd_pr__pfet_01v8_hvt (12->1) |sky130_fd_pr__pfet_01v8_hvt (12->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
Y |Y
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkinv_8 and sky130_fd_sc_hd__clkinv_8 are equivalent.
Class sky130_fd_sc_hd__or2_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__or2_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__or2_2 |Circuit 2: sky130_fd_sc_hd__or2_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3)
sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__or2_2 |Circuit 2: sky130_fd_sc_hd__or2_2
-------------------------------------------|-------------------------------------------
VPB |VPB
VGND |VGND
VNB |VNB
B |B
X |X
VPWR |VPWR
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__or2_2 and sky130_fd_sc_hd__or2_2 are equivalent.
Class sky130_fd_sc_hd__nand4_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__nand4_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand4_2 |Circuit 2: sky130_fd_sc_hd__nand4_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand4_2 |Circuit 2: sky130_fd_sc_hd__nand4_2
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
B |B
C |C
A |A
D |D
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand4_2 and sky130_fd_sc_hd__nand4_2 are equivalent.
Flattening unmatched subcell sky130_ef_io__gpiov2_pad in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__top_gpiov2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_switch in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__res75only_small in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(18 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_ctl_logic in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_drvr in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amx_pucsd_inv in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_drvr_lshv2hv in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amx_inv4 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(6 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amx_pdcsd_inv in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__amx_inv1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_drvr_ls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(6 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_decoder in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__nor2_1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__nand2_1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_nor in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_nand5 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_nand4 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_nand2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__xor2_1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__inv_1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(15 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_ls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_ls_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_ctl_lshv2hv in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_ctl_inv_1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_amux_ctl_ls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_opath in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_odrvr in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_odrvr_sub in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_pddrvr_strong in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em2s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(7 instances)
Flattening unmatched subcell sky130_fd_io__tk_em2o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(14 instances)
Flattening unmatched subcell sky130_fd_io__tk_tie_r_out_esd in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pddrvr_unit_2_5 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(28 instances)
Flattening unmatched subcell sky130_fd_io__gpio_pudrvr_strong in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em2s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__tk_em2o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(10 instances)
Flattening unmatched subcell sky130_fd_io__tk_tie_r_out_esd in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpio_pudrvr_unit_2_5 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(28 instances)
Flattening unmatched subcell sky130_fd_io__com_pudrvr_weak in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpio_pddrvr_weak in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpio_pddrvr_strong_slow in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pudrvr_strong_slow in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_res_strong_slow in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_res_weak in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__res250only_small in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pad in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_octl_dat in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_opath_datoe in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpio_dat_ls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__com_cclat in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_cclat_hvnor3 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_cclat_hvnand3 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_cclat_inv_in in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__com_cclat_inv_out in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_octl in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_nor in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_xor in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_nand2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(8 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__com_ctl_ls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_obpredrvr in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_pupredrvr_strong in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_pupredrvr_strong_nd2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_opti in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_opto in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__com_inv_x1_dnw in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pupredrvr_nbias in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_opto in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__com_nand2_dnw in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_pdpredrvr_strong in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_nand2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_octl_mux in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_pdpredrvr_strong_nr2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_pdpredrvr_strong_nr3 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_opto in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_opti in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_inv_x1_dnw in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pdpredrvr_pbias in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_opto in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__com_nor2_dnw in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pupredrvr_weak in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pdpredrvr_weak in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pupredrvr_strong_slow in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pdpredrvr_strong_slow in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_ctl in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_nor in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_ctl_hld in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_ctl_ls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_nor in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x4 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_nand2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x8 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_ctl_lsbank in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_opti in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(10 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(10 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(10 instances)
Flattening unmatched subcell sky130_fd_io__tk_optiB in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em2o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em2s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_optiA in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em2s in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_ctl_ls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(6 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_ipath in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_ibuf_se in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_nand2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_inbuf_lvinv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__gpiov2_ipath_lvls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_ipath_hvls in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_vcchib_in_buf in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_in_buf in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_nor in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpiov2_ictl_logic in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_nor in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_nand2 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(3 instances)
Flattening unmatched subcell sky130_fd_io__gpio_ovtv2_buf_localesd in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__res250only_small in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__signal_5_sym_hv_local_5term in circuit sky130_ef_io__gpiov2_pad_wrapped (1)(2 instances)
Cell sky130_ef_io__gpiov2_pad_wrapped (0) disconnected node: m3_516_11741#
Class sky130_ef_io__gpiov2_pad_wrapped (0): Merged 903 parallel devices.
Class sky130_ef_io__gpiov2_pad_wrapped (0): Merged 58 series devices.
Class sky130_ef_io__gpiov2_pad_wrapped (0): Merged 1 parallel devices.
Class sky130_ef_io__gpiov2_pad_wrapped (1): Merged 98 parallel devices.
Class sky130_ef_io__gpiov2_pad_wrapped (1): Merged 58 series devices.
Class sky130_ef_io__gpiov2_pad_wrapped (1): Merged 1 parallel devices.
Cell sky130_ef_io__gpiov2_pad_wrapped (0) disconnected node: m3_516_11741#
Subcircuit summary:
Circuit 1: sky130_ef_io__gpiov2_pad_wrappe |Circuit 2: sky130_ef_io__gpiov2_pad_wrappe
-------------------------------------------|-------------------------------------------
sky130_fd_pr__esd_nfet_g5v0d10v5 (2) |sky130_fd_pr__esd_nfet_g5v0d10v5 (2)
sky130_fd_pr__res_generic_m1 (135->77) |sky130_fd_pr__res_generic_m1 (127->73) **M
sky130_fd_pr__pfet_g5v0d10v5 (686->324) |sky130_fd_pr__pfet_g5v0d10v5 (686->324)
sky130_fd_pr__nfet_g5v0d10v5 (686->419) |sky130_fd_pr__nfet_g5v0d10v5 (686->419)
sky130_fd_pr__nfet_01v8 (84->71) |sky130_fd_pr__nfet_01v8 (84->71)
sky130_fd_pr__nfet_01v8_lvt (128->34) |sky130_fd_pr__nfet_01v8_lvt (128->34)
sky130_fd_pr__nfet_05v0_nvt (128->34) |sky130_fd_pr__nfet_05v0_nvt (128->34)
sky130_fd_pr__res_generic_m2 (78->34) |sky130_fd_pr__res_generic_m2 (78->34)
sky130_fd_pr__res_generic_po (45->31) |sky130_fd_pr__res_generic_po (37->29) **Mi
sky130_fd_pr__pfet_01v8_hvt (60) |sky130_fd_pr__pfet_01v8_hvt (60)
sky130_fd_pr__pfet_01v8 (25->15) |sky130_fd_pr__pfet_01v8 (25->15)
sky130_fd_pr__res_generic_m3 (2->1) |sky130_fd_pr__res_generic_m3 (2->1)
sky130_fd_pr__res_generic_l1 (8->3) |(no matching element)
sky130_fd_pr__res_generic_m4 (1) |sky130_fd_pr__res_generic_m4 (1)
Number of devices: 1106 **Mismatch** |Number of devices: 1097 **Mismatch**
Number of nets: 629 **Mismatch** |Number of nets: 626 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_ef_io__gpiov2_pad_wrappe |Circuit 2: sky130_ef_io__gpiov2_pad_wrappe
---------------------------------------------------------------------------------------
Net: a_672_39874# |Net: sky130_ef_io__gpiov2_pad:gpiov2_ef_q0
sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) = | sky130_fd_pr__res_generic_m1/(end_a|end_
sky130_fd_pr__nfet_g5v0d10v5/2 = 4 |
sky130_fd_pr__pfet_g5v0d10v5/2 = 3 |
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 |
sky130_fd_pr__res_generic_l1/(end_a|end_ |
sky130_fd_pr__res_generic_po/(end_a|end_ |
sky130_fd_pr__res_generic_m1/(end_a|end_ |
|
Net: m1_2356_40665# |Net: sky130_ef_io__gpiov2_pad:gpiov2_ef_q0
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
| sky130_fd_pr__res_generic_m1/(end_a|end_
|
Net: m1_7332_7862# |Net: sky130_ef_io__gpiov2_pad:gpiov2_ef_q0
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__nfet_g5v0d10v5/2 = 4
| sky130_fd_pr__pfet_g5v0d10v5/2 = 3
| sky130_fd_pr__res_generic_po/(end_a|end_
| sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) =
| sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
|
Net: PAD |Net: PAD
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 10 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 10
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 7 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 7
sky130_fd_pr__res_generic_m4/(end_a|end_ | sky130_fd_pr__res_generic_m4/(end_a|end_
sky130_fd_pr__res_generic_m3/(end_a|end_ | sky130_fd_pr__res_generic_m3/(end_a|end_
sky130_fd_pr__res_generic_l1/(end_a|end_ |
sky130_fd_pr__res_generic_m1/(end_a|end_ |
|
Net: VDDIO_Q |Net: VDDIO_Q
sky130_fd_pr__pfet_g5v0d10v5/4 = 106 | sky130_fd_pr__pfet_g5v0d10v5/4 = 106
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 92 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 92
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 | sky130_fd_pr__pfet_g5v0d10v5/2 = 1
sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) = | sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) =
sky130_fd_pr__res_generic_m1/(end_a|end_ |
|
Net: VDDIO |Net: VDDIO
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 9 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 115
sky130_fd_pr__pfet_g5v0d10v5/4 = 9 | sky130_fd_pr__pfet_g5v0d10v5/4 = 152
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
| sky130_fd_pr__pfet_g5v0d10v5/2 = 1
| sky130_fd_pr__nfet_g5v0d10v5/2 = 2
| sky130_fd_pr__res_generic_m1/(end_a|end_
|
Net: VSSIO |Net: VSSIO
sky130_fd_pr__nfet_g5v0d10v5/4 = 69 | sky130_fd_pr__nfet_g5v0d10v5/4 = 81
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 47 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 59
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__res_generic_m1/(end_a|end_
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 | sky130_fd_pr__pfet_g5v0d10v5/2 = 1
| sky130_fd_pr__res_generic_po/(end_a|end_
|
Net: a_11731_29281# |(no matching net)
sky130_fd_pr__res_generic_po/(end_a|end_ |
sky130_fd_pr__res_generic_l1/(end_a|end_ |
sky130_fd_pr__res_generic_m1/(end_a|end_ |
|
Net: dw_1000_5756# |(no matching net)
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 106 |
sky130_fd_pr__pfet_g5v0d10v5/4 = 143 |
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 |
sky130_fd_pr__nfet_g5v0d10v5/2 = 2 |
sky130_fd_pr__res_generic_m1/(end_a|end_ |
|
Net: w_1277_31531# |(no matching net)
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 12 |
sky130_fd_pr__nfet_g5v0d10v5/4 = 12 |
sky130_fd_pr__res_generic_po/(end_a|end_ |
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_ef_io__gpiov2_pad_wrappe |Circuit 2: sky130_ef_io__gpiov2_pad_wrappe
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__res_generic_m1:9 |Instance: sky130_ef_io__gpiov2_pad:gpiov2_
(end_a,end_b) = (201,1) | (end_a,end_b) = (145,1)
|
Instance: sky130_fd_pr__res_generic_m1:67 |Instance: sky130_ef_io__gpiov2_pad:gpiov2_
(end_a,end_b) = (120,1) | (end_a,end_b) = (31,31)
|
Instance: sky130_fd_pr__res_generic_m1:132 |Instance: sky130_ef_io__gpiov2_pad:gpiov2_
(end_a,end_b) = (10,10) | (end_a,end_b) = (31,4)
|
Instance: sky130_fd_pr__res_generic_m1:176 |Instance: sky130_ef_io__gpiov2_pad:gpiov2_
(end_a,end_b) = (35,35) | (end_a,end_b) = (31,11)
|
Instance: sky130_fd_pr__res_generic_m1:198 |(no matching instance)
(end_a,end_b) = (17,17) |
|
|
Instance: sky130_fd_pr__res_generic_po:29 |(no matching instance)
(end_a,end_b) = (35,35) |
|
|
Instance: sky130_fd_pr__res_generic_po:34 |(no matching instance)
(end_a,end_b) = (10,10) |
|
|
Instance: sky130_fd_pr__res_generic_po:95 |(no matching instance)
(end_a,end_b) = (35,10) |
|
|
Instance: sky130_fd_pr__res_generic_po:127 |(no matching instance)
(end_a,end_b) = (35,17) |
|
|
Instance: sky130_fd_pr__res_generic_po:197 |(no matching instance)
(end_a,end_b) = (17,17) |
|
|
Instance: sky130_fd_pr__res_generic_l1:80 |(no matching instance)
(end_a,end_b) = (10,10) |
|
|
Instance: sky130_fd_pr__res_generic_l1:110 |(no matching instance)
(end_a,end_b) = (17,17) |
|
|
Instance: sky130_fd_pr__res_generic_l1:136 |(no matching instance)
(end_a,end_b) = (35,35) |
|
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_ef_io__gpiov2_pad_wrapped sky130_ef_io__gpiov2_pad_wrapped
Flattening unmatched subcell sky130_fd_io__top_power_lvc_wpad in circuit sky130_ef_io__vccd_lvc_clamped_pad (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gnd2gnd_120x2_lv_isosub in circuit sky130_ef_io__vccd_lvc_clamped_pad (1)(1 instance)
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDIO_uq0
Class sky130_ef_io__vccd_lvc_clamped_pad (0): Merged 458 parallel devices.
Class sky130_ef_io__vccd_lvc_clamped_pad (0): Merged 3 series devices.
Class sky130_ef_io__vccd_lvc_clamped_pad (1): Merged 4 parallel devices.
Class sky130_ef_io__vccd_lvc_clamped_pad (1): Merged 3 series devices.
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vccd_lvc_clamped_pad (0) disconnected node: VDDIO_uq0
Subcircuit summary:
Circuit 1: sky130_ef_io__vccd_lvc_clamped_ |Circuit 2: sky130_ef_io__vccd_lvc_clamped_
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (413->6) |sky130_fd_pr__nfet_01v8 (413->6)
sky130_fd_pr__pfet_01v8 (40->2) |sky130_fd_pr__pfet_01v8 (40->2)
sky130_fd_pr__diode_pw2nd_05v5 (10->3) |(no matching element)
sky130_fd_pr__diode_pd2nw_05v5 (8->2) |sky130_fd_pr__diode_pd2nw_05v5 (2)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (5->2) |sky130_fd_pr__res_generic_po (5->2)
Number of devices: 16 **Mismatch** |Number of devices: 13 **Mismatch**
Number of nets: 10 **Mismatch** |Number of nets: 9 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_ef_io__vccd_lvc_clamped_ |Circuit 2: sky130_ef_io__vccd_lvc_clamped_
---------------------------------------------------------------------------------------
Net: VSSIO |Net: VSSD
sky130_fd_pr__nfet_01v8/(1|3) = 4 | sky130_fd_pr__nfet_01v8/(1|3) = 4
sky130_fd_pr__nfet_01v8/4 = 3 | sky130_fd_pr__nfet_01v8/4 = 3
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 |
|
Net: VSSA_uq2 |(no matching net)
sky130_fd_pr__diode_pd2nw_05v5/cathode = |
sky130_fd_pr__diode_pw2nd_05v5/cathode = |
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 |
sky130_fd_pr__diode_pw2nd_05v5/anode = 1 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: w_7483_429# |Net: VSSA
sky130_fd_pr__diode_pw2nd_05v5/cathode = | sky130_fd_pr__diode_pd2nw_05v5/anode = 1
sky130_fd_pr__diode_pd2nw_05v5/cathode = | sky130_fd_pr__diode_pd2nw_05v5/cathode =
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSD |Net: VSSIO
sky130_fd_pr__nfet_01v8/(1|3) = 4 | sky130_fd_pr__nfet_01v8/(1|3) = 4
sky130_fd_pr__nfet_01v8/4 = 3 | sky130_fd_pr__nfet_01v8/4 = 3
sky130_fd_pr__diode_pw2nd_05v5/anode = 2 | sky130_fd_pr__diode_pd2nw_05v5/anode = 1
| sky130_fd_pr__diode_pd2nw_05v5/cathode =
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_ef_io__vccd_lvc_clamped_ |Circuit 2: sky130_ef_io__vccd_lvc_clamped_
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pw2nd_05v5:0 |(no matching instance)
anode = 9 |
cathode = 2 |
|
Instance: sky130_fd_pr__diode_pw2nd_05v5:2 |(no matching instance)
anode = 9 |
cathode = 5 |
|
Instance: sky130_fd_pr__diode_pw2nd_05v5:1 |(no matching instance)
anode = 5 |
cathode = 5 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pd2nw_05v5:3 |Instance: sky130_fd_io__top_power_lvc_wpad
anode = 5 | anode = 2
cathode = 2 | cathode = 9
|
Instance: sky130_fd_pr__diode_pd2nw_05v5:1 |Instance: sky130_fd_io__top_power_lvc_wpad
anode = 8 | anode = 9
cathode = 5 | cathode = 2
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_ef_io__vccd_lvc_clamped_pad sky130_ef_io__vccd_lvc_clamped_pad
Circuit 2 cell constant_block is a black box; will not flatten Circuit 1
Subcircuit pins:
Circuit 1: constant_block |Circuit 2: constant_block
-------------------------------------------|-------------------------------------------
one |one
vccd |vccd
zero |zero
vssd |vssd
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes constant_block and constant_block are equivalent.
Flattening unmatched subcell sky130_fd_io__top_power_hvc_wpadv2 in circuit sky130_ef_io__vddio_hvc_clamped_pad (1)(1 instance)
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA_uq2
Class sky130_ef_io__vddio_hvc_clamped_pad (0): Merged 223 parallel devices.
Class sky130_ef_io__vddio_hvc_clamped_pad (0): Merged 2 series devices.
Class sky130_ef_io__vddio_hvc_clamped_pad (1): Merged 5 parallel devices.
Class sky130_ef_io__vddio_hvc_clamped_pad (1): Merged 2 series devices.
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vddio_hvc_clamped_pad (0) disconnected node: VSSA_uq2
Subcircuit summary:
Circuit 1: sky130_ef_io__vddio_hvc_clamped |Circuit 2: sky130_ef_io__vddio_hvc_clamped
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (177->3) |sky130_fd_pr__nfet_g5v0d10v5 (177->3)
sky130_fd_pr__pfet_g5v0d10v5 (50->1) |sky130_fd_pr__pfet_g5v0d10v5 (50->1)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (3->1) |sky130_fd_pr__res_generic_po (3->1)
(no matching element) |sky130_fd_pr__res_generic_m3 (4->1)
Number of devices: 6 **Mismatch** |Number of devices: 7 **Mismatch**
Number of nets: 5 **Mismatch** |Number of nets: 6 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_ef_io__vddio_hvc_clamped |Circuit 2: sky130_ef_io__vddio_hvc_clamped
---------------------------------------------------------------------------------------
Net: VDDIO |Net: VDDIO
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__pfet_g5v0d10v5/4 = 1 | sky130_fd_pr__pfet_g5v0d10v5/4 = 1
sky130_fd_pr__res_generic_m5/(end_a|end_ | sky130_fd_pr__res_generic_m5/(end_a|end_
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
| sky130_fd_pr__res_generic_m3/(end_a|end_
|
(no matching net) |Net: VDDIO_Q
| sky130_fd_pr__res_generic_m3/(end_a|end_
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_ef_io__vddio_hvc_clamped |Circuit 2: sky130_ef_io__vddio_hvc_clamped
---------------------------------------------------------------------------------------
(no matching instance) |Instance: sky130_fd_pr__res_generic_m3:tes
| (end_a,end_b) = (6,1)
|
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_ef_io__vddio_hvc_clamped_pad sky130_ef_io__vddio_hvc_clamped_pad
Flattening unmatched subcell sky130_fd_io__top_ground_hvc_wpad in circuit sky130_ef_io__vssio_hvc_clamped_pad (1)(1 instance)
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA_uq2
Class sky130_ef_io__vssio_hvc_clamped_pad (0): Merged 223 parallel devices.
Class sky130_ef_io__vssio_hvc_clamped_pad (0): Merged 2 series devices.
Class sky130_ef_io__vssio_hvc_clamped_pad (1): Merged 5 parallel devices.
Class sky130_ef_io__vssio_hvc_clamped_pad (1): Merged 2 series devices.
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vssio_hvc_clamped_pad (0) disconnected node: VSSA_uq2
Subcircuit summary:
Circuit 1: sky130_ef_io__vssio_hvc_clamped |Circuit 2: sky130_ef_io__vssio_hvc_clamped
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (177->3) |sky130_fd_pr__nfet_g5v0d10v5 (177->3)
sky130_fd_pr__pfet_g5v0d10v5 (50->1) |sky130_fd_pr__pfet_g5v0d10v5 (50->1)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (3->1) |sky130_fd_pr__res_generic_po (3->1)
(no matching element) |sky130_fd_pr__res_generic_m3 (4->1)
Number of devices: 6 **Mismatch** |Number of devices: 7 **Mismatch**
Number of nets: 5 **Mismatch** |Number of nets: 6 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_ef_io__vssio_hvc_clamped |Circuit 2: sky130_ef_io__vssio_hvc_clamped
---------------------------------------------------------------------------------------
Net: VSSIO |Net: VSSIO
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4
sky130_fd_pr__nfet_g5v0d10v5/4 = 3 | sky130_fd_pr__nfet_g5v0d10v5/4 = 3
sky130_fd_pr__res_generic_m5/(end_a|end_ | sky130_fd_pr__res_generic_m5/(end_a|end_
| sky130_fd_pr__res_generic_m3/(end_a|end_
|
(no matching net) |Net: VSSIO_Q
| sky130_fd_pr__res_generic_m3/(end_a|end_
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_ef_io__vssio_hvc_clamped |Circuit 2: sky130_ef_io__vssio_hvc_clamped
---------------------------------------------------------------------------------------
(no matching instance) |Instance: sky130_fd_pr__res_generic_m3:tes
| (end_a,end_b) = (9,1)
|
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_ef_io__vssio_hvc_clamped_pad sky130_ef_io__vssio_hvc_clamped_pad
Flattening unmatched subcell sky130_fd_io__top_power_hvc_wpadv2 in circuit sky130_ef_io__vdda_hvc_clamped_pad (1)(1 instance)
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSIO
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VDDIO_uq0
Class sky130_ef_io__vdda_hvc_clamped_pad (0): Merged 223 parallel devices.
Class sky130_ef_io__vdda_hvc_clamped_pad (0): Merged 2 series devices.
Class sky130_ef_io__vdda_hvc_clamped_pad (1): Merged 2 parallel devices.
Class sky130_ef_io__vdda_hvc_clamped_pad (1): Merged 2 series devices.
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSIO
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vdda_hvc_clamped_pad (0) disconnected node: VDDIO_uq0
Subcircuit summary:
Circuit 1: sky130_ef_io__vdda_hvc_clamped_ |Circuit 2: sky130_ef_io__vdda_hvc_clamped_
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (177->3) |sky130_fd_pr__nfet_g5v0d10v5 (177->3)
sky130_fd_pr__pfet_g5v0d10v5 (50->1) |sky130_fd_pr__pfet_g5v0d10v5 (50->1)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (3->1) |sky130_fd_pr__res_generic_po (3->1)
Number of devices: 6 |Number of devices: 6
Number of nets: 5 |Number of nets: 5
---------------------------------------------------------------------------------------
Netlists match uniquely with port errors.
Subcircuit pins:
Circuit 1: sky130_ef_io__vdda_hvc_clamped_ |Circuit 2: sky130_ef_io__vdda_hvc_clamped_
-------------------------------------------|-------------------------------------------
VDDA_PAD |VDDA_PAD
VSSA_uq2 |VSSA **Mismatch**
VDDA |VDDA
(no matching pin) |AMUXBUS_A
(no matching pin) |AMUXBUS_B
(no matching pin) |VSWITCH
(no matching pin) |VDDIO_Q
(no matching pin) |VCCHIB
(no matching pin) |VDDIO
(no matching pin) |VCCD
(no matching pin) |VSSIO
(no matching pin) |VSSD
(no matching pin) |VSSIO_Q
AMUXBUS_A |(no matching pin)
AMUXBUS_B |(no matching pin)
VSSA |(no matching pin)
VSWITCH |(no matching pin)
VDDIO_Q |(no matching pin)
VCCHIB |(no matching pin)
VDDIO |(no matching pin)
VCCD |(no matching pin)
VSSIO |(no matching pin)
VSSD |(no matching pin)
VSSIO_Q |(no matching pin)
VSSA_uq0 |(no matching pin)
VSSA_uq1 |(no matching pin)
VSSIO_uq0 |(no matching pin)
VDDIO_uq0 |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists for sky130_ef_io__vdda_hvc_clamped_pad and sky130_ef_io__vdda_hvc_clamped_pad altered to match.
Device classes sky130_ef_io__vdda_hvc_clamped_pad and sky130_ef_io__vdda_hvc_clamped_pad are equivalent.
Flattening non-matched subcircuits sky130_ef_io__vdda_hvc_clamped_pad sky130_ef_io__vdda_hvc_clamped_pad
Flattening unmatched subcell sky130_fd_io__top_power_hvc_wpadv2 in circuit sky130_ef_io__top_power_hvc (1)(1 instance)
Cell sky130_ef_io__top_power_hvc (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__top_power_hvc (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDA
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSWITCH
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VCCHIB
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDIO
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VCCD
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSIO
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSD
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA_uq2
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDIO_uq0
Cell sky130_ef_io__top_power_hvc (1) disconnected node: VCCD_PAD
Class sky130_ef_io__top_power_hvc (0): Merged 223 parallel devices.
Class sky130_ef_io__top_power_hvc (0): Merged 2 series devices.
Class sky130_ef_io__top_power_hvc (1): Merged 2 parallel devices.
Class sky130_ef_io__top_power_hvc (1): Merged 2 series devices.
Cell sky130_ef_io__top_power_hvc (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__top_power_hvc (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDA
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSWITCH
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VCCHIB
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDIO
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VCCD
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSIO
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSD
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSA_uq2
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__top_power_hvc (0) disconnected node: VDDIO_uq0
Cell sky130_ef_io__top_power_hvc (1) disconnected node: VCCD_PAD
Subcircuit summary:
Circuit 1: sky130_ef_io__top_power_hvc |Circuit 2: sky130_ef_io__top_power_hvc
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (177->3) |sky130_fd_pr__nfet_g5v0d10v5 (177->3)
sky130_fd_pr__pfet_g5v0d10v5 (50->1) |sky130_fd_pr__pfet_g5v0d10v5 (50->1)
sky130_fd_pr__res_generic_po (3->1) |sky130_fd_pr__res_generic_po (3->1)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
Number of devices: 6 |Number of devices: 6
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely with port errors.
Subcircuit pins:
Circuit 1: sky130_ef_io__top_power_hvc |Circuit 2: sky130_ef_io__top_power_hvc
-------------------------------------------|-------------------------------------------
P_PAD |P_PAD
P_CORE |P_CORE
DRN_HVC |DRN_HVC
SRC_BDY_HVC |SRC_BDY_HVC
(no matching pin) |AMUXBUS_A
(no matching pin) |AMUXBUS_B
(no matching pin) |VCCD_PAD
(no matching pin) |VSSA
(no matching pin) |VDDA
(no matching pin) |VSWITCH
(no matching pin) |VDDIO_Q
(no matching pin) |VCCHIB
(no matching pin) |VDDIO
(no matching pin) |VCCD
(no matching pin) |VSSIO
(no matching pin) |VSSD
(no matching pin) |VSSIO_Q
AMUXBUS_A |(no matching pin)
AMUXBUS_B |(no matching pin)
VSSA |(no matching pin)
VDDA |(no matching pin)
VSWITCH |(no matching pin)
VDDIO_Q |(no matching pin)
VCCHIB |(no matching pin)
VDDIO |(no matching pin)
VCCD |(no matching pin)
VSSIO |(no matching pin)
VSSD |(no matching pin)
VSSIO_Q |(no matching pin)
VSSA_uq0 |(no matching pin)
VSSA_uq1 |(no matching pin)
VSSA_uq2 |(no matching pin)
VSSIO_uq0 |(no matching pin)
VDDIO_uq0 |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_ef_io__top_power_hvc and sky130_ef_io__top_power_hvc are equivalent.
Flattening non-matched subcircuits sky130_ef_io__top_power_hvc sky130_ef_io__top_power_hvc
Flattening unmatched subcell sky130_fd_io__top_ground_lvc_wpad in circuit sky130_ef_io__vssd_lvc_clamped3_pad (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gnd2gnd_120x2_lv_isosub in circuit sky130_ef_io__vssd_lvc_clamped3_pad (1)(1 instance)
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA_uq2
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDIO_uq0
Class sky130_ef_io__vssd_lvc_clamped3_pad (0): Merged 457 parallel devices.
Class sky130_ef_io__vssd_lvc_clamped3_pad (0): Merged 3 series devices.
Class sky130_ef_io__vssd_lvc_clamped3_pad (1): Merged 4 parallel devices.
Class sky130_ef_io__vssd_lvc_clamped3_pad (1): Merged 3 series devices.
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VSSA_uq2
Cell sky130_ef_io__vssd_lvc_clamped3_pad (0) disconnected node: VDDIO_uq0
Subcircuit summary:
Circuit 1: sky130_ef_io__vssd_lvc_clamped3 |Circuit 2: sky130_ef_io__vssd_lvc_clamped3
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (413->6) |sky130_fd_pr__nfet_01v8 (413->6)
sky130_fd_pr__pfet_01v8 (40->2) |sky130_fd_pr__pfet_01v8 (40->2)
sky130_fd_pr__diode_pw2nd_05v5 (10->4) |(no matching element)
sky130_fd_pr__diode_pd2nw_05v5 (8->2) |sky130_fd_pr__diode_pd2nw_05v5 (2)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (5->2) |sky130_fd_pr__res_generic_po (5->2)
Number of devices: 17 **Mismatch** |Number of devices: 13 **Mismatch**
Number of nets: 10 **Mismatch** |Number of nets: 8 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_ef_io__vssd_lvc_clamped3 |Circuit 2: sky130_ef_io__vssd_lvc_clamped3
---------------------------------------------------------------------------------------
Net: w_7483_429# |(no matching net)
sky130_fd_pr__diode_pw2nd_05v5/cathode = |
sky130_fd_pr__diode_pd2nw_05v5/cathode = |
|
Net: VSSIO |(no matching net)
sky130_fd_pr__diode_pd2nw_05v5/cathode = |
sky130_fd_pr__diode_pw2nd_05v5/cathode = |
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 |
sky130_fd_pr__diode_pw2nd_05v5/anode = 1 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSD |Net: VSSIO
sky130_fd_pr__diode_pw2nd_05v5/anode = 2 | sky130_fd_pr__diode_pd2nw_05v5/cathode =
| sky130_fd_pr__diode_pd2nw_05v5/anode = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSD1 |Net: VSSD1
sky130_fd_pr__nfet_01v8/(1|3) = 8 | sky130_fd_pr__nfet_01v8/(1|3) = 8
sky130_fd_pr__nfet_01v8/4 = 6 | sky130_fd_pr__nfet_01v8/4 = 6
sky130_fd_pr__diode_pw2nd_05v5/anode = 1 | sky130_fd_pr__diode_pd2nw_05v5/cathode =
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 | sky130_fd_pr__diode_pd2nw_05v5/anode = 1
sky130_fd_pr__res_generic_m5/(end_a|end_ | sky130_fd_pr__res_generic_m5/(end_a|end_
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_ef_io__vssd_lvc_clamped3 |Circuit 2: sky130_ef_io__vssd_lvc_clamped3
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pw2nd_05v5:0 |(no matching instance)
anode = 17 |
cathode = 3 |
|
Instance: sky130_fd_pr__diode_pw2nd_05v5:1 |(no matching instance)
anode = 5 |
cathode = 5 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pd2nw_05v5:3 |Instance: sky130_fd_io__top_ground_lvc_wpa
anode = 5 | anode = 2
cathode = 3 | cathode = 17
|
Instance: sky130_fd_pr__diode_pd2nw_05v5:1 |Instance: sky130_fd_io__top_ground_lvc_wpa
anode = 17 | anode = 17
cathode = 5 | cathode = 2
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_ef_io__vssd_lvc_clamped3_pad sky130_ef_io__vssd_lvc_clamped3_pad
Flattening unmatched subcell sky130_fd_io__top_ground_lvc_wpad in circuit sky130_ef_io__vssd_lvc_clamped_pad (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gnd2gnd_120x2_lv_isosub in circuit sky130_ef_io__vssd_lvc_clamped_pad (1)(1 instance)
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDIO_uq0
Class sky130_ef_io__vssd_lvc_clamped_pad (0): Merged 458 parallel devices.
Class sky130_ef_io__vssd_lvc_clamped_pad (0): Merged 3 series devices.
Class sky130_ef_io__vssd_lvc_clamped_pad (1): Merged 4 parallel devices.
Class sky130_ef_io__vssd_lvc_clamped_pad (1): Merged 3 series devices.
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vssd_lvc_clamped_pad (0) disconnected node: VDDIO_uq0
Subcircuit summary:
Circuit 1: sky130_ef_io__vssd_lvc_clamped_ |Circuit 2: sky130_ef_io__vssd_lvc_clamped_
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (413->6) |sky130_fd_pr__nfet_01v8 (413->6)
sky130_fd_pr__pfet_01v8 (40->2) |sky130_fd_pr__pfet_01v8 (40->2)
sky130_fd_pr__diode_pw2nd_05v5 (10->3) |(no matching element)
sky130_fd_pr__diode_pd2nw_05v5 (8->2) |sky130_fd_pr__diode_pd2nw_05v5 (2)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (5->2) |sky130_fd_pr__res_generic_po (5->2)
Number of devices: 16 **Mismatch** |Number of devices: 13 **Mismatch**
Number of nets: 10 **Mismatch** |Number of nets: 9 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_ef_io__vssd_lvc_clamped_ |Circuit 2: sky130_ef_io__vssd_lvc_clamped_
---------------------------------------------------------------------------------------
Net: VSSD |Net: VSSIO
sky130_fd_pr__nfet_01v8/(1|3) = 4 | sky130_fd_pr__diode_pd2nw_05v5/anode = 1
sky130_fd_pr__nfet_01v8/4 = 3 | sky130_fd_pr__diode_pd2nw_05v5/cathode =
sky130_fd_pr__diode_pw2nd_05v5/anode = 2 | sky130_fd_pr__nfet_01v8/(1|3) = 4
sky130_fd_pr__res_generic_m5/(end_a|end_ | sky130_fd_pr__nfet_01v8/4 = 3
|
Net: VSSA_uq2 |(no matching net)
sky130_fd_pr__diode_pd2nw_05v5/cathode = |
sky130_fd_pr__diode_pw2nd_05v5/cathode = |
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 |
sky130_fd_pr__diode_pw2nd_05v5/anode = 1 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSD_PAD |Net: VSSD_PAD
sky130_fd_pr__res_generic_m5/(end_a|end_ | sky130_fd_pr__res_generic_m5/(end_a|end_
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: w_7483_429# |Net: VSSA
sky130_fd_pr__diode_pw2nd_05v5/cathode = | sky130_fd_pr__diode_pd2nw_05v5/anode = 1
sky130_fd_pr__diode_pd2nw_05v5/cathode = | sky130_fd_pr__diode_pd2nw_05v5/cathode =
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSIO |Net: VSSD
sky130_fd_pr__nfet_01v8/(1|3) = 4 | sky130_fd_pr__nfet_01v8/(1|3) = 4
sky130_fd_pr__nfet_01v8/4 = 3 | sky130_fd_pr__nfet_01v8/4 = 3
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 | sky130_fd_pr__res_generic_m5/(end_a|end_
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_ef_io__vssd_lvc_clamped_ |Circuit 2: sky130_ef_io__vssd_lvc_clamped_
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pw2nd_05v5:0 |(no matching instance)
anode = 10 |
cathode = 2 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__res_generic_m5:0 |Instance: sky130_fd_io__top_ground_lvc_wpa
(end_a,end_b) = (10,1) | (end_a,end_b) = (8,1)
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pd2nw_05v5:1 |Instance: sky130_fd_io__top_ground_lvc_wpa
anode = 8 | anode = 2
cathode = 5 | cathode = 9
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_ef_io__vssd_lvc_clamped_pad sky130_ef_io__vssd_lvc_clamped_pad
Flattening unmatched subcell sky130_fd_io__top_power_lvc_wpad in circuit sky130_ef_io__vccd_lvc_clamped3_pad (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gnd2gnd_120x2_lv_isosub in circuit sky130_ef_io__vccd_lvc_clamped3_pad (1)(1 instance)
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA_uq2
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDIO_uq0
Class sky130_ef_io__vccd_lvc_clamped3_pad (0): Merged 457 parallel devices.
Class sky130_ef_io__vccd_lvc_clamped3_pad (0): Merged 3 series devices.
Class sky130_ef_io__vccd_lvc_clamped3_pad (1): Merged 4 parallel devices.
Class sky130_ef_io__vccd_lvc_clamped3_pad (1): Merged 3 series devices.
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDA
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA_uq0
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA_uq1
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VSSA_uq2
Cell sky130_ef_io__vccd_lvc_clamped3_pad (0) disconnected node: VDDIO_uq0
Subcircuit summary:
Circuit 1: sky130_ef_io__vccd_lvc_clamped3 |Circuit 2: sky130_ef_io__vccd_lvc_clamped3
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (413->6) |sky130_fd_pr__nfet_01v8 (413->6)
sky130_fd_pr__pfet_01v8 (40->2) |sky130_fd_pr__pfet_01v8 (40->2)
sky130_fd_pr__diode_pw2nd_05v5 (10->4) |(no matching element)
sky130_fd_pr__diode_pd2nw_05v5 (8->2) |sky130_fd_pr__diode_pd2nw_05v5 (2)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (5->2) |sky130_fd_pr__res_generic_po (5->2)
Number of devices: 17 **Mismatch** |Number of devices: 13 **Mismatch**
Number of nets: 10 **Mismatch** |Number of nets: 8 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_ef_io__vccd_lvc_clamped3 |Circuit 2: sky130_ef_io__vccd_lvc_clamped3
---------------------------------------------------------------------------------------
Net: w_7483_429# |(no matching net)
sky130_fd_pr__diode_pw2nd_05v5/cathode = |
sky130_fd_pr__diode_pd2nw_05v5/cathode = |
|
Net: VSSIO |(no matching net)
sky130_fd_pr__diode_pd2nw_05v5/cathode = |
sky130_fd_pr__diode_pw2nd_05v5/cathode = |
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 |
sky130_fd_pr__diode_pw2nd_05v5/anode = 1 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSD |Net: VSSIO
sky130_fd_pr__diode_pw2nd_05v5/anode = 2 | sky130_fd_pr__diode_pd2nw_05v5/cathode =
| sky130_fd_pr__diode_pd2nw_05v5/anode = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSD1 |Net: VSSD1
sky130_fd_pr__nfet_01v8/(1|3) = 8 | sky130_fd_pr__nfet_01v8/(1|3) = 8
sky130_fd_pr__nfet_01v8/4 = 6 | sky130_fd_pr__nfet_01v8/4 = 6
sky130_fd_pr__diode_pw2nd_05v5/anode = 1 | sky130_fd_pr__diode_pd2nw_05v5/cathode =
sky130_fd_pr__diode_pd2nw_05v5/anode = 1 | sky130_fd_pr__diode_pd2nw_05v5/anode = 1
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_ef_io__vccd_lvc_clamped3 |Circuit 2: sky130_ef_io__vccd_lvc_clamped3
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pw2nd_05v5:0 |(no matching instance)
anode = 16 |
cathode = 3 |
|
Instance: sky130_fd_pr__diode_pw2nd_05v5:1 |(no matching instance)
anode = 5 |
cathode = 5 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__diode_pd2nw_05v5:3 |Instance: sky130_fd_io__top_power_lvc_wpad
anode = 5 | anode = 2
cathode = 3 | cathode = 16
|
Instance: sky130_fd_pr__diode_pd2nw_05v5:1 |Instance: sky130_fd_io__top_power_lvc_wpad
anode = 16 | anode = 16
cathode = 5 | cathode = 2
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_ef_io__vccd_lvc_clamped3_pad sky130_ef_io__vccd_lvc_clamped3_pad
Flattening unmatched subcell sky130_fd_io__top_ground_hvc_wpad in circuit sky130_ef_io__vssa_hvc_clamped_pad (1)(1 instance)
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSIO
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VDDIO_uq0
Class sky130_ef_io__vssa_hvc_clamped_pad (0): Merged 223 parallel devices.
Class sky130_ef_io__vssa_hvc_clamped_pad (0): Merged 2 series devices.
Class sky130_ef_io__vssa_hvc_clamped_pad (1): Merged 2 parallel devices.
Class sky130_ef_io__vssa_hvc_clamped_pad (1): Merged 2 series devices.
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: AMUXBUS_A
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: AMUXBUS_B
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSWITCH
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VDDIO_Q
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VCCHIB
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VDDIO
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VCCD
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSIO
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSD
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSIO_Q
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VSSIO_uq0
Cell sky130_ef_io__vssa_hvc_clamped_pad (0) disconnected node: VDDIO_uq0
Subcircuit summary:
Circuit 1: sky130_ef_io__vssa_hvc_clamped_ |Circuit 2: sky130_ef_io__vssa_hvc_clamped_
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (177->3) |sky130_fd_pr__nfet_g5v0d10v5 (177->3)
sky130_fd_pr__pfet_g5v0d10v5 (50->1) |sky130_fd_pr__pfet_g5v0d10v5 (50->1)
sky130_fd_pr__res_generic_m5 (1) |sky130_fd_pr__res_generic_m5 (1)
sky130_fd_pr__res_generic_po (3->1) |sky130_fd_pr__res_generic_po (3->1)
Number of devices: 6 |Number of devices: 6
Number of nets: 5 |Number of nets: 5
---------------------------------------------------------------------------------------
Netlists match uniquely with port errors.
Subcircuit pins:
Circuit 1: sky130_ef_io__vssa_hvc_clamped_ |Circuit 2: sky130_ef_io__vssa_hvc_clamped_
-------------------------------------------|-------------------------------------------
VSSA_PAD |VSSA_PAD
VSSA |VSSA
VDDA |VDDA
(no matching pin) |AMUXBUS_A
(no matching pin) |AMUXBUS_B
(no matching pin) |VSWITCH
(no matching pin) |VDDIO_Q
(no matching pin) |VCCHIB
(no matching pin) |VDDIO
(no matching pin) |VCCD
(no matching pin) |VSSIO
(no matching pin) |VSSD
(no matching pin) |VSSIO_Q
AMUXBUS_A |(no matching pin)
AMUXBUS_B |(no matching pin)
VSWITCH |(no matching pin)
VDDIO_Q |(no matching pin)
VCCHIB |(no matching pin)
VDDIO |(no matching pin)
VCCD |(no matching pin)
VSSIO |(no matching pin)
VSSD |(no matching pin)
VSSIO_Q |(no matching pin)
VSSIO_uq0 |(no matching pin)
VDDIO_uq0 |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_ef_io__vssa_hvc_clamped_pad and sky130_ef_io__vssa_hvc_clamped_pad are equivalent.
Flattening non-matched subcircuits sky130_ef_io__vssa_hvc_clamped_pad sky130_ef_io__vssa_hvc_clamped_pad
Flattening unmatched subcell sky130_fd_io__tk_tie_r_out_esd in circuit sky130_fd_io__top_xres4v2 (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__xres4v2_in_buf in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__inv_1 in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x1 in circuit sky130_fd_io__top_xres4v2 (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__hvsbt_nand2 in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__xres_esd in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpio_buf_localesd in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__res250only_small in circuit sky130_fd_io__top_xres4v2 (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__signal_5_sym_hv_local_5term in circuit sky130_fd_io__top_xres4v2 (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__gpio_pddrvr_strong in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em2s in circuit sky130_fd_io__top_xres4v2 (1)(8 instances)
Flattening unmatched subcell sky130_fd_io__tk_em2o in circuit sky130_fd_io__top_xres4v2 (1)(16 instances)
Flattening unmatched subcell sky130_fd_io__tk_tie_r_out_esd in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_pddrvr_unit_2_5 in circuit sky130_fd_io__top_xres4v2 (1)(28 instances)
Flattening unmatched subcell sky130_fd_io__gpio_pudrvr_strong in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em2s in circuit sky130_fd_io__top_xres4v2 (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__tk_em2o in circuit sky130_fd_io__top_xres4v2 (1)(10 instances)
Flattening unmatched subcell sky130_fd_io__tk_tie_r_out_esd in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__gpio_pudrvr_unit_2_5 in circuit sky130_fd_io__top_xres4v2 (1)(28 instances)
Flattening unmatched subcell sky130_fd_io__xres_wpu in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__res250only_small in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_res_weak in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_fd_io__top_xres4v2 (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__com_xres_weak_pu in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_fd_io__top_xres4v2 (1)(5 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x2 in circuit sky130_fd_io__top_xres4v2 (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__xres_rcfilter_lpf in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__xres_tk_emlo in circuit sky130_fd_io__top_xres4v2 (1)(16 instances)
Flattening unmatched subcell sky130_fd_io__xres_tk_emlc in circuit sky130_fd_io__top_xres4v2 (1)(8 instances)
Flattening unmatched subcell sky130_fd_io__xres_rcfilter_lpf_rcunit in circuit sky130_fd_io__top_xres4v2 (1)(12 instances)
Flattening unmatched subcell sky130_fd_io__xres_rcfilter_lpf_res_sub in circuit sky130_fd_io__top_xres4v2 (1)(24 instances)
Flattening unmatched subcell sky130_fd_io__xres_tk_emlc in circuit sky130_fd_io__top_xres4v2 (1)(24 instances)
Flattening unmatched subcell sky130_fd_io__xres_tk_emlo in circuit sky130_fd_io__top_xres4v2 (1)(24 instances)
Flattening unmatched subcell sky130_fd_io__xres_inv_hys in circuit sky130_fd_io__top_xres4v2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_io__hvsbt_inv_x4 in circuit sky130_fd_io__top_xres4v2 (1)(2 instances)
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: AMUXBUS_B
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: AMUXBUS_A
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSWITCH
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VDDA
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VCCD
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSIO_Q
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA_uq0
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA_uq1
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA_uq2
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: AMUXBUS_A
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: AMUXBUS_B
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VCCD
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VDDA
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VSSA
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VSSIO_Q
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VSWITCH
Class sky130_fd_io__top_xres4v2 (0): Merged 313 parallel devices.
Class sky130_fd_io__top_xres4v2 (0): Merged 25 series devices.
Class sky130_fd_io__top_xres4v2 (1): Merged 181 parallel devices.
Class sky130_fd_io__top_xres4v2 (1): Merged 25 series devices.
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: AMUXBUS_B
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: AMUXBUS_A
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSWITCH
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VDDA
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VCCD
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSIO_Q
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA_uq0
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA_uq1
Cell sky130_fd_io__top_xres4v2 (0) disconnected node: VSSA_uq2
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: AMUXBUS_A
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: AMUXBUS_B
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VCCD
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VDDA
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VSSA
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VSSIO_Q
Cell sky130_fd_io__top_xres4v2 (1) disconnected node: VSWITCH
Subcircuit summary:
Circuit 1: sky130_fd_io__top_xres4v2 |Circuit 2: sky130_fd_io__top_xres4v2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (114->46) |sky130_fd_pr__nfet_g5v0d10v5 (114->46)
sky130_fd_pr__res_generic_m2 (78->28) |sky130_fd_pr__res_generic_m2 (78->28)
sky130_fd_pr__res_generic_m1 (182->69) |sky130_fd_pr__res_generic_m1 (168->63) **M
sky130_fd_pr__res_generic_po (36->27) |sky130_fd_pr__res_generic_po (24->22) **Mi
sky130_fd_pr__res_generic_nd (72->68) |sky130_fd_pr__res_generic_nd (72->68)
sky130_fd_pr__pfet_g5v0d10v5 (138->51) |sky130_fd_pr__pfet_g5v0d10v5 (138->51)
sky130_fd_pr__nfet_05v0_nvt (4) |sky130_fd_pr__nfet_05v0_nvt (4)
sky130_fd_pr__res_generic_l1 (12->5) |(no matching element)
sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
sky130_fd_pr__esd_nfet_g5v0d10v5 (4) |sky130_fd_pr__esd_nfet_g5v0d10v5 (4)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
sky130_fd_pr__res_generic_nd__hv (1) |sky130_fd_pr__res_generic_nd__hv (1)
Number of devices: 305 **Mismatch** |Number of devices: 289 **Mismatch**
Number of nets: 200 **Mismatch** |Number of nets: 197 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: sky130_fd_io__top_xres4v2 |Circuit 2: sky130_fd_io__top_xres4v2
---------------------------------------------------------------------------------------
Net: m1_2388_13987# |Net: net86
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) =
| sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
|
Net: a_1384_6392# |Net: sky130_fd_io__xres4v2_in_buf:gpio_inb
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 2 | sky130_fd_pr__res_generic_nd__hv/(1|2) =
sky130_fd_pr__res_generic_nd__hv/(1|2) = | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 2
|
Net: a_1597_12303# |Net: sky130_fd_io__xres_wpu:weakpullup_q0/
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__res_generic_po/(end_a|end_
sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) = | sky130_fd_pr__res_generic_m1/(end_a|end_
|
Net: VDDIO |Net: VDDIO
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) = | sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) =
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 9 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 9
sky130_fd_pr__pfet_g5v0d10v5/4 = 9 | sky130_fd_pr__pfet_g5v0d10v5/4 = 9
sky130_fd_pr__res_generic_m1/(end_a|end_ |
|
Net: PAD_A_ESD_H |Net: sky130_fd_io__xres4v2_in_buf:gpio_inb
sky130_fd_pr__res_generic_l1/(end_a|end_ | sky130_fd_pr__nfet_05v0_nvt/(1|3) = 1
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 3
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__pfet_g5v0d10v5/4 = 2
| sky130_fd_pr__pfet_g5v0d10v5/2 = 1
|
Net: VSSIO |Net: VSSIO
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 9 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 9
sky130_fd_pr__nfet_g5v0d10v5/4 = 9 | sky130_fd_pr__nfet_g5v0d10v5/4 = 9
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
|
Net: PAD |Net: PAD
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 9 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 9
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 6 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 6
sky130_fd_pr__res_generic_m1/(end_a|end_ |
sky130_fd_pr__res_generic_l1/(end_a|end_ |
|
Net: w_1244_1840# |(no matching net)
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 3 |
sky130_fd_pr__pfet_g5v0d10v5/4 = 2 |
sky130_fd_pr__pfet_g5v0d10v5/2 = 1 |
sky130_fd_pr__nfet_05v0_nvt/(1|3) = 1 |
|
Net: TIE_WEAK_HI_H |(no matching net)
sky130_fd_pr__res_generic_l1/(end_a|end_ |
sky130_fd_pr__res_generic_po/(end_a|end_ |
sky130_fd_pr__res_generic_m1/(end_a|end_ |
|
Net: a_1352_6292# |(no matching net)
sky130_fd_pr__pfet_g5v0d10v5/2 = 2 |
sky130_fd_pr__nfet_05v0_nvt/2 = 1 |
sky130_fd_pr__res_generic_l1/(end_a|end_ |
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 |
sky130_fd_pr__nfet_g5v0d10v5/2 = 2 |
sky130_fd_pr__res_generic_po/(end_a|end_ |
sky130_fd_pr__res_generic_m1/(end_a|end_ |
sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) = |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSIO_uq0 |Net: PAD_A_ESD_H
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
|
Net: VDDIO_uq0 |Net: TIE_WEAK_HI_H
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
|
Net: TIE_HI_ESD |Net: TIE_HI_ESD
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
|
Net: TIE_LO_ESD |Net: TIE_LO_ESD
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: a_11027_27088# |Net: sky130_fd_io__xres4v2_in_buf:gpio_inb
sky130_fd_pr__res_generic_l1/(end_a|end_ | sky130_fd_pr__nfet_g5v0d10v5/2 = 4
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__pfet_g5v0d10v5/2 = 2
| sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 2
|
Net: a_1384_6236# |Net: in_h
sky130_fd_pr__nfet_g5v0d10v5/2 = 4 | sky130_fd_pr__nfet_g5v0d10v5/2 = 2
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 2 | sky130_fd_pr__nfet_05v0_nvt/2 = 1
sky130_fd_pr__pfet_g5v0d10v5/2 = 2 | sky130_fd_pr__pfet_g5v0d10v5/2 = 2
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__res_generic_po/(end_a|end_
| sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) =
| sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VDDIO_Q |Net: VDDIO_Q
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 41 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 41
sky130_fd_pr__pfet_g5v0d10v5/4 = 37 | sky130_fd_pr__pfet_g5v0d10v5/4 = 37
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: VSSD |Net: VSSD
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 40 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 40
sky130_fd_pr__nfet_g5v0d10v5/4 = 37 | sky130_fd_pr__nfet_g5v0d10v5/4 = 37
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__res_generic_m1/(end_a|end_
sky130_fd_pr__res_generic_nd/3 = 68 | sky130_fd_pr__res_generic_nd/3 = 68
sky130_fd_pr__nfet_05v0_nvt/4 = 4 | sky130_fd_pr__nfet_05v0_nvt/4 = 4
sky130_fd_pr__res_generic_nd/(1|2) = 6 | sky130_fd_pr__res_generic_nd/(1|2) = 6
sky130_fd_pr__nfet_g5v0d10v5/2 = 1 | sky130_fd_pr__nfet_g5v0d10v5/2 = 1
sky130_fd_pr__nfet_05v0_nvt/(1|3) = 2 | sky130_fd_pr__nfet_05v0_nvt/(1|3) = 2
sky130_fd_pr__nfet_05v0_nvt/2 = 1 | sky130_fd_pr__nfet_05v0_nvt/2 = 1
sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) = | sky130_fd_pr__esd_nfet_g5v0d10v5/(1|3) =
sky130_fd_pr__esd_nfet_g5v0d10v5/2 = 4 | sky130_fd_pr__esd_nfet_g5v0d10v5/2 = 4
sky130_fd_pr__esd_nfet_g5v0d10v5/4 = 4 | sky130_fd_pr__esd_nfet_g5v0d10v5/4 = 4
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
sky130_fd_pr__nfet_01v8/4 = 1 | sky130_fd_pr__nfet_01v8/4 = 1
sky130_fd_pr__res_generic_nd__hv/3 = 1 | sky130_fd_pr__res_generic_nd__hv/3 = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: a_11566_26616# |Net: sky130_fd_io__xres_wpu:weakpullup_q0/
sky130_fd_pr__res_generic_m1/(end_a|end_ | sky130_fd_pr__res_generic_m1/(end_a|end_
sky130_fd_pr__res_generic_po/(end_a|end_ | sky130_fd_pr__res_generic_po/(end_a|end_
|
Net: a_3063_5593# |Net: sky130_fd_io__xres4v2_in_buf:gpio_inb
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: a_1384_7279# |Net: sky130_fd_io__xres4v2_in_buf:gpio_inb
sky130_fd_pr__nfet_05v0_nvt/(1|3) = 1 | sky130_fd_pr__nfet_05v0_nvt/(1|3) = 1
sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1
|
Net: a_2727_6967# |Net: sky130_fd_io__xres4v2_in_buf:gpio_inb
sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1
sky130_fd_pr__nfet_05v0_nvt/(1|3) = 1 | sky130_fd_pr__nfet_05v0_nvt/(1|3) = 1
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: sky130_fd_io__top_xres4v2 |Circuit 2: sky130_fd_io__top_xres4v2
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__res_generic_m1:36 |Instance: sky130_fd_io__xres_wpu:weakpullu
(end_a,end_b) = (23,23) | (end_a,end_b) = (4,3)
|
Instance: sky130_fd_pr__res_generic_m1:61 |Instance: sky130_fd_io__tk_tie_r_out_esd:I
(end_a,end_b) = (23,1) | (end_a,end_b) = (20,1)
|
Instance: sky130_fd_pr__res_generic_m1:155 |Instance: sky130_fd_io__tk_tie_r_out_esd:I
(end_a,end_b) = (15,15) | (end_a,end_b) = (23,1)
|
Instance: sky130_fd_pr__res_generic_m1:236 |Instance: sky130_fd_io__xres_wpu:weakpullu
(end_a,end_b) = (7,7) | (end_a,end_b) = (3,1)
|
Instance: sky130_fd_pr__res_generic_m1:248 |Instance: sky130_fd_io__res250only_small:e
(end_a,end_b) = (7,7) | (end_a,end_b) = (17,1)
|
Instance: sky130_fd_pr__res_generic_m1:66 |Instance: sky130_fd_io__xres_wpu:weakpullu
(end_a,end_b) = (9,4) | (end_a,end_b) = (4,3)
|
Instance: sky130_fd_pr__res_generic_m1:179 |(no matching instance)
(end_a,end_b) = (9,9) |
|
|
Instance: sky130_fd_pr__res_generic_po:3 |(no matching instance)
(end_a,end_b) = (23,23) |
|
|
Instance: sky130_fd_pr__res_generic_po:62 |(no matching instance)
(end_a,end_b) = (23,7) |
|
|
Instance: sky130_fd_pr__res_generic_po:112 |(no matching instance)
(end_a,end_b) = (23,15) |
|
|
Instance: sky130_fd_pr__res_generic_po:120 |(no matching instance)
(end_a,end_b) = (7,7) |
|
|
Instance: sky130_fd_pr__res_generic_po:153 |(no matching instance)
(end_a,end_b) = (15,15) |
|
|
Instance: sky130_fd_pr__res_generic_po:244 |(no matching instance)
(end_a,end_b) = (7,7) |
|
|
Instance: sky130_fd_pr__res_generic_po:64 |(no matching instance)
(end_a,end_b) = (9,9) |
|
|
Instance: sky130_fd_pr__res_generic_po:75 |(no matching instance)
(end_a,end_b) = (9,4) |
|
|
Instance: sky130_fd_pr__res_generic_l1:20 |(no matching instance)
(end_a,end_b) = (9,9) |
|
|
Instance: sky130_fd_pr__res_generic_l1:45 |(no matching instance)
(end_a,end_b) = (7,7) |
|
|
Instance: sky130_fd_pr__res_generic_l1:50 |(no matching instance)
(end_a,end_b) = (23,23) |
|
|
Instance: sky130_fd_pr__res_generic_l1:57 |(no matching instance)
(end_a,end_b) = (15,15) |
|
|
Instance: sky130_fd_pr__res_generic_l1:72 |(no matching instance)
(end_a,end_b) = (7,7) |
|
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__esd_nfet_g5v0d10v5 |Instance: sky130_fd_io__xres_esd:xresesd_q
(1,3) = (23,15) | (1,3) = (173,9)
2 = 173 | 2 = 173
4 = 173 | 4 = 173
|
Instance: sky130_fd_pr__esd_nfet_g5v0d10v5 |Instance: sky130_fd_io__xres_esd:xresesd_q
(1,3) = (23,3) | (1,3) = (23,3)
2 = 173 | 2 = 173
4 = 173 | 4 = 173
|
Instance: sky130_fd_pr__esd_nfet_g5v0d10v5 |Instance: sky130_fd_io__xres_esd:xresesd_q
(1,3) = (173,15) | (1,3) = (23,9)
2 = 173 | 2 = 173
4 = 173 | 4 = 173
|
Instance: sky130_fd_pr__esd_nfet_g5v0d10v5 |Instance: sky130_fd_io__xres_esd:xresesd_q
(1,3) = (173,3) | (1,3) = (173,3)
2 = 173 | 2 = 173
4 = 173 | 4 = 173
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__nfet_05v0_nvt:49 |Instance: sky130_fd_io__xres4v2_in_buf:gpi
(1,3) = (2,2) | (1,3) = (2,2)
2 = 15 | 2 = 9
4 = 173 | 4 = 173
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__pfet_g5v0d10v5:57 |Instance: sky130_fd_io__xres4v2_in_buf:gpi
(1,3) = (9,7) | (1,3) = (9,3)
2 = 15 | 2 = 9
4 = 7 | 4 = 78
|
Instance: sky130_fd_pr__pfet_g5v0d10v5:35 |Instance: sky130_fd_io__xres4v2_in_buf:gpi
(1,3) = (9,3) | (1,3) = (9,7)
2 = 15 | 2 = 9
4 = 78 | 4 = 7
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: sky130_fd_pr__nfet_g5v0d10v5:105 |Instance: sky130_fd_io__xres_esd:xresesd_q
(1,3) = (173,4) | (1,3) = (9,3)
2 = 15 | 2 = 173
4 = 173 | 4 = 173
|
Instance: sky130_fd_pr__nfet_g5v0d10v5:103 |Instance: sky130_fd_io__xres4v2_in_buf:gpi
(1,3) = (9,4) | (1,3) = (173,4)
2 = 15 | 2 = 9
4 = 173 | 4 = 173
|
Instance: sky130_fd_pr__nfet_g5v0d10v5:73 |Instance: sky130_fd_io__xres4v2_in_buf:gpi
(1,3) = (15,3) | (1,3) = (9,4)
2 = 173 | 2 = 9
4 = 173 | 4 = 173
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits sky130_fd_io__top_xres4v2 sky130_fd_io__top_xres4v2
Class QI_sky130_fd_sc_hd__a211oi_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__a211oi_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a211oi_2 |Circuit 2: sky130_fd_sc_hd__a211oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a211oi_2 |Circuit 2: sky130_fd_sc_hd__a211oi_2
-------------------------------------------|-------------------------------------------
VPB |VPB
Y |Y
VNB |VNB
B1 |B1
C1 |C1
VPWR |VPWR
A2 |A2
A1 |A1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a211oi_2 and sky130_fd_sc_hd__a211oi_2 are equivalent.
Class QI_sky130_fd_sc_hd__dfxtp_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__dfxtp_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__dfxtp_4 |Circuit 2: sky130_fd_sc_hd__dfxtp_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (15->12) |sky130_fd_pr__pfet_01v8_hvt (15->12)
sky130_fd_pr__nfet_01v8 (15->12) |sky130_fd_pr__nfet_01v8 (15->12)
Number of devices: 24 |Number of devices: 24
Number of nets: 18 |Number of nets: 18
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__dfxtp_4 |Circuit 2: sky130_fd_sc_hd__dfxtp_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VGND |VGND
VPWR |VPWR
Q |Q
D |D
CLK |CLK
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__dfxtp_4 and sky130_fd_sc_hd__dfxtp_4 are equivalent.
Class QI_sky130_fd_sc_hd__or4b_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__or4b_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or4b_4 |Circuit 2: sky130_fd_sc_hd__or4b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (9->6) |sky130_fd_pr__pfet_01v8_hvt (9->6)
sky130_fd_pr__nfet_01v8 (9->6) |sky130_fd_pr__nfet_01v8 (9->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or4b_4 |Circuit 2: sky130_fd_sc_hd__or4b_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VGND |VGND
VNB |VNB
VPWR |VPWR
X |X
B |B
C |C
A |A
D_N |D_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or4b_4 and sky130_fd_sc_hd__or4b_4 are equivalent.
Class QI_sky130_fd_sc_hd__a31o_4 (0): Merged 11 parallel devices.
Class sky130_fd_sc_hd__a31o_4 (1): Merged 11 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a31o_4 |Circuit 2: sky130_fd_sc_hd__a31o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
sky130_fd_pr__nfet_01v8 (12->8) |sky130_fd_pr__nfet_01v8 (12->8)
Number of devices: 13 |Number of devices: 13
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a31o_4 |Circuit 2: sky130_fd_sc_hd__a31o_4
-------------------------------------------|-------------------------------------------
VNB |VNB
A2 |A2
A1 |A1
A3 |A3
VPB |VPB
B1 |B1
X |X
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a31o_4 and sky130_fd_sc_hd__a31o_4 are equivalent.
Class QI_sky130_fd_sc_hd__and3_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__and3_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__and3_4 |Circuit 2: sky130_fd_sc_hd__and3_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__and3_4 |Circuit 2: sky130_fd_sc_hd__and3_4
-------------------------------------------|-------------------------------------------
X |X
VGND |VGND
A |A
C |C
B |B
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__and3_4 and sky130_fd_sc_hd__and3_4 are equivalent.
Class QI_sky130_fd_sc_hd__a211oi_4 (0): Merged 20 parallel devices.
Class sky130_fd_sc_hd__a211oi_4 (1): Merged 20 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a211oi_4 |Circuit 2: sky130_fd_sc_hd__a211oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
sky130_fd_pr__pfet_01v8_hvt (16->8) |sky130_fd_pr__pfet_01v8_hvt (16->8)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a211oi_4 |Circuit 2: sky130_fd_sc_hd__a211oi_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VGND |VGND
C1 |C1
VNB |VNB
B1 |B1
A1 |A1
VPWR |VPWR
A2 |A2
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a211oi_4 and sky130_fd_sc_hd__a211oi_4 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
B1 |B1
A1 |A1
VGND |VGND
A3 |A3
A2 |A2
Y |Y
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a31oi_1 and sky130_fd_sc_hd__a31oi_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
A2 |A2
A1 |A1
B1 |B1
X |X
B2 |B2
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a22o_1 and sky130_fd_sc_hd__a22o_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or3b_1 |Circuit 2: sky130_fd_sc_hd__or3b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or3b_1 |Circuit 2: sky130_fd_sc_hd__or3b_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VNB |VNB
VPB |VPB
X |X
B |B
A |A
C_N |C_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or3b_1 and sky130_fd_sc_hd__or3b_1 are equivalent.
Class QI_sky130_fd_sc_hd__a22o_4 (0): Merged 14 parallel devices.
Class sky130_fd_sc_hd__a22o_4 (1): Merged 14 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a22o_4 |Circuit 2: sky130_fd_sc_hd__a22o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
sky130_fd_pr__nfet_01v8 (12->5) |sky130_fd_pr__nfet_01v8 (12->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a22o_4 |Circuit 2: sky130_fd_sc_hd__a22o_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
A1 |A1
X |X
B2 |B2
A2 |A2
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a22o_4 and sky130_fd_sc_hd__a22o_4 are equivalent.
Class QI_sky130_fd_sc_hd__dfxtp_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__dfxtp_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__dfxtp_2 |Circuit 2: sky130_fd_sc_hd__dfxtp_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (13->12) |sky130_fd_pr__nfet_01v8 (13->12)
sky130_fd_pr__pfet_01v8_hvt (13->12) |sky130_fd_pr__pfet_01v8_hvt (13->12)
Number of devices: 24 |Number of devices: 24
Number of nets: 18 |Number of nets: 18
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__dfxtp_2 |Circuit 2: sky130_fd_sc_hd__dfxtp_2
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VGND |VGND
VPWR |VPWR
D |D
Q |Q
CLK |CLK
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__dfxtp_2 and sky130_fd_sc_hd__dfxtp_2 are equivalent.
Class QI_sky130_fd_sc_hd__a311oi_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__a311oi_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a311oi_4 |Circuit 2: sky130_fd_sc_hd__a311oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a311oi_4 |Circuit 2: sky130_fd_sc_hd__a311oi_4
-------------------------------------------|-------------------------------------------
Y |Y
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
A1 |A1
A2 |A2
B1 |B1
C1 |C1
A3 |A3
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a311oi_4 and sky130_fd_sc_hd__a311oi_4 are equivalent.
Class QI_sky130_fd_sc_hd__mux4_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__mux4_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__mux4_2 |Circuit 2: sky130_fd_sc_hd__mux4_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (14->13) |sky130_fd_pr__pfet_01v8_hvt (14->13)
sky130_fd_pr__nfet_01v8 (14->13) |sky130_fd_pr__nfet_01v8 (14->13)
Number of devices: 26 |Number of devices: 26
Number of nets: 24 |Number of nets: 24
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__mux4_2 |Circuit 2: sky130_fd_sc_hd__mux4_2
-------------------------------------------|-------------------------------------------
X |X
A1 |A1
A3 |A3
A0 |A0
A2 |A2
S0 |S0
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
S1 |S1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__mux4_2 and sky130_fd_sc_hd__mux4_2 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or4b_1 |Circuit 2: sky130_fd_sc_hd__or4b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or4b_1 |Circuit 2: sky130_fd_sc_hd__or4b_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
A |A
B |B
C |C
X |X
D_N |D_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or4b_1 and sky130_fd_sc_hd__or4b_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1
-------------------------------------------|-------------------------------------------
A |A
VPWR |VPWR
X |X
B |B
VPB |VPB
VGND |VGND
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or2_1 and sky130_fd_sc_hd__or2_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a311oi_1 |Circuit 2: sky130_fd_sc_hd__a311oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a311oi_1 |Circuit 2: sky130_fd_sc_hd__a311oi_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
A1 |A1
A2 |A2
A3 |A3
B1 |B1
C1 |C1
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a311oi_1 and sky130_fd_sc_hd__a311oi_1 are equivalent.
Class QI_sky130_fd_sc_hd__clkinv_16 (0): Merged 38 parallel devices.
Class sky130_fd_sc_hd__clkinv_16 (1): Merged 38 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__clkinv_16 |Circuit 2: sky130_fd_sc_hd__clkinv_16
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->1) |sky130_fd_pr__nfet_01v8 (16->1)
sky130_fd_pr__pfet_01v8_hvt (24->1) |sky130_fd_pr__pfet_01v8_hvt (24->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__clkinv_16 |Circuit 2: sky130_fd_sc_hd__clkinv_16
-------------------------------------------|-------------------------------------------
Y |Y
A |A
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__clkinv_16 and sky130_fd_sc_hd__clkinv_16 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2o_1 |Circuit 2: sky130_fd_sc_hd__a2bb2o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2o_1 |Circuit 2: sky130_fd_sc_hd__a2bb2o_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
A1_N |A1_N
A2_N |A2_N
X |X
B2 |B2
B1 |B1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2bb2o_1 and sky130_fd_sc_hd__a2bb2o_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or4bb_1 |Circuit 2: sky130_fd_sc_hd__or4bb_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (7) |sky130_fd_pr__nfet_01v8 (7)
sky130_fd_pr__pfet_01v8_hvt (7) |sky130_fd_pr__pfet_01v8_hvt (7)
Number of devices: 14 |Number of devices: 14
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or4bb_1 |Circuit 2: sky130_fd_sc_hd__or4bb_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
B |B
A |A
X |X
D_N |D_N
C_N |C_N
VGND |VGND
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or4bb_1 and sky130_fd_sc_hd__or4bb_1 are equivalent.
Class QI_sky130_fd_sc_hd__a221oi_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__a221oi_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a221oi_4 |Circuit 2: sky130_fd_sc_hd__a221oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a221oi_4 |Circuit 2: sky130_fd_sc_hd__a221oi_4
-------------------------------------------|-------------------------------------------
VGND |VGND
VPB |VPB
VNB |VNB
B1 |B1
C1 |C1
A1 |A1
A2 |A2
VPWR |VPWR
B2 |B2
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a221oi_4 and sky130_fd_sc_hd__a221oi_4 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o211ai_1 |Circuit 2: sky130_fd_sc_hd__o211ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o211ai_1 |Circuit 2: sky130_fd_sc_hd__o211ai_1
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
VPWR |VPWR
A2 |A2
A1 |A1
VGND |VGND
C1 |C1
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o211ai_1 and sky130_fd_sc_hd__o211ai_1 are equivalent.
Class QI_sky130_fd_sc_hd__or4bb_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__or4bb_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or4bb_4 |Circuit 2: sky130_fd_sc_hd__or4bb_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->7) |sky130_fd_pr__pfet_01v8_hvt (10->7)
sky130_fd_pr__nfet_01v8 (10->7) |sky130_fd_pr__nfet_01v8 (10->7)
Number of devices: 14 |Number of devices: 14
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or4bb_4 |Circuit 2: sky130_fd_sc_hd__or4bb_4
-------------------------------------------|-------------------------------------------
X |X
B |B
A |A
D_N |D_N
C_N |C_N
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or4bb_4 and sky130_fd_sc_hd__or4bb_4 are equivalent.
Class QI_sky130_fd_sc_hd__a2bb2o_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__a2bb2o_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2o_4 |Circuit 2: sky130_fd_sc_hd__a2bb2o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2o_4 |Circuit 2: sky130_fd_sc_hd__a2bb2o_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
A2_N |A2_N
X |X
A1_N |A1_N
B2 |B2
B1 |B1
VNB |VNB
VPB |VPB
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2bb2o_4 and sky130_fd_sc_hd__a2bb2o_4 are equivalent.
Class QI_sky130_fd_sc_hd__o22a_4 (0): Merged 14 parallel devices.
Class sky130_fd_sc_hd__o22a_4 (1): Merged 14 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o22a_4 |Circuit 2: sky130_fd_sc_hd__o22a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
sky130_fd_pr__nfet_01v8 (12->5) |sky130_fd_pr__nfet_01v8 (12->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o22a_4 |Circuit 2: sky130_fd_sc_hd__o22a_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
A2 |A2
X |X
B1 |B1
A1 |A1
B2 |B2
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o22a_4 and sky130_fd_sc_hd__o22a_4 are equivalent.
Class QI_sky130_fd_sc_hd__and4_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__and4_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__and4_4 |Circuit 2: sky130_fd_sc_hd__and4_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__and4_4 |Circuit 2: sky130_fd_sc_hd__and4_4
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
C |C
D |D
B |B
A |A
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__and4_4 and sky130_fd_sc_hd__and4_4 are equivalent.
Class QI_sky130_fd_sc_hd__or4b_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__or4b_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or4b_2 |Circuit 2: sky130_fd_sc_hd__or4b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or4b_2 |Circuit 2: sky130_fd_sc_hd__or4b_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VNB |VNB
VPB |VPB
X |X
D_N |D_N
B |B
C |C
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or4b_2 and sky130_fd_sc_hd__or4b_2 are equivalent.
Class QI_sky130_fd_sc_hd__a22oi_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__a22oi_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a22oi_2 |Circuit 2: sky130_fd_sc_hd__a22oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a22oi_2 |Circuit 2: sky130_fd_sc_hd__a22oi_2
-------------------------------------------|-------------------------------------------
VGND |VGND
A2 |A2
A1 |A1
VPWR |VPWR
B1 |B1
B2 |B2
VNB |VNB
Y |Y
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a22oi_2 and sky130_fd_sc_hd__a22oi_2 are equivalent.
Class QI_sky130_fd_sc_hd__nand4_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__nand4_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__nand4_4 |Circuit 2: sky130_fd_sc_hd__nand4_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__nand4_4 |Circuit 2: sky130_fd_sc_hd__nand4_4
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VPWR |VPWR
VPB |VPB
VNB |VNB
A |A
B |B
C |C
D |D
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__nand4_4 and sky130_fd_sc_hd__nand4_4 are equivalent.
Class QI_sky130_fd_sc_hd__o2111ai_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__o2111ai_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o2111ai_4 |Circuit 2: sky130_fd_sc_hd__o2111ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o2111ai_4 |Circuit 2: sky130_fd_sc_hd__o2111ai_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VNB |VNB
Y |Y
VPB |VPB
B1 |B1
C1 |C1
A1 |A1
VGND |VGND
A2 |A2
D1 |D1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o2111ai_4 and sky130_fd_sc_hd__o2111ai_4 are equivalent.
Class QI_sky130_fd_sc_hd__o22ai_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__o22ai_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o22ai_4 |Circuit 2: sky130_fd_sc_hd__o22ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o22ai_4 |Circuit 2: sky130_fd_sc_hd__o22ai_4
-------------------------------------------|-------------------------------------------
B2 |B2
A2 |A2
VGND |VGND
B1 |B1
A1 |A1
VPWR |VPWR
Y |Y
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o22ai_4 and sky130_fd_sc_hd__o22ai_4 are equivalent.
Class QI_sky130_fd_sc_hd__a32oi_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__a32oi_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a32oi_4 |Circuit 2: sky130_fd_sc_hd__a32oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a32oi_4 |Circuit 2: sky130_fd_sc_hd__a32oi_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VNB |VNB
VPB |VPB
Y |Y
A1 |A1
B1 |B1
B2 |B2
A3 |A3
A2 |A2
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a32oi_4 and sky130_fd_sc_hd__a32oi_4 are equivalent.
Class QI_sky130_fd_sc_hd__o2bb2ai_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__o2bb2ai_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o2bb2ai_2 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o2bb2ai_2 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_2
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VPWR |VPWR
A1_N |A1_N
B2 |B2
A2_N |A2_N
B1 |B1
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o2bb2ai_2 and sky130_fd_sc_hd__o2bb2ai_2 are equivalent.
Class QI_sky130_fd_sc_hd__or3b_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__or3b_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or3b_2 |Circuit 2: sky130_fd_sc_hd__or3b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->5) |sky130_fd_pr__pfet_01v8_hvt (6->5)
sky130_fd_pr__nfet_01v8 (6->5) |sky130_fd_pr__nfet_01v8 (6->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or3b_2 |Circuit 2: sky130_fd_sc_hd__or3b_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
VPWR |VPWR
B |B
X |X
C_N |C_N
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or3b_2 and sky130_fd_sc_hd__or3b_2 are equivalent.
Class QI_sky130_fd_sc_hd__or3b_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__or3b_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or3b_4 |Circuit 2: sky130_fd_sc_hd__or3b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or3b_4 |Circuit 2: sky130_fd_sc_hd__or3b_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VNB |VNB
VPB |VPB
X |X
B |B
C_N |C_N
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or3b_4 and sky130_fd_sc_hd__or3b_4 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a22oi_1 |Circuit 2: sky130_fd_sc_hd__a22oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a22oi_1 |Circuit 2: sky130_fd_sc_hd__a22oi_1
-------------------------------------------|-------------------------------------------
B1 |B1
A2 |A2
VPWR |VPWR
A1 |A1
VGND |VGND
B2 |B2
Y |Y
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a22oi_1 and sky130_fd_sc_hd__a22oi_1 are equivalent.
Class QI_sky130_fd_sc_hd__or2_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__or2_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__or2_4 |Circuit 2: sky130_fd_sc_hd__or2_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__or2_4 |Circuit 2: sky130_fd_sc_hd__or2_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VGND |VGND
VNB |VNB
B |B
X |X
VPWR |VPWR
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__or2_4 and sky130_fd_sc_hd__or2_4 are equivalent.
Class QI_sky130_fd_sc_hd__and4bb_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__and4bb_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__and4bb_4 |Circuit 2: sky130_fd_sc_hd__and4bb_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->7) |sky130_fd_pr__pfet_01v8_hvt (10->7)
sky130_fd_pr__nfet_01v8 (10->7) |sky130_fd_pr__nfet_01v8 (10->7)
Number of devices: 14 |Number of devices: 14
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__and4bb_4 |Circuit 2: sky130_fd_sc_hd__and4bb_4
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
C |C
D |D
B_N |B_N
A_N |A_N
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__and4bb_4 and sky130_fd_sc_hd__and4bb_4 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o41ai_1 |Circuit 2: sky130_fd_sc_hd__o41ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o41ai_1 |Circuit 2: sky130_fd_sc_hd__o41ai_1
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
VPB |VPB
VNB |VNB
A2 |A2
A1 |A1
A3 |A3
A4 |A4
VPWR |VPWR
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o41ai_1 and sky130_fd_sc_hd__o41ai_1 are equivalent.
Class QI_sky130_fd_sc_hd__a32o_2 (0): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a32o_2 |Circuit 2: sky130_fd_sc_hd__a32o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a32o_2 |Circuit 2: sky130_fd_sc_hd__a32o_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
A2 |A2
B2 |B2
A1 |A1
B1 |B1
A3 |A3
X |X
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a32o_2 and sky130_fd_sc_hd__a32o_2 are equivalent.
Class QI_sky130_fd_sc_hd__a32o_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__a32o_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a32o_4 |Circuit 2: sky130_fd_sc_hd__a32o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a32o_4 |Circuit 2: sky130_fd_sc_hd__a32o_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
B2 |B2
A1 |A1
B1 |B1
A3 |A3
A2 |A2
X |X
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a32o_4 and sky130_fd_sc_hd__a32o_4 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o311ai_1 |Circuit 2: sky130_fd_sc_hd__o311ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o311ai_1 |Circuit 2: sky130_fd_sc_hd__o311ai_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
Y |Y
B1 |B1
C1 |C1
A3 |A3
A2 |A2
A1 |A1
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o311ai_1 and sky130_fd_sc_hd__o311ai_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__nor4b_1 |Circuit 2: sky130_fd_sc_hd__nor4b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__nor4b_1 |Circuit 2: sky130_fd_sc_hd__nor4b_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
D_N |D_N
A |A
C |C
B |B
VPB |VPB
VGND |VGND
VNB |VNB
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__nor4b_1 and sky130_fd_sc_hd__nor4b_1 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o22ai_1 |Circuit 2: sky130_fd_sc_hd__o22ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o22ai_1 |Circuit 2: sky130_fd_sc_hd__o22ai_1
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
A2 |A2
A1 |A1
VPWR |VPWR
B2 |B2
VGND |VGND
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o22ai_1 and sky130_fd_sc_hd__o22ai_1 are equivalent.
Class QI_sky130_fd_sc_hd__o21bai_4 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__o21bai_4 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o21bai_4 |Circuit 2: sky130_fd_sc_hd__o21bai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o21bai_4 |Circuit 2: sky130_fd_sc_hd__o21bai_4
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
B1_N |B1_N
VNB |VNB
VPB |VPB
Y |Y
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o21bai_4 and sky130_fd_sc_hd__o21bai_4 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a211oi_1 |Circuit 2: sky130_fd_sc_hd__a211oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a211oi_1 |Circuit 2: sky130_fd_sc_hd__a211oi_1
-------------------------------------------|-------------------------------------------
VNB |VNB
Y |Y
VPB |VPB
A2 |A2
C1 |C1
VPWR |VPWR
A1 |A1
B1 |B1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a211oi_1 and sky130_fd_sc_hd__a211oi_1 are equivalent.
Class QI_sky130_fd_sc_hd__a22oi_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__a22oi_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a22oi_4 |Circuit 2: sky130_fd_sc_hd__a22oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a22oi_4 |Circuit 2: sky130_fd_sc_hd__a22oi_4
-------------------------------------------|-------------------------------------------
VPB |VPB
Y |Y
VNB |VNB
VPWR |VPWR
A2 |A2
A1 |A1
B1 |B1
VGND |VGND
B2 |B2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a22oi_4 and sky130_fd_sc_hd__a22oi_4 are equivalent.
Class QI_sky130_fd_sc_hd__a41o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a41o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a41o_2 |Circuit 2: sky130_fd_sc_hd__a41o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a41o_2 |Circuit 2: sky130_fd_sc_hd__a41o_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
A3 |A3
A2 |A2
A4 |A4
B1 |B1
A1 |A1
X |X
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a41o_2 and sky130_fd_sc_hd__a41o_2 are equivalent.
Class QI_sky130_fd_sc_hd__o221ai_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__o221ai_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o221ai_4 |Circuit 2: sky130_fd_sc_hd__o221ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o221ai_4 |Circuit 2: sky130_fd_sc_hd__o221ai_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
B2 |B2
C1 |C1
B1 |B1
VGND |VGND
A2 |A2
A1 |A1
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o221ai_4 and sky130_fd_sc_hd__o221ai_4 are equivalent.
Class QI_sky130_fd_sc_hd__a311o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a311o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a311o_2 |Circuit 2: sky130_fd_sc_hd__a311o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a311o_2 |Circuit 2: sky130_fd_sc_hd__a311o_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
A2 |A2
B1 |B1
A3 |A3
C1 |C1
X |X
A1 |A1
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a311o_2 and sky130_fd_sc_hd__a311o_2 are equivalent.
Class QI_sky130_fd_sc_hd__o41a_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__o41a_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o41a_4 |Circuit 2: sky130_fd_sc_hd__o41a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o41a_4 |Circuit 2: sky130_fd_sc_hd__o41a_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
A2 |A2
A3 |A3
A4 |A4
B1 |B1
X |X
A1 |A1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o41a_4 and sky130_fd_sc_hd__o41a_4 are equivalent.
Class QI_sky130_fd_sc_hd__nand4b_2 (0): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__nand4b_2 |Circuit 2: sky130_fd_sc_hd__nand4b_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (9->5) |sky130_fd_pr__nfet_01v8 (9->5)
sky130_fd_pr__pfet_01v8_hvt (9->5) |sky130_fd_pr__pfet_01v8_hvt (9->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__nand4b_2 |Circuit 2: sky130_fd_sc_hd__nand4b_2
-------------------------------------------|-------------------------------------------
C |C
D |D
B |B
A_N |A_N
VGND |VGND
VPWR |VPWR
Y |Y
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__nand4b_2 and sky130_fd_sc_hd__nand4b_2 are equivalent.
Class QI_sky130_fd_sc_hd__xor2_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__xor2_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__xor2_4 |Circuit 2: sky130_fd_sc_hd__xor2_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__xor2_4 |Circuit 2: sky130_fd_sc_hd__xor2_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
X |X
VPWR |VPWR
A |A
VGND |VGND
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__xor2_4 and sky130_fd_sc_hd__xor2_4 are equivalent.
Class QI_sky130_fd_sc_hd__a2bb2o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a2bb2o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2o_2 |Circuit 2: sky130_fd_sc_hd__a2bb2o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2o_2 |Circuit 2: sky130_fd_sc_hd__a2bb2o_2
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
A1_N |A1_N
X |X
B1 |B1
B2 |B2
A2_N |A2_N
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2bb2o_2 and sky130_fd_sc_hd__a2bb2o_2 are equivalent.
Class QI_sky130_fd_sc_hd__o211ai_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__o211ai_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o211ai_2 |Circuit 2: sky130_fd_sc_hd__o211ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o211ai_2 |Circuit 2: sky130_fd_sc_hd__o211ai_2
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
A2 |A2
C1 |C1
A1 |A1
B1 |B1
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o211ai_2 and sky130_fd_sc_hd__o211ai_2 are equivalent.
Class QI_sky130_fd_sc_hd__o311ai_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__o311ai_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o311ai_4 |Circuit 2: sky130_fd_sc_hd__o311ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o311ai_4 |Circuit 2: sky130_fd_sc_hd__o311ai_4
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
A1 |A1
A3 |A3
A2 |A2
B1 |B1
C1 |C1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o311ai_4 and sky130_fd_sc_hd__o311ai_4 are equivalent.
Class QI_sky130_fd_sc_hd__a2bb2oi_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__a2bb2oi_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2oi_4 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2oi_4 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_4
-------------------------------------------|-------------------------------------------
VGND |VGND
VPB |VPB
VNB |VNB
A1_N |A1_N
A2_N |A2_N
B2 |B2
B1 |B1
Y |Y
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2bb2oi_4 and sky130_fd_sc_hd__a2bb2oi_4 are equivalent.
Class QI_sky130_fd_sc_hd__a2bb2oi_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__a2bb2oi_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2oi_2 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2oi_2 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
B2 |B2
A2_N |A2_N
A1_N |A1_N
B1 |B1
Y |Y
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2bb2oi_2 and sky130_fd_sc_hd__a2bb2oi_2 are equivalent.
Class QI_sky130_fd_sc_hd__o311a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o311a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o311a_2 |Circuit 2: sky130_fd_sc_hd__o311a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o311a_2 |Circuit 2: sky130_fd_sc_hd__o311a_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
X |X
A2 |A2
B1 |B1
A3 |A3
A1 |A1
C1 |C1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o311a_2 and sky130_fd_sc_hd__o311a_2 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o221ai_1 |Circuit 2: sky130_fd_sc_hd__o221ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o221ai_1 |Circuit 2: sky130_fd_sc_hd__o221ai_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
Y |Y
B1 |B1
C1 |C1
VGND |VGND
A1 |A1
A2 |A2
B2 |B2
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o221ai_1 and sky130_fd_sc_hd__o221ai_1 are equivalent.
Class QI_sky130_fd_sc_hd__o211a_4 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__o211a_4 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o211a_4 |Circuit 2: sky130_fd_sc_hd__o211a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (12->7) |sky130_fd_pr__nfet_01v8 (12->7)
sky130_fd_pr__pfet_01v8_hvt (12->7) |sky130_fd_pr__pfet_01v8_hvt (12->7)
Number of devices: 14 |Number of devices: 14
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o211a_4 |Circuit 2: sky130_fd_sc_hd__o211a_4
-------------------------------------------|-------------------------------------------
X |X
VPWR |VPWR
VPB |VPB
VNB |VNB
B1 |B1
C1 |C1
A2 |A2
VGND |VGND
A1 |A1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o211a_4 and sky130_fd_sc_hd__o211a_4 are equivalent.
Class QI_sky130_fd_sc_hd__o311a_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__o311a_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o311a_4 |Circuit 2: sky130_fd_sc_hd__o311a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o311a_4 |Circuit 2: sky130_fd_sc_hd__o311a_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
C1 |C1
B1 |B1
A1 |A1
X |X
A2 |A2
A3 |A3
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o311a_4 and sky130_fd_sc_hd__o311a_4 are equivalent.
Class QI_sky130_fd_sc_hd__a41oi_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__a41oi_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a41oi_2 |Circuit 2: sky130_fd_sc_hd__a41oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a41oi_2 |Circuit 2: sky130_fd_sc_hd__a41oi_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
Y |Y
A1 |A1
B1 |B1
VGND |VGND
A3 |A3
A2 |A2
A4 |A4
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a41oi_2 and sky130_fd_sc_hd__a41oi_2 are equivalent.
Class QI_sky130_fd_sc_hd__o41a_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__o41a_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o41a_2 |Circuit 2: sky130_fd_sc_hd__o41a_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o41a_2 |Circuit 2: sky130_fd_sc_hd__o41a_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
B1 |B1
A3 |A3
A2 |A2
A1 |A1
A4 |A4
X |X
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o41a_2 and sky130_fd_sc_hd__o41a_2 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2oi_1 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2bb2oi_1 |Circuit 2: sky130_fd_sc_hd__a2bb2oi_1
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VPWR |VPWR
A2_N |A2_N
B1 |B1
B2 |B2
A1_N |A1_N
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2bb2oi_1 and sky130_fd_sc_hd__a2bb2oi_1 are equivalent.
Class QI_sky130_fd_sc_hd__nor4b_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__nor4b_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__nor4b_4 |Circuit 2: sky130_fd_sc_hd__nor4b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (17->5) |sky130_fd_pr__nfet_01v8 (17->5)
sky130_fd_pr__pfet_01v8_hvt (17->5) |sky130_fd_pr__pfet_01v8_hvt (17->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__nor4b_4 |Circuit 2: sky130_fd_sc_hd__nor4b_4
-------------------------------------------|-------------------------------------------
C |C
A |A
B |B
D_N |D_N
VPWR |VPWR
Y |Y
VPB |VPB
VGND |VGND
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__nor4b_4 and sky130_fd_sc_hd__nor4b_4 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o32ai_1 |Circuit 2: sky130_fd_sc_hd__o32ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o32ai_1 |Circuit 2: sky130_fd_sc_hd__o32ai_1
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
B2 |B2
VPWR |VPWR
A1 |A1
A2 |A2
A3 |A3
B1 |B1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o32ai_1 and sky130_fd_sc_hd__o32ai_1 are equivalent.
Class QI_sky130_fd_sc_hd__nor3b_4 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__nor3b_4 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__nor3b_4 |Circuit 2: sky130_fd_sc_hd__nor3b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__nor3b_4 |Circuit 2: sky130_fd_sc_hd__nor3b_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
A |A
B |B
C_N |C_N
VPB |VPB
VGND |VGND
Y |Y
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__nor3b_4 and sky130_fd_sc_hd__nor3b_4 are equivalent.
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_4 in circuit QI_RAM128 (0)(153 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4bb_2 in circuit QI_RAM128 (0)(48 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__dfxtp_1 in circuit QI_RAM128 (0)(128 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__diode_2 in circuit QI_RAM128 (0)(770 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_12 in circuit QI_RAM128 (0)(475 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_8 in circuit QI_RAM128 (0)(55 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_2 in circuit QI_RAM128 (0)(348 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_16 in circuit QI_RAM128 (0)(160 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_4 in circuit QI_RAM128 (0)(30 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_6 in circuit QI_RAM128 (0)(12 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_3 in circuit QI_RAM128 (0)(62 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4b_2 in circuit QI_RAM128 (0)(48 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__conb_1 in circuit QI_RAM128 (0)(16 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4_2 in circuit QI_RAM128 (0)(16 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor3b_2 in circuit QI_RAM128 (0)(5 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3b_2 in circuit QI_RAM128 (0)(10 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3_2 in circuit QI_RAM128 (0)(5 instances)
Flattening instances of sky130_fd_sc_hd__clkbuf_16 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4b_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__conb_1 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__dfxtp_1 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__diode_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor3b_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4bb_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_12 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3b_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_2 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_4 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_3 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_4 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_6 in cell RAM128 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_8 in cell RAM128 (1) makes a better match
Making another compare attempt.
Class QI_RAM128 (0): Merged 9323 parallel devices.
Class RAM128 (1): Merged 1665 parallel devices.
Subcircuit summary:
Circuit 1: QI_RAM128 |Circuit 2: RAM128
-------------------------------------------|-------------------------------------------
QI_sky130_fd_sc_hd__ebufn_2 (4224) |sky130_fd_sc_hd__ebufn_2 (4224)
sky130_fd_pr__pfet_01v8_hvt (8115->3653) |sky130_fd_pr__pfet_01v8_hvt (8115->3653)
sky130_fd_pr__nfet_01v8 (8115->3653) |sky130_fd_pr__nfet_01v8 (8115->3653)
QI_sky130_fd_sc_hd__dlclkp_1 (512) |sky130_fd_sc_hd__dlclkp_1 (512)
QI_sky130_fd_sc_hd__dlxtp_1 (4096) |sky130_fd_sc_hd__dlxtp_1 (4096)
QI_sky130_fd_sc_hd__inv_1 (1024) |sky130_fd_sc_hd__inv_1 (1024)
QI_sky130_fd_sc_hd__and2_1 (512) |sky130_fd_sc_hd__and2_1 (512)
sky130_fd_pr__diode_pw2nd_05v5 (770->386) |sky130_fd_pr__diode_pw2nd_05v5 (770->386)
QI_sky130_fd_sc_hd__mux4_1 (32) |sky130_fd_sc_hd__mux4_1 (32)
sky130_fd_pr__res_generic_po (32->17) |sky130_fd_pr__res_generic_po (32->17)
QI_sky130_fd_sc_hd__nor4b_2 (16) |sky130_fd_sc_hd__nor4b_2 (16)
Number of devices: 18125 |Number of devices: 18125
Number of nets: 10036 |Number of nets: 10036
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_RAM128 |Circuit 2: RAM128
-------------------------------------------|-------------------------------------------
Do0[22] |Do0[22]
Do0[28] |Do0[28]
Do0[30] |Do0[30]
Do0[1] |Do0[1]
Do0[3] |Do0[3]
Do0[9] |Do0[9]
Do0[5] |Do0[5]
Do0[11] |Do0[11]
Do0[17] |Do0[17]
Do0[7] |Do0[7]
Do0[13] |Do0[13]
Do0[19] |Do0[19]
Do0[25] |Do0[25]
Do0[15] |Do0[15]
Do0[21] |Do0[21]
Do0[27] |Do0[27]
Do0[23] |Do0[23]
Do0[29] |Do0[29]
Do0[0] |Do0[0]
Do0[31] |Do0[31]
Do0[2] |Do0[2]
Do0[8] |Do0[8]
Do0[4] |Do0[4]
Do0[10] |Do0[10]
Do0[16] |Do0[16]
Do0[6] |Do0[6]
Do0[12] |Do0[12]
Do0[18] |Do0[18]
Do0[24] |Do0[24]
Do0[14] |Do0[14]
Do0[20] |Do0[20]
Do0[26] |Do0[26]
VPWR |VPWR
VGND |VGND
EN0 |EN0
CLK |CLK
A0[3] |A0[3]
A0[4] |A0[4]
A0[0] |A0[0]
A0[1] |A0[1]
A0[2] |A0[2]
WE0[0] |WE0[0]
WE0[1] |WE0[1]
WE0[2] |WE0[2]
WE0[3] |WE0[3]
Di0[15] |Di0[15]
Di0[9] |Di0[9]
Di0[25] |Di0[25]
Di0[16] |Di0[16]
Di0[26] |Di0[26]
Di0[17] |Di0[17]
Di0[0] |Di0[0]
Di0[27] |Di0[27]
Di0[18] |Di0[18]
Di0[1] |Di0[1]
Di0[28] |Di0[28]
Di0[19] |Di0[19]
Di0[2] |Di0[2]
Di0[29] |Di0[29]
Di0[3] |Di0[3]
Di0[10] |Di0[10]
Di0[4] |Di0[4]
Di0[20] |Di0[20]
Di0[30] |Di0[30]
Di0[11] |Di0[11]
Di0[5] |Di0[5]
Di0[21] |Di0[21]
Di0[31] |Di0[31]
Di0[12] |Di0[12]
Di0[6] |Di0[6]
Di0[22] |Di0[22]
Di0[13] |Di0[13]
Di0[7] |Di0[7]
Di0[23] |Di0[23]
Di0[14] |Di0[14]
Di0[8] |Di0[8]
Di0[24] |Di0[24]
A0[5] |A0[5]
A0[6] |A0[6]
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_RAM128 and RAM128 are equivalent.
Class QI_sky130_fd_sc_hd__xnor2_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__xnor2_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__xnor2_4 |Circuit 2: sky130_fd_sc_hd__xnor2_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__xnor2_4 |Circuit 2: sky130_fd_sc_hd__xnor2_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
A |A
B |B
VPWR |VPWR
VGND |VGND
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__xnor2_4 and sky130_fd_sc_hd__xnor2_4 are equivalent.
Class QI_sky130_fd_sc_hd__a2111oi_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__a2111oi_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2111oi_4 |Circuit 2: sky130_fd_sc_hd__a2111oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2111oi_4 |Circuit 2: sky130_fd_sc_hd__a2111oi_4
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
A1 |A1
A2 |A2
C1 |C1
D1 |D1
B1 |B1
VPB |VPB
Y |Y
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2111oi_4 and sky130_fd_sc_hd__a2111oi_4 are equivalent.
Class QI_sky130_fd_sc_hd__a311o_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__a311o_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a311o_4 |Circuit 2: sky130_fd_sc_hd__a311o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a311o_4 |Circuit 2: sky130_fd_sc_hd__a311o_4
-------------------------------------------|-------------------------------------------
X |X
A1 |A1
B1 |B1
A2 |A2
A3 |A3
C1 |C1
VNB |VNB
VPB |VPB
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a311o_4 and sky130_fd_sc_hd__a311o_4 are equivalent.
Class QI_sky130_fd_sc_hd__a221oi_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__a221oi_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a221oi_2 |Circuit 2: sky130_fd_sc_hd__a221oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a221oi_2 |Circuit 2: sky130_fd_sc_hd__a221oi_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VPB |VPB
VNB |VNB
VPWR |VPWR
A1 |A1
B1 |B1
A2 |A2
C1 |C1
B2 |B2
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a221oi_2 and sky130_fd_sc_hd__a221oi_2 are equivalent.
Class QI_sky130_fd_sc_hd__o22ai_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__o22ai_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o22ai_2 |Circuit 2: sky130_fd_sc_hd__o22ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o22ai_2 |Circuit 2: sky130_fd_sc_hd__o22ai_2
-------------------------------------------|-------------------------------------------
B2 |B2
VPWR |VPWR
B1 |B1
A2 |A2
VGND |VGND
A1 |A1
Y |Y
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o22ai_2 and sky130_fd_sc_hd__o22ai_2 are equivalent.
Class QI_sky130_fd_sc_hd__a31oi_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__a31oi_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a31oi_2 |Circuit 2: sky130_fd_sc_hd__a31oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a31oi_2 |Circuit 2: sky130_fd_sc_hd__a31oi_2
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
Y |Y
VPWR |VPWR
VGND |VGND
A1 |A1
B1 |B1
A3 |A3
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a31oi_2 and sky130_fd_sc_hd__a31oi_2 are equivalent.
Class QI_sky130_fd_sc_hd__o41ai_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__o41ai_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o41ai_2 |Circuit 2: sky130_fd_sc_hd__o41ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o41ai_2 |Circuit 2: sky130_fd_sc_hd__o41ai_2
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
A1 |A1
A3 |A3
A2 |A2
A4 |A4
B1 |B1
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o41ai_2 and sky130_fd_sc_hd__o41ai_2 are equivalent.
Class QI_sky130_fd_sc_hd__o31ai_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__o31ai_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o31ai_4 |Circuit 2: sky130_fd_sc_hd__o31ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o31ai_4 |Circuit 2: sky130_fd_sc_hd__o31ai_4
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
A2 |A2
A1 |A1
VPWR |VPWR
B1 |B1
A3 |A3
VGND |VGND
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o31ai_4 and sky130_fd_sc_hd__o31ai_4 are equivalent.
Class QI_sky130_fd_sc_hd__o2111a_4 (0): Merged 12 parallel devices.
Class sky130_fd_sc_hd__o2111a_4 (1): Merged 12 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o2111a_4 |Circuit 2: sky130_fd_sc_hd__o2111a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->8) |sky130_fd_pr__nfet_01v8 (14->8)
sky130_fd_pr__pfet_01v8_hvt (14->8) |sky130_fd_pr__pfet_01v8_hvt (14->8)
Number of devices: 16 |Number of devices: 16
Number of nets: 17 |Number of nets: 17
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o2111a_4 |Circuit 2: sky130_fd_sc_hd__o2111a_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
X |X
D1 |D1
VNB |VNB
VPB |VPB
VGND |VGND
A2 |A2
A1 |A1
B1 |B1
C1 |C1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o2111a_4 and sky130_fd_sc_hd__o2111a_4 are equivalent.
Class QI_sky130_fd_sc_hd__o2bb2a_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__o2bb2a_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o2bb2a_4 |Circuit 2: sky130_fd_sc_hd__o2bb2a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o2bb2a_4 |Circuit 2: sky130_fd_sc_hd__o2bb2a_4
-------------------------------------------|-------------------------------------------
VGND |VGND
A2_N |A2_N
X |X
A1_N |A1_N
B2 |B2
B1 |B1
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o2bb2a_4 and sky130_fd_sc_hd__o2bb2a_4 are equivalent.
Class QI_sky130_fd_sc_hd__a41o_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__a41o_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a41o_4 |Circuit 2: sky130_fd_sc_hd__a41o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a41o_4 |Circuit 2: sky130_fd_sc_hd__a41o_4
-------------------------------------------|-------------------------------------------
VGND |VGND
VPB |VPB
VNB |VNB
VPWR |VPWR
A3 |A3
A2 |A2
A1 |A1
B1 |B1
X |X
A4 |A4
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a41o_4 and sky130_fd_sc_hd__a41o_4 are equivalent.
Class QI_sky130_fd_sc_hd__a32oi_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__a32oi_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a32oi_2 |Circuit 2: sky130_fd_sc_hd__a32oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a32oi_2 |Circuit 2: sky130_fd_sc_hd__a32oi_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VNB |VNB
VPB |VPB
B1 |B1
A1 |A1
A3 |A3
A2 |A2
VGND |VGND
B2 |B2
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a32oi_2 and sky130_fd_sc_hd__a32oi_2 are equivalent.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a32oi_1 |Circuit 2: sky130_fd_sc_hd__a32oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a32oi_1 |Circuit 2: sky130_fd_sc_hd__a32oi_1
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
A1 |A1
A2 |A2
A3 |A3
B1 |B1
VGND |VGND
B2 |B2
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a32oi_1 and sky130_fd_sc_hd__a32oi_1 are equivalent.
Flattening unmatched subcell QI_sky130_fd_sc_hd__diode_2 in circuit QI_RAM256 (0)(1604 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4_2 in circuit QI_RAM256 (0)(32 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_12 in circuit QI_RAM256 (0)(1319 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__dfxtp_1 in circuit QI_RAM256 (0)(256 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_4 in circuit QI_RAM256 (0)(306 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3b_2 in circuit QI_RAM256 (0)(20 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_16 in circuit QI_RAM256 (0)(320 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_3 in circuit QI_RAM256 (0)(148 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_2 in circuit QI_RAM256 (0)(700 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4bb_2 in circuit QI_RAM256 (0)(96 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_8 in circuit QI_RAM256 (0)(102 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4b_2 in circuit QI_RAM256 (0)(96 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_4 in circuit QI_RAM256 (0)(25 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3_2 in circuit QI_RAM256 (0)(10 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_6 in circuit QI_RAM256 (0)(54 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__mux2_1 in circuit QI_RAM256 (0)(32 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__conb_1 in circuit QI_RAM256 (0)(32 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor3b_2 in circuit QI_RAM256 (0)(10 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and2b_2 in circuit QI_RAM256 (0)(1 instance)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and2_2 in circuit QI_RAM256 (0)(1 instance)
Flattening instances of sky130_fd_sc_hd__clkbuf_16 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4b_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__conb_1 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__mux2_1 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__dfxtp_1 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__diode_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor3b_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4bb_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2b_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_12 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3b_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_2 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_4 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_3 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_4 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_6 in cell RAM256 (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_8 in cell RAM256 (1) makes a better match
Making another compare attempt.
Class QI_RAM256 (0): Merged 19421 parallel devices.
Class RAM256 (1): Merged 4093 parallel devices.
Subcircuit summary:
Circuit 1: QI_RAM256 |Circuit 2: RAM256
-------------------------------------------|-------------------------------------------
QI_sky130_fd_sc_hd__and2_1 (1024) |sky130_fd_sc_hd__and2_1 (1024)
QI_sky130_fd_sc_hd__dlxtp_1 (8192) |sky130_fd_sc_hd__dlxtp_1 (8192)
QI_sky130_fd_sc_hd__ebufn_2 (8448) |sky130_fd_sc_hd__ebufn_2 (8448)
QI_sky130_fd_sc_hd__dlclkp_1 (1024) |sky130_fd_sc_hd__dlclkp_1 (1024)
sky130_fd_pr__diode_pw2nd_05v5 (1604->836) |sky130_fd_pr__diode_pw2nd_05v5 (1604->836)
sky130_fd_pr__nfet_01v8 (16823->7512) |sky130_fd_pr__nfet_01v8 (16823->7512)
sky130_fd_pr__pfet_01v8_hvt (16823->7512) |sky130_fd_pr__pfet_01v8_hvt (16823->7512)
QI_sky130_fd_sc_hd__inv_1 (2048) |sky130_fd_sc_hd__inv_1 (2048)
QI_sky130_fd_sc_hd__mux4_1 (64) |sky130_fd_sc_hd__mux4_1 (64)
QI_sky130_fd_sc_hd__nor4b_2 (32) |sky130_fd_sc_hd__nor4b_2 (32)
sky130_fd_pr__res_generic_po (64->33) |sky130_fd_pr__res_generic_po (64->33)
Number of devices: 36725 |Number of devices: 36725
Number of nets: 20264 |Number of nets: 20264
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_RAM256 |Circuit 2: RAM256
-------------------------------------------|-------------------------------------------
A0[7] |A0[7]
A0[5] |A0[5]
A0[6] |A0[6]
CLK |CLK
A0[3] |A0[3]
A0[4] |A0[4]
A0[0] |A0[0]
A0[1] |A0[1]
A0[2] |A0[2]
WE0[0] |WE0[0]
WE0[1] |WE0[1]
WE0[2] |WE0[2]
WE0[3] |WE0[3]
Di0[15] |Di0[15]
Di0[25] |Di0[25]
Di0[0] |Di0[0]
Di0[16] |Di0[16]
Di0[26] |Di0[26]
Di0[1] |Di0[1]
Di0[17] |Di0[17]
Di0[27] |Di0[27]
Di0[2] |Di0[2]
Di0[18] |Di0[18]
Di0[28] |Di0[28]
Di0[3] |Di0[3]
Di0[19] |Di0[19]
Di0[29] |Di0[29]
Di0[4] |Di0[4]
Di0[5] |Di0[5]
Di0[10] |Di0[10]
Di0[20] |Di0[20]
Di0[30] |Di0[30]
Di0[6] |Di0[6]
Di0[11] |Di0[11]
Di0[21] |Di0[21]
Di0[31] |Di0[31]
Di0[9] |Di0[9]
Di0[13] |Di0[13]
Di0[23] |Di0[23]
Di0[7] |Di0[7]
Di0[12] |Di0[12]
Di0[22] |Di0[22]
Di0[14] |Di0[14]
Di0[24] |Di0[24]
Di0[8] |Di0[8]
EN0 |EN0
Do0[22] |Do0[22]
Do0[28] |Do0[28]
Do0[30] |Do0[30]
Do0[1] |Do0[1]
Do0[3] |Do0[3]
Do0[9] |Do0[9]
Do0[5] |Do0[5]
Do0[11] |Do0[11]
Do0[17] |Do0[17]
Do0[7] |Do0[7]
Do0[13] |Do0[13]
Do0[19] |Do0[19]
Do0[25] |Do0[25]
Do0[15] |Do0[15]
Do0[21] |Do0[21]
Do0[27] |Do0[27]
Do0[23] |Do0[23]
Do0[29] |Do0[29]
Do0[0] |Do0[0]
Do0[31] |Do0[31]
Do0[2] |Do0[2]
Do0[8] |Do0[8]
Do0[4] |Do0[4]
Do0[10] |Do0[10]
Do0[16] |Do0[16]
Do0[6] |Do0[6]
Do0[12] |Do0[12]
Do0[18] |Do0[18]
Do0[24] |Do0[24]
Do0[14] |Do0[14]
Do0[20] |Do0[20]
Do0[26] |Do0[26]
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_RAM256 and RAM256 are equivalent.
Class QI_sky130_fd_sc_hd__o21bai_2 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__o21bai_2 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o21bai_2 |Circuit 2: sky130_fd_sc_hd__o21bai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o21bai_2 |Circuit 2: sky130_fd_sc_hd__o21bai_2
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
Y |Y
VPWR |VPWR
VGND |VGND
B1_N |B1_N
A1 |A1
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o21bai_2 and sky130_fd_sc_hd__o21bai_2 are equivalent.
Class QI_sky130_fd_sc_hd__o2bb2ai_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__o2bb2ai_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o2bb2ai_4 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o2bb2ai_4 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_4
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VPB |VPB
VNB |VNB
VPWR |VPWR
A1_N |A1_N
B2 |B2
B1 |B1
A2_N |A2_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o2bb2ai_4 and sky130_fd_sc_hd__o2bb2ai_4 are equivalent.
Class QI_sky130_fd_sc_hd__o311ai_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__o311ai_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o311ai_2 |Circuit 2: sky130_fd_sc_hd__o311ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o311ai_2 |Circuit 2: sky130_fd_sc_hd__o311ai_2
-------------------------------------------|-------------------------------------------
Y |Y
VNB |VNB
VPB |VPB
A3 |A3
A1 |A1
B1 |B1
C1 |C1
A2 |A2
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o311ai_2 and sky130_fd_sc_hd__o311ai_2 are equivalent.
Class QI_sky130_fd_sc_hd__a2111oi_2 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__a2111oi_2 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a2111oi_2 |Circuit 2: sky130_fd_sc_hd__a2111oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->7) |sky130_fd_pr__pfet_01v8_hvt (10->7)
sky130_fd_pr__nfet_01v8 (10->7) |sky130_fd_pr__nfet_01v8 (10->7)
Number of devices: 14 |Number of devices: 14
Number of nets: 16 |Number of nets: 16
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a2111oi_2 |Circuit 2: sky130_fd_sc_hd__a2111oi_2
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VNB |VNB
VPB |VPB
VPWR |VPWR
B1 |B1
D1 |D1
A2 |A2
A1 |A1
C1 |C1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a2111oi_2 and sky130_fd_sc_hd__a2111oi_2 are equivalent.
Class QI_sky130_fd_sc_hd__o32ai_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__o32ai_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__o32ai_4 |Circuit 2: sky130_fd_sc_hd__o32ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__o32ai_4 |Circuit 2: sky130_fd_sc_hd__o32ai_4
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
VNB |VNB
VPB |VPB
A3 |A3
VPWR |VPWR
B1 |B1
A2 |A2
A1 |A1
B2 |B2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__o32ai_4 and sky130_fd_sc_hd__o32ai_4 are equivalent.
Class QI_sky130_fd_sc_hd__a41oi_4 (0): Merged 30 parallel devices.
Class sky130_fd_sc_hd__a41oi_4 (1): Merged 30 parallel devices.
Subcircuit summary:
Circuit 1: QI_sky130_fd_sc_hd__a41oi_4 |Circuit 2: sky130_fd_sc_hd__a41oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (20->5) |sky130_fd_pr__pfet_01v8_hvt (20->5)
sky130_fd_pr__nfet_01v8 (20->5) |sky130_fd_pr__nfet_01v8 (20->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: QI_sky130_fd_sc_hd__a41oi_4 |Circuit 2: sky130_fd_sc_hd__a41oi_4
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VNB |VNB
A1 |A1
VGND |VGND
B1 |B1
A3 |A3
A4 |A4
A2 |A2
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes QI_sky130_fd_sc_hd__a41oi_4 and sky130_fd_sc_hd__a41oi_4 are equivalent.
Subcircuit summary:
Circuit 1: EQ_sky130_fd_sc_hvl__schmittbuf |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (4) |sky130_fd_pr__nfet_g5v0d10v5 (4)
sky130_fd_pr__pfet_g5v0d10v5 (4) |sky130_fd_pr__pfet_g5v0d10v5 (4)
sky130_fd_pr__res_generic_nd__hv (1) |sky130_fd_pr__res_generic_nd__hv (1)
sky130_fd_pr__res_generic_pd__hv (1) |sky130_fd_pr__res_generic_pd__hv (1)
Number of devices: 10 |Number of devices: 10
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: EQ_sky130_fd_sc_hvl__schmittbuf |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1
-------------------------------------------|-------------------------------------------
A |A
VPB |VPB
VNB |VNB
VGND |VGND
VPWR |VPWR
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes EQ_sky130_fd_sc_hvl__schmittbuf_1 and sky130_fd_sc_hvl__schmittbuf_1 are equivalent.
Class EQ_sky130_fd_sc_hvl__buf_8 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hvl__buf_8 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: EQ_sky130_fd_sc_hvl__buf_8 |Circuit 2: sky130_fd_sc_hvl__buf_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (11->2) |sky130_fd_pr__nfet_g5v0d10v5 (11->2)
sky130_fd_pr__pfet_g5v0d10v5 (11->2) |sky130_fd_pr__pfet_g5v0d10v5 (11->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: EQ_sky130_fd_sc_hvl__buf_8 |Circuit 2: sky130_fd_sc_hvl__buf_8
-------------------------------------------|-------------------------------------------
A |A
VPWR |VPWR
VPB |VPB
X |X
VGND |VGND
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes EQ_sky130_fd_sc_hvl__buf_8 and sky130_fd_sc_hvl__buf_8 are equivalent.
Class EQ_sky130_fd_sc_hvl__inv_8 (0): Merged 14 parallel devices.
Class sky130_fd_sc_hvl__inv_8 (1): Merged 14 parallel devices.
Subcircuit summary:
Circuit 1: EQ_sky130_fd_sc_hvl__inv_8 |Circuit 2: sky130_fd_sc_hvl__inv_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (8->1) |sky130_fd_pr__pfet_g5v0d10v5 (8->1)
sky130_fd_pr__nfet_g5v0d10v5 (8->1) |sky130_fd_pr__nfet_g5v0d10v5 (8->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: EQ_sky130_fd_sc_hvl__inv_8 |Circuit 2: sky130_fd_sc_hvl__inv_8
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
A |A
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes EQ_sky130_fd_sc_hvl__inv_8 and sky130_fd_sc_hvl__inv_8 are equivalent.
Circuit 1 cell sky130_fd_pr__res_xhigh_po and Circuit 2 cell sky130_fd_pr__res_xhigh_po are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__res_xhigh_po |Circuit 2: sky130_fd_pr__res_xhigh_po
-------------------------------------------|-------------------------------------------
1 |1
2 |2
3 |3
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__res_xhigh_po and sky130_fd_pr__res_xhigh_po are equivalent.
Circuit 1 cell sky130_fd_pr__cap_mim_m3_1 and Circuit 2 cell sky130_fd_pr__cap_mim_m3_1 are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__cap_mim_m3_1 |Circuit 2: sky130_fd_pr__cap_mim_m3_1
-------------------------------------------|-------------------------------------------
1 |1
2 |2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__cap_mim_m3_1 and sky130_fd_pr__cap_mim_m3_1 are equivalent.
Circuit 1 cell sky130_fd_pr__cap_mim_m3_2 and Circuit 2 cell sky130_fd_pr__cap_mim_m3_2 are black boxes.
Subcircuit pins:
Circuit 1: sky130_fd_pr__cap_mim_m3_2 |Circuit 2: sky130_fd_pr__cap_mim_m3_2
-------------------------------------------|-------------------------------------------
1 |1
2 |2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_pr__cap_mim_m3_2 and sky130_fd_pr__cap_mim_m3_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfrtp_1 |Circuit 2: sky130_fd_sc_hd__dfrtp_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14) |sky130_fd_pr__nfet_01v8 (14)
sky130_fd_pr__pfet_01v8_hvt (14) |sky130_fd_pr__pfet_01v8_hvt (14)
Number of devices: 28 |Number of devices: 28
Number of nets: 21 |Number of nets: 21
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfrtp_1 |Circuit 2: sky130_fd_sc_hd__dfrtp_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
RESET_B |RESET_B
VPB |VPB
VNB |VNB
VGND |VGND
D |D
Q |Q
CLK |CLK
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfrtp_1 and sky130_fd_sc_hd__dfrtp_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor2_1 |Circuit 2: sky130_fd_sc_hd__nor2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor2_1 |Circuit 2: sky130_fd_sc_hd__nor2_1
-------------------------------------------|-------------------------------------------
Y |Y
A |A
VPB |VPB
VGND |VGND
VNB |VNB
B |B
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor2_1 and sky130_fd_sc_hd__nor2_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand2_1 |Circuit 2: sky130_fd_sc_hd__nand2_1
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
A |A
VPWR |VPWR
VPB |VPB
B |B
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand2_1 and sky130_fd_sc_hd__nand2_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21ai_1 |Circuit 2: sky130_fd_sc_hd__o21ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21ai_1 |Circuit 2: sky130_fd_sc_hd__o21ai_1
-------------------------------------------|-------------------------------------------
A2 |A2
B1 |B1
VPWR |VPWR
A1 |A1
VGND |VGND
Y |Y
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21ai_1 and sky130_fd_sc_hd__o21ai_1 are equivalent.
Class sky130_fd_sc_hd__dfstp_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__dfstp_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfstp_2 |Circuit 2: sky130_fd_sc_hd__dfstp_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (17->16) |sky130_fd_pr__nfet_01v8 (17->16)
sky130_fd_pr__pfet_01v8_hvt (17->16) |sky130_fd_pr__pfet_01v8_hvt (17->16)
Number of devices: 32 |Number of devices: 32
Number of nets: 24 |Number of nets: 24
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfstp_2 |Circuit 2: sky130_fd_sc_hd__dfstp_2
-------------------------------------------|-------------------------------------------
SET_B |SET_B
VPWR |VPWR
VPB |VPB
VNB |VNB
Q |Q
D |D
CLK |CLK
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfstp_2 and sky130_fd_sc_hd__dfstp_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1
-------------------------------------------|-------------------------------------------
Y |Y
VNB |VNB
VPWR |VPWR
VPB |VPB
A_N |A_N
VGND |VGND
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand2b_1 and sky130_fd_sc_hd__nand2b_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand4bb_1 |Circuit 2: sky130_fd_sc_hd__nand4bb_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand4bb_1 |Circuit 2: sky130_fd_sc_hd__nand4bb_1
-------------------------------------------|-------------------------------------------
Y |Y
VPWR |VPWR
VPB |VPB
VNB |VNB
A_N |A_N
B_N |B_N
C |C
D |D
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand4bb_1 and sky130_fd_sc_hd__nand4bb_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfstp_1 |Circuit 2: sky130_fd_sc_hd__dfstp_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16) |sky130_fd_pr__nfet_01v8 (16)
sky130_fd_pr__pfet_01v8_hvt (16) |sky130_fd_pr__pfet_01v8_hvt (16)
Number of devices: 32 |Number of devices: 32
Number of nets: 24 |Number of nets: 24
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfstp_1 |Circuit 2: sky130_fd_sc_hd__dfstp_1
-------------------------------------------|-------------------------------------------
SET_B |SET_B
VPWR |VPWR
VPB |VPB
VNB |VNB
D |D
Q |Q
CLK |CLK
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfstp_1 and sky130_fd_sc_hd__dfstp_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21a_1 |Circuit 2: sky130_fd_sc_hd__o21a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21a_1 |Circuit 2: sky130_fd_sc_hd__o21a_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
A1 |A1
B1 |B1
X |X
A2 |A2
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21a_1 and sky130_fd_sc_hd__o21a_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o2bb2ai_1 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o2bb2ai_1 |Circuit 2: sky130_fd_sc_hd__o2bb2ai_1
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
VPB |VPB
VNB |VNB
A2_N |A2_N
B2 |B2
B1 |B1
A1_N |A1_N
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o2bb2ai_1 and sky130_fd_sc_hd__o2bb2ai_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor3_1 |Circuit 2: sky130_fd_sc_hd__nor3_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor3_1 |Circuit 2: sky130_fd_sc_hd__nor3_1
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
VNB |VNB
VPB |VPB
A |A
B |B
C |C
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor3_1 and sky130_fd_sc_hd__nor3_1 are equivalent.
Class sky130_fd_sc_hd__buf_12 (0): Merged 28 parallel devices.
Class sky130_fd_sc_hd__buf_12 (1): Merged 28 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12
-------------------------------------------|-------------------------------------------
X |X
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__buf_12 and sky130_fd_sc_hd__buf_12 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21oi_1 |Circuit 2: sky130_fd_sc_hd__a21oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21oi_1 |Circuit 2: sky130_fd_sc_hd__a21oi_1
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
Y |Y
A2 |A2
VGND |VGND
A1 |A1
VPWR |VPWR
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21oi_1 and sky130_fd_sc_hd__a21oi_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__xnor2_1 |Circuit 2: sky130_fd_sc_hd__xnor2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__xnor2_1 |Circuit 2: sky130_fd_sc_hd__xnor2_1
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
VPB |VPB
VNB |VNB
VPWR |VPWR
A |A
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__xnor2_1 and sky130_fd_sc_hd__xnor2_1 are equivalent.
Class sky130_fd_sc_hd__o2111ai_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__o2111ai_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o2111ai_2 |Circuit 2: sky130_fd_sc_hd__o2111ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o2111ai_2 |Circuit 2: sky130_fd_sc_hd__o2111ai_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
A2 |A2
A1 |A1
B1 |B1
D1 |D1
VGND |VGND
C1 |C1
Y |Y
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o2111ai_2 and sky130_fd_sc_hd__o2111ai_2 are equivalent.
Class sky130_fd_sc_hd__o31ai_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__o31ai_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o31ai_2 |Circuit 2: sky130_fd_sc_hd__o31ai_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o31ai_2 |Circuit 2: sky130_fd_sc_hd__o31ai_2
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
Y |Y
VGND |VGND
VPWR |VPWR
A1 |A1
A2 |A2
B1 |B1
A3 |A3
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o31ai_2 and sky130_fd_sc_hd__o31ai_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
A |A
B |B
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a41oi_1 |Circuit 2: sky130_fd_sc_hd__a41oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a41oi_1 |Circuit 2: sky130_fd_sc_hd__a41oi_1
-------------------------------------------|-------------------------------------------
Y |Y
VPWR |VPWR
VNB |VNB
VPB |VPB
A3 |A3
A2 |A2
A4 |A4
A1 |A1
VGND |VGND
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a41oi_1 and sky130_fd_sc_hd__a41oi_1 are equivalent.
Class sky130_fd_sc_hd__clkinv_4 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__clkinv_4 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->1) |sky130_fd_pr__pfet_01v8_hvt (6->1)
sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
A |A
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkinv_4 and sky130_fd_sc_hd__clkinv_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfrtn_1 |Circuit 2: sky130_fd_sc_hd__dfrtn_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14) |sky130_fd_pr__nfet_01v8 (14)
sky130_fd_pr__pfet_01v8_hvt (14) |sky130_fd_pr__pfet_01v8_hvt (14)
Number of devices: 28 |Number of devices: 28
Number of nets: 21 |Number of nets: 21
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfrtn_1 |Circuit 2: sky130_fd_sc_hd__dfrtn_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
RESET_B |RESET_B
VGND |VGND
VPB |VPB
VNB |VNB
D |D
Q |Q
CLK_N |CLK_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfrtn_1 and sky130_fd_sc_hd__dfrtn_1 are equivalent.
Class sky130_fd_sc_hd__inv_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__inv_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4->1) |sky130_fd_pr__pfet_01v8_hvt (4->1)
sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
-------------------------------------------|-------------------------------------------
Y |Y
A |A
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__inv_4 and sky130_fd_sc_hd__inv_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o2111ai_1 |Circuit 2: sky130_fd_sc_hd__o2111ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o2111ai_1 |Circuit 2: sky130_fd_sc_hd__o2111ai_1
-------------------------------------------|-------------------------------------------
VNB |VNB
Y |Y
VPB |VPB
B1 |B1
A2 |A2
VGND |VGND
A1 |A1
D1 |D1
C1 |C1
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o2111ai_1 and sky130_fd_sc_hd__o2111ai_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand3_1 |Circuit 2: sky130_fd_sc_hd__nand3_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand3_1 |Circuit 2: sky130_fd_sc_hd__nand3_1
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
A |A
B |B
C |C
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand3_1 and sky130_fd_sc_hd__nand3_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o31a_1 |Circuit 2: sky130_fd_sc_hd__o31a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o31a_1 |Circuit 2: sky130_fd_sc_hd__o31a_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
A2 |A2
A1 |A1
X |X
B1 |B1
A3 |A3
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o31a_1 and sky130_fd_sc_hd__o31a_1 are equivalent.
Class sky130_fd_sc_hd__nor3_2 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__nor3_2 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor3_2 |Circuit 2: sky130_fd_sc_hd__nor3_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor3_2 |Circuit 2: sky130_fd_sc_hd__nor3_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VNB |VNB
VPB |VPB
B |B
C |C
A |A
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor3_2 and sky130_fd_sc_hd__nor3_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1
-------------------------------------------|-------------------------------------------
A |A
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dlymetal6s2s_1 and sky130_fd_sc_hd__dlymetal6s2s_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21bai_1 |Circuit 2: sky130_fd_sc_hd__o21bai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21bai_1 |Circuit 2: sky130_fd_sc_hd__o21bai_1
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
VGND |VGND
Y |Y
VPWR |VPWR
A1 |A1
A2 |A2
B1_N |B1_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21bai_1 and sky130_fd_sc_hd__o21bai_1 are equivalent.
Class sky130_fd_sc_hd__buf_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__buf_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
-------------------------------------------|-------------------------------------------
X |X
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand3b_1 |Circuit 2: sky130_fd_sc_hd__nand3b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand3b_1 |Circuit 2: sky130_fd_sc_hd__nand3b_1
-------------------------------------------|-------------------------------------------
A_N |A_N
VGND |VGND
B |B
C |C
VNB |VNB
VPWR |VPWR
VPB |VPB
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand3b_1 and sky130_fd_sc_hd__nand3b_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a31o_1 |Circuit 2: sky130_fd_sc_hd__a31o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a31o_1 |Circuit 2: sky130_fd_sc_hd__a31o_1
-------------------------------------------|-------------------------------------------
VGND |VGND
B1 |B1
X |X
A2 |A2
A1 |A1
A3 |A3
VNB |VNB
VPB |VPB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a31o_1 and sky130_fd_sc_hd__a31o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o22a_1 |Circuit 2: sky130_fd_sc_hd__o22a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o22a_1 |Circuit 2: sky130_fd_sc_hd__o22a_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
B1 |B1
X |X
B2 |B2
A1 |A1
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o22a_1 and sky130_fd_sc_hd__o22a_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o31ai_1 |Circuit 2: sky130_fd_sc_hd__o31ai_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o31ai_1 |Circuit 2: sky130_fd_sc_hd__o31ai_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
A3 |A3
B1 |B1
VPWR |VPWR
A1 |A1
A2 |A2
Y |Y
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o31ai_1 and sky130_fd_sc_hd__o31ai_1 are equivalent.
Class sky130_fd_sc_hd__o211ai_4 (0): Merged 20 parallel devices.
Class sky130_fd_sc_hd__o211ai_4 (1): Merged 20 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o211ai_4 |Circuit 2: sky130_fd_sc_hd__o211ai_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
sky130_fd_pr__nfet_01v8 (16->8) |sky130_fd_pr__nfet_01v8 (16->8)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o211ai_4 |Circuit 2: sky130_fd_sc_hd__o211ai_4
-------------------------------------------|-------------------------------------------
VNB |VNB
Y |Y
B1 |B1
C1 |C1
VPB |VPB
A1 |A1
VGND |VGND
A2 |A2
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o211ai_4 and sky130_fd_sc_hd__o211ai_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21o_1 |Circuit 2: sky130_fd_sc_hd__a21o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21o_1 |Circuit 2: sky130_fd_sc_hd__a21o_1
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
VGND |VGND
VPWR |VPWR
A2 |A2
X |X
B1 |B1
A1 |A1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21o_1 and sky130_fd_sc_hd__a21o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor4_1 |Circuit 2: sky130_fd_sc_hd__nor4_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor4_1 |Circuit 2: sky130_fd_sc_hd__nor4_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VNB |VNB
VPB |VPB
A |A
C |C
B |B
D |D
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor4_1 and sky130_fd_sc_hd__nor4_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a2bb2o_1 |Circuit 2: sky130_fd_sc_hd__a2bb2o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a2bb2o_1 |Circuit 2: sky130_fd_sc_hd__a2bb2o_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
A1_N |A1_N
A2_N |A2_N
X |X
B2 |B2
B1 |B1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a2bb2o_1 and sky130_fd_sc_hd__a2bb2o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfbbp_1 |Circuit 2: sky130_fd_sc_hd__dfbbp_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (20) |sky130_fd_pr__nfet_01v8 (20)
sky130_fd_pr__pfet_01v8_hvt (20) |sky130_fd_pr__pfet_01v8_hvt (20)
Number of devices: 40 |Number of devices: 40
Number of nets: 29 |Number of nets: 29
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfbbp_1 |Circuit 2: sky130_fd_sc_hd__dfbbp_1
-------------------------------------------|-------------------------------------------
SET_B |SET_B
VGND |VGND
D |D
RESET_B |RESET_B
Q |Q
Q_N |Q_N
CLK |CLK
VPWR |VPWR
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfbbp_1 and sky130_fd_sc_hd__dfbbp_1 are equivalent.
Class sky130_fd_sc_hd__inv_8 (0): Merged 14 parallel devices.
Class sky130_fd_sc_hd__inv_8 (1): Merged 14 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__inv_8 |Circuit 2: sky130_fd_sc_hd__inv_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->1) |sky130_fd_pr__pfet_01v8_hvt (8->1)
sky130_fd_pr__nfet_01v8 (8->1) |sky130_fd_pr__nfet_01v8 (8->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__inv_8 |Circuit 2: sky130_fd_sc_hd__inv_8
-------------------------------------------|-------------------------------------------
A |A
Y |Y
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__inv_8 and sky130_fd_sc_hd__inv_8 are equivalent.
Class sky130_fd_sc_hd__buf_8 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__buf_8 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (11->2) |sky130_fd_pr__nfet_01v8 (11->2)
sky130_fd_pr__pfet_01v8_hvt (11->2) |sky130_fd_pr__pfet_01v8_hvt (11->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
-------------------------------------------|-------------------------------------------
X |X
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__buf_8 and sky130_fd_sc_hd__buf_8 are equivalent.
Class sky130_fd_sc_hd__buf_6 (0): Merged 12 parallel devices.
Class sky130_fd_sc_hd__buf_6 (1): Merged 12 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
VNB |VNB
A |A
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__buf_6 and sky130_fd_sc_hd__buf_6 are equivalent.
Class sky130_fd_sc_hd__and2_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__and2_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
-------------------------------------------|-------------------------------------------
B |B
A |A
VGND |VGND
X |X
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and2_4 and sky130_fd_sc_hd__and2_4 are equivalent.
Class sky130_fd_sc_hd__and3b_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__and3b_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPWR |VPWR
VPB |VPB
VGND |VGND
X |X
C |C
B |B
A_N |A_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and3b_4 and sky130_fd_sc_hd__and3b_4 are equivalent.
Class sky130_fd_sc_hd__nand2_8 (0): Merged 28 parallel devices.
Class sky130_fd_sc_hd__nand2_8 (1): Merged 28 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
-------------------------------------------|-------------------------------------------
Y |Y
VGND |VGND
A |A
VPWR |VPWR
VPB |VPB
B |B
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand2_8 and sky130_fd_sc_hd__nand2_8 are equivalent.
Class sky130_fd_sc_hd__nand2_4 (0): Merged 12 parallel devices.
Class sky130_fd_sc_hd__nand2_4 (1): Merged 12 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
A |A
VNB |VNB
VPWR |VPWR
VPB |VPB
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand2_4 and sky130_fd_sc_hd__nand2_4 are equivalent.
Class sky130_fd_sc_hd__clkbuf_8 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__clkbuf_8 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2)
sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 7 |Number of nets: 7
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
-------------------------------------------|-------------------------------------------
X |X
VGND |VGND
VNB |VNB
A |A
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and3b_1 |Circuit 2: sky130_fd_sc_hd__and3b_1
-------------------------------------------|-------------------------------------------
VNB |VNB
VPWR |VPWR
VPB |VPB
VGND |VGND
X |X
A_N |A_N
C |C
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and3b_1 and sky130_fd_sc_hd__and3b_1 are equivalent.
Class sky130_fd_sc_hd__inv_12 (0): Merged 22 parallel devices.
Class sky130_fd_sc_hd__inv_12 (1): Merged 22 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__inv_12 |Circuit 2: sky130_fd_sc_hd__inv_12
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->1) |sky130_fd_pr__pfet_01v8_hvt (12->1)
sky130_fd_pr__nfet_01v8 (12->1) |sky130_fd_pr__nfet_01v8 (12->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__inv_12 |Circuit 2: sky130_fd_sc_hd__inv_12
-------------------------------------------|-------------------------------------------
Y |Y
A |A
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__inv_12 and sky130_fd_sc_hd__inv_12 are equivalent.
Class mprj2_logic_high (0): Merged 44 parallel devices.
Class mprj2_logic_high (1): Merged 44 parallel devices.
Subcircuit summary:
Circuit 1: mprj2_logic_high |Circuit 2: mprj2_logic_high
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_12 (29->1) |sky130_fd_sc_hd__decap_12 (29->1)
sky130_fd_sc_hd__decap_4 (3->1) |sky130_fd_sc_hd__decap_4 (3->1)
sky130_fd_sc_hd__decap_3 (15->1) |sky130_fd_sc_hd__decap_3 (15->1)
sky130_fd_sc_hd__decap_6 (1) |sky130_fd_sc_hd__decap_6 (1)
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
Number of devices: 5 |Number of devices: 5
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: mprj2_logic_high |Circuit 2: mprj2_logic_high
-------------------------------------------|-------------------------------------------
HI |HI
vssd2 |vssd2
vccd2 |vccd2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes mprj2_logic_high and mprj2_logic_high are equivalent.
Class mprj_logic_high (0): Merged 141 parallel devices.
Class mprj_logic_high (1): Merged 141 parallel devices.
Subcircuit summary:
Circuit 1: mprj_logic_high |Circuit 2: mprj_logic_high
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__conb_1 (463) |sky130_fd_sc_hd__conb_1 (463)
sky130_fd_sc_hd__decap_6 (22->1) |sky130_fd_sc_hd__decap_6 (22->1)
sky130_fd_sc_hd__decap_12 (89->1) |sky130_fd_sc_hd__decap_12 (89->1)
sky130_fd_sc_hd__decap_3 (19->1) |sky130_fd_sc_hd__decap_3 (19->1)
sky130_fd_sc_hd__decap_8 (10->1) |sky130_fd_sc_hd__decap_8 (10->1)
sky130_fd_sc_hd__decap_4 (6->1) |sky130_fd_sc_hd__decap_4 (6->1)
Number of devices: 468 |Number of devices: 468
Number of nets: 928 |Number of nets: 928
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: mprj_logic_high |Circuit 2: mprj_logic_high
-------------------------------------------|-------------------------------------------
vssd1 |vssd1
vccd1 |vccd1
HI[295] |HI[295]
HI[462] |HI[462]
HI[58] |HI[58]
HI[345] |HI[345]
HI[178] |HI[178]
HI[10] |HI[10]
HI[228] |HI[228]
HI[130] |HI[130]
HI[95] |HI[95]
HI[382] |HI[382]
HI[432] |HI[432]
HI[265] |HI[265]
HI[28] |HI[28]
HI[315] |HI[315]
HI[148] |HI[148]
HI[100] |HI[100]
HI[65] |HI[65]
HI[185] |HI[185]
HI[352] |HI[352]
HI[235] |HI[235]
HI[402] |HI[402]
HI[118] |HI[118]
HI[272] |HI[272]
HI[35] |HI[35]
HI[322] |HI[322]
HI[155] |HI[155]
HI[205] |HI[205]
HI[72] |HI[72]
HI[192] |HI[192]
HI[457] |HI[457]
HI[242] |HI[242]
HI[125] |HI[125]
HI[0] |HI[0]
HI[377] |HI[377]
HI[42] |HI[42]
HI[427] |HI[427]
HI[162] |HI[162]
HI[212] |HI[212]
HI[297] |HI[297]
HI[347] |HI[347]
HI[12] |HI[12]
HI[132] |HI[132]
HI[97] |HI[97]
HI[384] |HI[384]
HI[267] |HI[267]
HI[434] |HI[434]
HI[317] |HI[317]
HI[102] |HI[102]
HI[67] |HI[67]
HI[187] |HI[187]
HI[354] |HI[354]
HI[237] |HI[237]
HI[404] |HI[404]
HI[391] |HI[391]
HI[274] |HI[274]
HI[441] |HI[441]
HI[37] |HI[37]
HI[324] |HI[324]
HI[157] |HI[157]
HI[207] |HI[207]
HI[74] |HI[74]
HI[194] |HI[194]
HI[361] |HI[361]
HI[459] |HI[459]
HI[244] |HI[244]
HI[411] |HI[411]
HI[127] |HI[127]
HI[281] |HI[281]
HI[2] |HI[2]
HI[379] |HI[379]
HI[44] |HI[44]
HI[331] |HI[331]
HI[164] |HI[164]
HI[429] |HI[429]
HI[214] |HI[214]
HI[81] |HI[81]
HI[299] |HI[299]
HI[251] |HI[251]
HI[349] |HI[349]
HI[14] |HI[14]
HI[301] |HI[301]
HI[134] |HI[134]
HI[99] |HI[99]
HI[386] |HI[386]
HI[51] |HI[51]
HI[269] |HI[269]
HI[171] |HI[171]
HI[436] |HI[436]
HI[319] |HI[319]
HI[221] |HI[221]
HI[104] |HI[104]
HI[69] |HI[69]
HI[189] |HI[189]
HI[356] |HI[356]
HI[21] |HI[21]
HI[239] |HI[239]
HI[141] |HI[141]
HI[406] |HI[406]
HI[393] |HI[393]
HI[276] |HI[276]
HI[443] |HI[443]
HI[39] |HI[39]
HI[326] |HI[326]
HI[159] |HI[159]
HI[111] |HI[111]
HI[209] |HI[209]
HI[76] |HI[76]
HI[363] |HI[363]
HI[196] |HI[196]
HI[246] |HI[246]
HI[413] |HI[413]
HI[129] |HI[129]
HI[4] |HI[4]
HI[283] |HI[283]
HI[450] |HI[450]
HI[46] |HI[46]
HI[333] |HI[333]
HI[166] |HI[166]
HI[216] |HI[216]
HI[83] |HI[83]
HI[370] |HI[370]
HI[253] |HI[253]
HI[420] |HI[420]
HI[16] |HI[16]
HI[303] |HI[303]
HI[136] |HI[136]
HI[290] |HI[290]
HI[388] |HI[388]
HI[53] |HI[53]
HI[173] |HI[173]
HI[340] |HI[340]
HI[438] |HI[438]
HI[223] |HI[223]
HI[90] |HI[90]
HI[106] |HI[106]
HI[260] |HI[260]
HI[358] |HI[358]
HI[23] |HI[23]
HI[310] |HI[310]
HI[143] |HI[143]
HI[408] |HI[408]
HI[395] |HI[395]
HI[60] |HI[60]
HI[180] |HI[180]
HI[278] |HI[278]
HI[445] |HI[445]
HI[328] |HI[328]
HI[230] |HI[230]
HI[113] |HI[113]
HI[78] |HI[78]
HI[198] |HI[198]
HI[365] |HI[365]
HI[30] |HI[30]
HI[248] |HI[248]
HI[150] |HI[150]
HI[415] |HI[415]
HI[200] |HI[200]
HI[285] |HI[285]
HI[452] |HI[452]
HI[6] |HI[6]
HI[48] |HI[48]
HI[168] |HI[168]
HI[335] |HI[335]
HI[218] |HI[218]
HI[120] |HI[120]
HI[85] |HI[85]
HI[372] |HI[372]
HI[255] |HI[255]
HI[422] |HI[422]
HI[18] |HI[18]
HI[305] |HI[305]
HI[138] |HI[138]
HI[292] |HI[292]
HI[55] |HI[55]
HI[175] |HI[175]
HI[342] |HI[342]
HI[225] |HI[225]
HI[92] |HI[92]
HI[108] |HI[108]
HI[262] |HI[262]
HI[25] |HI[25]
HI[312] |HI[312]
HI[145] |HI[145]
HI[397] |HI[397]
HI[62] |HI[62]
HI[182] |HI[182]
HI[447] |HI[447]
HI[232] |HI[232]
HI[115] |HI[115]
HI[367] |HI[367]
HI[32] |HI[32]
HI[152] |HI[152]
HI[417] |HI[417]
HI[202] |HI[202]
HI[287] |HI[287]
HI[454] |HI[454]
HI[8] |HI[8]
HI[337] |HI[337]
HI[122] |HI[122]
HI[87] |HI[87]
HI[374] |HI[374]
HI[257] |HI[257]
HI[424] |HI[424]
HI[307] |HI[307]
HI[294] |HI[294]
HI[461] |HI[461]
HI[57] |HI[57]
HI[177] |HI[177]
HI[344] |HI[344]
HI[227] |HI[227]
HI[94] |HI[94]
HI[381] |HI[381]
HI[264] |HI[264]
HI[431] |HI[431]
HI[27] |HI[27]
HI[314] |HI[314]
HI[147] |HI[147]
HI[399] |HI[399]
HI[64] |HI[64]
HI[184] |HI[184]
HI[449] |HI[449]
HI[351] |HI[351]
HI[401] |HI[401]
HI[234] |HI[234]
HI[117] |HI[117]
HI[271] |HI[271]
HI[369] |HI[369]
HI[34] |HI[34]
HI[321] |HI[321]
HI[154] |HI[154]
HI[419] |HI[419]
HI[204] |HI[204]
HI[71] |HI[71]
HI[191] |HI[191]
HI[289] |HI[289]
HI[456] |HI[456]
HI[339] |HI[339]
HI[241] |HI[241]
HI[124] |HI[124]
HI[89] |HI[89]
HI[376] |HI[376]
HI[41] |HI[41]
HI[259] |HI[259]
HI[161] |HI[161]
HI[426] |HI[426]
HI[211] |HI[211]
HI[309] |HI[309]
HI[296] |HI[296]
HI[59] |HI[59]
HI[179] |HI[179]
HI[346] |HI[346]
HI[11] |HI[11]
HI[229] |HI[229]
HI[131] |HI[131]
HI[96] |HI[96]
HI[383] |HI[383]
HI[266] |HI[266]
HI[433] |HI[433]
HI[29] |HI[29]
HI[316] |HI[316]
HI[149] |HI[149]
HI[101] |HI[101]
HI[66] |HI[66]
HI[186] |HI[186]
HI[353] |HI[353]
HI[236] |HI[236]
HI[403] |HI[403]
HI[119] |HI[119]
HI[390] |HI[390]
HI[440] |HI[440]
HI[273] |HI[273]
HI[36] |HI[36]
HI[323] |HI[323]
HI[156] |HI[156]
HI[206] |HI[206]
HI[73] |HI[73]
HI[193] |HI[193]
HI[360] |HI[360]
HI[458] |HI[458]
HI[243] |HI[243]
HI[410] |HI[410]
HI[126] |HI[126]
HI[1] |HI[1]
HI[280] |HI[280]
HI[378] |HI[378]
HI[43] |HI[43]
HI[163] |HI[163]
HI[330] |HI[330]
HI[428] |HI[428]
HI[213] |HI[213]
HI[80] |HI[80]
HI[298] |HI[298]
HI[250] |HI[250]
HI[348] |HI[348]
HI[13] |HI[13]
HI[300] |HI[300]
HI[133] |HI[133]
HI[98] |HI[98]
HI[385] |HI[385]
HI[50] |HI[50]
HI[268] |HI[268]
HI[435] |HI[435]
HI[170] |HI[170]
HI[220] |HI[220]
HI[318] |HI[318]
HI[103] |HI[103]
HI[68] |HI[68]
HI[188] |HI[188]
HI[355] |HI[355]
HI[20] |HI[20]
HI[238] |HI[238]
HI[140] |HI[140]
HI[405] |HI[405]
HI[392] |HI[392]
HI[275] |HI[275]
HI[442] |HI[442]
HI[38] |HI[38]
HI[325] |HI[325]
HI[158] |HI[158]
HI[208] |HI[208]
HI[110] |HI[110]
HI[75] |HI[75]
HI[195] |HI[195]
HI[362] |HI[362]
HI[245] |HI[245]
HI[412] |HI[412]
HI[128] |HI[128]
HI[282] |HI[282]
HI[3] |HI[3]
HI[45] |HI[45]
HI[332] |HI[332]
HI[165] |HI[165]
HI[215] |HI[215]
HI[82] |HI[82]
HI[252] |HI[252]
HI[15] |HI[15]
HI[302] |HI[302]
HI[135] |HI[135]
HI[387] |HI[387]
HI[52] |HI[52]
HI[172] |HI[172]
HI[437] |HI[437]
HI[222] |HI[222]
HI[105] |HI[105]
HI[357] |HI[357]
HI[22] |HI[22]
HI[142] |HI[142]
HI[407] |HI[407]
HI[394] |HI[394]
HI[277] |HI[277]
HI[444] |HI[444]
HI[327] |HI[327]
HI[112] |HI[112]
HI[77] |HI[77]
HI[197] |HI[197]
HI[364] |HI[364]
HI[414] |HI[414]
HI[247] |HI[247]
HI[284] |HI[284]
HI[451] |HI[451]
HI[5] |HI[5]
HI[47] |HI[47]
HI[167] |HI[167]
HI[334] |HI[334]
HI[217] |HI[217]
HI[84] |HI[84]
HI[371] |HI[371]
HI[254] |HI[254]
HI[421] |HI[421]
HI[17] |HI[17]
HI[304] |HI[304]
HI[137] |HI[137]
HI[291] |HI[291]
HI[389] |HI[389]
HI[54] |HI[54]
HI[341] |HI[341]
HI[174] |HI[174]
HI[439] |HI[439]
HI[224] |HI[224]
HI[91] |HI[91]
HI[107] |HI[107]
HI[261] |HI[261]
HI[359] |HI[359]
HI[24] |HI[24]
HI[311] |HI[311]
HI[409] |HI[409]
HI[144] |HI[144]
HI[396] |HI[396]
HI[61] |HI[61]
HI[279] |HI[279]
HI[181] |HI[181]
HI[446] |HI[446]
HI[231] |HI[231]
HI[329] |HI[329]
HI[114] |HI[114]
HI[79] |HI[79]
HI[199] |HI[199]
HI[366] |HI[366]
HI[31] |HI[31]
HI[151] |HI[151]
HI[249] |HI[249]
HI[416] |HI[416]
HI[201] |HI[201]
HI[453] |HI[453]
HI[7] |HI[7]
HI[286] |HI[286]
HI[49] |HI[49]
HI[169] |HI[169]
HI[336] |HI[336]
HI[219] |HI[219]
HI[121] |HI[121]
HI[86] |HI[86]
HI[373] |HI[373]
HI[256] |HI[256]
HI[423] |HI[423]
HI[19] |HI[19]
HI[306] |HI[306]
HI[139] |HI[139]
HI[293] |HI[293]
HI[460] |HI[460]
HI[56] |HI[56]
HI[176] |HI[176]
HI[343] |HI[343]
HI[226] |HI[226]
HI[93] |HI[93]
HI[109] |HI[109]
HI[380] |HI[380]
HI[263] |HI[263]
HI[430] |HI[430]
HI[26] |HI[26]
HI[313] |HI[313]
HI[146] |HI[146]
HI[398] |HI[398]
HI[63] |HI[63]
HI[448] |HI[448]
HI[350] |HI[350]
HI[183] |HI[183]
HI[233] |HI[233]
HI[400] |HI[400]
HI[116] |HI[116]
HI[270] |HI[270]
HI[368] |HI[368]
HI[33] |HI[33]
HI[320] |HI[320]
HI[153] |HI[153]
HI[418] |HI[418]
HI[203] |HI[203]
HI[70] |HI[70]
HI[190] |HI[190]
HI[288] |HI[288]
HI[455] |HI[455]
HI[9] |HI[9]
HI[240] |HI[240]
HI[338] |HI[338]
HI[123] |HI[123]
HI[88] |HI[88]
HI[375] |HI[375]
HI[40] |HI[40]
HI[258] |HI[258]
HI[160] |HI[160]
HI[425] |HI[425]
HI[308] |HI[308]
HI[210] |HI[210]
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes mprj_logic_high and mprj_logic_high are equivalent.
Subcircuit summary:
Circuit 1: mgmt_protect_hv |Circuit 2: mgmt_protect_hv
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hvl__conb_1 (2) |sky130_fd_sc_hvl__conb_1 (2)
sky130_fd_pr__pfet_g5v0d10v5 (4) |sky130_fd_pr__pfet_g5v0d10v5 (4)
sky130_fd_pr__nfet_g5v0d10v5 (20->8) |sky130_fd_pr__nfet_g5v0d10v5 (20->8)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
Number of devices: 22 |Number of devices: 22
Number of nets: 20 |Number of nets: 20
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: mgmt_protect_hv |Circuit 2: mgmt_protect_hv
-------------------------------------------|-------------------------------------------
vccd |vccd
vssd |vssd
vdda2 |vdda2
vdda1 |vdda1
vssa2 |vssa2
vssa1 |vssa1
mprj2_vdd_logic1 |mprj2_vdd_logic1
mprj_vdd_logic1 |mprj_vdd_logic1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes mgmt_protect_hv and mgmt_protect_hv are equivalent.
Class sky130_fd_sc_hd__bufbuf_8 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__bufbuf_8 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__bufbuf_8 |Circuit 2: sky130_fd_sc_hd__bufbuf_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__bufbuf_8 |Circuit 2: sky130_fd_sc_hd__bufbuf_8
-------------------------------------------|-------------------------------------------
X |X
A |A
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__bufbuf_8 and sky130_fd_sc_hd__bufbuf_8 are equivalent.
Class sky130_fd_sc_hd__and2b_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__and2b_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
VGND |VGND
A_N |A_N
X |X
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and2b_4 and sky130_fd_sc_hd__and2b_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hvl__decap_4 |Circuit 2: sky130_fd_sc_hvl__decap_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_g5v0d10v5 (1) |sky130_fd_pr__nfet_g5v0d10v5 (1)
sky130_fd_pr__pfet_g5v0d10v5 (1) |sky130_fd_pr__pfet_g5v0d10v5 (1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hvl__decap_4 |Circuit 2: sky130_fd_sc_hvl__decap_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hvl__decap_4 and sky130_fd_sc_hvl__decap_4 are equivalent.
Class sky130_fd_sc_hvl__decap_8 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hvl__decap_8 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hvl__decap_8 |Circuit 2: sky130_fd_sc_hvl__decap_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (2->1) |sky130_fd_pr__pfet_g5v0d10v5 (2->1)
sky130_fd_pr__nfet_g5v0d10v5 (2->1) |sky130_fd_pr__nfet_g5v0d10v5 (2->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 4 |Number of nets: 4
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hvl__decap_8 |Circuit 2: sky130_fd_sc_hvl__decap_8
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hvl__decap_8 and sky130_fd_sc_hvl__decap_8 are equivalent.
Cell sky130_fd_sc_hvl__diode_2 (0) disconnected node: VGND
Cell sky130_fd_sc_hvl__diode_2 (0) disconnected node: VPWR
Cell sky130_fd_sc_hvl__diode_2 (0) disconnected node: VPB
Cell sky130_fd_sc_hvl__diode_2 (1) disconnected node: VGND
Cell sky130_fd_sc_hvl__diode_2 (1) disconnected node: VPB
Cell sky130_fd_sc_hvl__diode_2 (1) disconnected node: VPWR
Subcircuit summary:
Circuit 1: sky130_fd_sc_hvl__diode_2 |Circuit 2: sky130_fd_sc_hvl__diode_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__diode_pw2nd_11v0 (1) |sky130_fd_pr__diode_pw2nd_11v0 (1)
Number of devices: 1 |Number of devices: 1
Number of nets: 2 |Number of nets: 2
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hvl__diode_2 |Circuit 2: sky130_fd_sc_hvl__diode_2
-------------------------------------------|-------------------------------------------
VNB |VNB
DIODE |DIODE
VGND |VGND
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hvl__diode_2 and sky130_fd_sc_hvl__diode_2 are equivalent.
Class sky130_fd_sc_hd__dfstp_4 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__dfstp_4 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__dfstp_4 |Circuit 2: sky130_fd_sc_hd__dfstp_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (20->16) |sky130_fd_pr__pfet_01v8_hvt (20->16)
sky130_fd_pr__nfet_01v8 (20->16) |sky130_fd_pr__nfet_01v8 (20->16)
Number of devices: 32 |Number of devices: 32
Number of nets: 24 |Number of nets: 24
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__dfstp_4 |Circuit 2: sky130_fd_sc_hd__dfstp_4
-------------------------------------------|-------------------------------------------
Q |Q
D |D
CLK |CLK
VGND |VGND
VPB |VPB
VNB |VNB
VPWR |VPWR
SET_B |SET_B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__dfstp_4 and sky130_fd_sc_hd__dfstp_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a211o_1 |Circuit 2: sky130_fd_sc_hd__a211o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a211o_1 |Circuit 2: sky130_fd_sc_hd__a211o_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
A2 |A2
X |X
A1 |A1
B1 |B1
C1 |C1
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a211o_1 and sky130_fd_sc_hd__a211o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o211a_1 |Circuit 2: sky130_fd_sc_hd__o211a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o211a_1 |Circuit 2: sky130_fd_sc_hd__o211a_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
C1 |C1
A1 |A1
B1 |B1
A2 |A2
X |X
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o211a_1 and sky130_fd_sc_hd__o211a_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o221a_1 |Circuit 2: sky130_fd_sc_hd__o221a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o221a_1 |Circuit 2: sky130_fd_sc_hd__o221a_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
VGND |VGND
X |X
B1 |B1
A1 |A1
C1 |C1
B2 |B2
A2 |A2
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o221a_1 and sky130_fd_sc_hd__o221a_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a221o_1 |Circuit 2: sky130_fd_sc_hd__a221o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a221o_1 |Circuit 2: sky130_fd_sc_hd__a221o_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
VPB |VPB
VNB |VNB
X |X
B1 |B1
A1 |A1
C1 |C1
A2 |A2
B2 |B2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a221o_1 and sky130_fd_sc_hd__a221o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o2111a_1 |Circuit 2: sky130_fd_sc_hd__o2111a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o2111a_1 |Circuit 2: sky130_fd_sc_hd__o2111a_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
D1 |D1
C1 |C1
A1 |A1
A2 |A2
B1 |B1
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o2111a_1 and sky130_fd_sc_hd__o2111a_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a22o_1 |Circuit 2: sky130_fd_sc_hd__a22o_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
A2 |A2
A1 |A1
B1 |B1
X |X
B2 |B2
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a22o_1 and sky130_fd_sc_hd__a22o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand4_1 |Circuit 2: sky130_fd_sc_hd__nand4_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand4_1 |Circuit 2: sky130_fd_sc_hd__nand4_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPWR |VPWR
VPB |VPB
A |A
C |C
B |B
D |D
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand4_1 and sky130_fd_sc_hd__nand4_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and3_1 |Circuit 2: sky130_fd_sc_hd__and3_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and3_1 |Circuit 2: sky130_fd_sc_hd__and3_1
-------------------------------------------|-------------------------------------------
VGND |VGND
A |A
B |B
C |C
X |X
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and3_1 and sky130_fd_sc_hd__and3_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o2bb2a_1 |Circuit 2: sky130_fd_sc_hd__o2bb2a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o2bb2a_1 |Circuit 2: sky130_fd_sc_hd__o2bb2a_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
A1_N |A1_N
A2_N |A2_N
X |X
B1 |B1
B2 |B2
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o2bb2a_1 and sky130_fd_sc_hd__o2bb2a_1 are equivalent.
Class sky130_fd_sc_hd__nor2_4 (0): Merged 12 parallel devices.
Class sky130_fd_sc_hd__nor2_4 (1): Merged 12 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor2_4 |Circuit 2: sky130_fd_sc_hd__nor2_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor2_4 |Circuit 2: sky130_fd_sc_hd__nor2_4
-------------------------------------------|-------------------------------------------
Y |Y
B |B
VPB |VPB
A |A
VGND |VGND
VNB |VNB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor2_4 and sky130_fd_sc_hd__nor2_4 are equivalent.
Class sky130_fd_sc_hd__nor2_8 (0): Merged 28 parallel devices.
Class sky130_fd_sc_hd__nor2_8 (1): Merged 28 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor2_8 |Circuit 2: sky130_fd_sc_hd__nor2_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
Number of devices: 4 |Number of devices: 4
Number of nets: 8 |Number of nets: 8
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor2_8 |Circuit 2: sky130_fd_sc_hd__nor2_8
-------------------------------------------|-------------------------------------------
Y |Y
A |A
VPB |VPB
VGND |VGND
VNB |VNB
B |B
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor2_8 and sky130_fd_sc_hd__nor2_8 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and4_1 |Circuit 2: sky130_fd_sc_hd__and4_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and4_1 |Circuit 2: sky130_fd_sc_hd__and4_1
-------------------------------------------|-------------------------------------------
VNB |VNB
VPWR |VPWR
VPB |VPB
VGND |VGND
X |X
D |D
B |B
C |C
A |A
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and4_1 and sky130_fd_sc_hd__and4_1 are equivalent.
Class sky130_fd_sc_hd__and3_4 (0): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and3_4 |Circuit 2: sky130_fd_sc_hd__and3_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and3_4 |Circuit 2: sky130_fd_sc_hd__and3_4
-------------------------------------------|-------------------------------------------
X |X
VGND |VGND
A |A
C |C
B |B
VNB |VNB
VPWR |VPWR
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and3_4 and sky130_fd_sc_hd__and3_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and4b_1 |Circuit 2: sky130_fd_sc_hd__and4b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and4b_1 |Circuit 2: sky130_fd_sc_hd__and4b_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
VPB |VPB
VNB |VNB
X |X
D |D
A_N |A_N
C |C
B |B
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and4b_1 and sky130_fd_sc_hd__and4b_1 are equivalent.
Class sky130_fd_sc_hd__a221o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a221o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a221o_2 |Circuit 2: sky130_fd_sc_hd__a221o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a221o_2 |Circuit 2: sky130_fd_sc_hd__a221o_2
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
B1 |B1
A1 |A1
C1 |C1
A2 |A2
B2 |B2
VPB |VPB
VNB |VNB
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a221o_2 and sky130_fd_sc_hd__a221o_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and2b_1 |Circuit 2: sky130_fd_sc_hd__and2b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and2b_1 |Circuit 2: sky130_fd_sc_hd__and2b_1
-------------------------------------------|-------------------------------------------
VGND |VGND
B |B
X |X
A_N |A_N
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and2b_1 and sky130_fd_sc_hd__and2b_1 are equivalent.
Class sky130_fd_sc_hd__o31a_4 (0): Merged 14 parallel devices.
Class sky130_fd_sc_hd__o31a_4 (1): Merged 14 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o31a_4 |Circuit 2: sky130_fd_sc_hd__o31a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->5) |sky130_fd_pr__pfet_01v8_hvt (12->5)
sky130_fd_pr__nfet_01v8 (12->5) |sky130_fd_pr__nfet_01v8 (12->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o31a_4 |Circuit 2: sky130_fd_sc_hd__o31a_4
-------------------------------------------|-------------------------------------------
VGND |VGND
VPB |VPB
VNB |VNB
X |X
A3 |A3
A1 |A1
B1 |B1
A2 |A2
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o31a_4 and sky130_fd_sc_hd__o31a_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a32o_1 |Circuit 2: sky130_fd_sc_hd__a32o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a32o_1 |Circuit 2: sky130_fd_sc_hd__a32o_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
B2 |B2
X |X
B1 |B1
A2 |A2
A3 |A3
A1 |A1
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a32o_1 and sky130_fd_sc_hd__a32o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and4bb_1 |Circuit 2: sky130_fd_sc_hd__and4bb_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7) |sky130_fd_pr__pfet_01v8_hvt (7)
sky130_fd_pr__nfet_01v8 (7) |sky130_fd_pr__nfet_01v8 (7)
Number of devices: 14 |Number of devices: 14
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and4bb_1 |Circuit 2: sky130_fd_sc_hd__and4bb_1
-------------------------------------------|-------------------------------------------
VGND |VGND
C |C
A_N |A_N
B_N |B_N
X |X
D |D
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and4bb_1 and sky130_fd_sc_hd__and4bb_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a41o_1 |Circuit 2: sky130_fd_sc_hd__a41o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a41o_1 |Circuit 2: sky130_fd_sc_hd__a41o_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VNB |VNB
VPB |VPB
B1 |B1
A4 |A4
A3 |A3
A2 |A2
A1 |A1
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a41o_1 and sky130_fd_sc_hd__a41o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a2111o_1 |Circuit 2: sky130_fd_sc_hd__a2111o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a2111o_1 |Circuit 2: sky130_fd_sc_hd__a2111o_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VNB |VNB
VPB |VPB
D1 |D1
X |X
A1 |A1
B1 |B1
A2 |A2
C1 |C1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a2111o_1 and sky130_fd_sc_hd__a2111o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a2111oi_1 |Circuit 2: sky130_fd_sc_hd__a2111oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a2111oi_1 |Circuit 2: sky130_fd_sc_hd__a2111oi_1
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VNB |VNB
VPB |VPB
C1 |C1
B1 |B1
A1 |A1
D1 |D1
VPWR |VPWR
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a2111oi_1 and sky130_fd_sc_hd__a2111oi_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o41a_1 |Circuit 2: sky130_fd_sc_hd__o41a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o41a_1 |Circuit 2: sky130_fd_sc_hd__o41a_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VPB |VPB
VNB |VNB
A2 |A2
A3 |A3
A4 |A4
B1 |B1
A1 |A1
X |X
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o41a_1 and sky130_fd_sc_hd__o41a_1 are equivalent.
Class sky130_fd_sc_hd__mux2_8 (0): Merged 22 parallel devices.
Class sky130_fd_sc_hd__mux2_8 (1): Merged 22 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__mux2_8 |Circuit 2: sky130_fd_sc_hd__mux2_8
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (17->6) |sky130_fd_pr__nfet_01v8 (17->6)
sky130_fd_pr__pfet_01v8_hvt (17->6) |sky130_fd_pr__pfet_01v8_hvt (17->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__mux2_8 |Circuit 2: sky130_fd_sc_hd__mux2_8
-------------------------------------------|-------------------------------------------
X |X
A0 |A0
A1 |A1
VNB |VNB
VPB |VPB
VGND |VGND
S |S
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__mux2_8 and sky130_fd_sc_hd__mux2_8 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a311o_1 |Circuit 2: sky130_fd_sc_hd__a311o_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a311o_1 |Circuit 2: sky130_fd_sc_hd__a311o_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
A1 |A1
A3 |A3
B1 |B1
C1 |C1
A2 |A2
X |X
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a311o_1 and sky130_fd_sc_hd__a311o_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o32a_1 |Circuit 2: sky130_fd_sc_hd__o32a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o32a_1 |Circuit 2: sky130_fd_sc_hd__o32a_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
X |X
A1 |A1
B1 |B1
A2 |A2
B2 |B2
A3 |A3
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o32a_1 and sky130_fd_sc_hd__o32a_1 are equivalent.
Class sky130_fd_sc_hd__nor4_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__nor4_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor4_4 |Circuit 2: sky130_fd_sc_hd__nor4_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor4_4 |Circuit 2: sky130_fd_sc_hd__nor4_4
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VGND |VGND
VNB |VNB
B |B
C |C
A |A
D |D
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor4_4 and sky130_fd_sc_hd__nor4_4 are equivalent.
Class sky130_fd_sc_hd__nand3_4 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__nand3_4 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand3_4 |Circuit 2: sky130_fd_sc_hd__nand3_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand3_4 |Circuit 2: sky130_fd_sc_hd__nand3_4
-------------------------------------------|-------------------------------------------
VGND |VGND
Y |Y
VNB |VNB
VPWR |VPWR
VPB |VPB
A |A
B |B
C |C
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand3_4 and sky130_fd_sc_hd__nand3_4 are equivalent.
Class sky130_fd_sc_hd__nand2b_4 (0): Merged 12 parallel devices.
Class sky130_fd_sc_hd__nand2b_4 (1): Merged 12 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand2b_4 |Circuit 2: sky130_fd_sc_hd__nand2b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (9->3) |sky130_fd_pr__nfet_01v8 (9->3)
sky130_fd_pr__pfet_01v8_hvt (9->3) |sky130_fd_pr__pfet_01v8_hvt (9->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand2b_4 |Circuit 2: sky130_fd_sc_hd__nand2b_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
Y |Y
VPB |VPB
VNB |VNB
B |B
VGND |VGND
A_N |A_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand2b_4 and sky130_fd_sc_hd__nand2b_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21boi_1 |Circuit 2: sky130_fd_sc_hd__a21boi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21boi_1 |Circuit 2: sky130_fd_sc_hd__a21boi_1
-------------------------------------------|-------------------------------------------
A1 |A1
A2 |A2
B1_N |B1_N
VNB |VNB
VPB |VPB
VGND |VGND
Y |Y
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21boi_1 and sky130_fd_sc_hd__a21boi_1 are equivalent.
Class sky130_fd_sc_hd__o21a_4 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__o21a_4 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21a_4 |Circuit 2: sky130_fd_sc_hd__o21a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (10->4) |sky130_fd_pr__nfet_01v8 (10->4)
sky130_fd_pr__pfet_01v8_hvt (10->6) |sky130_fd_pr__pfet_01v8_hvt (10->6)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21a_4 |Circuit 2: sky130_fd_sc_hd__o21a_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPWR |VPWR
A2 |A2
VGND |VGND
A1 |A1
VPB |VPB
X |X
B1 |B1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21a_4 and sky130_fd_sc_hd__o21a_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a31oi_1 |Circuit 2: sky130_fd_sc_hd__a31oi_1
-------------------------------------------|-------------------------------------------
VPB |VPB
VNB |VNB
B1 |B1
A1 |A1
VGND |VGND
A3 |A3
A2 |A2
Y |Y
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a31oi_1 and sky130_fd_sc_hd__a31oi_1 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand4b_1 |Circuit 2: sky130_fd_sc_hd__nand4b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand4b_1 |Circuit 2: sky130_fd_sc_hd__nand4b_1
-------------------------------------------|-------------------------------------------
A_N |A_N
C |C
D |D
B |B
VGND |VGND
Y |Y
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand4b_1 and sky130_fd_sc_hd__nand4b_1 are equivalent.
Class sky130_fd_sc_hd__nand3b_4 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__nand3b_4 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand3b_4 |Circuit 2: sky130_fd_sc_hd__nand3b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (13->4) |sky130_fd_pr__nfet_01v8 (13->4)
sky130_fd_pr__pfet_01v8_hvt (13->4) |sky130_fd_pr__pfet_01v8_hvt (13->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand3b_4 |Circuit 2: sky130_fd_sc_hd__nand3b_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPWR |VPWR
Y |Y
VPB |VPB
B |B
C |C
VGND |VGND
A_N |A_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand3b_4 and sky130_fd_sc_hd__nand3b_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o21ba_1 |Circuit 2: sky130_fd_sc_hd__o21ba_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o21ba_1 |Circuit 2: sky130_fd_sc_hd__o21ba_1
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
A2 |A2
B1_N |B1_N
A1 |A1
X |X
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o21ba_1 and sky130_fd_sc_hd__o21ba_1 are equivalent.
Class sky130_fd_sc_hd__nor4_2 (0): Merged 8 parallel devices.
Class sky130_fd_sc_hd__nor4_2 (1): Merged 8 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor4_2 |Circuit 2: sky130_fd_sc_hd__nor4_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (8->4) |sky130_fd_pr__pfet_01v8_hvt (8->4)
sky130_fd_pr__nfet_01v8 (8->4) |sky130_fd_pr__nfet_01v8 (8->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor4_2 |Circuit 2: sky130_fd_sc_hd__nor4_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
Y |Y
VGND |VGND
VNB |VNB
VPB |VPB
A |A
C |C
B |B
D |D
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor4_2 and sky130_fd_sc_hd__nor4_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o311a_1 |Circuit 2: sky130_fd_sc_hd__o311a_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o311a_1 |Circuit 2: sky130_fd_sc_hd__o311a_1
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
VGND |VGND
VPWR |VPWR
B1 |B1
A1 |A1
C1 |C1
A2 |A2
X |X
A3 |A3
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o311a_1 and sky130_fd_sc_hd__o311a_1 are equivalent.
Class sky130_fd_sc_hd__a2111o_2 (0): Merged 2 parallel devices.
Class sky130_fd_sc_hd__a2111o_2 (1): Merged 2 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a2111o_2 |Circuit 2: sky130_fd_sc_hd__a2111o_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a2111o_2 |Circuit 2: sky130_fd_sc_hd__a2111o_2
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
A1 |A1
X |X
A2 |A2
D1 |D1
C1 |C1
B1 |B1
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a2111o_2 and sky130_fd_sc_hd__a2111o_2 are equivalent.
Class sky130_fd_sc_hd__nand4b_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__nand4b_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nand4b_4 |Circuit 2: sky130_fd_sc_hd__nand4b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (17->5) |sky130_fd_pr__nfet_01v8 (17->5)
sky130_fd_pr__pfet_01v8_hvt (17->5) |sky130_fd_pr__pfet_01v8_hvt (17->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 13 |Number of nets: 13
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nand4b_4 |Circuit 2: sky130_fd_sc_hd__nand4b_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPWR |VPWR
Y |Y
VPB |VPB
VGND |VGND
D |D
B |B
C |C
A_N |A_N
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nand4b_4 and sky130_fd_sc_hd__nand4b_4 are equivalent.
Class sky130_fd_sc_hd__a311oi_2 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__a311oi_2 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a311oi_2 |Circuit 2: sky130_fd_sc_hd__a311oi_2
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (10->5) |sky130_fd_pr__nfet_01v8 (10->5)
sky130_fd_pr__pfet_01v8_hvt (10->5) |sky130_fd_pr__pfet_01v8_hvt (10->5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a311oi_2 |Circuit 2: sky130_fd_sc_hd__a311oi_2
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
A2 |A2
A1 |A1
C1 |C1
B1 |B1
A3 |A3
Y |Y
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a311oi_2 and sky130_fd_sc_hd__a311oi_2 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__xor2_1 |Circuit 2: sky130_fd_sc_hd__xor2_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__xor2_1 |Circuit 2: sky130_fd_sc_hd__xor2_1
-------------------------------------------|-------------------------------------------
A |A
VGND |VGND
B |B
VNB |VNB
VPB |VPB
X |X
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__xor2_1 and sky130_fd_sc_hd__xor2_1 are equivalent.
Class sky130_fd_sc_hd__o221a_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__o221a_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__o221a_4 |Circuit 2: sky130_fd_sc_hd__o221a_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__o221a_4 |Circuit 2: sky130_fd_sc_hd__o221a_4
-------------------------------------------|-------------------------------------------
VNB |VNB
VPB |VPB
VPWR |VPWR
X |X
B2 |B2
A2 |A2
A1 |A1
B1 |B1
C1 |C1
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__o221a_4 and sky130_fd_sc_hd__o221a_4 are equivalent.
Class sky130_fd_sc_hd__a211o_4 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__a211o_4 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a211o_4 |Circuit 2: sky130_fd_sc_hd__a211o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->7) |sky130_fd_pr__pfet_01v8_hvt (12->7)
sky130_fd_pr__nfet_01v8 (12->7) |sky130_fd_pr__nfet_01v8 (12->7)
Number of devices: 14 |Number of devices: 14
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a211o_4 |Circuit 2: sky130_fd_sc_hd__a211o_4
-------------------------------------------|-------------------------------------------
VGND |VGND
VPB |VPB
VNB |VNB
C1 |C1
A2 |A2
VPWR |VPWR
A1 |A1
B1 |B1
X |X
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a211o_4 and sky130_fd_sc_hd__a211o_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21bo_1 |Circuit 2: sky130_fd_sc_hd__a21bo_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21bo_1 |Circuit 2: sky130_fd_sc_hd__a21bo_1
-------------------------------------------|-------------------------------------------
X |X
A2 |A2
A1 |A1
B1_N |B1_N
VPB |VPB
VNB |VNB
VPWR |VPWR
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21bo_1 and sky130_fd_sc_hd__a21bo_1 are equivalent.
Class sky130_fd_sc_hd__a221o_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__a221o_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a221o_4 |Circuit 2: sky130_fd_sc_hd__a221o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a221o_4 |Circuit 2: sky130_fd_sc_hd__a221o_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VNB |VNB
VPB |VPB
C1 |C1
B2 |B2
A2 |A2
A1 |A1
B1 |B1
X |X
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a221o_4 and sky130_fd_sc_hd__a221o_4 are equivalent.
Class sky130_fd_sc_hd__and4b_4 (0): Merged 6 parallel devices.
Class sky130_fd_sc_hd__and4b_4 (1): Merged 6 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__and4b_4 |Circuit 2: sky130_fd_sc_hd__and4b_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (9->6) |sky130_fd_pr__pfet_01v8_hvt (9->6)
sky130_fd_pr__nfet_01v8 (9->6) |sky130_fd_pr__nfet_01v8 (9->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__and4b_4 |Circuit 2: sky130_fd_sc_hd__and4b_4
-------------------------------------------|-------------------------------------------
VGND |VGND
X |X
D |D
A_N |A_N
C |C
B |B
VPWR |VPWR
VPB |VPB
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__and4b_4 and sky130_fd_sc_hd__and4b_4 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor3b_1 |Circuit 2: sky130_fd_sc_hd__nor3b_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
Number of devices: 8 |Number of devices: 8
Number of nets: 11 |Number of nets: 11
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor3b_1 |Circuit 2: sky130_fd_sc_hd__nor3b_1
-------------------------------------------|-------------------------------------------
VPWR |VPWR
C_N |C_N
A |A
B |B
Y |Y
VGND |VGND
VNB |VNB
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor3b_1 and sky130_fd_sc_hd__nor3b_1 are equivalent.
Class sky130_fd_sc_hd__nor3_4 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__nor3_4 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__nor3_4 |Circuit 2: sky130_fd_sc_hd__nor3_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__nor3_4 |Circuit 2: sky130_fd_sc_hd__nor3_4
-------------------------------------------|-------------------------------------------
Y |Y
VPB |VPB
VGND |VGND
VNB |VNB
B |B
A |A
C |C
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__nor3_4 and sky130_fd_sc_hd__nor3_4 are equivalent.
Class sky130_fd_sc_hd__a21oi_4 (0): Merged 18 parallel devices.
Class sky130_fd_sc_hd__a21oi_4 (1): Merged 18 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21oi_4 |Circuit 2: sky130_fd_sc_hd__a21oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (12->3) |sky130_fd_pr__pfet_01v8_hvt (12->3)
sky130_fd_pr__nfet_01v8 (12->3) |sky130_fd_pr__nfet_01v8 (12->3)
Number of devices: 6 |Number of devices: 6
Number of nets: 10 |Number of nets: 10
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21oi_4 |Circuit 2: sky130_fd_sc_hd__a21oi_4
-------------------------------------------|-------------------------------------------
A2 |A2
VGND |VGND
B1 |B1
VPWR |VPWR
A1 |A1
VNB |VNB
Y |Y
VPB |VPB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21oi_4 and sky130_fd_sc_hd__a21oi_4 are equivalent.
Class sky130_fd_sc_hd__a21o_4 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__a21o_4 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a21o_4 |Circuit 2: sky130_fd_sc_hd__a21o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (10->6) |sky130_fd_pr__nfet_01v8 (10->6)
sky130_fd_pr__pfet_01v8_hvt (10->4) |sky130_fd_pr__pfet_01v8_hvt (10->4)
Number of devices: 10 |Number of devices: 10
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a21o_4 |Circuit 2: sky130_fd_sc_hd__a21o_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
A2 |A2
A1 |A1
VNB |VNB
X |X
B1 |B1
VPB |VPB
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a21o_4 and sky130_fd_sc_hd__a21o_4 are equivalent.
Class sky130_fd_sc_hd__a31oi_4 (0): Merged 24 parallel devices.
Class sky130_fd_sc_hd__a31oi_4 (1): Merged 24 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a31oi_4 |Circuit 2: sky130_fd_sc_hd__a31oi_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (16->4) |sky130_fd_pr__nfet_01v8 (16->4)
sky130_fd_pr__pfet_01v8_hvt (16->4) |sky130_fd_pr__pfet_01v8_hvt (16->4)
Number of devices: 8 |Number of devices: 8
Number of nets: 12 |Number of nets: 12
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a31oi_4 |Circuit 2: sky130_fd_sc_hd__a31oi_4
-------------------------------------------|-------------------------------------------
Y |Y
VPWR |VPWR
VPB |VPB
VNB |VNB
B1 |B1
A1 |A1
VGND |VGND
A3 |A3
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a31oi_4 and sky130_fd_sc_hd__a31oi_4 are equivalent.
Class sky130_fd_sc_hd__a2111o_4 (0): Merged 16 parallel devices.
Class sky130_fd_sc_hd__a2111o_4 (1): Merged 16 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a2111o_4 |Circuit 2: sky130_fd_sc_hd__a2111o_4
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (14->6) |sky130_fd_pr__pfet_01v8_hvt (14->6)
sky130_fd_pr__nfet_01v8 (14->6) |sky130_fd_pr__nfet_01v8 (14->6)
Number of devices: 12 |Number of devices: 12
Number of nets: 15 |Number of nets: 15
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a2111o_4 |Circuit 2: sky130_fd_sc_hd__a2111o_4
-------------------------------------------|-------------------------------------------
VPWR |VPWR
VGND |VGND
VPB |VPB
VNB |VNB
B1 |B1
A1 |A1
X |X
D1 |D1
C1 |C1
A2 |A2
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a2111o_4 and sky130_fd_sc_hd__a2111o_4 are equivalent.
Class sky130_fd_sc_hd__inv_6 (0): Merged 10 parallel devices.
Class sky130_fd_sc_hd__inv_6 (1): Merged 10 parallel devices.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__inv_6 |Circuit 2: sky130_fd_sc_hd__inv_6
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (6->1) |sky130_fd_pr__pfet_01v8_hvt (6->1)
sky130_fd_pr__nfet_01v8 (6->1) |sky130_fd_pr__nfet_01v8 (6->1)
Number of devices: 2 |Number of devices: 2
Number of nets: 6 |Number of nets: 6
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__inv_6 |Circuit 2: sky130_fd_sc_hd__inv_6
-------------------------------------------|-------------------------------------------
A |A
Y |Y
VPWR |VPWR
VPB |VPB
VGND |VGND
VNB |VNB
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__inv_6 and sky130_fd_sc_hd__inv_6 are equivalent.
Subcircuit summary:
Circuit 1: sky130_fd_sc_hd__a221oi_1 |Circuit 2: sky130_fd_sc_hd__a221oi_1
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5) |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8_hvt (5) |sky130_fd_pr__pfet_01v8_hvt (5)
Number of devices: 10 |Number of devices: 10
Number of nets: 14 |Number of nets: 14
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: sky130_fd_sc_hd__a221oi_1 |Circuit 2: sky130_fd_sc_hd__a221oi_1
-------------------------------------------|-------------------------------------------
VGND |VGND
VNB |VNB
VPB |VPB
Y |Y
B2 |B2
A2 |A2
VPWR |VPWR
A1 |A1
B1 |B1
C1 |C1
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_fd_sc_hd__a221oi_1 and sky130_fd_sc_hd__a221oi_1 are equivalent.
Class gpio_control_block (0): Merged 57 parallel devices.
Class gpio_control_block (1): Merged 57 parallel devices.
Subcircuit summary:
Circuit 1: gpio_control_block |Circuit 2: gpio_control_block
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__dfrtp_4 (13) |sky130_fd_sc_hd__dfrtp_4 (13)
sky130_fd_sc_hd__nand2b_2 (14) |sky130_fd_sc_hd__nand2b_2 (14)
sky130_fd_sc_hd__dfbbn_2 (13) |sky130_fd_sc_hd__dfbbn_2 (13)
sky130_fd_sc_hd__inv_2 (16) |sky130_fd_sc_hd__inv_2 (16)
sky130_fd_sc_hd__buf_16 (19) |sky130_fd_sc_hd__buf_16 (19)
sky130_fd_sc_hd__mux2_4 (1) |sky130_fd_sc_hd__mux2_4 (1)
sky130_fd_sc_hd__clkbuf_16 (8) |sky130_fd_sc_hd__clkbuf_16 (8)
sky130_fd_sc_hd__and2_0 (1) |sky130_fd_sc_hd__and2_0 (1)
sky130_fd_sc_hd__dlygate4sd3_1 (13) |sky130_fd_sc_hd__dlygate4sd3_1 (13)
sky130_fd_sc_hd__diode_2 (39->23) |sky130_fd_sc_hd__diode_2 (39->23)
sky130_fd_sc_hd__decap_3 (42->1) |sky130_fd_sc_hd__decap_3 (42->1)
sky130_fd_sc_hd__conb_1 (2) |sky130_fd_sc_hd__conb_1 (2)
sky130_fd_sc_hd__buf_2 (16) |sky130_fd_sc_hd__buf_2 (16)
sky130_fd_sc_hd__or2_0 (13) |sky130_fd_sc_hd__or2_0 (13)
sky130_fd_sc_hd__nand2_2 (2) |sky130_fd_sc_hd__nand2_2 (2)
sky130_fd_sc_hd__nor2_2 (2) |sky130_fd_sc_hd__nor2_2 (2)
gpio_logic_high (1) |gpio_logic_high (1)
sky130_fd_sc_hd__and2_2 (1) |sky130_fd_sc_hd__and2_2 (1)
sky130_fd_sc_hd__o21ai_4 (1) |sky130_fd_sc_hd__o21ai_4 (1)
sky130_fd_sc_hd__o21ai_2 (1) |sky130_fd_sc_hd__o21ai_2 (1)
sky130_fd_sc_hd__and2b_2 (1) |sky130_fd_sc_hd__and2b_2 (1)
sky130_fd_sc_hd__dfrtp_2 (1) |sky130_fd_sc_hd__dfrtp_2 (1)
sky130_fd_sc_hd__and3b_2 (1) |sky130_fd_sc_hd__and3b_2 (1)
Number of devices: 164 |Number of devices: 164
Number of nets: 181 |Number of nets: 181
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: gpio_control_block |Circuit 2: gpio_control_block
---------------------------------------------------------------------------------------
Net: spare_cell/LO |Net: _noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: sky130_fd_sc_hd__macro_sparecell:spar |Net: spare_cell/sky130_fd_sc_hd__conb_1_0/
sky130_fd_sc_hd__conb_1/HI = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: vccd |Net: vccd
sky130_fd_sc_hd__dfrtp_4/VPWR = 13 | sky130_fd_sc_hd__dfrtp_4/VPWR = 13
sky130_fd_sc_hd__dfrtp_4/VPB = 13 | sky130_fd_sc_hd__dfrtp_4/VPB = 13
sky130_fd_sc_hd__nand2b_2/VPWR = 14 | sky130_fd_sc_hd__nand2b_2/VPWR = 14
sky130_fd_sc_hd__nand2b_2/VPB = 14 | sky130_fd_sc_hd__nand2b_2/VPB = 14
sky130_fd_sc_hd__dfbbn_2/VPWR = 13 | sky130_fd_sc_hd__dfbbn_2/VPWR = 13
sky130_fd_sc_hd__dfbbn_2/VPB = 13 | sky130_fd_sc_hd__dfbbn_2/VPB = 13
sky130_fd_sc_hd__inv_2/VPWR = 16 | sky130_fd_sc_hd__inv_2/VPWR = 16
sky130_fd_sc_hd__inv_2/VPB = 16 | sky130_fd_sc_hd__inv_2/VPB = 14
sky130_fd_sc_hd__buf_16/VPWR = 19 | sky130_fd_sc_hd__buf_16/VPWR = 19
sky130_fd_sc_hd__buf_16/VPB = 19 | sky130_fd_sc_hd__buf_16/VPB = 19
sky130_fd_sc_hd__mux2_4/VPWR = 1 | sky130_fd_sc_hd__mux2_4/VPWR = 1
sky130_fd_sc_hd__mux2_4/VPB = 1 | sky130_fd_sc_hd__mux2_4/VPB = 1
sky130_fd_sc_hd__clkbuf_16/VPWR = 8 | sky130_fd_sc_hd__clkbuf_16/VPWR = 8
sky130_fd_sc_hd__clkbuf_16/VPB = 8 | sky130_fd_sc_hd__clkbuf_16/VPB = 8
sky130_fd_sc_hd__and2_0/VPWR = 1 | sky130_fd_sc_hd__and2_0/VPWR = 1
sky130_fd_sc_hd__and2_0/VPB = 1 | sky130_fd_sc_hd__and2_0/VPB = 1
sky130_fd_sc_hd__dlygate4sd3_1/VPWR = 13 | sky130_fd_sc_hd__dlygate4sd3_1/VPWR = 13
sky130_fd_sc_hd__dlygate4sd3_1/VPB = 13 | sky130_fd_sc_hd__dlygate4sd3_1/VPB = 13
sky130_fd_sc_hd__diode_2/VPWR = 23 | sky130_fd_sc_hd__diode_2/VPWR = 23
sky130_fd_sc_hd__diode_2/VPB = 23 | sky130_fd_sc_hd__diode_2/VPB = 23
sky130_fd_sc_hd__decap_3/VPWR = 1 | sky130_fd_sc_hd__decap_3/VPWR = 1
sky130_fd_sc_hd__decap_3/VPB = 1 | sky130_fd_sc_hd__decap_3/VPB = 1
sky130_fd_sc_hd__conb_1/VPB = 2 | sky130_fd_sc_hd__conb_1/VPB = 2
sky130_fd_sc_hd__conb_1/VPWR = 2 | sky130_fd_sc_hd__conb_1/VPWR = 1
sky130_fd_sc_hd__buf_2/VPWR = 16 | sky130_fd_sc_hd__buf_2/VPWR = 16
sky130_fd_sc_hd__buf_2/VPB = 16 | sky130_fd_sc_hd__buf_2/VPB = 16
sky130_fd_sc_hd__or2_0/VPWR = 13 | sky130_fd_sc_hd__or2_0/VPWR = 13
sky130_fd_sc_hd__or2_0/VPB = 13 | sky130_fd_sc_hd__or2_0/VPB = 13
sky130_fd_sc_hd__nand2_2/VPWR = 2 | sky130_fd_sc_hd__nand2_2/Y = 2
sky130_fd_sc_hd__nand2_2/VPB = 2 | sky130_fd_sc_hd__nand2_2/VNB = 2
sky130_fd_sc_hd__nor2_2/VPWR = 2 | sky130_fd_sc_hd__inv_2/VNB = 2
sky130_fd_sc_hd__nor2_2/VPB = 2 | sky130_fd_sc_hd__nor2_2/Y = 2
sky130_fd_sc_hd__and2_2/VPWR = 1 | sky130_fd_sc_hd__and2_2/VPWR = 1
sky130_fd_sc_hd__and2_2/VPB = 1 | sky130_fd_sc_hd__and2_2/VPB = 1
sky130_fd_sc_hd__o21ai_4/VPWR = 1 | sky130_fd_sc_hd__o21ai_4/VPWR = 1
sky130_fd_sc_hd__o21ai_4/VPB = 1 | sky130_fd_sc_hd__o21ai_4/VPB = 1
sky130_fd_sc_hd__o21ai_2/VPWR = 1 | sky130_fd_sc_hd__o21ai_2/VPWR = 1
sky130_fd_sc_hd__o21ai_2/VPB = 1 | sky130_fd_sc_hd__o21ai_2/VPB = 1
sky130_fd_sc_hd__and2b_2/VPWR = 1 | sky130_fd_sc_hd__and2b_2/VPWR = 1
sky130_fd_sc_hd__and2b_2/VPB = 1 | sky130_fd_sc_hd__and2b_2/VPB = 1
sky130_fd_sc_hd__dfrtp_2/VPWR = 1 | sky130_fd_sc_hd__dfrtp_2/VPWR = 1
sky130_fd_sc_hd__dfrtp_2/VPB = 1 | sky130_fd_sc_hd__dfrtp_2/VPB = 1
sky130_fd_sc_hd__and3b_2/VPWR = 1 | sky130_fd_sc_hd__and3b_2/VPWR = 1
sky130_fd_sc_hd__and3b_2/VPB = 1 | sky130_fd_sc_hd__and3b_2/VPB = 1
| sky130_fd_sc_hd__nor2_2/VNB = 2
| sky130_fd_sc_hd__conb_1/LO = 1
|
Net: vssd |Net: vssd
sky130_fd_sc_hd__dfrtp_4/VGND = 13 | sky130_fd_sc_hd__dfrtp_4/VGND = 13
sky130_fd_sc_hd__dfrtp_4/VNB = 13 | sky130_fd_sc_hd__dfrtp_4/VNB = 13
sky130_fd_sc_hd__nand2b_2/VGND = 14 | sky130_fd_sc_hd__nand2b_2/VGND = 14
sky130_fd_sc_hd__nand2b_2/VNB = 14 | sky130_fd_sc_hd__nand2b_2/VNB = 14
sky130_fd_sc_hd__dfbbn_2/VGND = 13 | sky130_fd_sc_hd__dfbbn_2/VGND = 13
sky130_fd_sc_hd__dfbbn_2/VNB = 13 | sky130_fd_sc_hd__dfbbn_2/VNB = 13
sky130_fd_sc_hd__inv_2/VGND = 16 | sky130_fd_sc_hd__inv_2/VGND = 14
sky130_fd_sc_hd__inv_2/VNB = 16 | sky130_fd_sc_hd__inv_2/VNB = 14
sky130_fd_sc_hd__buf_16/VGND = 19 | sky130_fd_sc_hd__buf_16/VGND = 19
sky130_fd_sc_hd__buf_16/VNB = 19 | sky130_fd_sc_hd__buf_16/VNB = 19
sky130_fd_sc_hd__mux2_4/VGND = 1 | sky130_fd_sc_hd__mux2_4/VGND = 1
sky130_fd_sc_hd__mux2_4/VNB = 1 | sky130_fd_sc_hd__mux2_4/VNB = 1
sky130_fd_sc_hd__clkbuf_16/VGND = 8 | sky130_fd_sc_hd__clkbuf_16/VGND = 8
sky130_fd_sc_hd__clkbuf_16/VNB = 8 | sky130_fd_sc_hd__clkbuf_16/VNB = 8
sky130_fd_sc_hd__and2_0/VGND = 1 | sky130_fd_sc_hd__and2_0/VGND = 1
sky130_fd_sc_hd__and2_0/VNB = 1 | sky130_fd_sc_hd__and2_0/VNB = 1
sky130_fd_sc_hd__dlygate4sd3_1/VGND = 13 | sky130_fd_sc_hd__dlygate4sd3_1/VGND = 13
sky130_fd_sc_hd__dlygate4sd3_1/VNB = 13 | sky130_fd_sc_hd__dlygate4sd3_1/VNB = 13
sky130_fd_sc_hd__diode_2/VGND = 23 | sky130_fd_sc_hd__diode_2/VGND = 23
sky130_fd_sc_hd__diode_2/VNB = 23 | sky130_fd_sc_hd__diode_2/VNB = 23
sky130_fd_sc_hd__decap_3/VGND = 1 | sky130_fd_sc_hd__decap_3/VGND = 1
sky130_fd_sc_hd__decap_3/VNB = 1 | sky130_fd_sc_hd__decap_3/VNB = 1
sky130_fd_sc_hd__conb_1/VNB = 2 | sky130_fd_sc_hd__conb_1/VNB = 1
sky130_fd_sc_hd__conb_1/VGND = 2 | sky130_fd_sc_hd__conb_1/VGND = 1
sky130_fd_sc_hd__buf_2/VGND = 16 | sky130_fd_sc_hd__buf_2/VGND = 16
sky130_fd_sc_hd__buf_2/VNB = 16 | sky130_fd_sc_hd__buf_2/VNB = 16
sky130_fd_sc_hd__or2_0/VGND = 13 | sky130_fd_sc_hd__or2_0/VGND = 13
sky130_fd_sc_hd__or2_0/VNB = 13 | sky130_fd_sc_hd__or2_0/VNB = 13
sky130_fd_sc_hd__nand2_2/VGND = 2 | sky130_fd_sc_hd__nand2_2/VPWR = 2
sky130_fd_sc_hd__nand2_2/VNB = 2 | sky130_fd_sc_hd__nand2_2/VPB = 2
sky130_fd_sc_hd__nor2_2/VGND = 2 | sky130_fd_sc_hd__inv_2/Y = 2
sky130_fd_sc_hd__nor2_2/VNB = 2 | sky130_fd_sc_hd__inv_2/VPB = 2
sky130_fd_sc_hd__and2_2/VGND = 1 | sky130_fd_sc_hd__and2_2/VGND = 1
sky130_fd_sc_hd__and2_2/VNB = 1 | sky130_fd_sc_hd__and2_2/VNB = 1
sky130_fd_sc_hd__o21ai_4/VGND = 1 | sky130_fd_sc_hd__o21ai_4/VGND = 1
sky130_fd_sc_hd__o21ai_4/VNB = 1 | sky130_fd_sc_hd__o21ai_4/VNB = 1
sky130_fd_sc_hd__o21ai_2/VGND = 1 | sky130_fd_sc_hd__o21ai_2/VGND = 1
sky130_fd_sc_hd__o21ai_2/VNB = 1 | sky130_fd_sc_hd__o21ai_2/VNB = 1
sky130_fd_sc_hd__and2b_2/VGND = 1 | sky130_fd_sc_hd__and2b_2/VGND = 1
sky130_fd_sc_hd__and2b_2/VNB = 1 | sky130_fd_sc_hd__and2b_2/VNB = 1
sky130_fd_sc_hd__dfrtp_2/VGND = 1 | sky130_fd_sc_hd__dfrtp_2/VGND = 1
sky130_fd_sc_hd__dfrtp_2/VNB = 1 | sky130_fd_sc_hd__dfrtp_2/VNB = 1
sky130_fd_sc_hd__and3b_2/VGND = 1 | sky130_fd_sc_hd__and3b_2/VGND = 1
sky130_fd_sc_hd__and3b_2/VNB = 1 | sky130_fd_sc_hd__and3b_2/VNB = 1
| sky130_fd_sc_hd__nor2_2/VPWR = 2
| sky130_fd_sc_hd__nor2_2/VPB = 2
| sky130_fd_sc_hd__conb_1/HI = 1
| sky130_fd_sc_hd__conb_1/VPWR = 1
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: gpio_control_block |Circuit 2: gpio_control_block
---------------------------------------------------------------------------------------
Instance: sky130_fd_sc_hd__macro_sparecell |Instance: spare_cell//sky130_fd_sc_hd__con
LO = 5 | LO = 326
HI = 1 | HI = 326
VPB = 326 | VPB = 326
VNB = 326 | VNB = 1
VGND = 326 | VGND = 5
VPWR = 326 | VPWR = 326
---------------------------------------------------------------------------------------
Netlists do not match.
Flattening non-matched subcircuits gpio_control_block gpio_control_block
Class gpio_defaults_block_0403 (0): Merged 15 parallel devices.
Class gpio_defaults_block_0403 (1): Merged 15 parallel devices.
Subcircuit summary:
Circuit 1: gpio_defaults_block_0403 |Circuit 2: gpio_defaults_block_0403
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__conb_1 (13) |sky130_fd_sc_hd__conb_1 (13)
sky130_fd_sc_hd__decap_12 (8->1) |sky130_fd_sc_hd__decap_12 (8->1)
sky130_fd_sc_hd__decap_4 (3->1) |sky130_fd_sc_hd__decap_4 (3->1)
sky130_fd_sc_hd__decap_3 (7->1) |sky130_fd_sc_hd__decap_3 (7->1)
sky130_fd_sc_hd__decap_6 (1) |sky130_fd_sc_hd__decap_6 (1)
Number of devices: 17 |Number of devices: 17
Number of nets: 28 |Number of nets: 28
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: gpio_defaults_block_0403 |Circuit 2: gpio_defaults_block_0403
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
gpio_defaults[1] |gpio_defaults[1]
gpio_defaults[10] |gpio_defaults[10]
gpio_defaults[0] |gpio_defaults[0]
gpio_defaults[11] |gpio_defaults[11]
gpio_defaults[3] |gpio_defaults[3]
gpio_defaults[5] |gpio_defaults[5]
gpio_defaults[7] |gpio_defaults[7]
gpio_defaults[9] |gpio_defaults[9]
gpio_defaults[12] |gpio_defaults[12]
gpio_defaults[2] |gpio_defaults[2]
gpio_defaults[4] |gpio_defaults[4]
gpio_defaults[6] |gpio_defaults[6]
gpio_defaults[8] |gpio_defaults[8]
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes gpio_defaults_block_0403 and gpio_defaults_block_0403 are equivalent.
Class digital_pll (0): Merged 220 parallel devices.
Class digital_pll (1): Merged 220 parallel devices.
Subcircuit summary:
Circuit 1: digital_pll |Circuit 2: digital_pll
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__xnor2_2 (11) |sky130_fd_sc_hd__xnor2_2 (11)
sky130_fd_sc_hd__a211o_2 (3) |sky130_fd_sc_hd__a211o_2 (3)
sky130_fd_sc_hd__nor2_2 (42) |sky130_fd_sc_hd__nor2_2 (42)
sky130_fd_sc_hd__decap_4 (85->1) |sky130_fd_sc_hd__decap_4 (85->1)
sky130_fd_sc_hd__clkinv_1 (13) |sky130_fd_sc_hd__clkinv_1 (13)
sky130_fd_sc_hd__o21ai_2 (6) |sky130_fd_sc_hd__o21ai_2 (6)
sky130_fd_sc_hd__buf_2 (32) |sky130_fd_sc_hd__buf_2 (32)
sky130_fd_sc_hd__o21a_2 (5) |sky130_fd_sc_hd__o21a_2 (5)
sky130_fd_sc_hd__einvp_2 (26) |sky130_fd_sc_hd__einvp_2 (26)
sky130_fd_sc_hd__decap_3 (105->1) |sky130_fd_sc_hd__decap_3 (105->1)
sky130_fd_sc_hd__diode_2 (56->37) |sky130_fd_sc_hd__diode_2 (56->37)
sky130_fd_sc_hd__einvn_8 (13) |sky130_fd_sc_hd__einvn_8 (13)
sky130_fd_sc_hd__o2111a_2 (2) |sky130_fd_sc_hd__o2111a_2 (2)
sky130_fd_sc_hd__mux2_2 (11) |sky130_fd_sc_hd__mux2_2 (11)
sky130_fd_sc_hd__inv_2 (13) |sky130_fd_sc_hd__inv_2 (13)
sky130_fd_sc_hd__a21o_2 (14) |sky130_fd_sc_hd__a21o_2 (14)
sky130_fd_sc_hd__nand2_2 (20) |sky130_fd_sc_hd__nand2_2 (20)
sky130_fd_sc_hd__einvn_4 (13) |sky130_fd_sc_hd__einvn_4 (13)
sky130_fd_sc_hd__o31a_2 (4) |sky130_fd_sc_hd__o31a_2 (4)
sky130_fd_sc_hd__o211a_2 (7) |sky130_fd_sc_hd__o211a_2 (7)
sky130_fd_sc_hd__decap_6 (7->1) |sky130_fd_sc_hd__decap_6 (7->1)
sky130_fd_sc_hd__and2_2 (14) |sky130_fd_sc_hd__and2_2 (14)
sky130_fd_sc_hd__clkbuf_2 (12) |sky130_fd_sc_hd__clkbuf_2 (12)
sky130_fd_sc_hd__and3b_2 (2) |sky130_fd_sc_hd__and3b_2 (2)
sky130_fd_sc_hd__o22a_2 (4) |sky130_fd_sc_hd__o22a_2 (4)
sky130_fd_sc_hd__nand3b_2 (2) |sky130_fd_sc_hd__nand3b_2 (2)
sky130_fd_sc_hd__clkbuf_1 (13) |sky130_fd_sc_hd__clkbuf_1 (13)
sky130_fd_sc_hd__nand4b_2 (1) |sky130_fd_sc_hd__nand4b_2 (1)
sky130_fd_sc_hd__nand3_2 (3) |sky130_fd_sc_hd__nand3_2 (3)
sky130_fd_sc_hd__a22o_2 (7) |sky130_fd_sc_hd__a22o_2 (7)
sky130_fd_sc_hd__xor2_2 (4) |sky130_fd_sc_hd__xor2_2 (4)
sky130_fd_sc_hd__nand2b_2 (7) |sky130_fd_sc_hd__nand2b_2 (7)
sky130_fd_sc_hd__a21boi_2 (1) |sky130_fd_sc_hd__a21boi_2 (1)
sky130_fd_sc_hd__a32o_2 (6) |sky130_fd_sc_hd__a32o_2 (6)
sky130_fd_sc_hd__dfrtp_2 (23) |sky130_fd_sc_hd__dfrtp_2 (23)
sky130_fd_sc_hd__o2bb2a_2 (1) |sky130_fd_sc_hd__o2bb2a_2 (1)
sky130_fd_sc_hd__einvp_1 (1) |sky130_fd_sc_hd__einvp_1 (1)
sky130_ef_sc_hd__decap_12 (3->1) |sky130_ef_sc_hd__decap_12 (3->1)
sky130_fd_sc_hd__a21oi_2 (5) |sky130_fd_sc_hd__a21oi_2 (5)
sky130_fd_sc_hd__and4b_2 (2) |sky130_fd_sc_hd__and4b_2 (2)
sky130_fd_sc_hd__o221a_2 (1) |sky130_fd_sc_hd__o221a_2 (1)
sky130_fd_sc_hd__and3_2 (6) |sky130_fd_sc_hd__and3_2 (6)
sky130_fd_sc_hd__and2b_2 (1) |sky130_fd_sc_hd__and2b_2 (1)
sky130_fd_sc_hd__o21ba_2 (1) |sky130_fd_sc_hd__o21ba_2 (1)
sky130_fd_sc_hd__o32a_2 (1) |sky130_fd_sc_hd__o32a_2 (1)
sky130_fd_sc_hd__clkbuf_16 (2) |sky130_fd_sc_hd__clkbuf_16 (2)
sky130_fd_sc_hd__decap_8 (6->1) |sky130_fd_sc_hd__decap_8 (6->1)
sky130_fd_sc_hd__a31o_2 (1) |sky130_fd_sc_hd__a31o_2 (1)
sky130_fd_sc_hd__clkinv_2 (2) |sky130_fd_sc_hd__clkinv_2 (2)
sky130_fd_sc_hd__clkinv_8 (2) |sky130_fd_sc_hd__clkinv_8 (2)
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
sky130_fd_sc_hd__or2_2 (1) |sky130_fd_sc_hd__or2_2 (1)
sky130_fd_sc_hd__nand4_2 (1) |sky130_fd_sc_hd__nand4_2 (1)
Number of devices: 405 |Number of devices: 405
Number of nets: 374 |Number of nets: 374
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: digital_pll |Circuit 2: digital_pll
-------------------------------------------|-------------------------------------------
clockp[0] |clockp[0]
clockp[1] |clockp[1]
div[3] |div[3]
div[2] |div[2]
ext_trim[0] |ext_trim[0]
ext_trim[1] |ext_trim[1]
ext_trim[2] |ext_trim[2]
ext_trim[3] |ext_trim[3]
ext_trim[5] |ext_trim[5]
ext_trim[4] |ext_trim[4]
ext_trim[6] |ext_trim[6]
ext_trim[8] |ext_trim[8]
ext_trim[10] |ext_trim[10]
ext_trim[11] |ext_trim[11]
ext_trim[7] |ext_trim[7]
ext_trim[12] |ext_trim[12]
ext_trim[14] |ext_trim[14]
ext_trim[9] |ext_trim[9]
ext_trim[15] |ext_trim[15]
ext_trim[17] |ext_trim[17]
ext_trim[18] |ext_trim[18]
ext_trim[19] |ext_trim[19]
ext_trim[20] |ext_trim[20]
ext_trim[21] |ext_trim[21]
ext_trim[13] |ext_trim[13]
ext_trim[22] |ext_trim[22]
ext_trim[16] |ext_trim[16]
ext_trim[23] |ext_trim[23]
ext_trim[24] |ext_trim[24]
ext_trim[25] |ext_trim[25]
enable |enable
resetb |resetb
osc |osc
dco |dco
div[1] |div[1]
div[0] |div[0]
div[4] |div[4]
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes digital_pll and digital_pll are equivalent.
Circuit 2 cell chip_io_alt is a black box; will not flatten Circuit 1
Class chip_io_alt (0): Merged 191 parallel devices.
Subcircuit pins:
Circuit 1: chip_io_alt |Circuit 2: chip_io_alt
-------------------------------------------|-------------------------------------------
clock |clock
clock_core |clock_core
por |por
flash_clk |flash_clk
flash_csb |flash_csb
flash_io0 |flash_io0
flash_io0_di_core |flash_io0_di_core
flash_io0_do_core |flash_io0_do_core
flash_io0_ieb_core |flash_io0_ieb_core
flash_io0_oeb_core |flash_io0_oeb_core
flash_io1 |flash_io1
flash_io1_di_core |flash_io1_di_core
flash_io1_do_core |flash_io1_do_core
flash_io1_ieb_core |flash_io1_ieb_core
flash_io1_oeb_core |flash_io1_oeb_core
gpio |gpio
gpio_in_core |gpio_in_core
gpio_inenb_core |gpio_inenb_core
gpio_mode0_core |gpio_mode0_core
gpio_out_core |gpio_out_core
gpio_outenb_core |gpio_outenb_core
vccd_pad |vccd_pad
vdda_pad |vdda_pad
vddio_pad |vddio_pad
vssa_pad |vssa_pad
vssio_pad |vssio_pad
vssio_pad2 |vssio_pad2
mprj_io[0] |mprj_io[0]
mprj_io_analog_en[0] |mprj_io_analog_en[0]
mprj_io_analog_pol[0] |mprj_io_analog_pol[0]
mprj_io_analog_sel[0] |mprj_io_analog_sel[0]
mprj_io_dm[0] |mprj_io_dm[0]
mprj_io_dm[1] |mprj_io_dm[1]
mprj_io_dm[2] |mprj_io_dm[2]
mprj_io_holdover[0] |mprj_io_holdover[0]
mprj_io_ib_mode_sel[0] |mprj_io_ib_mode_sel[0]
mprj_io_inp_dis[0] |mprj_io_inp_dis[0]
mprj_io_oeb[0] |mprj_io_oeb[0]
mprj_io_out[0] |mprj_io_out[0]
mprj_io_slow_sel[0] |mprj_io_slow_sel[0]
mprj_io_vtrip_sel[0] |mprj_io_vtrip_sel[0]
mprj_io_in[0] |mprj_io_in[0]
mprj_io_in_3v3[0] |mprj_io_in_3v3[0]
mprj_gpio_analog[3] |mprj_gpio_analog[3]
mprj_gpio_noesd[3] |mprj_gpio_noesd[3]
mprj_io[10] |mprj_io[10]
mprj_io_analog_en[10] |mprj_io_analog_en[10]
mprj_io_analog_pol[10] |mprj_io_analog_pol[10]
mprj_io_analog_sel[10] |mprj_io_analog_sel[10]
mprj_io_dm[30] |mprj_io_dm[30]
mprj_io_dm[31] |mprj_io_dm[31]
mprj_io_dm[32] |mprj_io_dm[32]
mprj_io_holdover[10] |mprj_io_holdover[10]
mprj_io_ib_mode_sel[10] |mprj_io_ib_mode_sel[10]
mprj_io_inp_dis[10] |mprj_io_inp_dis[10]
mprj_io_oeb[10] |mprj_io_oeb[10]
mprj_io_out[10] |mprj_io_out[10]
mprj_io_slow_sel[10] |mprj_io_slow_sel[10]
mprj_io_vtrip_sel[10] |mprj_io_vtrip_sel[10]
mprj_io_in[10] |mprj_io_in[10]
mprj_io_in_3v3[10] |mprj_io_in_3v3[10]
mprj_gpio_analog[4] |mprj_gpio_analog[4]
mprj_gpio_noesd[4] |mprj_gpio_noesd[4]
mprj_io[11] |mprj_io[11]
mprj_io_analog_en[11] |mprj_io_analog_en[11]
mprj_io_analog_pol[11] |mprj_io_analog_pol[11]
mprj_io_analog_sel[11] |mprj_io_analog_sel[11]
mprj_io_dm[33] |mprj_io_dm[33]
mprj_io_dm[34] |mprj_io_dm[34]
mprj_io_dm[35] |mprj_io_dm[35]
mprj_io_holdover[11] |mprj_io_holdover[11]
mprj_io_ib_mode_sel[11] |mprj_io_ib_mode_sel[11]
mprj_io_inp_dis[11] |mprj_io_inp_dis[11]
mprj_io_oeb[11] |mprj_io_oeb[11]
mprj_io_out[11] |mprj_io_out[11]
mprj_io_slow_sel[11] |mprj_io_slow_sel[11]
mprj_io_vtrip_sel[11] |mprj_io_vtrip_sel[11]
mprj_io_in[11] |mprj_io_in[11]
mprj_io_in_3v3[11] |mprj_io_in_3v3[11]
mprj_gpio_analog[5] |mprj_gpio_analog[5]
mprj_gpio_noesd[5] |mprj_gpio_noesd[5]
mprj_io[12] |mprj_io[12]
mprj_io_analog_en[12] |mprj_io_analog_en[12]
mprj_io_analog_pol[12] |mprj_io_analog_pol[12]
mprj_io_analog_sel[12] |mprj_io_analog_sel[12]
mprj_io_dm[36] |mprj_io_dm[36]
mprj_io_dm[37] |mprj_io_dm[37]
mprj_io_dm[38] |mprj_io_dm[38]
mprj_io_holdover[12] |mprj_io_holdover[12]
mprj_io_ib_mode_sel[12] |mprj_io_ib_mode_sel[12]
mprj_io_inp_dis[12] |mprj_io_inp_dis[12]
mprj_io_oeb[12] |mprj_io_oeb[12]
mprj_io_out[12] |mprj_io_out[12]
mprj_io_slow_sel[12] |mprj_io_slow_sel[12]
mprj_io_vtrip_sel[12] |mprj_io_vtrip_sel[12]
mprj_io_in[12] |mprj_io_in[12]
mprj_io_in_3v3[12] |mprj_io_in_3v3[12]
mprj_gpio_analog[6] |mprj_gpio_analog[6]
mprj_gpio_noesd[6] |mprj_gpio_noesd[6]
mprj_io[13] |mprj_io[13]
mprj_io_analog_en[13] |mprj_io_analog_en[13]
mprj_io_analog_pol[13] |mprj_io_analog_pol[13]
mprj_io_analog_sel[13] |mprj_io_analog_sel[13]
mprj_io_dm[39] |mprj_io_dm[39]
mprj_io_dm[40] |mprj_io_dm[40]
mprj_io_dm[41] |mprj_io_dm[41]
mprj_io_holdover[13] |mprj_io_holdover[13]
mprj_io_ib_mode_sel[13] |mprj_io_ib_mode_sel[13]
mprj_io_inp_dis[13] |mprj_io_inp_dis[13]
mprj_io_oeb[13] |mprj_io_oeb[13]
mprj_io_out[13] |mprj_io_out[13]
mprj_io_slow_sel[13] |mprj_io_slow_sel[13]
mprj_io_vtrip_sel[13] |mprj_io_vtrip_sel[13]
mprj_io_in[13] |mprj_io_in[13]
mprj_io_in_3v3[13] |mprj_io_in_3v3[13]
mprj_io[1] |mprj_io[1]
mprj_io_analog_en[1] |mprj_io_analog_en[1]
mprj_io_analog_pol[1] |mprj_io_analog_pol[1]
mprj_io_analog_sel[1] |mprj_io_analog_sel[1]
mprj_io_dm[3] |mprj_io_dm[3]
mprj_io_dm[4] |mprj_io_dm[4]
mprj_io_dm[5] |mprj_io_dm[5]
mprj_io_holdover[1] |mprj_io_holdover[1]
mprj_io_ib_mode_sel[1] |mprj_io_ib_mode_sel[1]
mprj_io_inp_dis[1] |mprj_io_inp_dis[1]
mprj_io_oeb[1] |mprj_io_oeb[1]
mprj_io_out[1] |mprj_io_out[1]
mprj_io_slow_sel[1] |mprj_io_slow_sel[1]
mprj_io_vtrip_sel[1] |mprj_io_vtrip_sel[1]
mprj_io_in[1] |mprj_io_in[1]
mprj_io_in_3v3[1] |mprj_io_in_3v3[1]
mprj_io[2] |mprj_io[2]
mprj_io_analog_en[2] |mprj_io_analog_en[2]
mprj_io_analog_pol[2] |mprj_io_analog_pol[2]
mprj_io_analog_sel[2] |mprj_io_analog_sel[2]
mprj_io_dm[6] |mprj_io_dm[6]
mprj_io_dm[7] |mprj_io_dm[7]
mprj_io_dm[8] |mprj_io_dm[8]
mprj_io_holdover[2] |mprj_io_holdover[2]
mprj_io_ib_mode_sel[2] |mprj_io_ib_mode_sel[2]
mprj_io_inp_dis[2] |mprj_io_inp_dis[2]
mprj_io_oeb[2] |mprj_io_oeb[2]
mprj_io_out[2] |mprj_io_out[2]
mprj_io_slow_sel[2] |mprj_io_slow_sel[2]
mprj_io_vtrip_sel[2] |mprj_io_vtrip_sel[2]
mprj_io_in[2] |mprj_io_in[2]
mprj_io_in_3v3[2] |mprj_io_in_3v3[2]
mprj_io[3] |mprj_io[3]
mprj_io_analog_en[3] |mprj_io_analog_en[3]
mprj_io_analog_pol[3] |mprj_io_analog_pol[3]
mprj_io_analog_sel[3] |mprj_io_analog_sel[3]
mprj_io_dm[10] |mprj_io_dm[10]
mprj_io_dm[11] |mprj_io_dm[11]
mprj_io_dm[9] |mprj_io_dm[9]
mprj_io_holdover[3] |mprj_io_holdover[3]
mprj_io_ib_mode_sel[3] |mprj_io_ib_mode_sel[3]
mprj_io_inp_dis[3] |mprj_io_inp_dis[3]
mprj_io_oeb[3] |mprj_io_oeb[3]
mprj_io_out[3] |mprj_io_out[3]
mprj_io_slow_sel[3] |mprj_io_slow_sel[3]
mprj_io_vtrip_sel[3] |mprj_io_vtrip_sel[3]
mprj_io_in[3] |mprj_io_in[3]
mprj_io_in_3v3[3] |mprj_io_in_3v3[3]
mprj_io[4] |mprj_io[4]
mprj_io_analog_en[4] |mprj_io_analog_en[4]
mprj_io_analog_pol[4] |mprj_io_analog_pol[4]
mprj_io_analog_sel[4] |mprj_io_analog_sel[4]
mprj_io_dm[12] |mprj_io_dm[12]
mprj_io_dm[13] |mprj_io_dm[13]
mprj_io_dm[14] |mprj_io_dm[14]
mprj_io_holdover[4] |mprj_io_holdover[4]
mprj_io_ib_mode_sel[4] |mprj_io_ib_mode_sel[4]
mprj_io_inp_dis[4] |mprj_io_inp_dis[4]
mprj_io_oeb[4] |mprj_io_oeb[4]
mprj_io_out[4] |mprj_io_out[4]
mprj_io_slow_sel[4] |mprj_io_slow_sel[4]
mprj_io_vtrip_sel[4] |mprj_io_vtrip_sel[4]
mprj_io_in[4] |mprj_io_in[4]
mprj_io_in_3v3[4] |mprj_io_in_3v3[4]
mprj_io[5] |mprj_io[5]
mprj_io_analog_en[5] |mprj_io_analog_en[5]
mprj_io_analog_pol[5] |mprj_io_analog_pol[5]
mprj_io_analog_sel[5] |mprj_io_analog_sel[5]
mprj_io_dm[15] |mprj_io_dm[15]
mprj_io_dm[16] |mprj_io_dm[16]
mprj_io_dm[17] |mprj_io_dm[17]
mprj_io_holdover[5] |mprj_io_holdover[5]
mprj_io_ib_mode_sel[5] |mprj_io_ib_mode_sel[5]
mprj_io_inp_dis[5] |mprj_io_inp_dis[5]
mprj_io_oeb[5] |mprj_io_oeb[5]
mprj_io_out[5] |mprj_io_out[5]
mprj_io_slow_sel[5] |mprj_io_slow_sel[5]
mprj_io_vtrip_sel[5] |mprj_io_vtrip_sel[5]
mprj_io_in[5] |mprj_io_in[5]
mprj_io_in_3v3[5] |mprj_io_in_3v3[5]
mprj_io[6] |mprj_io[6]
mprj_io_analog_en[6] |mprj_io_analog_en[6]
mprj_io_analog_pol[6] |mprj_io_analog_pol[6]
mprj_io_analog_sel[6] |mprj_io_analog_sel[6]
mprj_io_dm[18] |mprj_io_dm[18]
mprj_io_dm[19] |mprj_io_dm[19]
mprj_io_dm[20] |mprj_io_dm[20]
mprj_io_holdover[6] |mprj_io_holdover[6]
mprj_io_ib_mode_sel[6] |mprj_io_ib_mode_sel[6]
mprj_io_inp_dis[6] |mprj_io_inp_dis[6]
mprj_io_oeb[6] |mprj_io_oeb[6]
mprj_io_out[6] |mprj_io_out[6]
mprj_io_slow_sel[6] |mprj_io_slow_sel[6]
mprj_io_vtrip_sel[6] |mprj_io_vtrip_sel[6]
mprj_io_in[6] |mprj_io_in[6]
mprj_io_in_3v3[6] |mprj_io_in_3v3[6]
mprj_gpio_analog[0] |mprj_gpio_analog[0]
mprj_gpio_noesd[0] |mprj_gpio_noesd[0]
mprj_io[7] |mprj_io[7]
mprj_io_analog_en[7] |mprj_io_analog_en[7]
mprj_io_analog_pol[7] |mprj_io_analog_pol[7]
mprj_io_analog_sel[7] |mprj_io_analog_sel[7]
mprj_io_dm[21] |mprj_io_dm[21]
mprj_io_dm[22] |mprj_io_dm[22]
mprj_io_dm[23] |mprj_io_dm[23]
mprj_io_holdover[7] |mprj_io_holdover[7]
mprj_io_ib_mode_sel[7] |mprj_io_ib_mode_sel[7]
mprj_io_inp_dis[7] |mprj_io_inp_dis[7]
mprj_io_oeb[7] |mprj_io_oeb[7]
mprj_io_out[7] |mprj_io_out[7]
mprj_io_slow_sel[7] |mprj_io_slow_sel[7]
mprj_io_vtrip_sel[7] |mprj_io_vtrip_sel[7]
mprj_io_in[7] |mprj_io_in[7]
mprj_io_in_3v3[7] |mprj_io_in_3v3[7]
mprj_gpio_analog[1] |mprj_gpio_analog[1]
mprj_gpio_noesd[1] |mprj_gpio_noesd[1]
mprj_io[8] |mprj_io[8]
mprj_io_analog_en[8] |mprj_io_analog_en[8]
mprj_io_analog_pol[8] |mprj_io_analog_pol[8]
mprj_io_analog_sel[8] |mprj_io_analog_sel[8]
mprj_io_dm[24] |mprj_io_dm[24]
mprj_io_dm[25] |mprj_io_dm[25]
mprj_io_dm[26] |mprj_io_dm[26]
mprj_io_holdover[8] |mprj_io_holdover[8]
mprj_io_ib_mode_sel[8] |mprj_io_ib_mode_sel[8]
mprj_io_inp_dis[8] |mprj_io_inp_dis[8]
mprj_io_oeb[8] |mprj_io_oeb[8]
mprj_io_out[8] |mprj_io_out[8]
mprj_io_slow_sel[8] |mprj_io_slow_sel[8]
mprj_io_vtrip_sel[8] |mprj_io_vtrip_sel[8]
mprj_io_in[8] |mprj_io_in[8]
mprj_io_in_3v3[8] |mprj_io_in_3v3[8]
mprj_gpio_analog[2] |mprj_gpio_analog[2]
mprj_gpio_noesd[2] |mprj_gpio_noesd[2]
mprj_io[9] |mprj_io[9]
mprj_io_analog_en[9] |mprj_io_analog_en[9]
mprj_io_analog_pol[9] |mprj_io_analog_pol[9]
mprj_io_analog_sel[9] |mprj_io_analog_sel[9]
mprj_io_dm[27] |mprj_io_dm[27]
mprj_io_dm[28] |mprj_io_dm[28]
mprj_io_dm[29] |mprj_io_dm[29]
mprj_io_holdover[9] |mprj_io_holdover[9]
mprj_io_ib_mode_sel[9] |mprj_io_ib_mode_sel[9]
mprj_io_inp_dis[9] |mprj_io_inp_dis[9]
mprj_io_oeb[9] |mprj_io_oeb[9]
mprj_io_out[9] |mprj_io_out[9]
mprj_io_slow_sel[9] |mprj_io_slow_sel[9]
mprj_io_vtrip_sel[9] |mprj_io_vtrip_sel[9]
mprj_io_in[9] |mprj_io_in[9]
mprj_io_in_3v3[9] |mprj_io_in_3v3[9]
mprj_gpio_analog[7] |mprj_gpio_analog[7]
mprj_gpio_noesd[7] |mprj_gpio_noesd[7]
mprj_io[25] |mprj_io[25]
mprj_io_analog_en[14] |mprj_io_analog_en[14]
mprj_io_analog_pol[14] |mprj_io_analog_pol[14]
mprj_io_analog_sel[14] |mprj_io_analog_sel[14]
mprj_io_dm[42] |mprj_io_dm[42]
mprj_io_dm[43] |mprj_io_dm[43]
mprj_io_dm[44] |mprj_io_dm[44]
mprj_io_holdover[14] |mprj_io_holdover[14]
mprj_io_ib_mode_sel[14] |mprj_io_ib_mode_sel[14]
mprj_io_inp_dis[14] |mprj_io_inp_dis[14]
mprj_io_oeb[14] |mprj_io_oeb[14]
mprj_io_out[14] |mprj_io_out[14]
mprj_io_slow_sel[14] |mprj_io_slow_sel[14]
mprj_io_vtrip_sel[14] |mprj_io_vtrip_sel[14]
mprj_io_in[14] |mprj_io_in[14]
mprj_io_in_3v3[14] |mprj_io_in_3v3[14]
mprj_gpio_analog[17] |mprj_gpio_analog[17]
mprj_gpio_noesd[17] |mprj_gpio_noesd[17]
mprj_io[35] |mprj_io[35]
mprj_io_analog_en[24] |mprj_io_analog_en[24]
mprj_io_analog_pol[24] |mprj_io_analog_pol[24]
mprj_io_analog_sel[24] |mprj_io_analog_sel[24]
mprj_io_dm[72] |mprj_io_dm[72]
mprj_io_dm[73] |mprj_io_dm[73]
mprj_io_dm[74] |mprj_io_dm[74]
mprj_io_holdover[24] |mprj_io_holdover[24]
mprj_io_ib_mode_sel[24] |mprj_io_ib_mode_sel[24]
mprj_io_inp_dis[24] |mprj_io_inp_dis[24]
mprj_io_oeb[24] |mprj_io_oeb[24]
mprj_io_out[24] |mprj_io_out[24]
mprj_io_slow_sel[24] |mprj_io_slow_sel[24]
mprj_io_vtrip_sel[24] |mprj_io_vtrip_sel[24]
mprj_io_in[24] |mprj_io_in[24]
mprj_io_in_3v3[24] |mprj_io_in_3v3[24]
mprj_io[36] |mprj_io[36]
mprj_io_analog_en[25] |mprj_io_analog_en[25]
mprj_io_analog_pol[25] |mprj_io_analog_pol[25]
mprj_io_analog_sel[25] |mprj_io_analog_sel[25]
mprj_io_dm[75] |mprj_io_dm[75]
mprj_io_dm[76] |mprj_io_dm[76]
mprj_io_dm[77] |mprj_io_dm[77]
mprj_io_holdover[25] |mprj_io_holdover[25]
mprj_io_ib_mode_sel[25] |mprj_io_ib_mode_sel[25]
mprj_io_inp_dis[25] |mprj_io_inp_dis[25]
mprj_io_oeb[25] |mprj_io_oeb[25]
mprj_io_out[25] |mprj_io_out[25]
mprj_io_slow_sel[25] |mprj_io_slow_sel[25]
mprj_io_vtrip_sel[25] |mprj_io_vtrip_sel[25]
mprj_io_in[25] |mprj_io_in[25]
mprj_io_in_3v3[25] |mprj_io_in_3v3[25]
mprj_io[37] |mprj_io[37]
mprj_io_analog_en[26] |mprj_io_analog_en[26]
mprj_io_analog_pol[26] |mprj_io_analog_pol[26]
mprj_io_analog_sel[26] |mprj_io_analog_sel[26]
mprj_io_dm[78] |mprj_io_dm[78]
mprj_io_dm[79] |mprj_io_dm[79]
mprj_io_dm[80] |mprj_io_dm[80]
mprj_io_holdover[26] |mprj_io_holdover[26]
mprj_io_ib_mode_sel[26] |mprj_io_ib_mode_sel[26]
mprj_io_inp_dis[26] |mprj_io_inp_dis[26]
mprj_io_oeb[26] |mprj_io_oeb[26]
mprj_io_out[26] |mprj_io_out[26]
mprj_io_slow_sel[26] |mprj_io_slow_sel[26]
mprj_io_vtrip_sel[26] |mprj_io_vtrip_sel[26]
mprj_io_in[26] |mprj_io_in[26]
mprj_io_in_3v3[26] |mprj_io_in_3v3[26]
mprj_gpio_analog[8] |mprj_gpio_analog[8]
mprj_gpio_noesd[8] |mprj_gpio_noesd[8]
mprj_io[26] |mprj_io[26]
mprj_io_analog_en[15] |mprj_io_analog_en[15]
mprj_io_analog_pol[15] |mprj_io_analog_pol[15]
mprj_io_analog_sel[15] |mprj_io_analog_sel[15]
mprj_io_dm[45] |mprj_io_dm[45]
mprj_io_dm[46] |mprj_io_dm[46]
mprj_io_dm[47] |mprj_io_dm[47]
mprj_io_holdover[15] |mprj_io_holdover[15]
mprj_io_ib_mode_sel[15] |mprj_io_ib_mode_sel[15]
mprj_io_inp_dis[15] |mprj_io_inp_dis[15]
mprj_io_oeb[15] |mprj_io_oeb[15]
mprj_io_out[15] |mprj_io_out[15]
mprj_io_slow_sel[15] |mprj_io_slow_sel[15]
mprj_io_vtrip_sel[15] |mprj_io_vtrip_sel[15]
mprj_io_in[15] |mprj_io_in[15]
mprj_io_in_3v3[15] |mprj_io_in_3v3[15]
mprj_gpio_analog[9] |mprj_gpio_analog[9]
mprj_gpio_noesd[9] |mprj_gpio_noesd[9]
mprj_io[27] |mprj_io[27]
mprj_io_analog_en[16] |mprj_io_analog_en[16]
mprj_io_analog_pol[16] |mprj_io_analog_pol[16]
mprj_io_analog_sel[16] |mprj_io_analog_sel[16]
mprj_io_dm[48] |mprj_io_dm[48]
mprj_io_dm[49] |mprj_io_dm[49]
mprj_io_dm[50] |mprj_io_dm[50]
mprj_io_holdover[16] |mprj_io_holdover[16]
mprj_io_ib_mode_sel[16] |mprj_io_ib_mode_sel[16]
mprj_io_inp_dis[16] |mprj_io_inp_dis[16]
mprj_io_oeb[16] |mprj_io_oeb[16]
mprj_io_out[16] |mprj_io_out[16]
mprj_io_slow_sel[16] |mprj_io_slow_sel[16]
mprj_io_vtrip_sel[16] |mprj_io_vtrip_sel[16]
mprj_io_in[16] |mprj_io_in[16]
mprj_io_in_3v3[16] |mprj_io_in_3v3[16]
mprj_gpio_analog[10] |mprj_gpio_analog[10]
mprj_gpio_noesd[10] |mprj_gpio_noesd[10]
mprj_io[28] |mprj_io[28]
mprj_io_analog_en[17] |mprj_io_analog_en[17]
mprj_io_analog_pol[17] |mprj_io_analog_pol[17]
mprj_io_analog_sel[17] |mprj_io_analog_sel[17]
mprj_io_dm[51] |mprj_io_dm[51]
mprj_io_dm[52] |mprj_io_dm[52]
mprj_io_dm[53] |mprj_io_dm[53]
mprj_io_holdover[17] |mprj_io_holdover[17]
mprj_io_ib_mode_sel[17] |mprj_io_ib_mode_sel[17]
mprj_io_inp_dis[17] |mprj_io_inp_dis[17]
mprj_io_oeb[17] |mprj_io_oeb[17]
mprj_io_out[17] |mprj_io_out[17]
mprj_io_slow_sel[17] |mprj_io_slow_sel[17]
mprj_io_vtrip_sel[17] |mprj_io_vtrip_sel[17]
mprj_io_in[17] |mprj_io_in[17]
mprj_io_in_3v3[17] |mprj_io_in_3v3[17]
mprj_gpio_analog[11] |mprj_gpio_analog[11]
mprj_gpio_noesd[11] |mprj_gpio_noesd[11]
mprj_io[29] |mprj_io[29]
mprj_io_analog_en[18] |mprj_io_analog_en[18]
mprj_io_analog_pol[18] |mprj_io_analog_pol[18]
mprj_io_analog_sel[18] |mprj_io_analog_sel[18]
mprj_io_dm[54] |mprj_io_dm[54]
mprj_io_dm[55] |mprj_io_dm[55]
mprj_io_dm[56] |mprj_io_dm[56]
mprj_io_holdover[18] |mprj_io_holdover[18]
mprj_io_ib_mode_sel[18] |mprj_io_ib_mode_sel[18]
mprj_io_inp_dis[18] |mprj_io_inp_dis[18]
mprj_io_oeb[18] |mprj_io_oeb[18]
mprj_io_out[18] |mprj_io_out[18]
mprj_io_slow_sel[18] |mprj_io_slow_sel[18]
mprj_io_vtrip_sel[18] |mprj_io_vtrip_sel[18]
mprj_io_in[18] |mprj_io_in[18]
mprj_io_in_3v3[18] |mprj_io_in_3v3[18]
mprj_gpio_analog[12] |mprj_gpio_analog[12]
mprj_gpio_noesd[12] |mprj_gpio_noesd[12]
mprj_io[30] |mprj_io[30]
mprj_io_analog_en[19] |mprj_io_analog_en[19]
mprj_io_analog_pol[19] |mprj_io_analog_pol[19]
mprj_io_analog_sel[19] |mprj_io_analog_sel[19]
mprj_io_dm[57] |mprj_io_dm[57]
mprj_io_dm[58] |mprj_io_dm[58]
mprj_io_dm[59] |mprj_io_dm[59]
mprj_io_holdover[19] |mprj_io_holdover[19]
mprj_io_ib_mode_sel[19] |mprj_io_ib_mode_sel[19]
mprj_io_inp_dis[19] |mprj_io_inp_dis[19]
mprj_io_oeb[19] |mprj_io_oeb[19]
mprj_io_out[19] |mprj_io_out[19]
mprj_io_slow_sel[19] |mprj_io_slow_sel[19]
mprj_io_vtrip_sel[19] |mprj_io_vtrip_sel[19]
mprj_io_in[19] |mprj_io_in[19]
mprj_io_in_3v3[19] |mprj_io_in_3v3[19]
mprj_gpio_analog[13] |mprj_gpio_analog[13]
mprj_gpio_noesd[13] |mprj_gpio_noesd[13]
mprj_io[31] |mprj_io[31]
mprj_io_analog_en[20] |mprj_io_analog_en[20]
mprj_io_analog_pol[20] |mprj_io_analog_pol[20]
mprj_io_analog_sel[20] |mprj_io_analog_sel[20]
mprj_io_dm[60] |mprj_io_dm[60]
mprj_io_dm[61] |mprj_io_dm[61]
mprj_io_dm[62] |mprj_io_dm[62]
mprj_io_holdover[20] |mprj_io_holdover[20]
mprj_io_ib_mode_sel[20] |mprj_io_ib_mode_sel[20]
mprj_io_inp_dis[20] |mprj_io_inp_dis[20]
mprj_io_oeb[20] |mprj_io_oeb[20]
mprj_io_out[20] |mprj_io_out[20]
mprj_io_slow_sel[20] |mprj_io_slow_sel[20]
mprj_io_vtrip_sel[20] |mprj_io_vtrip_sel[20]
mprj_io_in[20] |mprj_io_in[20]
mprj_io_in_3v3[20] |mprj_io_in_3v3[20]
mprj_gpio_analog[14] |mprj_gpio_analog[14]
mprj_gpio_noesd[14] |mprj_gpio_noesd[14]
mprj_io[32] |mprj_io[32]
mprj_io_analog_en[21] |mprj_io_analog_en[21]
mprj_io_analog_pol[21] |mprj_io_analog_pol[21]
mprj_io_analog_sel[21] |mprj_io_analog_sel[21]
mprj_io_dm[63] |mprj_io_dm[63]
mprj_io_dm[64] |mprj_io_dm[64]
mprj_io_dm[65] |mprj_io_dm[65]
mprj_io_holdover[21] |mprj_io_holdover[21]
mprj_io_ib_mode_sel[21] |mprj_io_ib_mode_sel[21]
mprj_io_inp_dis[21] |mprj_io_inp_dis[21]
mprj_io_oeb[21] |mprj_io_oeb[21]
mprj_io_out[21] |mprj_io_out[21]
mprj_io_slow_sel[21] |mprj_io_slow_sel[21]
mprj_io_vtrip_sel[21] |mprj_io_vtrip_sel[21]
mprj_io_in[21] |mprj_io_in[21]
mprj_io_in_3v3[21] |mprj_io_in_3v3[21]
mprj_gpio_analog[15] |mprj_gpio_analog[15]
mprj_gpio_noesd[15] |mprj_gpio_noesd[15]
mprj_io[33] |mprj_io[33]
mprj_io_analog_en[22] |mprj_io_analog_en[22]
mprj_io_analog_pol[22] |mprj_io_analog_pol[22]
mprj_io_analog_sel[22] |mprj_io_analog_sel[22]
mprj_io_dm[66] |mprj_io_dm[66]
mprj_io_dm[67] |mprj_io_dm[67]
mprj_io_dm[68] |mprj_io_dm[68]
mprj_io_holdover[22] |mprj_io_holdover[22]
mprj_io_ib_mode_sel[22] |mprj_io_ib_mode_sel[22]
mprj_io_inp_dis[22] |mprj_io_inp_dis[22]
mprj_io_oeb[22] |mprj_io_oeb[22]
mprj_io_out[22] |mprj_io_out[22]
mprj_io_slow_sel[22] |mprj_io_slow_sel[22]
mprj_io_vtrip_sel[22] |mprj_io_vtrip_sel[22]
mprj_io_in[22] |mprj_io_in[22]
mprj_io_in_3v3[22] |mprj_io_in_3v3[22]
mprj_gpio_analog[16] |mprj_gpio_analog[16]
mprj_gpio_noesd[16] |mprj_gpio_noesd[16]
mprj_io[34] |mprj_io[34]
mprj_io_analog_en[23] |mprj_io_analog_en[23]
mprj_io_analog_pol[23] |mprj_io_analog_pol[23]
mprj_io_analog_sel[23] |mprj_io_analog_sel[23]
mprj_io_dm[69] |mprj_io_dm[69]
mprj_io_dm[70] |mprj_io_dm[70]
mprj_io_dm[71] |mprj_io_dm[71]
mprj_io_holdover[23] |mprj_io_holdover[23]
mprj_io_ib_mode_sel[23] |mprj_io_ib_mode_sel[23]
mprj_io_inp_dis[23] |mprj_io_inp_dis[23]
mprj_io_oeb[23] |mprj_io_oeb[23]
mprj_io_out[23] |mprj_io_out[23]
mprj_io_slow_sel[23] |mprj_io_slow_sel[23]
mprj_io_vtrip_sel[23] |mprj_io_vtrip_sel[23]
mprj_io_in[23] |mprj_io_in[23]
mprj_io_in_3v3[23] |mprj_io_in_3v3[23]
resetb |resetb
resetb_core_h |resetb_core_h
mprj_io[15] |mprj_io[15]
mprj_analog[2] |mprj_analog[2]
mprj_io[16] |mprj_io[16]
mprj_io[17] |mprj_io[17]
mprj_clamp_high[0] |mprj_clamp_high[0]
mprj_io[18] |mprj_io[18]
vccd1_pad |vccd1_pad
vdda1_pad |vdda1_pad
vdda1_pad2 |vdda1_pad2
vccd1 |vccd1
vdda1 |vdda1
vssd1_pad |vssd1_pad
mprj_analog[9] |mprj_analog[9]
mprj_analog[10] |mprj_analog[10]
mprj_io[24] |mprj_io[24]
mprj_analog[5] |mprj_analog[5]
mprj_clamp_high[1] |mprj_clamp_high[1]
mprj_clamp_low[1] |mprj_clamp_low[1]
mprj_io[19] |mprj_io[19]
vccd2_pad |vccd2_pad
vdda2_pad |vdda2_pad
vssa2_pad |vssa2_pad
vccd2 |vccd2
vdda2 |vdda2
vssd2_pad |vssd2_pad
flash_csb_core |flash_csb_core
flash_clk_oeb_core |flash_clk_oeb_core
flash_clk_core |flash_clk_core
flash_csb_oeb_core |flash_csb_oeb_core
mprj_io_one[0] |mprj_io_one[0]
mprj_io_one[1] |mprj_io_one[1]
mprj_io_one[2] |mprj_io_one[2]
mprj_io_one[3] |mprj_io_one[3]
mprj_io_one[4] |mprj_io_one[4]
mprj_io_one[5] |mprj_io_one[5]
mprj_io_one[6] |mprj_io_one[6]
mprj_io_one[7] |mprj_io_one[7]
mprj_io_one[8] |mprj_io_one[8]
mprj_io_one[9] |mprj_io_one[9]
mprj_io_one[10] |mprj_io_one[10]
mprj_io_one[11] |mprj_io_one[11]
mprj_io_one[12] |mprj_io_one[12]
mprj_io_one[13] |mprj_io_one[13]
mprj_io_one[14] |mprj_io_one[14]
mprj_io_one[15] |mprj_io_one[15]
mprj_io_one[16] |mprj_io_one[16]
mprj_io_one[17] |mprj_io_one[17]
mprj_io_one[18] |mprj_io_one[18]
mprj_io_one[19] |mprj_io_one[19]
mprj_io_one[20] |mprj_io_one[20]
mprj_io_one[21] |mprj_io_one[21]
mprj_io_one[22] |mprj_io_one[22]
mprj_io_one[23] |mprj_io_one[23]
mprj_io_one[24] |mprj_io_one[24]
mprj_io_one[25] |mprj_io_one[25]
mprj_io_one[26] |mprj_io_one[26]
porb_h |porb_h
gpio_mode1_core |gpio_mode1_core
mprj_io[21] |mprj_io[21]
mprj_analog[6] |mprj_analog[6]
mprj_analog[7] |mprj_analog[7]
mprj_io[20] |mprj_io[20]
mprj_io[22] |mprj_io[22]
mprj_analog[3] |mprj_analog[3]
mprj_clamp_low[0] |mprj_clamp_low[0]
vssd1 |vssd1
mprj_clamp_high[2] |mprj_clamp_high[2]
mprj_clamp_low[2] |mprj_clamp_low[2]
vssd2 |vssd2
mprj_analog[8] |mprj_analog[8]
mprj_io[23] |mprj_io[23]
vdda |vdda
vddio_pad2 |vddio_pad2
mprj_io[14] |mprj_io[14]
mprj_analog[0] |mprj_analog[0]
vssd_pad |vssd_pad
vssa1_pad |vssa1_pad
mprj_analog[1] |mprj_analog[1]
vssa2 |vssa2
vccd |vccd
vssa |vssa
vssa1_pad2 |vssa1_pad2
vssio |vssio
mprj_analog[4] |mprj_analog[4]
vddio |vddio
vssa1 |vssa1
vssd |vssd
xresloop |(no matching pin)
xres_vss_loop |(no matching pin)
w_694469_865869# |(no matching pin)
w_23367_407274# |(no matching pin)
w_694469_100152# |(no matching pin)
w_23367_534874# |(no matching pin)
w_404752_21253# |(no matching pin)
w_459552_23367# |(no matching pin)
w_23367_280765# |(no matching pin)
w_692253_776670# |(no matching pin)
w_23367_710765# |(no matching pin)
w_78010_1007543# |(no matching pin)
w_692355_547952# |(no matching pin)
w_23367_537965# |(no matching pin)
w_21151_364074# |(no matching pin)
w_459552_21253# |(no matching pin)
w_694469_145352# |(no matching pin)
w_692355_593152# |(no matching pin)
w_694469_190352# |(no matching pin)
w_349952_23367# |(no matching pin)
w_692355_325552# |(no matching pin)
w_189869_23367# |(no matching pin)
w_694469_235552# |(no matching pin)
w_21151_794074# |(no matching pin)
w_692355_683352# |(no matching pin)
w_21253_194365# |(no matching pin)
w_694469_280552# |(no matching pin)
w_21253_624365# |(no matching pin)
w_295152_23367# |(no matching pin)
w_349952_21253# |(no matching pin)
w_23367_578074# |(no matching pin)
w_692253_551270# |(no matching pin)
w_694469_370752# |(no matching pin)
w_189869_21253# |(no matching pin)
w_21151_277674# |(no matching pin)
w_692253_641470# |(no matching pin)
w_295152_21253# |(no matching pin)
w_21151_707674# |(no matching pin)
w_23367_234474# |(no matching pin)
w_692355_100152# |(no matching pin)
w_694469_776669# |(no matching pin)
w_692253_596470# |(no matching pin)
w_692253_731670# |(no matching pin)
w_21253_280765# |(no matching pin)
w_692253_328870# |(no matching pin)
w_23367_410365# |(no matching pin)
w_21253_710765# |(no matching pin)
w_462869_23367# |(no matching pin)
w_23367_237565# |(no matching pin)
w_21253_537965# |(no matching pin)
w_23367_664474# |(no matching pin)
w_692253_686670# |(no matching pin)
w_21151_191274# |(no matching pin)
w_692253_374070# |(no matching pin)
w_692355_145352# |(no matching pin)
w_21151_621274# |(no matching pin)
w_692355_190352# |(no matching pin)
w_694469_862552# |(no matching pin)
w_687543_952480# |(no matching pin)
w_180810_1007543# |(no matching pin)
w_462869_21253# |(no matching pin)
w_23367_667565# |(no matching pin)
w_692355_235552# |(no matching pin)
w_694469_551269# |(no matching pin)
w_23367_320874# |(no matching pin)
w_692355_280552# |(no matching pin)
w_692253_103470# |(no matching pin)
w_694469_641469# |(no matching pin)
w_129410_1007543# |(no matching pin)
w_692355_370752# |(no matching pin)
w_23367_323965# |(no matching pin)
w_23367_750874# |(no matching pin)
w_694469_596469# |(no matching pin)
w_23367_581165# |(no matching pin)
w_694469_731669# |(no matching pin)
w_526010_1007543# |(no matching pin)
w_21151_407274# |(no matching pin)
w_186552_23367# |(no matching pin)
w_517669_23367# |(no matching pin)
w_21151_534874# |(no matching pin)
w_694469_328869# |(no matching pin)
w_692253_148670# |(no matching pin)
w_23367_753965# |(no matching pin)
w_694469_686669# |(no matching pin)
w_692253_193670# |(no matching pin)
w_694469_374069# |(no matching pin)
w_21253_410365# |(no matching pin)
w_694469_638152# |(no matching pin)
w_186552_21253# |(no matching pin)
w_517669_21253# |(no matching pin)
w_21253_237565# |(no matching pin)
w_692253_238870# |(no matching pin)
w_23367_364074# |(no matching pin)
w_692253_283870# |(no matching pin)
w_474610_1007543# |(no matching pin)
w_694469_728352# |(no matching pin)
w_627810_1007543# |(no matching pin)
w_692355_862552# |(no matching pin)
w_694469_773352# |(no matching pin)
w_23367_367165# |(no matching pin)
w_21253_667565# |(no matching pin)
w_23367_794074# |(no matching pin)
w_694469_103469# |(no matching pin)
w_353269_23367# |(no matching pin)
w_21151_578074# |(no matching pin)
w_23367_797165# |(no matching pin)
w_21253_323965# |(no matching pin)
w_353269_21253# |(no matching pin)
w_23367_277674# |(no matching pin)
w_694469_148669# |(no matching pin)
w_21253_581165# |(no matching pin)
w_694469_193669# |(no matching pin)
w_4069_956010# |(no matching pin)
w_23367_707674# |(no matching pin)
w_21151_234474# |(no matching pin)
w_694469_238869# |(no matching pin)
w_21253_753965# |(no matching pin)
w_694469_283869# |(no matching pin)
w_692253_865870# |(no matching pin)
w_298469_23367# |(no matching pin)
w_694469_547952# |(no matching pin)
w_692355_638152# |(no matching pin)
w_21151_664474# |(no matching pin)
w_23367_191274# |(no matching pin)
w_408069_23367# |(no matching pin)
w_694469_593152# |(no matching pin)
w_23367_621274# |(no matching pin)
w_692355_728352# |(no matching pin)
w_514352_23367# |(no matching pin)
w_694469_325552# |(no matching pin)
w_692355_773352# |(no matching pin)
w_298469_21253# |(no matching pin)
w_694469_683352# |(no matching pin)
w_21253_367165# |(no matching pin)
w_23367_194365# |(no matching pin)
w_21151_320874# |(no matching pin)
w_408069_21253# |(no matching pin)
w_23367_624365# |(no matching pin)
w_514352_21253# |(no matching pin)
w_404752_23367# |(no matching pin)
w_21253_797165# |(no matching pin)
w_21151_750874# |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes chip_io_alt and chip_io_alt are equivalent.
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_6 in circuit mgmt_core_wrapper (0)(10271 instances)
Flattening unmatched subcell QI_sky130_ef_sc_hd__decap_12 in circuit mgmt_core_wrapper (0)(48747 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__diode_2 in circuit mgmt_core_wrapper (0)(37950 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_16 in circuit mgmt_core_wrapper (0)(578 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_4 in circuit mgmt_core_wrapper (0)(9275 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_3 in circuit mgmt_core_wrapper (0)(8721 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__decap_8 in circuit mgmt_core_wrapper (0)(7562 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a211o_1 in circuit mgmt_core_wrapper (0)(540 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__mux2_1 in circuit mgmt_core_wrapper (0)(3182 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o211a_1 in circuit mgmt_core_wrapper (0)(1019 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4b_1 in circuit mgmt_core_wrapper (0)(42 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o41a_1 in circuit mgmt_core_wrapper (0)(27 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a221o_1 in circuit mgmt_core_wrapper (0)(265 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a32o_1 in circuit mgmt_core_wrapper (0)(171 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor2_1 in circuit mgmt_core_wrapper (0)(215 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__dfxtp_1 in circuit mgmt_core_wrapper (0)(3755 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o31a_1 in circuit mgmt_core_wrapper (0)(254 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__dlygate4sd3_1 in circuit mgmt_core_wrapper (0)(3154 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__buf_6 in circuit mgmt_core_wrapper (0)(298 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__buf_12 in circuit mgmt_core_wrapper (0)(1138 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__buf_8 in circuit mgmt_core_wrapper (0)(237 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand2_1 in circuit mgmt_core_wrapper (0)(341 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__buf_4 in circuit mgmt_core_wrapper (0)(110 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a31o_1 in circuit mgmt_core_wrapper (0)(460 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21bo_1 in circuit mgmt_core_wrapper (0)(48 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21a_1 in circuit mgmt_core_wrapper (0)(314 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o221a_1 in circuit mgmt_core_wrapper (0)(293 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o311a_1 in circuit mgmt_core_wrapper (0)(302 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21o_1 in circuit mgmt_core_wrapper (0)(746 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a41o_1 in circuit mgmt_core_wrapper (0)(181 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3_1 in circuit mgmt_core_wrapper (0)(315 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o22a_1 in circuit mgmt_core_wrapper (0)(60 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a22o_2 in circuit mgmt_core_wrapper (0)(52 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and2b_1 in circuit mgmt_core_wrapper (0)(23 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21ai_1 in circuit mgmt_core_wrapper (0)(384 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4_1 in circuit mgmt_core_wrapper (0)(150 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a221o_4 in circuit mgmt_core_wrapper (0)(60 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__inv_2 in circuit mgmt_core_wrapper (0)(339 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a311o_1 in circuit mgmt_core_wrapper (0)(165 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3b_4 in circuit mgmt_core_wrapper (0)(6 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a2111o_1 in circuit mgmt_core_wrapper (0)(15 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor4_1 in circuit mgmt_core_wrapper (0)(34 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21ai_4 in circuit mgmt_core_wrapper (0)(51 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21ba_1 in circuit mgmt_core_wrapper (0)(146 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_8 in circuit mgmt_core_wrapper (0)(147 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a31oi_4 in circuit mgmt_core_wrapper (0)(16 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand4_1 in circuit mgmt_core_wrapper (0)(53 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor3_1 in circuit mgmt_core_wrapper (0)(46 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor2_2 in circuit mgmt_core_wrapper (0)(27 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand2_8 in circuit mgmt_core_wrapper (0)(27 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand3_1 in circuit mgmt_core_wrapper (0)(34 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a221o_2 in circuit mgmt_core_wrapper (0)(38 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21o_4 in circuit mgmt_core_wrapper (0)(7 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21boi_1 in circuit mgmt_core_wrapper (0)(18 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand2_2 in circuit mgmt_core_wrapper (0)(27 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21oi_2 in circuit mgmt_core_wrapper (0)(18 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21bai_1 in circuit mgmt_core_wrapper (0)(11 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3_2 in circuit mgmt_core_wrapper (0)(38 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21oi_1 in circuit mgmt_core_wrapper (0)(305 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__mux2_4 in circuit mgmt_core_wrapper (0)(11 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkinv_4 in circuit mgmt_core_wrapper (0)(27 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_4 in circuit mgmt_core_wrapper (0)(48 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor2_4 in circuit mgmt_core_wrapper (0)(16 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21oi_4 in circuit mgmt_core_wrapper (0)(36 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o2111ai_1 in circuit mgmt_core_wrapper (0)(29 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand2b_1 in circuit mgmt_core_wrapper (0)(66 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and2_2 in circuit mgmt_core_wrapper (0)(8 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4b_4 in circuit mgmt_core_wrapper (0)(37 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o2111a_1 in circuit mgmt_core_wrapper (0)(85 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4bb_1 in circuit mgmt_core_wrapper (0)(22 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__xnor2_1 in circuit mgmt_core_wrapper (0)(33 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4_2 in circuit mgmt_core_wrapper (0)(22 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand4_2 in circuit mgmt_core_wrapper (0)(14 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_1 in circuit mgmt_core_wrapper (0)(134 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkbuf_2 in circuit mgmt_core_wrapper (0)(26 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__dlymetal6s2s_1 in circuit mgmt_core_wrapper (0)(5 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__buf_2 in circuit mgmt_core_wrapper (0)(13 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__xor2_1 in circuit mgmt_core_wrapper (0)(39 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o32a_1 in circuit mgmt_core_wrapper (0)(27 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and2_4 in circuit mgmt_core_wrapper (0)(15 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a2111o_2 in circuit mgmt_core_wrapper (0)(4 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o2bb2a_1 in circuit mgmt_core_wrapper (0)(53 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4b_2 in circuit mgmt_core_wrapper (0)(8 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3b_1 in circuit mgmt_core_wrapper (0)(67 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a2111oi_1 in circuit mgmt_core_wrapper (0)(7 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a211o_2 in circuit mgmt_core_wrapper (0)(17 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and2b_4 in circuit mgmt_core_wrapper (0)(11 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkinv_2 in circuit mgmt_core_wrapper (0)(28 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__conb_1 in circuit mgmt_core_wrapper (0)(11 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o31a_2 in circuit mgmt_core_wrapper (0)(14 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21o_2 in circuit mgmt_core_wrapper (0)(6 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a31o_2 in circuit mgmt_core_wrapper (0)(14 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21ba_2 in circuit mgmt_core_wrapper (0)(3 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor3_2 in circuit mgmt_core_wrapper (0)(10 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21ai_2 in circuit mgmt_core_wrapper (0)(33 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__or2_2 in circuit mgmt_core_wrapper (0)(7 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand3_2 in circuit mgmt_core_wrapper (0)(11 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o211ai_4 in circuit mgmt_core_wrapper (0)(12 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o31ai_1 in circuit mgmt_core_wrapper (0)(16 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor4_2 in circuit mgmt_core_wrapper (0)(14 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand2_4 in circuit mgmt_core_wrapper (0)(16 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__inv_4 in circuit mgmt_core_wrapper (0)(13 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__mux2_8 in circuit mgmt_core_wrapper (0)(7 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__inv_6 in circuit mgmt_core_wrapper (0)(9 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor2_8 in circuit mgmt_core_wrapper (0)(34 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor4_4 in circuit mgmt_core_wrapper (0)(13 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__mux2_2 in circuit mgmt_core_wrapper (0)(18 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand2b_2 in circuit mgmt_core_wrapper (0)(4 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a211o_4 in circuit mgmt_core_wrapper (0)(12 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o2bb2a_2 in circuit mgmt_core_wrapper (0)(8 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand2b_4 in circuit mgmt_core_wrapper (0)(17 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21a_2 in circuit mgmt_core_wrapper (0)(5 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o2111ai_2 in circuit mgmt_core_wrapper (0)(3 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a221oi_1 in circuit mgmt_core_wrapper (0)(7 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o2bb2ai_1 in circuit mgmt_core_wrapper (0)(13 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o31a_4 in circuit mgmt_core_wrapper (0)(8 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor3_4 in circuit mgmt_core_wrapper (0)(10 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o211a_2 in circuit mgmt_core_wrapper (0)(13 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand3b_1 in circuit mgmt_core_wrapper (0)(16 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o22a_2 in circuit mgmt_core_wrapper (0)(5 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and2b_2 in circuit mgmt_core_wrapper (0)(3 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o21a_4 in circuit mgmt_core_wrapper (0)(14 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and4bb_2 in circuit mgmt_core_wrapper (0)(4 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__inv_12 in circuit mgmt_core_wrapper (0)(2 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand4b_4 in circuit mgmt_core_wrapper (0)(3 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__xor2_2 in circuit mgmt_core_wrapper (0)(7 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a2111o_4 in circuit mgmt_core_wrapper (0)(4 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o221a_2 in circuit mgmt_core_wrapper (0)(1 instance)
Flattening unmatched subcell QI_sky130_fd_sc_hd__and3b_2 in circuit mgmt_core_wrapper (0)(2 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor3b_2 in circuit mgmt_core_wrapper (0)(3 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__inv_8 in circuit mgmt_core_wrapper (0)(4 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand3b_4 in circuit mgmt_core_wrapper (0)(5 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand3_4 in circuit mgmt_core_wrapper (0)(5 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o2111a_2 in circuit mgmt_core_wrapper (0)(2 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__clkinv_8 in circuit mgmt_core_wrapper (0)(6 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__xnor2_2 in circuit mgmt_core_wrapper (0)(3 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__o31ai_2 in circuit mgmt_core_wrapper (0)(4 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a21boi_2 in circuit mgmt_core_wrapper (0)(1 instance)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand3b_2 in circuit mgmt_core_wrapper (0)(7 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nand4b_1 in circuit mgmt_core_wrapper (0)(1 instance)
Flattening unmatched subcell QI_sky130_fd_sc_hd__nor3b_1 in circuit mgmt_core_wrapper (0)(4 instances)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a41oi_1 in circuit mgmt_core_wrapper (0)(1 instance)
Flattening unmatched subcell QI_sky130_fd_sc_hd__a311oi_2 in circuit mgmt_core_wrapper (0)(1 instance)
Cell mgmt_core_wrapper (0) disconnected node: flash_io0_di
Cell mgmt_core_wrapper (0) disconnected node: flash_io2_di
Cell mgmt_core_wrapper (0) disconnected node: flash_io3_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io0_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io2_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io3_di
Flattening instances of sky130_ef_sc_hd__decap_12 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21bo_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_16 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o211ai_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o2111ai_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o2111ai_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o311a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o31a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o31a_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o31a_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkinv_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkinv_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkinv_8 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand3b_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand3b_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand3b_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4b_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4b_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4b_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a211o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a211o_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a211o_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21a_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21a_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__inv_12 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a31oi_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__or2_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__xor2_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__xor2_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand4b_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand4b_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__conb_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a41o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21ba_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21ba_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__xnor2_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__xnor2_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__buf_12 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a22o_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor2_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor2_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor2_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor2_8 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o2bb2a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o2bb2a_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o31ai_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o31ai_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o211a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o211a_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21boi_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21boi_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o32a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__mux2_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__mux2_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__mux2_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__mux2_8 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor3_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor3_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor3_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21bai_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a2111oi_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o22a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o22a_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21oi_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21oi_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21oi_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor4_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor4_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor4_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__dfxtp_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__diode_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a31o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a31o_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a311oi_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__dlygate4sd3_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21ai_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21ai_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o21ai_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o41a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21o_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a21o_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor3b_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nor3b_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a221o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a221o_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a221o_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4bb_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and4bb_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o2bb2ai_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a32o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand2_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand2_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand2_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand2_8 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o221a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o221a_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2b_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2b_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2b_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand3_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand3_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand3_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__dlymetal6s2s_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand4_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand4_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand2b_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand2b_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__nand2b_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a2111o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a2111o_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a2111o_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__buf_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__buf_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__buf_6 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__buf_8 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a221oi_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a41oi_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o2111a_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__o2111a_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3b_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3b_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and3b_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkbuf_8 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_3 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_6 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__decap_8 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a311o_1 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__inv_2 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__inv_4 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__inv_6 in cell mgmt_core_wrapper (1) makes a better match
Flattening instances of sky130_fd_sc_hd__inv_8 in cell mgmt_core_wrapper (1) makes a better match
Making another compare attempt.
Cell mgmt_core_wrapper (0) disconnected node: flash_io0_di
Cell mgmt_core_wrapper (0) disconnected node: flash_io2_di
Cell mgmt_core_wrapper (0) disconnected node: flash_io3_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io0_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io2_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io3_di
Class mgmt_core_wrapper (0): Merged 276317 parallel devices.
Class mgmt_core_wrapper (1): Merged 202069 parallel devices.
Cell mgmt_core_wrapper (0) disconnected node: flash_io0_di
Cell mgmt_core_wrapper (0) disconnected node: flash_io2_di
Cell mgmt_core_wrapper (0) disconnected node: flash_io3_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io0_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io2_di
Cell mgmt_core_wrapper (1) disconnected node: flash_io3_di
Subcircuit summary:
Circuit 1: mgmt_core_wrapper |Circuit 2: mgmt_core_wrapper
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_hvt (242424->12063 |sky130_fd_pr__pfet_01v8_hvt (242424->12063
sky130_fd_pr__nfet_01v8 (242318->120708) |sky130_fd_pr__nfet_01v8 (242294->120708)
sky130_fd_pr__diode_pw2nd_05v5 (37950->504 |sky130_fd_pr__diode_pw2nd_05v5 (37950->504
QI_sky130_fd_sc_hd__a211oi_2 (5) |sky130_fd_sc_hd__a211oi_2 (5)
QI_sky130_fd_sc_hd__dfxtp_4 (583) |sky130_fd_sc_hd__dfxtp_4 (583)
QI_sky130_fd_sc_hd__or4b_4 (30) |sky130_fd_sc_hd__or4b_4 (30)
QI_sky130_fd_sc_hd__a31o_4 (25) |sky130_fd_sc_hd__a31o_4 (25)
QI_sky130_fd_sc_hd__and3_4 (56) |sky130_fd_sc_hd__and3_4 (56)
QI_sky130_fd_sc_hd__a211oi_4 (5) |sky130_fd_sc_hd__a211oi_4 (5)
QI_sky130_fd_sc_hd__a31oi_1 (46) |sky130_fd_sc_hd__a31oi_1 (46)
QI_sky130_fd_sc_hd__a22o_1 (428) |sky130_fd_sc_hd__a22o_1 (428)
QI_sky130_fd_sc_hd__or3b_1 (155) |sky130_fd_sc_hd__or3b_1 (155)
QI_sky130_fd_sc_hd__a22o_4 (60) |sky130_fd_sc_hd__a22o_4 (60)
QI_sky130_fd_sc_hd__dfxtp_2 (389) |sky130_fd_sc_hd__dfxtp_2 (389)
QI_sky130_fd_sc_hd__and2_1 (107) |sky130_fd_sc_hd__and2_1 (107)
QI_sky130_fd_sc_hd__a311oi_4 (18) |sky130_fd_sc_hd__a311oi_4 (18)
QI_sky130_fd_sc_hd__mux4_2 (14) |sky130_fd_sc_hd__mux4_2 (14)
QI_sky130_fd_sc_hd__or4b_1 (178) |sky130_fd_sc_hd__or4b_1 (178)
QI_sky130_fd_sc_hd__mux4_1 (80) |sky130_fd_sc_hd__mux4_1 (80)
QI_sky130_fd_sc_hd__or2_1 (215) |sky130_fd_sc_hd__or2_1 (215)
QI_sky130_fd_sc_hd__a311oi_1 (44) |sky130_fd_sc_hd__a311oi_1 (44)
QI_sky130_fd_sc_hd__clkinv_16 (26) |sky130_fd_sc_hd__clkinv_16 (26)
QI_sky130_fd_sc_hd__a2bb2o_1 (77) |sky130_fd_sc_hd__a2bb2o_1 (77)
QI_sky130_fd_sc_hd__or4bb_1 (9) |sky130_fd_sc_hd__or4bb_1 (9)
QI_sky130_fd_sc_hd__a221oi_4 (17) |sky130_fd_sc_hd__a221oi_4 (17)
QI_sky130_fd_sc_hd__o211ai_1 (20) |sky130_fd_sc_hd__o211ai_1 (20)
QI_sky130_fd_sc_hd__or4bb_4 (11) |sky130_fd_sc_hd__or4bb_4 (11)
QI_sky130_fd_sc_hd__a2bb2o_4 (7) |sky130_fd_sc_hd__a2bb2o_4 (7)
QI_sky130_fd_sc_hd__o22a_4 (5) |sky130_fd_sc_hd__o22a_4 (5)
QI_sky130_fd_sc_hd__and4_4 (45) |sky130_fd_sc_hd__and4_4 (45)
QI_sky130_fd_sc_hd__or4b_2 (16) |sky130_fd_sc_hd__or4b_2 (16)
QI_sky130_fd_sc_hd__a22oi_2 (13) |sky130_fd_sc_hd__a22oi_2 (13)
QI_sky130_fd_sc_hd__nand4_4 (21) |sky130_fd_sc_hd__nand4_4 (21)
QI_sky130_fd_sc_hd__o2111ai_4 (10) |sky130_fd_sc_hd__o2111ai_4 (10)
QI_sky130_fd_sc_hd__o22ai_4 (7) |sky130_fd_sc_hd__o22ai_4 (7)
QI_sky130_fd_sc_hd__a32oi_4 (4) |sky130_fd_sc_hd__a32oi_4 (4)
sky130_fd_pr__res_generic_po (22->13) |sky130_fd_pr__res_generic_po (22->13)
QI_sky130_fd_sc_hd__o2bb2ai_2 (2) |sky130_fd_sc_hd__o2bb2ai_2 (2)
QI_sky130_fd_sc_hd__or3b_2 (8) |sky130_fd_sc_hd__or3b_2 (8)
QI_sky130_fd_sc_hd__or3b_4 (28) |sky130_fd_sc_hd__or3b_4 (28)
QI_sky130_fd_sc_hd__a22oi_1 (20) |sky130_fd_sc_hd__a22oi_1 (20)
QI_sky130_fd_sc_hd__or2_4 (27) |sky130_fd_sc_hd__or2_4 (27)
QI_sky130_fd_sc_hd__and4bb_4 (20) |sky130_fd_sc_hd__and4bb_4 (20)
QI_sky130_fd_sc_hd__o41ai_1 (6) |sky130_fd_sc_hd__o41ai_1 (6)
QI_sky130_fd_sc_hd__a32o_2 (7) |sky130_fd_sc_hd__a32o_2 (7)
QI_sky130_fd_sc_hd__a32o_4 (9) |sky130_fd_sc_hd__a32o_4 (9)
QI_sky130_fd_sc_hd__o311ai_1 (4) |sky130_fd_sc_hd__o311ai_1 (4)
QI_sky130_fd_sc_hd__nor4b_1 (2) |sky130_fd_sc_hd__nor4b_1 (2)
QI_sky130_fd_sc_hd__o22ai_1 (6) |sky130_fd_sc_hd__o22ai_1 (6)
QI_sky130_fd_sc_hd__o21bai_4 (2) |sky130_fd_sc_hd__o21bai_4 (2)
QI_sky130_fd_sc_hd__a211oi_1 (49) |sky130_fd_sc_hd__a211oi_1 (49)
QI_sky130_fd_sc_hd__a22oi_4 (21) |sky130_fd_sc_hd__a22oi_4 (21)
QI_sky130_fd_sc_hd__a41o_2 (6) |sky130_fd_sc_hd__a41o_2 (6)
QI_sky130_fd_sc_hd__o221ai_4 (12) |sky130_fd_sc_hd__o221ai_4 (12)
QI_sky130_fd_sc_hd__a311o_2 (8) |sky130_fd_sc_hd__a311o_2 (8)
QI_sky130_fd_sc_hd__o41a_4 (14) |sky130_fd_sc_hd__o41a_4 (14)
QI_sky130_fd_sc_hd__nand4b_2 (1) |sky130_fd_sc_hd__nand4b_2 (1)
QI_sky130_fd_sc_hd__xor2_4 (9) |sky130_fd_sc_hd__xor2_4 (9)
QI_sky130_fd_sc_hd__a2bb2o_2 (5) |sky130_fd_sc_hd__a2bb2o_2 (5)
QI_sky130_fd_sc_hd__o211ai_2 (5) |sky130_fd_sc_hd__o211ai_2 (5)
QI_sky130_fd_sc_hd__o311ai_4 (5) |sky130_fd_sc_hd__o311ai_4 (5)
QI_sky130_fd_sc_hd__a2bb2oi_4 (1) |sky130_fd_sc_hd__a2bb2oi_4 (1)
QI_sky130_fd_sc_hd__a2bb2oi_2 (1) |sky130_fd_sc_hd__a2bb2oi_2 (1)
QI_sky130_fd_sc_hd__o311a_2 (5) |sky130_fd_sc_hd__o311a_2 (5)
QI_sky130_fd_sc_hd__o221ai_1 (8) |sky130_fd_sc_hd__o221ai_1 (8)
QI_sky130_fd_sc_hd__o211a_4 (9) |sky130_fd_sc_hd__o211a_4 (9)
QI_sky130_fd_sc_hd__o311a_4 (1) |sky130_fd_sc_hd__o311a_4 (1)
QI_sky130_fd_sc_hd__a41oi_2 (1) |sky130_fd_sc_hd__a41oi_2 (1)
QI_sky130_fd_sc_hd__o41a_2 (6) |sky130_fd_sc_hd__o41a_2 (6)
QI_sky130_fd_sc_hd__a2bb2oi_1 (3) |sky130_fd_sc_hd__a2bb2oi_1 (3)
QI_sky130_fd_sc_hd__nor4b_4 (4) |sky130_fd_sc_hd__nor4b_4 (4)
QI_sky130_fd_sc_hd__o32ai_1 (2) |sky130_fd_sc_hd__o32ai_1 (2)
QI_sky130_fd_sc_hd__nor3b_4 (2) |sky130_fd_sc_hd__nor3b_4 (2)
QI_RAM128 (1) |RAM128 (1)
QI_sky130_fd_sc_hd__xnor2_4 (2) |sky130_fd_sc_hd__xnor2_4 (2)
QI_sky130_fd_sc_hd__a2111oi_4 (1) |sky130_fd_sc_hd__a2111oi_4 (1)
QI_sky130_fd_sc_hd__a311o_4 (3) |sky130_fd_sc_hd__a311o_4 (3)
QI_sky130_fd_sc_hd__a221oi_2 (6) |sky130_fd_sc_hd__a221oi_2 (6)
QI_sky130_fd_sc_hd__o22ai_2 (2) |sky130_fd_sc_hd__o22ai_2 (2)
QI_sky130_fd_sc_hd__a31oi_2 (4) |sky130_fd_sc_hd__a31oi_2 (4)
QI_sky130_fd_sc_hd__o41ai_2 (1) |sky130_fd_sc_hd__o41ai_2 (1)
QI_sky130_fd_sc_hd__o31ai_4 (5) |sky130_fd_sc_hd__o31ai_4 (5)
QI_sky130_fd_sc_hd__nor4b_2 (1) |sky130_fd_sc_hd__nor4b_2 (1)
QI_sky130_fd_sc_hd__o2111a_4 (3) |sky130_fd_sc_hd__o2111a_4 (3)
QI_sky130_fd_sc_hd__o2bb2a_4 (3) |sky130_fd_sc_hd__o2bb2a_4 (3)
QI_sky130_fd_sc_hd__a41o_4 (2) |sky130_fd_sc_hd__a41o_4 (2)
QI_sky130_fd_sc_hd__a32oi_2 (1) |sky130_fd_sc_hd__a32oi_2 (1)
QI_sky130_fd_sc_hd__a32oi_1 (2) |sky130_fd_sc_hd__a32oi_1 (2)
QI_RAM256 (1) |RAM256 (1)
QI_sky130_fd_sc_hd__o21bai_2 (1) |sky130_fd_sc_hd__o21bai_2 (1)
QI_sky130_fd_sc_hd__o2bb2ai_4 (1) |sky130_fd_sc_hd__o2bb2ai_4 (1)
QI_sky130_fd_sc_hd__o311ai_2 (3) |sky130_fd_sc_hd__o311ai_2 (3)
QI_sky130_fd_sc_hd__a2111oi_2 (3) |sky130_fd_sc_hd__a2111oi_2 (3)
QI_sky130_fd_sc_hd__o32ai_4 (1) |sky130_fd_sc_hd__o32ai_4 (1)
QI_sky130_fd_sc_hd__a41oi_4 (1) |sky130_fd_sc_hd__a41oi_4 (1)
Number of devices: 249490 |Number of devices: 249490
Number of nets: 127275 |Number of nets: 127275
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match with 228 symmetries.
Subcircuit pins:
Circuit 1: mgmt_core_wrapper |Circuit 2: mgmt_core_wrapper
-------------------------------------------|-------------------------------------------
mprj_adr_o[0] |mprj_adr_o[0]
flash_io3_do |flash_io3_do
flash_io2_do |flash_io2_do
flash_io1_do |flash_io1_do
debug_out |debug_out
trap |trap
qspi_enabled |qspi_enabled
mprj_adr_o[1] |mprj_adr_o[1]
flash_io3_oeb |flash_io3_oeb
flash_io2_oeb |flash_io2_oeb
flash_io1_oeb |flash_io1_oeb
debug_in |debug_in
mprj_dat_i[16] |mprj_dat_i[16]
core_clk |core_clk
irq[0] |irq[0]
la_input[56] |la_input[56]
la_input[58] |la_input[58]
la_input[55] |la_input[55]
la_input[57] |la_input[57]
irq[4] |irq[4]
irq[5] |irq[5]
irq[3] |irq[3]
irq[1] |irq[1]
flash_io1_di |flash_io1_di
ser_rx |ser_rx
mprj_dat_i[19] |mprj_dat_i[19]
mprj_dat_i[20] |mprj_dat_i[20]
mprj_dat_i[10] |mprj_dat_i[10]
spi_sdi |spi_sdi
mprj_dat_i[2] |mprj_dat_i[2]
mprj_dat_i[6] |mprj_dat_i[6]
mprj_dat_i[4] |mprj_dat_i[4]
mprj_dat_i[1] |mprj_dat_i[1]
mprj_dat_i[18] |mprj_dat_i[18]
mprj_dat_i[9] |mprj_dat_i[9]
mprj_dat_i[31] |mprj_dat_i[31]
mprj_dat_i[29] |mprj_dat_i[29]
mprj_dat_i[30] |mprj_dat_i[30]
mprj_ack_i |mprj_ack_i
serial_resetn_in |serial_resetn_in
serial_clock_in |serial_clock_in
serial_load_in |serial_load_in
serial_data_2_in |serial_data_2_in
la_input[94] |la_input[94]
la_input[92] |la_input[92]
la_input[91] |la_input[91]
la_input[89] |la_input[89]
la_input[87] |la_input[87]
la_input[95] |la_input[95]
la_input[93] |la_input[93]
la_input[118] |la_input[118]
resetn_in |resetn_in
clk_in |clk_in
por_l_in |por_l_in
porb_h_in |porb_h_in
mprj_dat_i[5] |mprj_dat_i[5]
mprj_dat_i[7] |mprj_dat_i[7]
mprj_dat_i[3] |mprj_dat_i[3]
mprj_dat_i[24] |mprj_dat_i[24]
mprj_dat_i[21] |mprj_dat_i[21]
mprj_dat_i[17] |mprj_dat_i[17]
mprj_dat_i[25] |mprj_dat_i[25]
mprj_dat_i[27] |mprj_dat_i[27]
mprj_dat_i[23] |mprj_dat_i[23]
mprj_dat_i[26] |mprj_dat_i[26]
mprj_dat_i[22] |mprj_dat_i[22]
mprj_dat_i[28] |mprj_dat_i[28]
mprj_dat_i[15] |mprj_dat_i[15]
mprj_dat_i[14] |mprj_dat_i[14]
mprj_dat_i[13] |mprj_dat_i[13]
mprj_dat_i[8] |mprj_dat_i[8]
mprj_dat_i[12] |mprj_dat_i[12]
mprj_dat_i[11] |mprj_dat_i[11]
mprj_dat_i[0] |mprj_dat_i[0]
gpio_in_pad |gpio_in_pad
core_rstn |core_rstn
rstb_l_in |rstb_l_in
la_input[60] |la_input[60]
la_input[59] |la_input[59]
hk_dat_i[15] |hk_dat_i[15]
hk_dat_i[13] |hk_dat_i[13]
hk_dat_i[6] |hk_dat_i[6]
hk_dat_i[10] |hk_dat_i[10]
hk_dat_i[5] |hk_dat_i[5]
hk_dat_i[3] |hk_dat_i[3]
hk_dat_i[7] |hk_dat_i[7]
hk_dat_i[0] |hk_dat_i[0]
hk_dat_i[12] |hk_dat_i[12]
hk_dat_i[11] |hk_dat_i[11]
hk_dat_i[8] |hk_dat_i[8]
hk_dat_i[14] |hk_dat_i[14]
hk_dat_i[19] |hk_dat_i[19]
hk_dat_i[20] |hk_dat_i[20]
hk_dat_i[22] |hk_dat_i[22]
hk_dat_i[21] |hk_dat_i[21]
hk_dat_i[23] |hk_dat_i[23]
la_input[61] |la_input[61]
la_input[62] |la_input[62]
la_input[124] |la_input[124]
la_input[122] |la_input[122]
la_input[120] |la_input[120]
la_input[119] |la_input[119]
la_input[121] |la_input[121]
la_input[123] |la_input[123]
la_input[125] |la_input[125]
la_input[127] |la_input[127]
la_input[126] |la_input[126]
la_input[9] |la_input[9]
la_input[8] |la_input[8]
la_input[7] |la_input[7]
la_input[6] |la_input[6]
la_input[5] |la_input[5]
la_input[1] |la_input[1]
la_input[4] |la_input[4]
la_input[2] |la_input[2]
la_input[0] |la_input[0]
la_input[3] |la_input[3]
la_input[115] |la_input[115]
la_input[112] |la_input[112]
la_input[111] |la_input[111]
la_input[116] |la_input[116]
la_input[109] |la_input[109]
la_input[108] |la_input[108]
la_input[113] |la_input[113]
la_input[110] |la_input[110]
la_input[114] |la_input[114]
la_input[117] |la_input[117]
hk_dat_i[25] |hk_dat_i[25]
hk_dat_i[27] |hk_dat_i[27]
hk_dat_i[28] |hk_dat_i[28]
hk_dat_i[24] |hk_dat_i[24]
hk_dat_i[26] |hk_dat_i[26]
hk_dat_i[17] |hk_dat_i[17]
hk_dat_i[9] |hk_dat_i[9]
hk_dat_i[18] |hk_dat_i[18]
hk_dat_i[16] |hk_dat_i[16]
hk_dat_i[1] |hk_dat_i[1]
hk_dat_i[4] |hk_dat_i[4]
hk_dat_i[2] |hk_dat_i[2]
hk_dat_i[29] |hk_dat_i[29]
hk_dat_i[31] |hk_dat_i[31]
hk_dat_i[30] |hk_dat_i[30]
hk_ack_i |hk_ack_i
la_input[85] |la_input[85]
la_input[84] |la_input[84]
la_input[80] |la_input[80]
la_input[83] |la_input[83]
la_input[82] |la_input[82]
la_input[79] |la_input[79]
la_input[81] |la_input[81]
la_input[78] |la_input[78]
la_input[77] |la_input[77]
la_input[76] |la_input[76]
la_input[71] |la_input[71]
la_input[75] |la_input[75]
la_input[74] |la_input[74]
la_input[73] |la_input[73]
la_input[72] |la_input[72]
la_input[70] |la_input[70]
la_input[69] |la_input[69]
la_input[68] |la_input[68]
la_input[49] |la_input[49]
la_input[66] |la_input[66]
la_input[65] |la_input[65]
la_input[67] |la_input[67]
la_input[64] |la_input[64]
la_input[63] |la_input[63]
la_input[48] |la_input[48]
la_input[45] |la_input[45]
la_input[47] |la_input[47]
la_input[46] |la_input[46]
la_input[44] |la_input[44]
la_input[43] |la_input[43]
la_input[42] |la_input[42]
la_input[41] |la_input[41]
la_input[40] |la_input[40]
la_input[39] |la_input[39]
la_input[37] |la_input[37]
la_input[38] |la_input[38]
la_input[35] |la_input[35]
la_input[34] |la_input[34]
la_input[36] |la_input[36]
la_input[33] |la_input[33]
la_input[96] |la_input[96]
la_input[90] |la_input[90]
la_input[88] |la_input[88]
la_input[86] |la_input[86]
la_input[27] |la_input[27]
la_input[24] |la_input[24]
la_input[28] |la_input[28]
la_input[26] |la_input[26]
la_input[25] |la_input[25]
la_input[13] |la_input[13]
la_input[16] |la_input[16]
la_input[17] |la_input[17]
la_input[15] |la_input[15]
la_input[14] |la_input[14]
la_input[18] |la_input[18]
la_input[12] |la_input[12]
la_input[11] |la_input[11]
la_input[10] |la_input[10]
la_input[23] |la_input[23]
la_input[22] |la_input[22]
la_input[21] |la_input[21]
la_input[19] |la_input[19]
la_input[20] |la_input[20]
la_input[54] |la_input[54]
la_input[51] |la_input[51]
la_input[53] |la_input[53]
la_input[52] |la_input[52]
la_input[50] |la_input[50]
la_input[107] |la_input[107]
la_input[32] |la_input[32]
la_input[30] |la_input[30]
la_input[29] |la_input[29]
la_input[31] |la_input[31]
la_input[103] |la_input[103]
la_input[106] |la_input[106]
la_input[105] |la_input[105]
la_input[104] |la_input[104]
la_input[102] |la_input[102]
la_input[99] |la_input[99]
la_input[101] |la_input[101]
la_input[98] |la_input[98]
la_input[97] |la_input[97]
la_input[100] |la_input[100]
irq[2] |irq[2]
mprj_adr_o[11] |mprj_adr_o[11]
mprj_adr_o[31] |mprj_adr_o[31]
mprj_adr_o[21] |mprj_adr_o[21]
uart_enabled |uart_enabled
mprj_adr_o[7] |mprj_adr_o[7]
mprj_adr_o[29] |mprj_adr_o[29]
mprj_we_o |mprj_we_o
spi_csb |spi_csb
mprj_dat_o[9] |mprj_dat_o[9]
mprj_dat_o[31] |mprj_dat_o[31]
mprj_dat_o[30] |mprj_dat_o[30]
mprj_dat_o[29] |mprj_dat_o[29]
mprj_dat_o[26] |mprj_dat_o[26]
mprj_dat_o[24] |mprj_dat_o[24]
mprj_dat_o[23] |mprj_dat_o[23]
mprj_dat_o[22] |mprj_dat_o[22]
mprj_dat_o[21] |mprj_dat_o[21]
mprj_dat_o[19] |mprj_dat_o[19]
mprj_dat_o[18] |mprj_dat_o[18]
mprj_dat_o[17] |mprj_dat_o[17]
mprj_dat_o[16] |mprj_dat_o[16]
mprj_dat_o[15] |mprj_dat_o[15]
mprj_dat_o[14] |mprj_dat_o[14]
mprj_dat_o[10] |mprj_dat_o[10]
la_output[78] |la_output[78]
la_output[74] |la_output[74]
la_output[72] |la_output[72]
la_output[64] |la_output[64]
la_output[16] |la_output[16]
hk_stb_o |hk_stb_o
mprj_sel_o[2] |mprj_sel_o[2]
mprj_adr_o[25] |mprj_adr_o[25]
mprj_adr_o[19] |mprj_adr_o[19]
mprj_adr_o[17] |mprj_adr_o[17]
mprj_adr_o[27] |mprj_adr_o[27]
mprj_adr_o[20] |mprj_adr_o[20]
mprj_adr_o[14] |mprj_adr_o[14]
mprj_adr_o[5] |mprj_adr_o[5]
mprj_adr_o[30] |mprj_adr_o[30]
mprj_adr_o[2] |mprj_adr_o[2]
mprj_adr_o[28] |mprj_adr_o[28]
mprj_adr_o[13] |mprj_adr_o[13]
mprj_adr_o[4] |mprj_adr_o[4]
mprj_adr_o[3] |mprj_adr_o[3]
mprj_adr_o[16] |mprj_adr_o[16]
mprj_adr_o[15] |mprj_adr_o[15]
mprj_adr_o[9] |mprj_adr_o[9]
mprj_adr_o[12] |mprj_adr_o[12]
mprj_dat_o[8] |mprj_dat_o[8]
mprj_dat_o[7] |mprj_dat_o[7]
mprj_dat_o[6] |mprj_dat_o[6]
mprj_dat_o[5] |mprj_dat_o[5]
mprj_dat_o[4] |mprj_dat_o[4]
mprj_dat_o[3] |mprj_dat_o[3]
mprj_dat_o[2] |mprj_dat_o[2]
mprj_dat_o[28] |mprj_dat_o[28]
mprj_dat_o[27] |mprj_dat_o[27]
mprj_dat_o[25] |mprj_dat_o[25]
mprj_dat_o[20] |mprj_dat_o[20]
mprj_dat_o[1] |mprj_dat_o[1]
mprj_dat_o[13] |mprj_dat_o[13]
mprj_dat_o[12] |mprj_dat_o[12]
mprj_dat_o[11] |mprj_dat_o[11]
mprj_dat_o[0] |mprj_dat_o[0]
mprj_adr_o[8] |mprj_adr_o[8]
mprj_adr_o[6] |mprj_adr_o[6]
mprj_adr_o[18] |mprj_adr_o[18]
mprj_adr_o[10] |mprj_adr_o[10]
la_output[89] |la_output[89]
la_output[93] |la_output[93]
la_output[90] |la_output[90]
la_output[92] |la_output[92]
la_output[91] |la_output[91]
la_output[82] |la_output[82]
la_output[81] |la_output[81]
la_output[79] |la_output[79]
la_output[88] |la_output[88]
la_output[87] |la_output[87]
la_output[77] |la_output[77]
la_output[85] |la_output[85]
la_output[75] |la_output[75]
la_output[73] |la_output[73]
la_output[71] |la_output[71]
la_output[67] |la_output[67]
la_output[55] |la_output[55]
la_output[30] |la_output[30]
user_irq_ena[2] |user_irq_ena[2]
user_irq_ena[1] |user_irq_ena[1]
user_irq_ena[0] |user_irq_ena[0]
spi_sdo |spi_sdo
spi_enabled |spi_enabled
mprj_wb_iena |mprj_wb_iena
mprj_adr_o[26] |mprj_adr_o[26]
mprj_adr_o[24] |mprj_adr_o[24]
mprj_adr_o[23] |mprj_adr_o[23]
mprj_adr_o[22] |mprj_adr_o[22]
la_output[97] |la_output[97]
la_output[96] |la_output[96]
la_output[95] |la_output[95]
la_output[94] |la_output[94]
la_output[8] |la_output[8]
la_output[86] |la_output[86]
la_output[80] |la_output[80]
la_output[6] |la_output[6]
la_output[66] |la_output[66]
la_output[65] |la_output[65]
la_output[84] |la_output[84]
la_output[83] |la_output[83]
la_output[70] |la_output[70]
la_output[69] |la_output[69]
la_output[61] |la_output[61]
la_output[60] |la_output[60]
la_output[57] |la_output[57]
la_output[52] |la_output[52]
la_output[51] |la_output[51]
la_output[49] |la_output[49]
la_output[47] |la_output[47]
la_output[44] |la_output[44]
la_output[41] |la_output[41]
la_output[50] |la_output[50]
la_output[68] |la_output[68]
la_output[76] |la_output[76]
la_output[53] |la_output[53]
la_output[43] |la_output[43]
la_output[39] |la_output[39]
la_output[38] |la_output[38]
la_output[36] |la_output[36]
la_output[35] |la_output[35]
la_output[58] |la_output[58]
la_output[37] |la_output[37]
la_output[59] |la_output[59]
la_output[56] |la_output[56]
la_output[46] |la_output[46]
la_output[45] |la_output[45]
la_output[34] |la_output[34]
la_output[33] |la_output[33]
la_output[32] |la_output[32]
la_output[40] |la_output[40]
la_output[42] |la_output[42]
la_output[27] |la_output[27]
la_output[4] |la_output[4]
la_output[28] |la_output[28]
la_output[25] |la_output[25]
la_output[22] |la_output[22]
la_output[31] |la_output[31]
la_output[21] |la_output[21]
la_output[20] |la_output[20]
la_output[3] |la_output[3]
la_output[2] |la_output[2]
la_output[1] |la_output[1]
la_output[18] |la_output[18]
la_output[62] |la_output[62]
la_output[7] |la_output[7]
la_output[9] |la_output[9]
la_output[23] |la_output[23]
la_output[29] |la_output[29]
la_output[48] |la_output[48]
la_output[19] |la_output[19]
la_output[17] |la_output[17]
la_output[26] |la_output[26]
la_output[54] |la_output[54]
la_output[24] |la_output[24]
la_output[63] |la_output[63]
la_output[14] |la_output[14]
la_output[13] |la_output[13]
la_output[12] |la_output[12]
la_output[15] |la_output[15]
la_output[127] |la_output[127]
la_output[126] |la_output[126]
la_output[125] |la_output[125]
la_output[123] |la_output[123]
la_output[122] |la_output[122]
la_output[120] |la_output[120]
la_output[11] |la_output[11]
la_output[5] |la_output[5]
la_output[119] |la_output[119]
la_output[118] |la_output[118]
la_output[115] |la_output[115]
la_output[117] |la_output[117]
la_output[124] |la_output[124]
la_output[116] |la_output[116]
la_output[114] |la_output[114]
la_output[113] |la_output[113]
la_output[112] |la_output[112]
la_output[110] |la_output[110]
la_output[10] |la_output[10]
la_output[108] |la_output[108]
la_output[107] |la_output[107]
la_output[121] |la_output[121]
la_output[111] |la_output[111]
la_output[109] |la_output[109]
la_output[106] |la_output[106]
la_output[104] |la_output[104]
la_output[98] |la_output[98]
la_output[105] |la_output[105]
la_output[102] |la_output[102]
la_output[101] |la_output[101]
la_output[103] |la_output[103]
la_output[100] |la_output[100]
la_output[99] |la_output[99]
la_output[0] |la_output[0]
gpio_out_pad |gpio_out_pad
gpio_mode1_pad |gpio_mode1_pad
gpio_mode0_pad |gpio_mode0_pad
debug_oeb |debug_oeb
debug_mode |debug_mode
ser_tx |ser_tx
rstb_l_out |rstb_l_out
spi_sck |spi_sck
mprj_sel_o[0] |mprj_sel_o[0]
mprj_stb_o |mprj_stb_o
mprj_sel_o[3] |mprj_sel_o[3]
mprj_sel_o[1] |mprj_sel_o[1]
serial_clock_out |serial_clock_out
serial_resetn_out |serial_resetn_out
serial_load_out |serial_load_out
serial_data_2_out |serial_data_2_out
la_oenb[91] |la_oenb[91]
la_oenb[90] |la_oenb[90]
la_oenb[78] |la_oenb[78]
la_oenb[85] |la_oenb[85]
la_oenb[93] |la_oenb[93]
la_oenb[88] |la_oenb[88]
la_oenb[73] |la_oenb[73]
la_iena[14] |la_iena[14]
la_iena[12] |la_iena[12]
la_iena[36] |la_iena[36]
la_oenb[44] |la_oenb[44]
la_oenb[41] |la_oenb[41]
la_oenb[87] |la_oenb[87]
la_iena[13] |la_iena[13]
la_oenb[10] |la_oenb[10]
la_iena[8] |la_iena[8]
la_oenb[12] |la_oenb[12]
la_oenb[121] |la_oenb[121]
la_oenb[8] |la_oenb[8]
la_oenb[15] |la_oenb[15]
la_oenb[14] |la_oenb[14]
la_oenb[13] |la_oenb[13]
gpio_outenb_pad |gpio_outenb_pad
gpio_inenb_pad |gpio_inenb_pad
la_oenb[55] |la_oenb[55]
la_oenb[25] |la_oenb[25]
la_oenb[94] |la_oenb[94]
la_oenb[86] |la_oenb[86]
la_iena[86] |la_iena[86]
la_iena[32] |la_iena[32]
la_iena[35] |la_iena[35]
la_iena[25] |la_iena[25]
la_iena[15] |la_iena[15]
la_oenb[59] |la_oenb[59]
la_oenb[54] |la_oenb[54]
la_oenb[61] |la_oenb[61]
la_oenb[56] |la_oenb[56]
la_oenb[53] |la_oenb[53]
la_oenb[52] |la_oenb[52]
la_oenb[50] |la_oenb[50]
la_oenb[58] |la_oenb[58]
la_oenb[45] |la_oenb[45]
la_oenb[51] |la_oenb[51]
la_oenb[49] |la_oenb[49]
la_oenb[43] |la_oenb[43]
la_oenb[37] |la_oenb[37]
la_oenb[39] |la_oenb[39]
la_oenb[38] |la_oenb[38]
la_oenb[35] |la_oenb[35]
la_oenb[34] |la_oenb[34]
la_oenb[33] |la_oenb[33]
la_oenb[32] |la_oenb[32]
mprj_cyc_o |mprj_cyc_o
la_oenb[3] |la_oenb[3]
la_oenb[2] |la_oenb[2]
la_oenb[1] |la_oenb[1]
la_iena[29] |la_iena[29]
la_oenb[60] |la_oenb[60]
la_oenb[57] |la_oenb[57]
la_iena[49] |la_iena[49]
la_iena[47] |la_iena[47]
la_iena[44] |la_iena[44]
la_iena[42] |la_iena[42]
la_iena[39] |la_iena[39]
la_oenb[82] |la_oenb[82]
la_oenb[62] |la_oenb[62]
la_iena[109] |la_iena[109]
la_oenb[71] |la_oenb[71]
la_iena[118] |la_iena[118]
la_iena[127] |la_iena[127]
la_oenb[4] |la_oenb[4]
la_oenb[92] |la_oenb[92]
la_oenb[89] |la_oenb[89]
la_oenb[79] |la_oenb[79]
la_oenb[69] |la_oenb[69]
la_oenb[68] |la_oenb[68]
la_iena[64] |la_iena[64]
la_iena[73] |la_iena[73]
la_iena[82] |la_iena[82]
la_iena[74] |la_iena[74]
la_iena[72] |la_iena[72]
la_iena[81] |la_iena[81]
la_iena[71] |la_iena[71]
la_oenb[118] |la_oenb[118]
la_oenb[108] |la_oenb[108]
la_iena[99] |la_iena[99]
la_iena[79] |la_iena[79]
la_oenb[127] |la_oenb[127]
la_iena[98] |la_iena[98]
la_iena[78] |la_iena[78]
la_iena[97] |la_iena[97]
la_iena[67] |la_iena[67]
la_iena[96] |la_iena[96]
la_iena[88] |la_iena[88]
la_iena[87] |la_iena[87]
la_iena[85] |la_iena[85]
la_iena[77] |la_iena[77]
la_iena[75] |la_iena[75]
la_oenb[112] |la_oenb[112]
la_iena[92] |la_iena[92]
la_iena[91] |la_iena[91]
la_iena[90] |la_iena[90]
la_iena[93] |la_iena[93]
la_iena[89] |la_iena[89]
la_iena[108] |la_iena[108]
la_iena[117] |la_iena[117]
la_iena[107] |la_iena[107]
la_iena[116] |la_iena[116]
la_iena[125] |la_iena[125]
la_iena[105] |la_iena[105]
la_iena[124] |la_iena[124]
la_iena[114] |la_iena[114]
la_iena[104] |la_iena[104]
la_oenb[72] |la_oenb[72]
la_oenb[67] |la_oenb[67]
la_iena[123] |la_iena[123]
la_iena[122] |la_iena[122]
la_iena[112] |la_iena[112]
la_oenb[75] |la_oenb[75]
la_oenb[65] |la_oenb[65]
la_iena[16] |la_iena[16]
la_iena[121] |la_iena[121]
la_iena[111] |la_iena[111]
la_iena[101] |la_iena[101]
la_oenb[84] |la_oenb[84]
la_oenb[77] |la_oenb[77]
la_oenb[64] |la_oenb[64]
la_iena[120] |la_iena[120]
la_iena[110] |la_iena[110]
la_iena[103] |la_iena[103]
la_iena[100] |la_iena[100]
la_iena[10] |la_iena[10]
la_iena[0] |la_iena[0]
la_oenb[42] |la_oenb[42]
la_oenb[22] |la_oenb[22]
la_iena[43] |la_iena[43]
la_iena[33] |la_iena[33]
la_iena[119] |la_iena[119]
la_oenb[31] |la_oenb[31]
la_oenb[70] |la_oenb[70]
la_iena[41] |la_iena[41]
la_oenb[7] |la_oenb[7]
la_oenb[6] |la_oenb[6]
la_oenb[5] |la_oenb[5]
la_iena[31] |la_iena[31]
la_iena[30] |la_iena[30]
la_iena[22] |la_iena[22]
la_iena[3] |la_iena[3]
la_iena[2] |la_iena[2]
la_oenb[99] |la_oenb[99]
la_oenb[98] |la_oenb[98]
la_oenb[97] |la_oenb[97]
la_oenb[95] |la_oenb[95]
la_oenb[100] |la_oenb[100]
la_iena[51] |la_iena[51]
la_oenb[0] |la_oenb[0]
la_iena[52] |la_iena[52]
la_iena[50] |la_iena[50]
la_iena[7] |la_iena[7]
la_iena[6] |la_iena[6]
la_iena[11] |la_iena[11]
la_iena[9] |la_iena[9]
la_iena[5] |la_iena[5]
la_iena[4] |la_iena[4]
la_iena[61] |la_iena[61]
la_iena[59] |la_iena[59]
la_oenb[126] |la_oenb[126]
la_iena[57] |la_iena[57]
la_iena[56] |la_iena[56]
la_oenb[125] |la_oenb[125]
la_oenb[115] |la_oenb[115]
la_oenb[124] |la_oenb[124]
la_oenb[107] |la_oenb[107]
la_oenb[103] |la_oenb[103]
la_iena[60] |la_iena[60]
la_oenb[122] |la_oenb[122]
la_oenb[117] |la_oenb[117]
la_oenb[104] |la_oenb[104]
la_oenb[102] |la_oenb[102]
la_iena[58] |la_iena[58]
la_oenb[16] |la_oenb[16]
la_oenb[111] |la_oenb[111]
la_oenb[105] |la_oenb[105]
la_oenb[101] |la_oenb[101]
la_oenb[120] |la_oenb[120]
la_oenb[110] |la_oenb[110]
la_oenb[30] |la_oenb[30]
la_iena[126] |la_iena[126]
la_iena[1] |la_iena[1]
la_oenb[123] |la_oenb[123]
la_oenb[119] |la_oenb[119]
la_oenb[116] |la_oenb[116]
la_oenb[113] |la_oenb[113]
la_iena[115] |la_iena[115]
la_oenb[28] |la_oenb[28]
la_iena[38] |la_iena[38]
la_iena[34] |la_iena[34]
la_iena[28] |la_iena[28]
la_oenb[114] |la_oenb[114]
la_iena[113] |la_iena[113]
la_iena[106] |la_iena[106]
la_oenb[66] |la_oenb[66]
la_oenb[40] |la_oenb[40]
la_oenb[46] |la_oenb[46]
la_iena[37] |la_iena[37]
la_oenb[96] |la_oenb[96]
la_oenb[109] |la_oenb[109]
la_oenb[106] |la_oenb[106]
la_iena[102] |la_iena[102]
la_iena[95] |la_iena[95]
la_iena[94] |la_iena[94]
la_iena[84] |la_iena[84]
la_iena[83] |la_iena[83]
la_iena[80] |la_iena[80]
la_iena[76] |la_iena[76]
la_iena[70] |la_iena[70]
la_iena[69] |la_iena[69]
la_iena[68] |la_iena[68]
la_iena[66] |la_iena[66]
la_iena[65] |la_iena[65]
la_iena[62] |la_iena[62]
la_iena[54] |la_iena[54]
la_iena[63] |la_iena[63]
la_iena[48] |la_iena[48]
la_iena[46] |la_iena[46]
la_iena[40] |la_iena[40]
la_iena[26] |la_iena[26]
la_iena[21] |la_iena[21]
la_iena[23] |la_iena[23]
la_iena[20] |la_iena[20]
la_iena[18] |la_iena[18]
la_iena[27] |la_iena[27]
la_oenb[29] |la_oenb[29]
la_oenb[19] |la_oenb[19]
la_oenb[24] |la_oenb[24]
la_oenb[17] |la_oenb[17]
la_oenb[9] |la_oenb[9]
la_oenb[11] |la_oenb[11]
la_iena[55] |la_iena[55]
la_iena[53] |la_iena[53]
la_iena[45] |la_iena[45]
la_oenb[81] |la_oenb[81]
la_oenb[83] |la_oenb[83]
la_oenb[74] |la_oenb[74]
la_oenb[63] |la_oenb[63]
la_oenb[47] |la_oenb[47]
la_oenb[36] |la_oenb[36]
la_oenb[80] |la_oenb[80]
la_oenb[76] |la_oenb[76]
la_oenb[48] |la_oenb[48]
la_oenb[26] |la_oenb[26]
la_oenb[21] |la_oenb[21]
la_oenb[20] |la_oenb[20]
la_oenb[18] |la_oenb[18]
la_oenb[27] |la_oenb[27]
la_oenb[23] |la_oenb[23]
la_iena[24] |la_iena[24]
la_iena[19] |la_iena[19]
la_iena[17] |la_iena[17]
hk_cyc_o |hk_cyc_o
spi_sdoenb |spi_sdoenb
flash_io0_oeb |flash_io0_oeb
flash_io0_do |flash_io0_do
flash_csb |flash_csb
flash_clk |flash_clk
porb_h_out |porb_h_out
por_l_out |por_l_out
resetn_out |resetn_out
clk_out |clk_out
VGND |VGND
VPWR |VPWR
flash_io0_di |flash_io0_di
flash_io2_di |flash_io2_di
flash_io3_di |flash_io3_di
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes mgmt_core_wrapper and mgmt_core_wrapper are equivalent.
Class simple_por (0): Merged 20 parallel devices.
Class simple_por (0): Merged 24 series devices.
Subcircuit summary:
Circuit 1: simple_por |Circuit 2: simple_por
-------------------------------------------|-------------------------------------------
EQ_sky130_fd_sc_hvl__schmittbuf_1 (1) |sky130_fd_sc_hvl__schmittbuf_1 (1)
EQ_sky130_fd_sc_hvl__buf_8 (2) |sky130_fd_sc_hvl__buf_8 (2)
EQ_sky130_fd_sc_hvl__inv_8 (1) |sky130_fd_sc_hvl__inv_8 (1)
sky130_fd_pr__pfet_g5v0d10v5 (21->8) |sky130_fd_pr__pfet_g5v0d10v5 (8)
sky130_fd_pr__nfet_g5v0d10v5 (9->3) |sky130_fd_pr__nfet_g5v0d10v5 (3)
sky130_fd_pr__res_xhigh_po (28->3) |sky130_fd_pr__res_xhigh_po (4->3)
sky130_fd_pr__cap_mim_m3_1 (1) |sky130_fd_pr__cap_mim_m3_1 (1)
sky130_fd_pr__cap_mim_m3_2 (1) |sky130_fd_pr__cap_mim_m3_2 (1)
Number of devices: 20 |Number of devices: 20
Number of nets: 17 |Number of nets: 17
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: simple_por |Circuit 2: simple_por
-------------------------------------------|-------------------------------------------
porb_h |porb_h
porb_l |porb_l
por_l |por_l
vss3v3 |vss3v3
vdd3v3 |vdd3v3
vss1v8 |vss1v8
vdd1v8 |vdd1v8
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes simple_por and simple_por are equivalent.
Class caravel_clocking (0): Merged 499 parallel devices.
Class caravel_clocking (1): Merged 499 parallel devices.
Subcircuit summary:
Circuit 1: caravel_clocking |Circuit 2: caravel_clocking
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_4 (120->1) |sky130_fd_sc_hd__decap_4 (120->1)
sky130_fd_sc_hd__dfrtp_1 (17) |sky130_fd_sc_hd__dfrtp_1 (17)
sky130_fd_sc_hd__nor2_1 (13) |sky130_fd_sc_hd__nor2_1 (13)
sky130_fd_sc_hd__nand2_1 (10) |sky130_fd_sc_hd__nand2_1 (10)
sky130_fd_sc_hd__decap_3 (146->1) |sky130_fd_sc_hd__decap_3 (146->1)
sky130_fd_sc_hd__o21ai_1 (18) |sky130_fd_sc_hd__o21ai_1 (18)
sky130_fd_sc_hd__nor3b_2 (2) |sky130_fd_sc_hd__nor3b_2 (2)
sky130_ef_sc_hd__decap_12 (80->1) |sky130_ef_sc_hd__decap_12 (80->1)
sky130_fd_sc_hd__clkbuf_16 (22) |sky130_fd_sc_hd__clkbuf_16 (22)
sky130_fd_sc_hd__dfstp_2 (4) |sky130_fd_sc_hd__dfstp_2 (4)
sky130_fd_sc_hd__decap_8 (72->1) |sky130_fd_sc_hd__decap_8 (72->1)
sky130_fd_sc_hd__nand2b_1 (14) |sky130_fd_sc_hd__nand2b_1 (14)
sky130_fd_sc_hd__diode_2 (61->17) |sky130_fd_sc_hd__diode_2 (61->17)
sky130_fd_sc_hd__decap_6 (42->1) |sky130_fd_sc_hd__decap_6 (42->1)
sky130_fd_sc_hd__nand4bb_1 (2) |sky130_fd_sc_hd__nand4bb_1 (2)
sky130_fd_sc_hd__dfstp_1 (17) |sky130_fd_sc_hd__dfstp_1 (17)
sky130_fd_sc_hd__mux2_1 (52) |sky130_fd_sc_hd__mux2_1 (52)
sky130_fd_sc_hd__o21a_1 (5) |sky130_fd_sc_hd__o21a_1 (5)
sky130_fd_sc_hd__dfrtp_2 (2) |sky130_fd_sc_hd__dfrtp_2 (2)
sky130_fd_sc_hd__o2bb2ai_1 (2) |sky130_fd_sc_hd__o2bb2ai_1 (2)
sky130_fd_sc_hd__inv_2 (8) |sky130_fd_sc_hd__inv_2 (8)
sky130_fd_sc_hd__nor3_1 (6) |sky130_fd_sc_hd__nor3_1 (6)
sky130_fd_sc_hd__buf_12 (1) |sky130_fd_sc_hd__buf_12 (1)
sky130_fd_sc_hd__a21oi_1 (4) |sky130_fd_sc_hd__a21oi_1 (4)
sky130_fd_sc_hd__xnor2_1 (10) |sky130_fd_sc_hd__xnor2_1 (10)
sky130_fd_sc_hd__o2111ai_2 (1) |sky130_fd_sc_hd__o2111ai_2 (1)
sky130_fd_sc_hd__o31ai_2 (2) |sky130_fd_sc_hd__o31ai_2 (2)
sky130_fd_sc_hd__and2_1 (4) |sky130_fd_sc_hd__and2_1 (4)
sky130_fd_sc_hd__a41oi_1 (2) |sky130_fd_sc_hd__a41oi_1 (2)
sky130_fd_sc_hd__clkinv_4 (5) |sky130_fd_sc_hd__clkinv_4 (5)
sky130_fd_sc_hd__nand2b_2 (2) |sky130_fd_sc_hd__nand2b_2 (2)
sky130_fd_sc_hd__clkinv_2 (4) |sky130_fd_sc_hd__clkinv_2 (4)
sky130_fd_sc_hd__clkbuf_2 (2) |sky130_fd_sc_hd__clkbuf_2 (2)
sky130_fd_sc_hd__dfrtn_1 (8) |sky130_fd_sc_hd__dfrtn_1 (8)
sky130_fd_sc_hd__inv_4 (9) |sky130_fd_sc_hd__inv_4 (9)
sky130_fd_sc_hd__o2111ai_1 (1) |sky130_fd_sc_hd__o2111ai_1 (1)
sky130_fd_sc_hd__clkbuf_4 (4) |sky130_fd_sc_hd__clkbuf_4 (4)
sky130_fd_sc_hd__nand3_1 (2) |sky130_fd_sc_hd__nand3_1 (2)
sky130_fd_sc_hd__o31a_1 (2) |sky130_fd_sc_hd__o31a_1 (2)
sky130_fd_sc_hd__nor3_2 (2) |sky130_fd_sc_hd__nor3_2 (2)
sky130_fd_sc_hd__dlymetal6s2s_1 (1) |sky130_fd_sc_hd__dlymetal6s2s_1 (1)
sky130_fd_sc_hd__o21bai_1 (2) |sky130_fd_sc_hd__o21bai_1 (2)
sky130_fd_sc_hd__dfrtp_4 (2) |sky130_fd_sc_hd__dfrtp_4 (2)
sky130_fd_sc_hd__clkbuf_1 (8) |sky130_fd_sc_hd__clkbuf_1 (8)
sky130_fd_sc_hd__buf_4 (10) |sky130_fd_sc_hd__buf_4 (10)
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
sky130_fd_sc_hd__dfxtp_1 (7) |sky130_fd_sc_hd__dfxtp_1 (7)
sky130_fd_sc_hd__nand3b_1 (4) |sky130_fd_sc_hd__nand3b_1 (4)
sky130_fd_sc_hd__a31o_1 (2) |sky130_fd_sc_hd__a31o_1 (2)
sky130_fd_sc_hd__o22a_1 (2) |sky130_fd_sc_hd__o22a_1 (2)
sky130_fd_sc_hd__buf_2 (1) |sky130_fd_sc_hd__buf_2 (1)
sky130_fd_sc_hd__o31ai_1 (2) |sky130_fd_sc_hd__o31ai_1 (2)
sky130_fd_sc_hd__o211ai_4 (2) |sky130_fd_sc_hd__o211ai_4 (2)
sky130_fd_sc_hd__o21ai_2 (2) |sky130_fd_sc_hd__o21ai_2 (2)
sky130_fd_sc_hd__o21a_2 (1) |sky130_fd_sc_hd__o21a_2 (1)
sky130_fd_sc_hd__nor2_2 (2) |sky130_fd_sc_hd__nor2_2 (2)
sky130_fd_sc_hd__a21o_1 (2) |sky130_fd_sc_hd__a21o_1 (2)
sky130_fd_sc_hd__nor4_1 (2) |sky130_fd_sc_hd__nor4_1 (2)
sky130_fd_sc_hd__a2bb2o_1 (2) |sky130_fd_sc_hd__a2bb2o_1 (2)
Number of devices: 336 |Number of devices: 336
Number of nets: 329 |Number of nets: 329
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: caravel_clocking |Circuit 2: caravel_clocking
-------------------------------------------|-------------------------------------------
user_clk |user_clk
resetb_sync |resetb_sync
core_clk |core_clk
sel[0] |sel[0]
sel[2] |sel[2]
sel2[1] |sel2[1]
resetb |resetb
ext_reset |ext_reset
sel2[0] |sel2[0]
sel2[2] |sel2[2]
sel[1] |sel[1]
ext_clk_sel |ext_clk_sel
pll_clk90 |pll_clk90
ext_clk |ext_clk
pll_clk |pll_clk
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes caravel_clocking and caravel_clocking are equivalent.
Class gpio_defaults_block_1803 (0): Merged 15 parallel devices.
Class gpio_defaults_block_1803 (1): Merged 15 parallel devices.
Subcircuit summary:
Circuit 1: gpio_defaults_block_1803 |Circuit 2: gpio_defaults_block_1803
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__conb_1 (13) |sky130_fd_sc_hd__conb_1 (13)
sky130_fd_sc_hd__decap_12 (8->1) |sky130_fd_sc_hd__decap_12 (8->1)
sky130_fd_sc_hd__decap_4 (3->1) |sky130_fd_sc_hd__decap_4 (3->1)
sky130_fd_sc_hd__decap_3 (7->1) |sky130_fd_sc_hd__decap_3 (7->1)
sky130_fd_sc_hd__decap_6 (1) |sky130_fd_sc_hd__decap_6 (1)
Number of devices: 17 |Number of devices: 17
Number of nets: 28 |Number of nets: 28
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: gpio_defaults_block_1803 |Circuit 2: gpio_defaults_block_1803
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
gpio_defaults[11] |gpio_defaults[11]
gpio_defaults[1] |gpio_defaults[1]
gpio_defaults[0] |gpio_defaults[0]
gpio_defaults[12] |gpio_defaults[12]
gpio_defaults[3] |gpio_defaults[3]
gpio_defaults[5] |gpio_defaults[5]
gpio_defaults[7] |gpio_defaults[7]
gpio_defaults[9] |gpio_defaults[9]
gpio_defaults[10] |gpio_defaults[10]
gpio_defaults[2] |gpio_defaults[2]
gpio_defaults[4] |gpio_defaults[4]
gpio_defaults[6] |gpio_defaults[6]
gpio_defaults[8] |gpio_defaults[8]
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes gpio_defaults_block_1803 and gpio_defaults_block_1803 are equivalent.
Class spare_logic_block (0): Merged 98 parallel devices.
Class spare_logic_block (1): Merged 98 parallel devices.
Subcircuit summary:
Circuit 1: spare_logic_block |Circuit 2: spare_logic_block
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_6 (10->1) |sky130_fd_sc_hd__decap_6 (10->1)
sky130_fd_sc_hd__decap_4 (27->1) |sky130_fd_sc_hd__decap_4 (27->1)
sky130_fd_sc_hd__decap_12 (24->1) |sky130_fd_sc_hd__decap_12 (24->1)
sky130_fd_sc_hd__conb_1 (27) |sky130_fd_sc_hd__conb_1 (27)
sky130_fd_sc_hd__nor2_2 (2) |sky130_fd_sc_hd__nor2_2 (2)
sky130_fd_sc_hd__decap_8 (12->1) |sky130_fd_sc_hd__decap_8 (12->1)
sky130_fd_sc_hd__decap_3 (30->1) |sky130_fd_sc_hd__decap_3 (30->1)
sky130_fd_sc_hd__dfbbp_1 (2) |sky130_fd_sc_hd__dfbbp_1 (2)
sky130_fd_sc_hd__mux2_2 (2) |sky130_fd_sc_hd__mux2_2 (2)
sky130_fd_sc_hd__inv_2 (4) |sky130_fd_sc_hd__inv_2 (4)
sky130_fd_sc_hd__nand2_2 (2) |sky130_fd_sc_hd__nand2_2 (2)
sky130_fd_sc_hd__inv_8 (1) |sky130_fd_sc_hd__inv_8 (1)
Number of devices: 45 |Number of devices: 45
Number of nets: 71 |Number of nets: 71
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: spare_logic_block |Circuit 2: spare_logic_block
-------------------------------------------|-------------------------------------------
spare_xib |spare_xib
spare_xfq[0] |spare_xfq[0]
spare_xfq[1] |spare_xfq[1]
spare_xfqn[0] |spare_xfqn[0]
spare_xfqn[1] |spare_xfqn[1]
spare_xi[0] |spare_xi[0]
spare_xi[1] |spare_xi[1]
spare_xi[2] |spare_xi[2]
spare_xi[3] |spare_xi[3]
spare_xmx[0] |spare_xmx[0]
spare_xmx[1] |spare_xmx[1]
spare_xna[0] |spare_xna[0]
spare_xna[1] |spare_xna[1]
spare_xno[0] |spare_xno[0]
spare_xno[1] |spare_xno[1]
spare_xz[4] |spare_xz[4]
spare_xz[11] |spare_xz[11]
spare_xz[12] |spare_xz[12]
spare_xz[13] |spare_xz[13]
spare_xz[14] |spare_xz[14]
spare_xz[15] |spare_xz[15]
spare_xz[16] |spare_xz[16]
spare_xz[17] |spare_xz[17]
spare_xz[18] |spare_xz[18]
spare_xz[19] |spare_xz[19]
spare_xz[20] |spare_xz[20]
spare_xz[21] |spare_xz[21]
spare_xz[22] |spare_xz[22]
spare_xz[23] |spare_xz[23]
spare_xz[24] |spare_xz[24]
spare_xz[25] |spare_xz[25]
spare_xz[26] |spare_xz[26]
spare_xz[0] |spare_xz[0]
spare_xz[1] |spare_xz[1]
spare_xz[2] |spare_xz[2]
spare_xz[3] |spare_xz[3]
spare_xz[5] |spare_xz[5]
spare_xz[6] |spare_xz[6]
spare_xz[7] |spare_xz[7]
spare_xz[8] |spare_xz[8]
spare_xz[10] |spare_xz[10]
spare_xz[9] |spare_xz[9]
vssd |vssd
vccd |vccd
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes spare_logic_block and spare_logic_block are equivalent.
Class user_id_programming (0): Merged 54 parallel devices.
Class user_id_programming (1): Merged 54 parallel devices.
Subcircuit summary:
Circuit 1: user_id_programming |Circuit 2: user_id_programming
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__conb_1 (32) |sky130_fd_sc_hd__conb_1 (32)
sky130_fd_sc_hd__decap_8 (7->1) |sky130_fd_sc_hd__decap_8 (7->1)
sky130_fd_sc_hd__decap_3 (24->1) |sky130_fd_sc_hd__decap_3 (24->1)
sky130_fd_sc_hd__decap_12 (12->1) |sky130_fd_sc_hd__decap_12 (12->1)
sky130_fd_sc_hd__decap_4 (8->1) |sky130_fd_sc_hd__decap_4 (8->1)
sky130_fd_sc_hd__decap_6 (8->1) |sky130_fd_sc_hd__decap_6 (8->1)
Number of devices: 37 |Number of devices: 37
Number of nets: 66 |Number of nets: 66
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Resolving automorphisms by pin name.
Netlists match uniquely.
Subcircuit pins:
Circuit 1: user_id_programming |Circuit 2: user_id_programming
-------------------------------------------|-------------------------------------------
VGND |VGND
VPWR |VPWR
mask_rev[18] |mask_rev[18]
mask_rev[25] |mask_rev[25]
mask_rev[3] |mask_rev[3]
mask_rev[27] |mask_rev[27]
mask_rev[5] |mask_rev[5]
mask_rev[0] |mask_rev[0]
mask_rev[29] |mask_rev[29]
mask_rev[7] |mask_rev[7]
mask_rev[13] |mask_rev[13]
mask_rev[20] |mask_rev[20]
mask_rev[9] |mask_rev[9]
mask_rev[15] |mask_rev[15]
mask_rev[22] |mask_rev[22]
mask_rev[11] |mask_rev[11]
mask_rev[17] |mask_rev[17]
mask_rev[24] |mask_rev[24]
mask_rev[31] |mask_rev[31]
mask_rev[2] |mask_rev[2]
mask_rev[19] |mask_rev[19]
mask_rev[26] |mask_rev[26]
mask_rev[4] |mask_rev[4]
mask_rev[10] |mask_rev[10]
mask_rev[28] |mask_rev[28]
mask_rev[6] |mask_rev[6]
mask_rev[12] |mask_rev[12]
mask_rev[8] |mask_rev[8]
mask_rev[14] |mask_rev[14]
mask_rev[21] |mask_rev[21]
mask_rev[16] |mask_rev[16]
mask_rev[23] |mask_rev[23]
mask_rev[30] |mask_rev[30]
mask_rev[1] |mask_rev[1]
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes user_id_programming and user_id_programming are equivalent.
Circuit 2 cell gpio_defaults_block_0801 is a black box; will not flatten Circuit 1
Class gpio_defaults_block_0801 (0): Merged 15 parallel devices.
Subcircuit pins:
Circuit 1: gpio_defaults_block_0801 |Circuit 2: gpio_defaults_block_0801
-------------------------------------------|-------------------------------------------
VPWR |VPWR
gpio_defaults[0] |gpio_defaults[0]
gpio_defaults[10] |gpio_defaults[10]
gpio_defaults[11] |gpio_defaults[11]
gpio_defaults[12] |gpio_defaults[12]
gpio_defaults[1] |gpio_defaults[1]
gpio_defaults[2] |gpio_defaults[2]
gpio_defaults[3] |gpio_defaults[3]
gpio_defaults[4] |gpio_defaults[4]
gpio_defaults[5] |gpio_defaults[5]
gpio_defaults[6] |gpio_defaults[6]
gpio_defaults[7] |gpio_defaults[7]
gpio_defaults[8] |gpio_defaults[8]
gpio_defaults[9] |gpio_defaults[9]
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes gpio_defaults_block_0801 and gpio_defaults_block_0801 are equivalent.
Circuit 2 cell gpio_signal_buffering_alt is a black box; will not flatten Circuit 1
Class gpio_signal_buffering_alt (0): Merged 54 parallel devices.
Subcircuit pins:
Circuit 1: gpio_signal_buffering_alt |Circuit 2: gpio_signal_buffering_alt
-------------------------------------------|-------------------------------------------
mgmt_io_in_unbuf[6] |mgmt_io_in_unbuf[6]
mgmt_io_out_buf[6] |mgmt_io_out_buf[6]
mgmt_io_in_unbuf[5] |mgmt_io_in_unbuf[5]
mgmt_io_in_unbuf[4] |mgmt_io_in_unbuf[4]
mgmt_io_in_unbuf[3] |mgmt_io_in_unbuf[3]
mgmt_io_in_unbuf[2] |mgmt_io_in_unbuf[2]
mgmt_io_in_unbuf[1] |mgmt_io_in_unbuf[1]
mgmt_io_in_unbuf[0] |mgmt_io_in_unbuf[0]
mgmt_io_out_buf[0] |mgmt_io_out_buf[0]
mgmt_io_out_buf[1] |mgmt_io_out_buf[1]
mgmt_io_out_buf[2] |mgmt_io_out_buf[2]
mgmt_io_out_buf[3] |mgmt_io_out_buf[3]
mgmt_io_out_buf[4] |mgmt_io_out_buf[4]
mgmt_io_out_buf[5] |mgmt_io_out_buf[5]
mgmt_io_out_unbuf[0] |mgmt_io_out_unbuf[0]
mgmt_io_out_unbuf[1] |mgmt_io_out_unbuf[1]
mgmt_io_out_unbuf[2] |mgmt_io_out_unbuf[2]
mgmt_io_out_unbuf[3] |mgmt_io_out_unbuf[3]
mgmt_io_out_unbuf[4] |mgmt_io_out_unbuf[4]
mgmt_io_out_unbuf[5] |mgmt_io_out_unbuf[5]
mgmt_io_out_unbuf[6] |mgmt_io_out_unbuf[6]
mgmt_io_in_buf[6] |mgmt_io_in_buf[6]
mgmt_io_in_buf[5] |mgmt_io_in_buf[5]
mgmt_io_in_buf[4] |mgmt_io_in_buf[4]
mgmt_io_in_buf[3] |mgmt_io_in_buf[3]
mgmt_io_in_buf[2] |mgmt_io_in_buf[2]
mgmt_io_in_buf[1] |mgmt_io_in_buf[1]
mgmt_io_in_buf[0] |mgmt_io_in_buf[0]
mgmt_io_out_buf[10] |mgmt_io_out_buf[10]
mgmt_io_out_buf[11] |mgmt_io_out_buf[11]
mgmt_io_in_unbuf[11] |mgmt_io_in_unbuf[11]
mgmt_io_in_unbuf[10] |mgmt_io_in_unbuf[10]
mgmt_io_out_buf[12] |mgmt_io_out_buf[12]
mgmt_io_out_buf[13] |mgmt_io_out_buf[13]
mgmt_io_out_buf[14] |mgmt_io_out_buf[14]
mgmt_io_out_buf[15] |mgmt_io_out_buf[15]
mgmt_io_in_unbuf[15] |mgmt_io_in_unbuf[15]
mgmt_io_in_unbuf[14] |mgmt_io_in_unbuf[14]
mgmt_io_in_unbuf[13] |mgmt_io_in_unbuf[13]
mgmt_io_in_unbuf[12] |mgmt_io_in_unbuf[12]
mgmt_io_out_buf[16] |mgmt_io_out_buf[16]
mgmt_io_out_buf[17] |mgmt_io_out_buf[17]
mgmt_io_out_buf[18] |mgmt_io_out_buf[18]
mgmt_io_out_buf[19] |mgmt_io_out_buf[19]
mgmt_io_in_unbuf[19] |mgmt_io_in_unbuf[19]
mgmt_io_in_unbuf[18] |mgmt_io_in_unbuf[18]
mgmt_io_in_unbuf[17] |mgmt_io_in_unbuf[17]
mgmt_io_in_unbuf[16] |mgmt_io_in_unbuf[16]
mgmt_io_oeb_buf[0] |mgmt_io_oeb_buf[0]
mgmt_io_oeb_buf[1] |mgmt_io_oeb_buf[1]
mgmt_io_oeb_buf[2] |mgmt_io_oeb_buf[2]
mgmt_io_oeb_unbuf[2] |mgmt_io_oeb_unbuf[2]
mgmt_io_oeb_unbuf[1] |mgmt_io_oeb_unbuf[1]
mgmt_io_oeb_unbuf[0] |mgmt_io_oeb_unbuf[0]
mgmt_io_in_buf[19] |mgmt_io_in_buf[19]
mgmt_io_in_buf[18] |mgmt_io_in_buf[18]
mgmt_io_in_buf[17] |mgmt_io_in_buf[17]
mgmt_io_in_buf[16] |mgmt_io_in_buf[16]
mgmt_io_out_unbuf[16] |mgmt_io_out_unbuf[16]
mgmt_io_out_unbuf[17] |mgmt_io_out_unbuf[17]
mgmt_io_out_unbuf[18] |mgmt_io_out_unbuf[18]
mgmt_io_out_unbuf[19] |mgmt_io_out_unbuf[19]
mgmt_io_out_unbuf[15] |mgmt_io_out_unbuf[15]
mgmt_io_out_unbuf[14] |mgmt_io_out_unbuf[14]
mgmt_io_out_unbuf[13] |mgmt_io_out_unbuf[13]
mgmt_io_out_unbuf[12] |mgmt_io_out_unbuf[12]
mgmt_io_out_unbuf[11] |mgmt_io_out_unbuf[11]
mgmt_io_out_unbuf[10] |mgmt_io_out_unbuf[10]
mgmt_io_out_unbuf[9] |mgmt_io_out_unbuf[9]
mgmt_io_out_unbuf[8] |mgmt_io_out_unbuf[8]
mgmt_io_out_unbuf[7] |mgmt_io_out_unbuf[7]
mgmt_io_in_buf[7] |mgmt_io_in_buf[7]
mgmt_io_in_buf[8] |mgmt_io_in_buf[8]
mgmt_io_in_buf[9] |mgmt_io_in_buf[9]
mgmt_io_in_buf[10] |mgmt_io_in_buf[10]
mgmt_io_in_buf[11] |mgmt_io_in_buf[11]
mgmt_io_in_buf[12] |mgmt_io_in_buf[12]
mgmt_io_in_buf[13] |mgmt_io_in_buf[13]
mgmt_io_in_buf[14] |mgmt_io_in_buf[14]
mgmt_io_in_buf[15] |mgmt_io_in_buf[15]
vssd |vssd
vccd |vccd
mgmt_io_out_buf[9] |mgmt_io_out_buf[9]
mgmt_io_in_unbuf[9] |mgmt_io_in_unbuf[9]
mgmt_io_out_buf[8] |mgmt_io_out_buf[8]
mgmt_io_in_unbuf[8] |mgmt_io_in_unbuf[8]
mgmt_io_out_buf[7] |mgmt_io_out_buf[7]
mgmt_io_in_unbuf[7] |mgmt_io_in_unbuf[7]
vccd_uq0 |(no matching pin)
vccd_uq1 |(no matching pin)
vccd_uq3 |(no matching pin)
vccd_uq4 |(no matching pin)
vccd_uq2 |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes gpio_signal_buffering_alt and gpio_signal_buffering_alt are equivalent.
Class mgmt_protect (0): Merged 20502 parallel devices.
Class mgmt_protect (1): Merged 20502 parallel devices.
Subcircuit summary:
Circuit 1: mgmt_protect |Circuit 2: mgmt_protect
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__diode_2 (3590->3181) |sky130_fd_sc_hd__diode_2 (3590->3181)
sky130_fd_sc_hd__decap_6 (2892->1) |sky130_fd_sc_hd__decap_6 (2892->1)
sky130_ef_sc_hd__decap_12 (11094->1) |sky130_ef_sc_hd__decap_12 (11094->1)
sky130_fd_sc_hd__decap_4 (3566->1) |sky130_fd_sc_hd__decap_4 (3566->1)
sky130_fd_sc_hd__decap_8 (1120->1) |sky130_fd_sc_hd__decap_8 (1120->1)
sky130_fd_sc_hd__buf_6 (1432) |sky130_fd_sc_hd__buf_6 (1432)
sky130_fd_sc_hd__decap_3 (1426->1) |sky130_fd_sc_hd__decap_3 (1426->1)
sky130_fd_sc_hd__and2_4 (211) |sky130_fd_sc_hd__and2_4 (211)
sky130_fd_sc_hd__and3b_4 (102) |sky130_fd_sc_hd__and3b_4 (102)
sky130_fd_sc_hd__and2_2 (101) |sky130_fd_sc_hd__and2_2 (101)
sky130_fd_sc_hd__nand2_8 (51) |sky130_fd_sc_hd__nand2_8 (51)
sky130_fd_sc_hd__nand2_2 (34) |sky130_fd_sc_hd__nand2_2 (34)
sky130_fd_sc_hd__buf_8 (559) |sky130_fd_sc_hd__buf_8 (559)
sky130_fd_sc_hd__clkinv_8 (19) |sky130_fd_sc_hd__clkinv_8 (19)
sky130_fd_sc_hd__clkinv_2 (44) |sky130_fd_sc_hd__clkinv_2 (44)
sky130_fd_sc_hd__clkbuf_4 (220) |sky130_fd_sc_hd__clkbuf_4 (220)
sky130_fd_sc_hd__buf_4 (85) |sky130_fd_sc_hd__buf_4 (85)
sky130_fd_sc_hd__clkinv_4 (35) |sky130_fd_sc_hd__clkinv_4 (35)
sky130_fd_sc_hd__and3b_2 (21) |sky130_fd_sc_hd__and3b_2 (21)
sky130_fd_sc_hd__and2_1 (21) |sky130_fd_sc_hd__and2_1 (21)
sky130_fd_sc_hd__nand2_4 (66) |sky130_fd_sc_hd__nand2_4 (66)
sky130_fd_sc_hd__inv_2 (58) |sky130_fd_sc_hd__inv_2 (58)
sky130_fd_sc_hd__clkbuf_8 (12) |sky130_fd_sc_hd__clkbuf_8 (12)
sky130_fd_sc_hd__and3b_1 (5) |sky130_fd_sc_hd__and3b_1 (5)
sky130_fd_sc_hd__nand2_1 (13) |sky130_fd_sc_hd__nand2_1 (13)
sky130_fd_sc_hd__inv_4 (3) |sky130_fd_sc_hd__inv_4 (3)
sky130_fd_sc_hd__inv_12 (5) |sky130_fd_sc_hd__inv_12 (5)
mprj2_logic_high (1) |mprj2_logic_high (1)
mprj_logic_high (1) |mprj_logic_high (1)
mgmt_protect_hv (1) |mgmt_protect_hv (1)
sky130_fd_sc_hd__bufbuf_8 (4) |sky130_fd_sc_hd__bufbuf_8 (4)
sky130_fd_sc_hd__and2b_4 (1) |sky130_fd_sc_hd__and2b_4 (1)
Number of devices: 6291 |Number of devices: 6291
Number of nets: 4204 |Number of nets: 4204
---------------------------------------------------------------------------------------
Resolving automorphisms by property value.
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance ANTENNA_wire1118_A network:
M = 1
M = 1
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance ANTENNA_wire1118_A network:
M = 1
M = 1
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance ANTENNA_wire1118_A network:
M = 1
M = 1
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance ANTENNA_wire1118_A network:
M = 1
M = 1
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance ANTENNA_wire1118_A network:
M = 1
M = 1
Resolving automorphisms by pin name.
Netlists match uniquely with property errors.
Subcircuit pins:
Circuit 1: mgmt_protect |Circuit 2: mgmt_protect
-------------------------------------------|-------------------------------------------
vccd2 |vccd2
vssd2 |vssd2
vccd1 |vccd1
vssd1 |vssd1
vdda1 |vdda1
vdda2 |vdda2
vssa2 |vssa2
vssa1 |vssa1
la_data_in_mprj[23] |la_data_in_mprj[23]
la_data_in_mprj[7] |la_data_in_mprj[7]
la_oenb_core[68] |la_oenb_core[68]
la_data_in_mprj[22] |la_data_in_mprj[22]
la_data_in_mprj[38] |la_data_in_mprj[38]
la_oenb_core[36] |la_oenb_core[36]
la_oenb_core[37] |la_oenb_core[37]
la_oenb_core[47] |la_oenb_core[47]
la_oenb_core[78] |la_oenb_core[78]
mprj_adr_o_user[21] |mprj_adr_o_user[21]
mprj_adr_o_user[29] |mprj_adr_o_user[29]
mprj_adr_o_user[28] |mprj_adr_o_user[28]
mprj_adr_o_user[27] |mprj_adr_o_user[27]
mprj_adr_o_user[26] |mprj_adr_o_user[26]
mprj_adr_o_user[25] |mprj_adr_o_user[25]
mprj_adr_o_user[24] |mprj_adr_o_user[24]
mprj_adr_o_user[30] |mprj_adr_o_user[30]
mprj_adr_o_user[31] |mprj_adr_o_user[31]
mprj_adr_o_user[1] |mprj_adr_o_user[1]
mprj_adr_o_user[0] |mprj_adr_o_user[0]
mprj_adr_o_user[5] |mprj_adr_o_user[5]
mprj_adr_o_user[4] |mprj_adr_o_user[4]
mprj_adr_o_user[3] |mprj_adr_o_user[3]
mprj_adr_o_user[2] |mprj_adr_o_user[2]
la_data_in_mprj[105] |la_data_in_mprj[105]
la_data_in_mprj[103] |la_data_in_mprj[103]
la_data_in_mprj[104] |la_data_in_mprj[104]
la_data_in_mprj[44] |la_data_in_mprj[44]
la_data_in_mprj[30] |la_data_in_mprj[30]
la_data_in_mprj[45] |la_data_in_mprj[45]
la_data_in_mprj[70] |la_data_in_mprj[70]
la_data_in_mprj[69] |la_data_in_mprj[69]
la_data_in_mprj[68] |la_data_in_mprj[68]
la_data_in_mprj[41] |la_data_in_mprj[41]
la_data_in_mprj[32] |la_data_in_mprj[32]
la_data_in_mprj[102] |la_data_in_mprj[102]
la_data_in_mprj[71] |la_data_in_mprj[71]
la_data_in_mprj[72] |la_data_in_mprj[72]
la_data_in_mprj[73] |la_data_in_mprj[73]
la_data_in_mprj[74] |la_data_in_mprj[74]
la_data_in_mprj[91] |la_data_in_mprj[91]
la_data_in_mprj[92] |la_data_in_mprj[92]
la_data_in_mprj[95] |la_data_in_mprj[95]
la_data_in_mprj[93] |la_data_in_mprj[93]
la_data_in_mprj[101] |la_data_in_mprj[101]
la_data_in_mprj[94] |la_data_in_mprj[94]
user2_vdd_powergood |user2_vdd_powergood
la_oenb_core[32] |la_oenb_core[32]
la_oenb_core[35] |la_oenb_core[35]
la_oenb_core[43] |la_oenb_core[43]
la_oenb_core[46] |la_oenb_core[46]
la_oenb_core[48] |la_oenb_core[48]
user1_vdd_powergood |user1_vdd_powergood
la_oenb_core[31] |la_oenb_core[31]
la_oenb_core[40] |la_oenb_core[40]
user_clock2 |user_clock2
mprj_sel_o_user[3] |mprj_sel_o_user[3]
mprj_sel_o_user[2] |mprj_sel_o_user[2]
mprj_sel_o_user[0] |mprj_sel_o_user[0]
mprj_sel_o_user[1] |mprj_sel_o_user[1]
mprj_dat_o_user[22] |mprj_dat_o_user[22]
mprj_dat_o_user[24] |mprj_dat_o_user[24]
mprj_dat_o_user[23] |mprj_dat_o_user[23]
mprj_dat_o_user[31] |mprj_dat_o_user[31]
mprj_dat_o_user[26] |mprj_dat_o_user[26]
mprj_dat_o_user[27] |mprj_dat_o_user[27]
mprj_dat_o_user[25] |mprj_dat_o_user[25]
mprj_dat_i_core[3] |mprj_dat_i_core[3]
mprj_dat_o_user[28] |mprj_dat_o_user[28]
mprj_dat_o_user[29] |mprj_dat_o_user[29]
mprj_dat_o_user[30] |mprj_dat_o_user[30]
mprj_dat_i_core[7] |mprj_dat_i_core[7]
mprj_we_o_user |mprj_we_o_user
la_data_in_mprj[28] |la_data_in_mprj[28]
la_data_in_mprj[127] |la_data_in_mprj[127]
la_data_in_mprj[29] |la_data_in_mprj[29]
la_data_in_mprj[27] |la_data_in_mprj[27]
la_data_in_mprj[42] |la_data_in_mprj[42]
la_data_in_mprj[31] |la_data_in_mprj[31]
la_data_in_mprj[43] |la_data_in_mprj[43]
la_data_in_mprj[21] |la_data_in_mprj[21]
la_data_in_mprj[126] |la_data_in_mprj[126]
la_data_in_mprj[39] |la_data_in_mprj[39]
la_data_in_mprj[18] |la_data_in_mprj[18]
la_data_in_mprj[49] |la_data_in_mprj[49]
la_data_in_mprj[17] |la_data_in_mprj[17]
la_data_in_mprj[125] |la_data_in_mprj[125]
la_data_in_mprj[19] |la_data_in_mprj[19]
la_data_in_mprj[20] |la_data_in_mprj[20]
la_data_in_mprj[46] |la_data_in_mprj[46]
la_data_in_mprj[67] |la_data_in_mprj[67]
la_data_in_mprj[40] |la_data_in_mprj[40]
la_data_in_mprj[33] |la_data_in_mprj[33]
la_data_in_mprj[47] |la_data_in_mprj[47]
la_data_in_mprj[48] |la_data_in_mprj[48]
la_data_in_mprj[75] |la_data_in_mprj[75]
la_data_in_mprj[89] |la_data_in_mprj[89]
la_data_in_mprj[90] |la_data_in_mprj[90]
la_data_in_mprj[106] |la_data_in_mprj[106]
la_data_in_mprj[96] |la_data_in_mprj[96]
la_data_in_mprj[107] |la_data_in_mprj[107]
la_data_in_mprj[100] |la_data_in_mprj[100]
la_data_in_mprj[76] |la_data_in_mprj[76]
la_data_in_mprj[98] |la_data_in_mprj[98]
la_data_in_mprj[88] |la_data_in_mprj[88]
la_data_in_mprj[99] |la_data_in_mprj[99]
la_data_in_mprj[77] |la_data_in_mprj[77]
la_data_in_mprj[97] |la_data_in_mprj[97]
la_data_in_mprj[123] |la_data_in_mprj[123]
la_data_in_mprj[117] |la_data_in_mprj[117]
la_data_in_mprj[115] |la_data_in_mprj[115]
la_data_in_mprj[116] |la_data_in_mprj[116]
la_data_in_mprj[122] |la_data_in_mprj[122]
la_data_in_mprj[34] |la_data_in_mprj[34]
la_data_in_mprj[50] |la_data_in_mprj[50]
la_data_in_mprj[64] |la_data_in_mprj[64]
la_data_in_mprj[66] |la_data_in_mprj[66]
la_oenb_core[102] |la_oenb_core[102]
la_oenb_core[103] |la_oenb_core[103]
la_oenb_core[107] |la_oenb_core[107]
la_oenb_core[106] |la_oenb_core[106]
la_oenb_core[108] |la_oenb_core[108]
la_oenb_core[109] |la_oenb_core[109]
la_oenb_core[110] |la_oenb_core[110]
la_oenb_core[111] |la_oenb_core[111]
la_oenb_core[122] |la_oenb_core[122]
la_oenb_core[101] |la_oenb_core[101]
la_oenb_core[104] |la_oenb_core[104]
la_oenb_core[105] |la_oenb_core[105]
la_oenb_core[123] |la_oenb_core[123]
la_oenb_core[124] |la_oenb_core[124]
la_oenb_core[125] |la_oenb_core[125]
la_oenb_core[27] |la_oenb_core[27]
la_oenb_core[29] |la_oenb_core[29]
la_oenb_core[51] |la_oenb_core[51]
la_oenb_core[54] |la_oenb_core[54]
la_oenb_core[59] |la_oenb_core[59]
la_oenb_core[62] |la_oenb_core[62]
la_oenb_core[100] |la_oenb_core[100]
la_oenb_core[63] |la_oenb_core[63]
la_oenb_core[74] |la_oenb_core[74]
la_oenb_core[73] |la_oenb_core[73]
la_oenb_core[80] |la_oenb_core[80]
la_oenb_core[81] |la_oenb_core[81]
la_oenb_core[72] |la_oenb_core[72]
la_oenb_core[79] |la_oenb_core[79]
la_oenb_core[75] |la_oenb_core[75]
la_oenb_core[76] |la_oenb_core[76]
la_oenb_core[77] |la_oenb_core[77]
la_oenb_core[82] |la_oenb_core[82]
la_oenb_core[83] |la_oenb_core[83]
la_oenb_core[84] |la_oenb_core[84]
la_oenb_core[85] |la_oenb_core[85]
la_oenb_core[86] |la_oenb_core[86]
la_oenb_core[116] |la_oenb_core[116]
la_oenb_core[87] |la_oenb_core[87]
la_oenb_core[88] |la_oenb_core[88]
la_oenb_core[93] |la_oenb_core[93]
la_oenb_core[92] |la_oenb_core[92]
la_oenb_core[64] |la_oenb_core[64]
la_oenb_core[97] |la_oenb_core[97]
la_oenb_core[98] |la_oenb_core[98]
la_oenb_core[94] |la_oenb_core[94]
la_oenb_core[95] |la_oenb_core[95]
la_oenb_core[117] |la_oenb_core[117]
la_oenb_core[113] |la_oenb_core[113]
la_oenb_core[118] |la_oenb_core[118]
la_oenb_core[115] |la_oenb_core[115]
la_oenb_core[114] |la_oenb_core[114]
la_oenb_core[71] |la_oenb_core[71]
la_oenb_core[112] |la_oenb_core[112]
la_oenb_core[121] |la_oenb_core[121]
la_oenb_core[120] |la_oenb_core[120]
la_oenb_core[119] |la_oenb_core[119]
la_oenb_core[96] |la_oenb_core[96]
la_oenb_core[99] |la_oenb_core[99]
la_data_in_core[32] |la_data_in_core[32]
la_data_in_core[100] |la_data_in_core[100]
la_data_in_core[107] |la_data_in_core[107]
la_data_in_core[125] |la_data_in_core[125]
la_data_in_core[33] |la_data_in_core[33]
la_data_in_core[62] |la_data_in_core[62]
la_data_in_core[31] |la_data_in_core[31]
la_data_in_core[30] |la_data_in_core[30]
la_data_in_core[29] |la_data_in_core[29]
la_data_in_core[101] |la_data_in_core[101]
la_data_in_core[124] |la_data_in_core[124]
la_data_in_core[105] |la_data_in_core[105]
la_data_in_core[104] |la_data_in_core[104]
la_data_in_core[123] |la_data_in_core[123]
la_data_in_core[122] |la_data_in_core[122]
la_data_in_core[108] |la_data_in_core[108]
la_data_in_core[106] |la_data_in_core[106]
la_data_in_core[96] |la_data_in_core[96]
la_data_in_core[99] |la_data_in_core[99]
la_oenb_core[61] |la_oenb_core[61]
la_oenb_core[8] |la_oenb_core[8]
la_oenb_core[126] |la_oenb_core[126]
la_oenb_core[57] |la_oenb_core[57]
la_oenb_core[25] |la_oenb_core[25]
la_oenb_core[15] |la_oenb_core[15]
la_oenb_core[7] |la_oenb_core[7]
la_oenb_core[44] |la_oenb_core[44]
la_oenb_core[91] |la_oenb_core[91]
la_oenb_core[12] |la_oenb_core[12]
mprj_adr_o_user[18] |mprj_adr_o_user[18]
mprj_cyc_o_user |mprj_cyc_o_user
la_data_in_core[109] |la_data_in_core[109]
la_data_in_core[110] |la_data_in_core[110]
la_data_in_core[111] |la_data_in_core[111]
la_data_in_core[117] |la_data_in_core[117]
la_data_in_core[112] |la_data_in_core[112]
la_data_in_core[120] |la_data_in_core[120]
la_data_in_core[121] |la_data_in_core[121]
la_data_in_core[119] |la_data_in_core[119]
la_data_in_core[65] |la_data_in_core[65]
la_data_in_core[69] |la_data_in_core[69]
la_data_in_core[70] |la_data_in_core[70]
la_data_in_core[67] |la_data_in_core[67]
la_data_in_core[66] |la_data_in_core[66]
la_data_in_core[71] |la_data_in_core[71]
la_data_in_core[64] |la_data_in_core[64]
la_data_in_core[63] |la_data_in_core[63]
la_data_in_core[113] |la_data_in_core[113]
la_data_in_core[118] |la_data_in_core[118]
la_data_in_core[115] |la_data_in_core[115]
la_data_in_core[114] |la_data_in_core[114]
la_data_in_core[73] |la_data_in_core[73]
la_data_in_core[78] |la_data_in_core[78]
la_data_in_core[79] |la_data_in_core[79]
la_data_in_core[77] |la_data_in_core[77]
la_data_in_core[76] |la_data_in_core[76]
la_data_in_core[75] |la_data_in_core[75]
la_data_in_core[74] |la_data_in_core[74]
la_data_in_core[72] |la_data_in_core[72]
la_data_in_core[80] |la_data_in_core[80]
la_data_in_core[81] |la_data_in_core[81]
la_data_in_core[82] |la_data_in_core[82]
la_data_in_core[84] |la_data_in_core[84]
la_data_in_core[83] |la_data_in_core[83]
la_data_in_core[116] |la_data_in_core[116]
la_data_in_core[88] |la_data_in_core[88]
la_data_in_core[87] |la_data_in_core[87]
la_data_in_core[86] |la_data_in_core[86]
la_data_in_core[85] |la_data_in_core[85]
la_data_in_core[98] |la_data_in_core[98]
la_data_in_core[97] |la_data_in_core[97]
la_data_in_core[35] |la_data_in_core[35]
la_data_in_core[13] |la_data_in_core[13]
la_data_in_core[4] |la_data_in_core[4]
la_data_in_core[39] |la_data_in_core[39]
la_data_in_core[51] |la_data_in_core[51]
la_data_in_core[38] |la_data_in_core[38]
la_data_in_core[57] |la_data_in_core[57]
la_data_in_core[37] |la_data_in_core[37]
la_data_in_core[36] |la_data_in_core[36]
la_data_in_core[11] |la_data_in_core[11]
la_data_in_core[17] |la_data_in_core[17]
la_data_in_core[127] |la_data_in_core[127]
la_data_in_core[126] |la_data_in_core[126]
la_data_in_core[42] |la_data_in_core[42]
la_data_in_core[41] |la_data_in_core[41]
la_data_in_core[60] |la_data_in_core[60]
la_data_in_core[50] |la_data_in_core[50]
la_data_in_core[19] |la_data_in_core[19]
la_data_in_core[20] |la_data_in_core[20]
la_data_in_core[93] |la_data_in_core[93]
la_data_in_core[92] |la_data_in_core[92]
la_data_in_core[91] |la_data_in_core[91]
la_data_in_core[90] |la_data_in_core[90]
la_data_in_core[102] |la_data_in_core[102]
la_data_in_core[103] |la_data_in_core[103]
la_data_in_core[12] |la_data_in_core[12]
la_data_in_core[25] |la_data_in_core[25]
la_data_in_core[44] |la_data_in_core[44]
la_data_in_core[34] |la_data_in_core[34]
la_data_in_core[43] |la_data_in_core[43]
la_data_in_core[61] |la_data_in_core[61]
la_data_in_core[40] |la_data_in_core[40]
la_data_in_core[8] |la_data_in_core[8]
la_data_in_core[15] |la_data_in_core[15]
la_data_in_core[7] |la_data_in_core[7]
la_data_in_core[21] |la_data_in_core[21]
la_data_in_core[22] |la_data_in_core[22]
la_data_in_core[24] |la_data_in_core[24]
la_data_in_core[14] |la_data_in_core[14]
la_data_in_core[0] |la_data_in_core[0]
la_data_in_core[5] |la_data_in_core[5]
la_data_in_core[3] |la_data_in_core[3]
la_data_in_core[89] |la_data_in_core[89]
la_data_in_core[59] |la_data_in_core[59]
la_data_in_core[49] |la_data_in_core[49]
la_data_in_core[48] |la_data_in_core[48]
la_data_in_core[28] |la_data_in_core[28]
la_data_in_core[23] |la_data_in_core[23]
la_data_in_core[6] |la_data_in_core[6]
la_data_in_core[2] |la_data_in_core[2]
la_data_in_core[1] |la_data_in_core[1]
la_data_in_core[18] |la_data_in_core[18]
la_data_in_core[47] |la_data_in_core[47]
la_data_in_core[27] |la_data_in_core[27]
la_data_in_core[46] |la_data_in_core[46]
la_data_in_core[45] |la_data_in_core[45]
la_data_in_core[94] |la_data_in_core[94]
la_data_in_core[95] |la_data_in_core[95]
la_data_in_core[16] |la_data_in_core[16]
la_data_in_core[10] |la_data_in_core[10]
la_data_in_core[9] |la_data_in_core[9]
la_oenb_core[60] |la_oenb_core[60]
la_oenb_core[20] |la_oenb_core[20]
la_oenb_core[19] |la_oenb_core[19]
la_oenb_core[38] |la_oenb_core[38]
la_oenb_core[26] |la_oenb_core[26]
la_oenb_core[55] |la_oenb_core[55]
la_oenb_core[45] |la_oenb_core[45]
la_oenb_core[28] |la_oenb_core[28]
la_oenb_core[34] |la_oenb_core[34]
la_oenb_core[33] |la_oenb_core[33]
la_oenb_core[18] |la_oenb_core[18]
la_oenb_core[23] |la_oenb_core[23]
la_oenb_core[2] |la_oenb_core[2]
la_oenb_core[1] |la_oenb_core[1]
la_oenb_core[6] |la_oenb_core[6]
la_oenb_core[42] |la_oenb_core[42]
la_oenb_core[14] |la_oenb_core[14]
la_oenb_core[21] |la_oenb_core[21]
la_oenb_core[22] |la_oenb_core[22]
la_oenb_core[24] |la_oenb_core[24]
la_oenb_core[5] |la_oenb_core[5]
la_oenb_core[0] |la_oenb_core[0]
la_oenb_core[3] |la_oenb_core[3]
la_oenb_core[89] |la_oenb_core[89]
la_oenb_core[127] |la_oenb_core[127]
la_oenb_core[17] |la_oenb_core[17]
la_oenb_core[90] |la_oenb_core[90]
la_oenb_core[11] |la_oenb_core[11]
la_oenb_core[10] |la_oenb_core[10]
la_oenb_core[16] |la_oenb_core[16]
la_oenb_core[9] |la_oenb_core[9]
mprj_adr_o_user[20] |mprj_adr_o_user[20]
la_data_in_core[58] |la_data_in_core[58]
la_data_in_core[26] |la_data_in_core[26]
la_data_in_core[52] |la_data_in_core[52]
la_data_in_core[53] |la_data_in_core[53]
la_data_in_core[54] |la_data_in_core[54]
la_data_in_core[55] |la_data_in_core[55]
la_data_in_core[56] |la_data_in_core[56]
la_oenb_core[41] |la_oenb_core[41]
la_oenb_core[49] |la_oenb_core[49]
la_oenb_core[53] |la_oenb_core[53]
la_oenb_core[56] |la_oenb_core[56]
mprj_adr_o_user[19] |mprj_adr_o_user[19]
mprj_adr_o_user[23] |mprj_adr_o_user[23]
mprj_adr_o_user[7] |mprj_adr_o_user[7]
mprj_adr_o_user[16] |mprj_adr_o_user[16]
mprj_adr_o_user[8] |mprj_adr_o_user[8]
mprj_adr_o_user[15] |mprj_adr_o_user[15]
la_oenb_core[39] |la_oenb_core[39]
la_oenb_core[13] |la_oenb_core[13]
la_oenb_core[4] |la_oenb_core[4]
mprj_dat_i_core[1] |mprj_dat_i_core[1]
mprj_dat_i_core[8] |mprj_dat_i_core[8]
la_oenb_core[58] |la_oenb_core[58]
mprj_adr_o_user[12] |mprj_adr_o_user[12]
mprj_adr_o_user[14] |mprj_adr_o_user[14]
mprj_adr_o_user[17] |mprj_adr_o_user[17]
mprj_adr_o_user[6] |mprj_adr_o_user[6]
mprj_adr_o_user[9] |mprj_adr_o_user[9]
mprj_dat_o_user[2] |mprj_dat_o_user[2]
mprj_adr_o_user[13] |mprj_adr_o_user[13]
mprj_adr_o_user[22] |mprj_adr_o_user[22]
mprj_dat_o_user[1] |mprj_dat_o_user[1]
mprj_dat_o_user[0] |mprj_dat_o_user[0]
mprj_adr_o_user[11] |mprj_adr_o_user[11]
mprj_dat_o_user[3] |mprj_dat_o_user[3]
mprj_dat_o_user[7] |mprj_dat_o_user[7]
mprj_dat_o_user[6] |mprj_dat_o_user[6]
la_oenb_core[50] |la_oenb_core[50]
la_oenb_core[52] |la_oenb_core[52]
mprj_adr_o_user[10] |mprj_adr_o_user[10]
mprj_dat_o_user[4] |mprj_dat_o_user[4]
mprj_dat_o_user[5] |mprj_dat_o_user[5]
mprj_dat_o_user[13] |mprj_dat_o_user[13]
mprj_dat_o_user[14] |mprj_dat_o_user[14]
mprj_stb_o_user |mprj_stb_o_user
mprj_dat_o_user[12] |mprj_dat_o_user[12]
mprj_dat_o_user[11] |mprj_dat_o_user[11]
mprj_dat_o_user[10] |mprj_dat_o_user[10]
mprj_dat_o_user[9] |mprj_dat_o_user[9]
mprj_dat_o_user[8] |mprj_dat_o_user[8]
mprj_dat_o_user[17] |mprj_dat_o_user[17]
mprj_dat_o_user[18] |mprj_dat_o_user[18]
mprj_dat_o_user[19] |mprj_dat_o_user[19]
mprj_dat_o_user[20] |mprj_dat_o_user[20]
mprj_dat_o_user[21] |mprj_dat_o_user[21]
mprj_dat_o_user[15] |mprj_dat_o_user[15]
mprj_dat_o_user[16] |mprj_dat_o_user[16]
user1_vcc_powergood |user1_vcc_powergood
mprj_dat_i_core[23] |mprj_dat_i_core[23]
mprj_dat_i_core[28] |mprj_dat_i_core[28]
mprj_dat_i_core[29] |mprj_dat_i_core[29]
mprj_dat_i_core[30] |mprj_dat_i_core[30]
mprj_dat_i_core[31] |mprj_dat_i_core[31]
mprj_dat_i_core[22] |mprj_dat_i_core[22]
mprj_dat_i_core[25] |mprj_dat_i_core[25]
mprj_dat_i_core[26] |mprj_dat_i_core[26]
mprj_dat_i_core[24] |mprj_dat_i_core[24]
mprj_dat_i_core[27] |mprj_dat_i_core[27]
mprj_dat_i_core[5] |mprj_dat_i_core[5]
mprj_dat_i_core[4] |mprj_dat_i_core[4]
mprj_dat_i_core[6] |mprj_dat_i_core[6]
mprj_dat_i_core[18] |mprj_dat_i_core[18]
mprj_dat_i_core[19] |mprj_dat_i_core[19]
mprj_dat_i_core[2] |mprj_dat_i_core[2]
mprj_dat_i_core[14] |mprj_dat_i_core[14]
mprj_dat_i_core[12] |mprj_dat_i_core[12]
mprj_dat_i_core[13] |mprj_dat_i_core[13]
mprj_dat_i_core[11] |mprj_dat_i_core[11]
mprj_dat_i_core[15] |mprj_dat_i_core[15]
mprj_dat_i_core[16] |mprj_dat_i_core[16]
mprj_dat_i_core[17] |mprj_dat_i_core[17]
mprj_dat_i_core[20] |mprj_dat_i_core[20]
mprj_dat_i_core[21] |mprj_dat_i_core[21]
mprj_ack_i_core |mprj_dat_i_core[0] **Mismatch**
mprj_dat_i_core[0] |mprj_ack_i_core **Mismatch**
mprj_dat_i_core[10] |mprj_dat_i_core[10]
mprj_dat_i_core[9] |mprj_dat_i_core[9]
user2_vcc_powergood |user2_vcc_powergood
user_clock |user_clock
la_data_in_core[68] |la_data_in_core[68]
la_data_in_mprj[57] |la_data_in_mprj[57]
la_data_in_mprj[58] |la_data_in_mprj[58]
la_data_in_mprj[59] |la_data_in_mprj[59]
la_data_in_mprj[60] |la_data_in_mprj[60]
la_data_in_mprj[6] |la_data_in_mprj[6]
la_data_in_mprj[10] |la_data_in_mprj[10]
la_data_in_mprj[1] |la_data_in_mprj[1]
la_data_in_mprj[2] |la_data_in_mprj[2]
la_data_in_mprj[3] |la_data_in_mprj[3]
la_data_in_mprj[0] |la_data_in_mprj[0]
la_data_in_mprj[5] |la_data_in_mprj[5]
user_reset |user_reset
la_data_in_mprj[118] |la_data_in_mprj[118]
la_data_in_mprj[114] |la_data_in_mprj[114]
la_data_in_mprj[119] |la_data_in_mprj[119]
la_data_in_mprj[121] |la_data_in_mprj[121]
la_data_in_mprj[120] |la_data_in_mprj[120]
la_data_in_mprj[15] |la_data_in_mprj[15]
la_data_in_mprj[13] |la_data_in_mprj[13]
la_data_in_mprj[16] |la_data_in_mprj[16]
la_data_in_mprj[51] |la_data_in_mprj[51]
la_data_in_mprj[62] |la_data_in_mprj[62]
la_data_in_mprj[63] |la_data_in_mprj[63]
la_data_in_mprj[65] |la_data_in_mprj[65]
la_data_in_mprj[78] |la_data_in_mprj[78]
la_data_in_mprj[79] |la_data_in_mprj[79]
la_data_in_mprj[87] |la_data_in_mprj[87]
la_data_in_mprj[82] |la_data_in_mprj[82]
la_data_in_mprj[83] |la_data_in_mprj[83]
la_data_in_mprj[84] |la_data_in_mprj[84]
la_data_in_mprj[85] |la_data_in_mprj[85]
la_data_in_mprj[108] |la_data_in_mprj[108]
la_data_in_mprj[8] |la_data_in_mprj[8]
la_data_in_mprj[14] |la_data_in_mprj[14]
la_data_in_mprj[124] |la_data_in_mprj[124]
la_data_in_mprj[12] |la_data_in_mprj[12]
la_data_in_mprj[35] |la_data_in_mprj[35]
la_data_in_mprj[24] |la_data_in_mprj[24]
la_data_in_mprj[4] |la_data_in_mprj[4]
la_data_in_mprj[26] |la_data_in_mprj[26]
la_data_in_mprj[25] |la_data_in_mprj[25]
user_irq[0] |user_irq[0]
la_data_in_mprj[36] |la_data_in_mprj[36]
la_data_in_mprj[37] |la_data_in_mprj[37]
user_irq[2] |user_irq[2]
user_irq[1] |user_irq[1]
la_data_in_mprj[111] |la_data_in_mprj[111]
la_data_in_mprj[110] |la_data_in_mprj[110]
la_data_in_mprj[109] |la_data_in_mprj[109]
la_data_in_mprj[113] |la_data_in_mprj[113]
la_data_in_mprj[112] |la_data_in_mprj[112]
la_data_in_mprj[52] |la_data_in_mprj[52]
la_data_in_mprj[53] |la_data_in_mprj[53]
la_data_in_mprj[54] |la_data_in_mprj[54]
la_data_in_mprj[61] |la_data_in_mprj[61]
la_data_in_mprj[80] |la_data_in_mprj[80]
la_data_in_mprj[81] |la_data_in_mprj[81]
la_data_in_mprj[86] |la_data_in_mprj[86]
la_data_in_mprj[11] |la_data_in_mprj[11]
la_data_in_mprj[55] |la_data_in_mprj[55]
la_data_in_mprj[56] |la_data_in_mprj[56]
la_data_in_mprj[9] |la_data_in_mprj[9]
la_oenb_core[30] |la_oenb_core[30]
la_oenb_core[69] |la_oenb_core[69]
la_oenb_core[65] |la_oenb_core[65]
la_oenb_core[70] |la_oenb_core[70]
la_oenb_core[67] |la_oenb_core[67]
la_oenb_core[66] |la_oenb_core[66]
la_data_out_core[28] |la_data_out_core[28]
la_data_out_core[29] |la_data_out_core[29]
la_data_out_core[27] |la_data_out_core[27]
la_data_out_core[127] |la_data_out_core[127]
la_data_out_core[31] |la_data_out_core[31]
la_data_out_core[43] |la_data_out_core[43]
la_data_out_core[42] |la_data_out_core[42]
la_data_out_core[38] |la_data_out_core[38]
la_data_out_core[22] |la_data_out_core[22]
la_data_out_core[24] |la_data_out_core[24]
la_data_out_core[4] |la_data_out_core[4]
la_data_out_core[23] |la_data_out_core[23]
la_data_out_core[58] |la_data_out_core[58]
la_data_out_core[59] |la_data_out_core[59]
la_data_out_core[60] |la_data_out_core[60]
la_data_out_core[36] |la_data_out_core[36]
la_data_out_core[37] |la_data_out_core[37]
la_data_out_core[26] |la_data_out_core[26]
user_irq_core[0] |user_irq_core[0]
la_data_out_core[25] |la_data_out_core[25]
la_data_out_core[126] |la_data_out_core[126]
la_data_out_core[61] |la_data_out_core[61]
la_data_out_core[21] |la_data_out_core[21]
user_irq_core[2] |user_irq_core[2]
user_irq_core[1] |user_irq_core[1]
la_data_out_core[6] |la_data_out_core[6]
la_data_out_core[10] |la_data_out_core[10]
la_data_out_core[0] |la_data_out_core[0]
la_data_out_core[5] |la_data_out_core[5]
la_data_out_core[1] |la_data_out_core[1]
la_data_out_core[2] |la_data_out_core[2]
la_data_out_core[3] |la_data_out_core[3]
la_data_out_core[13] |la_data_out_core[13]
la_data_out_core[15] |la_data_out_core[15]
la_data_out_core[44] |la_data_out_core[44]
la_data_out_core[52] |la_data_out_core[52]
la_data_out_core[53] |la_data_out_core[53]
la_data_out_core[17] |la_data_out_core[17]
la_data_out_core[125] |la_data_out_core[125]
la_data_out_core[19] |la_data_out_core[19]
la_data_out_core[20] |la_data_out_core[20]
la_data_out_core[67] |la_data_out_core[67]
la_data_out_core[46] |la_data_out_core[46]
la_data_out_core[50] |la_data_out_core[50]
la_data_out_core[64] |la_data_out_core[64]
la_data_out_core[66] |la_data_out_core[66]
la_data_out_core[30] |la_data_out_core[30]
la_data_out_core[45] |la_data_out_core[45]
la_data_out_core[68] |la_data_out_core[68]
la_data_out_core[70] |la_data_out_core[70]
la_data_out_core[69] |la_data_out_core[69]
la_data_out_core[18] |la_data_out_core[18]
la_data_out_core[49] |la_data_out_core[49]
la_data_out_core[16] |la_data_out_core[16]
la_data_out_core[51] |la_data_out_core[51]
la_data_out_core[62] |la_data_out_core[62]
la_data_out_core[63] |la_data_out_core[63]
la_data_out_core[65] |la_data_out_core[65]
la_data_out_core[57] |la_data_out_core[57]
la_data_out_core[12] |la_data_out_core[12]
la_data_out_core[7] |la_data_out_core[7]
la_data_out_core[121] |la_data_out_core[121]
la_data_out_core[122] |la_data_out_core[122]
la_data_out_core[123] |la_data_out_core[123]
la_data_out_core[97] |la_data_out_core[97]
la_data_out_core[77] |la_data_out_core[77]
la_data_out_core[95] |la_data_out_core[95]
la_data_out_core[91] |la_data_out_core[91]
la_data_out_core[92] |la_data_out_core[92]
la_data_out_core[120] |la_data_out_core[120]
la_data_out_core[35] |la_data_out_core[35]
la_data_out_core[88] |la_data_out_core[88]
la_data_out_core[99] |la_data_out_core[99]
la_data_out_core[98] |la_data_out_core[98]
la_data_out_core[9] |la_data_out_core[9]
la_data_out_core[11] |la_data_out_core[11]
la_data_out_core[39] |la_data_out_core[39]
la_data_out_core[78] |la_data_out_core[78]
la_data_out_core[55] |la_data_out_core[55]
la_data_out_core[56] |la_data_out_core[56]
mprj_dat_i_user[12] |mprj_dat_i_user[12]
mprj_dat_i_user[13] |mprj_dat_i_user[13]
mprj_dat_i_user[14] |mprj_dat_i_user[14]
la_data_out_core[105] |la_data_out_core[105]
mprj_dat_i_user[23] |mprj_dat_i_user[23]
la_data_out_core[114] |la_data_out_core[114]
la_data_out_core[118] |la_data_out_core[118]
la_data_out_core[119] |la_data_out_core[119]
la_data_out_core[106] |la_data_out_core[106]
la_data_out_core[96] |la_data_out_core[96]
la_data_out_core[117] |la_data_out_core[117]
la_data_out_core[115] |la_data_out_core[115]
la_data_out_core[116] |la_data_out_core[116]
la_data_out_core[89] |la_data_out_core[89]
la_data_out_core[90] |la_data_out_core[90]
la_data_out_core[113] |la_data_out_core[113]
la_data_out_core[112] |la_data_out_core[112]
la_data_out_core[103] |la_data_out_core[103]
la_data_out_core[104] |la_data_out_core[104]
la_data_out_core[110] |la_data_out_core[110]
la_data_out_core[109] |la_data_out_core[109]
la_data_out_core[111] |la_data_out_core[111]
la_data_out_core[84] |la_data_out_core[84]
la_data_out_core[83] |la_data_out_core[83]
la_data_out_core[82] |la_data_out_core[82]
la_data_out_core[85] |la_data_out_core[85]
la_data_out_core[86] |la_data_out_core[86]
la_data_out_core[81] |la_data_out_core[81]
la_data_out_core[107] |la_data_out_core[107]
la_data_out_core[100] |la_data_out_core[100]
la_data_out_core[76] |la_data_out_core[76]
la_data_out_core[41] |la_data_out_core[41]
la_data_out_core[93] |la_data_out_core[93]
la_data_out_core[40] |la_data_out_core[40]
la_data_out_core[54] |la_data_out_core[54]
la_data_out_core[79] |la_data_out_core[79]
la_data_out_core[80] |la_data_out_core[80]
la_data_out_core[87] |la_data_out_core[87]
mprj_dat_i_user[24] |mprj_dat_i_user[24]
la_data_out_core[14] |la_data_out_core[14]
la_data_out_core[124] |la_data_out_core[124]
la_data_out_core[101] |la_data_out_core[101]
la_data_out_core[94] |la_data_out_core[94]
la_data_out_core[108] |la_data_out_core[108]
la_data_out_core[8] |la_data_out_core[8]
la_data_out_core[32] |la_data_out_core[32]
la_data_out_core[102] |la_data_out_core[102]
la_data_out_core[71] |la_data_out_core[71]
la_data_out_core[72] |la_data_out_core[72]
la_data_out_core[73] |la_data_out_core[73]
la_data_out_core[74] |la_data_out_core[74]
la_data_out_core[33] |la_data_out_core[33]
la_data_out_core[47] |la_data_out_core[47]
la_data_out_core[48] |la_data_out_core[48]
la_data_out_core[75] |la_data_out_core[75]
la_data_out_core[34] |la_data_out_core[34]
mprj_dat_i_user[22] |mprj_dat_i_user[22]
mprj_dat_i_user[25] |mprj_dat_i_user[25]
mprj_dat_i_user[26] |mprj_dat_i_user[26]
mprj_dat_i_user[18] |mprj_dat_i_user[18]
mprj_dat_i_user[19] |mprj_dat_i_user[19]
mprj_dat_i_user[2] |mprj_dat_i_user[2]
mprj_dat_i_user[28] |mprj_dat_i_user[28]
mprj_dat_i_user[29] |mprj_dat_i_user[29]
mprj_dat_i_user[30] |mprj_dat_i_user[30]
mprj_dat_i_user[31] |mprj_dat_i_user[31]
mprj_dat_i_user[3] |mprj_dat_i_user[3]
mprj_dat_i_user[27] |mprj_dat_i_user[27]
mprj_dat_i_user[5] |mprj_dat_i_user[5]
mprj_dat_i_user[4] |mprj_dat_i_user[4]
mprj_dat_i_user[6] |mprj_dat_i_user[6]
mprj_dat_i_user[11] |mprj_dat_i_user[11]
mprj_dat_i_user[7] |mprj_dat_i_user[7]
mprj_dat_i_user[15] |mprj_dat_i_user[15]
mprj_dat_i_user[16] |mprj_dat_i_user[16]
mprj_dat_i_user[17] |mprj_dat_i_user[17]
mprj_dat_i_user[20] |mprj_dat_i_user[20]
mprj_dat_i_user[21] |mprj_dat_i_user[21]
mprj_dat_i_user[8] |mprj_dat_i_user[8]
mprj_dat_i_user[10] |mprj_dat_i_user[10]
mprj_dat_i_user[9] |mprj_dat_i_user[9]
mprj_dat_i_user[0] |mprj_ack_i_user **Mismatch**
mprj_ack_i_user |mprj_dat_i_user[0] **Mismatch**
mprj_dat_i_user[1] |mprj_dat_i_user[1]
la_oenb_mprj[46] |la_oenb_mprj[46]
la_oenb_mprj[48] |la_oenb_mprj[48]
la_oenb_mprj[54] |la_oenb_mprj[54]
la_oenb_mprj[107] |la_oenb_mprj[107]
la_oenb_mprj[7] |la_oenb_mprj[7]
la_oenb_mprj[15] |la_oenb_mprj[15]
la_oenb_mprj[12] |la_oenb_mprj[12]
la_oenb_mprj[103] |la_oenb_mprj[103]
la_oenb_mprj[102] |la_oenb_mprj[102]
la_oenb_mprj[109] |la_oenb_mprj[109]
la_oenb_mprj[110] |la_oenb_mprj[110]
la_oenb_mprj[111] |la_oenb_mprj[111]
la_oenb_mprj[27] |la_oenb_mprj[27]
la_oenb_mprj[106] |la_oenb_mprj[106]
la_oenb_mprj[108] |la_oenb_mprj[108]
la_oenb_mprj[126] |la_oenb_mprj[126]
la_oenb_mprj[38] |la_oenb_mprj[38]
la_oenb_mprj[17] |la_oenb_mprj[17]
la_oenb_mprj[127] |la_oenb_mprj[127]
la_oenb_mprj[90] |la_oenb_mprj[90]
la_oenb_mprj[125] |la_oenb_mprj[125]
la_oenb_mprj[33] |la_oenb_mprj[33]
la_oenb_mprj[19] |la_oenb_mprj[19]
la_oenb_mprj[20] |la_oenb_mprj[20]
la_oenb_mprj[42] |la_oenb_mprj[42]
la_oenb_mprj[60] |la_oenb_mprj[60]
la_oenb_mprj[61] |la_oenb_mprj[61]
la_oenb_mprj[45] |la_oenb_mprj[45]
la_oenb_mprj[14] |la_oenb_mprj[14]
la_oenb_mprj[0] |la_oenb_mprj[0]
la_oenb_mprj[3] |la_oenb_mprj[3]
la_oenb_mprj[5] |la_oenb_mprj[5]
la_oenb_mprj[89] |la_oenb_mprj[89]
la_oenb_mprj[24] |la_oenb_mprj[24]
la_oenb_mprj[22] |la_oenb_mprj[22]
la_oenb_mprj[21] |la_oenb_mprj[21]
la_oenb_mprj[57] |la_oenb_mprj[57]
la_oenb_mprj[8] |la_oenb_mprj[8]
la_oenb_mprj[47] |la_oenb_mprj[47]
la_oenb_mprj[78] |la_oenb_mprj[78]
la_oenb_mprj[59] |la_oenb_mprj[59]
la_oenb_mprj[94] |la_oenb_mprj[94]
la_oenb_mprj[95] |la_oenb_mprj[95]
la_oenb_mprj[40] |la_oenb_mprj[40]
la_oenb_mprj[43] |la_oenb_mprj[43]
la_oenb_mprj[36] |la_oenb_mprj[36]
la_oenb_mprj[37] |la_oenb_mprj[37]
la_oenb_mprj[92] |la_oenb_mprj[92]
la_oenb_mprj[93] |la_oenb_mprj[93]
la_oenb_mprj[31] |la_oenb_mprj[31]
la_oenb_mprj[122] |la_oenb_mprj[122]
la_oenb_mprj[11] |la_oenb_mprj[11]
la_oenb_mprj[50] |la_oenb_mprj[50]
la_oenb_mprj[9] |la_oenb_mprj[9]
la_oenb_mprj[10] |la_oenb_mprj[10]
la_oenb_mprj[16] |la_oenb_mprj[16]
la_oenb_mprj[101] |la_oenb_mprj[101]
la_oenb_mprj[104] |la_oenb_mprj[104]
la_oenb_mprj[105] |la_oenb_mprj[105]
la_oenb_mprj[123] |la_oenb_mprj[123]
la_oenb_mprj[124] |la_oenb_mprj[124]
la_oenb_mprj[26] |la_oenb_mprj[26]
la_oenb_mprj[55] |la_oenb_mprj[55]
la_oenb_mprj[25] |la_oenb_mprj[25]
la_oenb_mprj[44] |la_oenb_mprj[44]
la_oenb_mprj[49] |la_oenb_mprj[49]
la_oenb_mprj[53] |la_oenb_mprj[53]
la_oenb_mprj[56] |la_oenb_mprj[56]
la_oenb_mprj[52] |la_oenb_mprj[52]
la_oenb_mprj[28] |la_oenb_mprj[28]
la_oenb_mprj[34] |la_oenb_mprj[34]
la_oenb_mprj[1] |la_oenb_mprj[1]
la_oenb_mprj[2] |la_oenb_mprj[2]
la_oenb_mprj[23] |la_oenb_mprj[23]
la_oenb_mprj[18] |la_oenb_mprj[18]
la_oenb_mprj[6] |la_oenb_mprj[6]
la_oenb_mprj[91] |la_oenb_mprj[91]
la_oenb_mprj[41] |la_oenb_mprj[41]
la_iena_mprj[126] |la_iena_mprj[126]
la_data_out_mprj[52] |la_data_out_mprj[52]
la_data_out_mprj[53] |la_data_out_mprj[53]
la_data_out_mprj[54] |la_data_out_mprj[54]
la_data_out_mprj[55] |la_data_out_mprj[55]
la_data_out_mprj[56] |la_data_out_mprj[56]
la_data_out_mprj[110] |la_data_out_mprj[110]
la_data_out_mprj[111] |la_data_out_mprj[111]
la_data_out_mprj[120] |la_data_out_mprj[120]
la_data_out_mprj[119] |la_data_out_mprj[119]
la_data_out_mprj[121] |la_data_out_mprj[121]
la_data_out_mprj[79] |la_data_out_mprj[79]
la_data_out_mprj[77] |la_data_out_mprj[77]
la_data_out_mprj[76] |la_data_out_mprj[76]
la_data_out_mprj[75] |la_data_out_mprj[75]
la_data_out_mprj[74] |la_data_out_mprj[74]
la_data_out_mprj[72] |la_data_out_mprj[72]
la_iena_mprj[120] |la_iena_mprj[120]
la_iena_mprj[21] |la_iena_mprj[21]
la_iena_mprj[29] |la_iena_mprj[29]
la_iena_mprj[27] |la_iena_mprj[27]
la_iena_mprj[127] |la_iena_mprj[127]
la_iena_mprj[19] |la_iena_mprj[19]
la_iena_mprj[20] |la_iena_mprj[20]
la_iena_mprj[125] |la_iena_mprj[125]
la_iena_mprj[45] |la_iena_mprj[45]
la_iena_mprj[64] |la_iena_mprj[64]
la_iena_mprj[66] |la_iena_mprj[66]
la_iena_mprj[67] |la_iena_mprj[67]
la_iena_mprj[46] |la_iena_mprj[46]
la_iena_mprj[70] |la_iena_mprj[70]
la_iena_mprj[69] |la_iena_mprj[69]
la_iena_mprj[68] |la_iena_mprj[68]
la_iena_mprj[18] |la_iena_mprj[18]
la_iena_mprj[44] |la_iena_mprj[44]
la_iena_mprj[49] |la_iena_mprj[49]
la_data_out_mprj[58] |la_data_out_mprj[58]
la_iena_mprj[101] |la_iena_mprj[101]
la_iena_mprj[119] |la_iena_mprj[119]
la_iena_mprj[121] |la_iena_mprj[121]
la_iena_mprj[122] |la_iena_mprj[122]
la_iena_mprj[123] |la_iena_mprj[123]
la_iena_mprj[47] |la_iena_mprj[47]
mprj_sel_o_core[3] |mprj_sel_o_core[3]
la_oenb_mprj[30] |la_oenb_mprj[30]
la_oenb_mprj[32] |la_oenb_mprj[32]
la_oenb_mprj[35] |la_oenb_mprj[35]
la_oenb_mprj[51] |la_oenb_mprj[51]
la_oenb_mprj[58] |la_oenb_mprj[58]
la_oenb_mprj[100] |la_oenb_mprj[100]
la_oenb_mprj[29] |la_oenb_mprj[29]
la_oenb_mprj[62] |la_oenb_mprj[62]
la_oenb_mprj[66] |la_oenb_mprj[66]
la_oenb_mprj[67] |la_oenb_mprj[67]
la_oenb_mprj[70] |la_oenb_mprj[70]
la_oenb_mprj[117] |la_oenb_mprj[117]
la_oenb_mprj[63] |la_oenb_mprj[63]
la_oenb_mprj[97] |la_oenb_mprj[97]
la_oenb_mprj[98] |la_oenb_mprj[98]
la_oenb_mprj[112] |la_oenb_mprj[112]
la_oenb_mprj[120] |la_oenb_mprj[120]
la_oenb_mprj[119] |la_oenb_mprj[119]
la_oenb_mprj[121] |la_oenb_mprj[121]
la_oenb_mprj[113] |la_oenb_mprj[113]
la_oenb_mprj[114] |la_oenb_mprj[114]
la_oenb_mprj[115] |la_oenb_mprj[115]
la_oenb_mprj[118] |la_oenb_mprj[118]
la_oenb_mprj[64] |la_oenb_mprj[64]
la_oenb_mprj[71] |la_oenb_mprj[71]
la_oenb_mprj[96] |la_oenb_mprj[96]
la_oenb_mprj[99] |la_oenb_mprj[99]
la_oenb_mprj[73] |la_oenb_mprj[73]
la_oenb_mprj[80] |la_oenb_mprj[80]
la_oenb_mprj[81] |la_oenb_mprj[81]
la_oenb_mprj[72] |la_oenb_mprj[72]
la_oenb_mprj[74] |la_oenb_mprj[74]
la_oenb_mprj[75] |la_oenb_mprj[75]
la_oenb_mprj[76] |la_oenb_mprj[76]
la_oenb_mprj[77] |la_oenb_mprj[77]
la_oenb_mprj[79] |la_oenb_mprj[79]
la_data_out_mprj[65] |la_data_out_mprj[65]
la_data_out_mprj[66] |la_data_out_mprj[66]
la_data_out_mprj[67] |la_data_out_mprj[67]
la_data_out_mprj[70] |la_data_out_mprj[70]
la_data_out_mprj[81] |la_data_out_mprj[81]
la_data_out_mprj[80] |la_data_out_mprj[80]
la_data_out_mprj[113] |la_data_out_mprj[113]
la_data_out_mprj[114] |la_data_out_mprj[114]
la_data_out_mprj[115] |la_data_out_mprj[115]
la_data_out_mprj[118] |la_data_out_mprj[118]
la_data_out_mprj[63] |la_data_out_mprj[63]
la_data_out_mprj[64] |la_data_out_mprj[64]
la_data_out_mprj[71] |la_data_out_mprj[71]
la_iena_mprj[28] |la_iena_mprj[28]
mprj_dat_o_core[29] |mprj_dat_o_core[29]
mprj_dat_o_core[30] |mprj_dat_o_core[30]
caravel_rstn |caravel_rstn
mprj_adr_o_core[22] |mprj_adr_o_core[22]
mprj_adr_o_core[0] |mprj_adr_o_core[0]
mprj_adr_o_core[31] |mprj_adr_o_core[31]
mprj_adr_o_core[9] |mprj_adr_o_core[9]
mprj_adr_o_core[6] |mprj_adr_o_core[6]
mprj_iena_wb |mprj_iena_wb
mprj_dat_o_core[10] |mprj_dat_o_core[10]
mprj_dat_o_core[11] |mprj_dat_o_core[11]
mprj_dat_o_core[12] |mprj_dat_o_core[12]
mprj_dat_o_core[14] |mprj_dat_o_core[14]
mprj_dat_o_core[13] |mprj_dat_o_core[13]
mprj_dat_o_core[16] |mprj_dat_o_core[16]
mprj_dat_o_core[15] |mprj_dat_o_core[15]
mprj_dat_o_core[17] |mprj_dat_o_core[17]
mprj_dat_o_core[8] |mprj_dat_o_core[8]
mprj_dat_o_core[9] |mprj_dat_o_core[9]
mprj_stb_o_core |mprj_stb_o_core
la_oenb_mprj[68] |la_oenb_mprj[68]
la_oenb_mprj[69] |la_oenb_mprj[69]
la_oenb_mprj[65] |la_oenb_mprj[65]
la_oenb_mprj[84] |la_oenb_mprj[84]
la_oenb_mprj[88] |la_oenb_mprj[88]
la_oenb_mprj[116] |la_oenb_mprj[116]
la_oenb_mprj[86] |la_oenb_mprj[86]
la_oenb_mprj[85] |la_oenb_mprj[85]
la_oenb_mprj[87] |la_oenb_mprj[87]
la_oenb_mprj[83] |la_oenb_mprj[83]
la_oenb_mprj[82] |la_oenb_mprj[82]
la_data_out_mprj[68] |la_data_out_mprj[68]
la_data_out_mprj[69] |la_data_out_mprj[69]
la_data_out_mprj[83] |la_data_out_mprj[83]
la_data_out_mprj[84] |la_data_out_mprj[84]
la_data_out_mprj[116] |la_data_out_mprj[116]
la_data_out_mprj[85] |la_data_out_mprj[85]
la_data_out_mprj[86] |la_data_out_mprj[86]
la_data_out_mprj[87] |la_data_out_mprj[87]
la_data_out_mprj[88] |la_data_out_mprj[88]
la_data_out_mprj[82] |la_data_out_mprj[82]
la_data_out_mprj[117] |la_data_out_mprj[117]
mprj_dat_o_core[23] |mprj_dat_o_core[23]
mprj_dat_o_core[24] |mprj_dat_o_core[24]
mprj_dat_o_core[28] |mprj_dat_o_core[28]
mprj_dat_o_core[25] |mprj_dat_o_core[25]
mprj_dat_o_core[27] |mprj_dat_o_core[27]
mprj_dat_o_core[26] |mprj_dat_o_core[26]
mprj_dat_o_core[31] |mprj_dat_o_core[31]
mprj_adr_o_core[13] |mprj_adr_o_core[13]
mprj_dat_o_core[2] |mprj_dat_o_core[2]
mprj_adr_o_core[11] |mprj_adr_o_core[11]
mprj_dat_o_core[3] |mprj_dat_o_core[3]
mprj_dat_o_core[6] |mprj_dat_o_core[6]
mprj_dat_o_core[7] |mprj_dat_o_core[7]
mprj_adr_o_core[10] |mprj_adr_o_core[10]
mprj_dat_o_core[4] |mprj_dat_o_core[4]
mprj_dat_o_core[5] |mprj_dat_o_core[5]
mprj_adr_o_core[14] |mprj_adr_o_core[14]
mprj_adr_o_core[17] |mprj_adr_o_core[17]
mprj_adr_o_core[12] |mprj_adr_o_core[12]
mprj_adr_o_core[20] |mprj_adr_o_core[20]
mprj_adr_o_core[23] |mprj_adr_o_core[23]
mprj_adr_o_core[19] |mprj_adr_o_core[19]
mprj_adr_o_core[18] |mprj_adr_o_core[18]
mprj_adr_o_core[16] |mprj_adr_o_core[16]
mprj_adr_o_core[7] |mprj_adr_o_core[7]
mprj_cyc_o_core |mprj_cyc_o_core
mprj_adr_o_core[1] |mprj_adr_o_core[1]
mprj_adr_o_core[2] |mprj_adr_o_core[2]
mprj_adr_o_core[3] |mprj_adr_o_core[3]
mprj_adr_o_core[4] |mprj_adr_o_core[4]
mprj_adr_o_core[5] |mprj_adr_o_core[5]
mprj_adr_o_core[15] |mprj_adr_o_core[15]
mprj_adr_o_core[21] |mprj_adr_o_core[21]
mprj_adr_o_core[8] |mprj_adr_o_core[8]
mprj_adr_o_core[24] |mprj_adr_o_core[24]
mprj_adr_o_core[25] |mprj_adr_o_core[25]
mprj_adr_o_core[26] |mprj_adr_o_core[26]
mprj_adr_o_core[27] |mprj_adr_o_core[27]
mprj_adr_o_core[28] |mprj_adr_o_core[28]
mprj_adr_o_core[29] |mprj_adr_o_core[29]
mprj_adr_o_core[30] |mprj_adr_o_core[30]
mprj_dat_o_core[0] |mprj_dat_o_core[0]
mprj_dat_o_core[1] |mprj_dat_o_core[1]
mprj_dat_o_core[18] |mprj_dat_o_core[18]
mprj_dat_o_core[19] |mprj_dat_o_core[19]
mprj_dat_o_core[20] |mprj_dat_o_core[20]
mprj_dat_o_core[21] |mprj_dat_o_core[21]
mprj_dat_o_core[22] |mprj_dat_o_core[22]
mprj_we_o_core |mprj_we_o_core
la_data_out_mprj[39] |la_data_out_mprj[39]
la_data_out_mprj[13] |la_data_out_mprj[13]
la_data_out_mprj[4] |la_data_out_mprj[4]
la_iena_mprj[35] |la_iena_mprj[35]
la_iena_mprj[54] |la_iena_mprj[54]
la_iena_mprj[55] |la_iena_mprj[55]
la_iena_mprj[56] |la_iena_mprj[56]
la_iena_mprj[57] |la_iena_mprj[57]
la_iena_mprj[77] |la_iena_mprj[77]
la_iena_mprj[90] |la_iena_mprj[90]
la_iena_mprj[93] |la_iena_mprj[93]
la_data_out_mprj[51] |la_data_out_mprj[51]
la_iena_mprj[4] |la_iena_mprj[4]
la_iena_mprj[1] |la_iena_mprj[1]
la_iena_mprj[2] |la_iena_mprj[2]
la_iena_mprj[3] |la_iena_mprj[3]
user_irq_ena[1] |user_irq_ena[1]
la_iena_mprj[10] |la_iena_mprj[10]
la_iena_mprj[0] |la_iena_mprj[0]
la_iena_mprj[5] |la_iena_mprj[5]
la_data_out_mprj[102] |la_data_out_mprj[102]
la_data_out_mprj[103] |la_data_out_mprj[103]
la_data_out_mprj[11] |la_data_out_mprj[11]
la_data_out_mprj[126] |la_data_out_mprj[126]
la_data_out_mprj[127] |la_data_out_mprj[127]
la_data_out_mprj[17] |la_data_out_mprj[17]
la_data_out_mprj[19] |la_data_out_mprj[19]
la_data_out_mprj[20] |la_data_out_mprj[20]
la_data_out_mprj[41] |la_data_out_mprj[41]
la_data_out_mprj[42] |la_data_out_mprj[42]
la_data_out_mprj[50] |la_data_out_mprj[50]
la_data_out_mprj[60] |la_data_out_mprj[60]
la_data_out_mprj[90] |la_data_out_mprj[90]
la_data_out_mprj[91] |la_data_out_mprj[91]
la_data_out_mprj[92] |la_data_out_mprj[92]
la_data_out_mprj[93] |la_data_out_mprj[93]
la_iena_mprj[13] |la_iena_mprj[13]
la_iena_mprj[36] |la_iena_mprj[36]
la_iena_mprj[37] |la_iena_mprj[37]
la_iena_mprj[38] |la_iena_mprj[38]
la_iena_mprj[58] |la_iena_mprj[58]
la_iena_mprj[59] |la_iena_mprj[59]
la_iena_mprj[60] |la_iena_mprj[60]
la_iena_mprj[6] |la_iena_mprj[6]
la_iena_mprj[96] |la_iena_mprj[96]
la_data_out_mprj[112] |la_data_out_mprj[112]
caravel_clk |caravel_clk
caravel_clk2 |caravel_clk2
la_iena_mprj[117] |la_iena_mprj[117]
la_iena_mprj[115] |la_iena_mprj[115]
la_iena_mprj[116] |la_iena_mprj[116]
la_iena_mprj[111] |la_iena_mprj[111]
la_iena_mprj[110] |la_iena_mprj[110]
la_iena_mprj[109] |la_iena_mprj[109]
la_iena_mprj[34] |la_iena_mprj[34]
la_iena_mprj[39] |la_iena_mprj[39]
la_iena_mprj[40] |la_iena_mprj[40]
la_iena_mprj[41] |la_iena_mprj[41]
la_iena_mprj[42] |la_iena_mprj[42]
la_iena_mprj[78] |la_iena_mprj[78]
la_iena_mprj[7] |la_iena_mprj[7]
la_iena_mprj[81] |la_iena_mprj[81]
la_iena_mprj[82] |la_iena_mprj[82]
la_iena_mprj[83] |la_iena_mprj[83]
la_iena_mprj[84] |la_iena_mprj[84]
la_iena_mprj[85] |la_iena_mprj[85]
la_iena_mprj[86] |la_iena_mprj[86]
la_iena_mprj[89] |la_iena_mprj[89]
la_iena_mprj[108] |la_iena_mprj[108]
la_iena_mprj[8] |la_iena_mprj[8]
la_iena_mprj[88] |la_iena_mprj[88]
la_iena_mprj[87] |la_iena_mprj[87]
la_iena_mprj[92] |la_iena_mprj[92]
la_iena_mprj[91] |la_iena_mprj[91]
la_iena_mprj[95] |la_iena_mprj[95]
la_iena_mprj[9] |la_iena_mprj[9]
la_data_out_mprj[32] |la_data_out_mprj[32]
la_iena_mprj[79] |la_iena_mprj[79]
la_iena_mprj[80] |la_iena_mprj[80]
la_data_out_mprj[36] |la_data_out_mprj[36]
la_data_out_mprj[37] |la_data_out_mprj[37]
la_data_out_mprj[38] |la_data_out_mprj[38]
la_data_out_mprj[57] |la_data_out_mprj[57]
la_oenb_mprj[39] |la_oenb_mprj[39]
la_oenb_mprj[4] |la_oenb_mprj[4]
la_oenb_mprj[13] |la_oenb_mprj[13]
la_iena_mprj[15] |la_iena_mprj[15]
la_data_out_mprj[35] |la_data_out_mprj[35]
la_iena_mprj[118] |la_iena_mprj[118]
la_iena_mprj[107] |la_iena_mprj[107]
la_iena_mprj[113] |la_iena_mprj[113]
la_iena_mprj[103] |la_iena_mprj[103]
la_iena_mprj[104] |la_iena_mprj[104]
la_iena_mprj[112] |la_iena_mprj[112]
la_iena_mprj[114] |la_iena_mprj[114]
la_iena_mprj[100] |la_iena_mprj[100]
la_iena_mprj[31] |la_iena_mprj[31]
la_iena_mprj[43] |la_iena_mprj[43]
la_iena_mprj[48] |la_iena_mprj[48]
la_iena_mprj[71] |la_iena_mprj[71]
la_iena_mprj[72] |la_iena_mprj[72]
la_iena_mprj[73] |la_iena_mprj[73]
la_iena_mprj[74] |la_iena_mprj[74]
la_iena_mprj[75] |la_iena_mprj[75]
la_iena_mprj[76] |la_iena_mprj[76]
la_iena_mprj[94] |la_iena_mprj[94]
la_iena_mprj[124] |la_iena_mprj[124]
la_iena_mprj[102] |la_iena_mprj[102]
la_iena_mprj[32] |la_iena_mprj[32]
la_iena_mprj[14] |la_iena_mprj[14]
la_iena_mprj[33] |la_iena_mprj[33]
la_iena_mprj[12] |la_iena_mprj[12]
la_iena_mprj[97] |la_iena_mprj[97]
la_iena_mprj[98] |la_iena_mprj[98]
la_iena_mprj[11] |la_iena_mprj[11]
la_iena_mprj[99] |la_iena_mprj[99]
mprj_sel_o_core[0] |mprj_sel_o_core[0]
mprj_sel_o_core[1] |mprj_sel_o_core[1]
la_iena_mprj[61] |la_iena_mprj[61]
user_irq_ena[0] |user_irq_ena[0]
la_iena_mprj[26] |la_iena_mprj[26]
la_iena_mprj[25] |la_iena_mprj[25]
la_iena_mprj[23] |la_iena_mprj[23]
user_irq_ena[2] |user_irq_ena[2]
la_data_out_mprj[109] |la_data_out_mprj[109]
la_data_out_mprj[12] |la_data_out_mprj[12]
la_data_out_mprj[25] |la_data_out_mprj[25]
la_data_out_mprj[27] |la_data_out_mprj[27]
la_data_out_mprj[28] |la_data_out_mprj[28]
la_data_out_mprj[34] |la_data_out_mprj[34]
la_data_out_mprj[40] |la_data_out_mprj[40]
la_data_out_mprj[43] |la_data_out_mprj[43]
la_data_out_mprj[44] |la_data_out_mprj[44]
la_data_out_mprj[45] |la_data_out_mprj[45]
la_data_out_mprj[46] |la_data_out_mprj[46]
la_data_out_mprj[47] |la_data_out_mprj[47]
la_data_out_mprj[48] |la_data_out_mprj[48]
la_data_out_mprj[49] |la_data_out_mprj[49]
la_data_out_mprj[59] |la_data_out_mprj[59]
la_data_out_mprj[61] |la_data_out_mprj[61]
la_data_out_mprj[23] |la_data_out_mprj[23]
la_data_out_mprj[18] |la_data_out_mprj[18]
la_data_out_mprj[1] |la_data_out_mprj[1]
la_data_out_mprj[2] |la_data_out_mprj[2]
la_data_out_mprj[6] |la_data_out_mprj[6]
la_data_out_mprj[73] |la_data_out_mprj[73]
la_data_out_mprj[78] |la_data_out_mprj[78]
la_data_out_mprj[15] |la_data_out_mprj[15]
la_data_out_mprj[7] |la_data_out_mprj[7]
la_data_out_mprj[21] |la_data_out_mprj[21]
la_data_out_mprj[89] |la_data_out_mprj[89]
la_data_out_mprj[0] |la_data_out_mprj[0]
la_data_out_mprj[14] |la_data_out_mprj[14]
la_data_out_mprj[3] |la_data_out_mprj[3]
la_data_out_mprj[5] |la_data_out_mprj[5]
la_data_out_mprj[22] |la_data_out_mprj[22]
la_data_out_mprj[24] |la_data_out_mprj[24]
la_data_out_mprj[8] |la_data_out_mprj[8]
la_data_out_mprj[95] |la_data_out_mprj[95]
la_data_out_mprj[94] |la_data_out_mprj[94]
la_data_out_mprj[98] |la_data_out_mprj[98]
la_data_out_mprj[97] |la_data_out_mprj[97]
la_data_out_mprj[10] |la_data_out_mprj[10]
la_data_out_mprj[16] |la_data_out_mprj[16]
la_data_out_mprj[9] |la_data_out_mprj[9]
la_iena_mprj[105] |la_iena_mprj[105]
la_iena_mprj[106] |la_iena_mprj[106]
la_iena_mprj[22] |la_iena_mprj[22]
la_iena_mprj[24] |la_iena_mprj[24]
la_iena_mprj[30] |la_iena_mprj[30]
la_iena_mprj[17] |la_iena_mprj[17]
la_iena_mprj[16] |la_iena_mprj[16]
la_iena_mprj[50] |la_iena_mprj[50]
la_iena_mprj[51] |la_iena_mprj[51]
la_iena_mprj[52] |la_iena_mprj[52]
la_iena_mprj[53] |la_iena_mprj[53]
la_iena_mprj[62] |la_iena_mprj[62]
la_iena_mprj[63] |la_iena_mprj[63]
la_iena_mprj[65] |la_iena_mprj[65]
mprj_sel_o_core[2] |mprj_sel_o_core[2]
la_data_out_mprj[100] |la_data_out_mprj[100]
la_data_out_mprj[107] |la_data_out_mprj[107]
la_data_out_mprj[125] |la_data_out_mprj[125]
la_data_out_mprj[26] |la_data_out_mprj[26]
la_data_out_mprj[101] |la_data_out_mprj[101]
la_data_out_mprj[104] |la_data_out_mprj[104]
la_data_out_mprj[105] |la_data_out_mprj[105]
la_data_out_mprj[123] |la_data_out_mprj[123]
la_data_out_mprj[124] |la_data_out_mprj[124]
la_data_out_mprj[29] |la_data_out_mprj[29]
la_data_out_mprj[30] |la_data_out_mprj[30]
la_data_out_mprj[31] |la_data_out_mprj[31]
la_data_out_mprj[33] |la_data_out_mprj[33]
la_data_out_mprj[62] |la_data_out_mprj[62]
la_data_out_mprj[106] |la_data_out_mprj[106]
la_data_out_mprj[108] |la_data_out_mprj[108]
la_data_out_mprj[122] |la_data_out_mprj[122]
la_data_out_mprj[99] |la_data_out_mprj[99]
la_data_out_mprj[96] |la_data_out_mprj[96]
vssd |vssd
vccd |vccd
---------------------------------------------------------------------------------------
Cell pin lists for mgmt_protect and mgmt_protect altered to match.
Device classes mgmt_protect and mgmt_protect are equivalent.
Cell xres_buf (0) disconnected node: LVGND
Cell xres_buf (1) disconnected node: LVGND
Class xres_buf (0): Merged 5 parallel devices.
Class xres_buf (1): Merged 5 parallel devices.
Cell xres_buf (0) disconnected node: LVGND
Cell xres_buf (1) disconnected node: LVGND
Subcircuit summary:
Circuit 1: xres_buf |Circuit 2: xres_buf
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hvl__decap_4 (2->1) |sky130_fd_sc_hvl__decap_4 (2->1)
sky130_fd_sc_hvl__decap_8 (5->1) |sky130_fd_sc_hvl__decap_8 (5->1)
sky130_fd_sc_hvl__diode_2 (1) |sky130_fd_sc_hvl__diode_2 (1)
sky130_fd_pr__pfet_g5v0d10v5 (2) |sky130_fd_pr__pfet_g5v0d10v5 (2)
sky130_fd_pr__nfet_g5v0d10v5 (10->4) |sky130_fd_pr__nfet_g5v0d10v5 (10->4)
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
Number of devices: 13 |Number of devices: 13
Number of nets: 9 |Number of nets: 9
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: xres_buf |Circuit 2: xres_buf
-------------------------------------------|-------------------------------------------
LVPWR |LVPWR
X |X
A |A
VPWR |VPWR
VGND |VGND
LVGND |LVGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes xres_buf and xres_buf are equivalent.
Class housekeeping (0): Merged 10728 parallel devices.
Class housekeeping (1): Merged 10728 parallel devices.
Subcircuit summary:
Circuit 1: housekeeping |Circuit 2: housekeeping
-------------------------------------------|-------------------------------------------
sky130_ef_sc_hd__decap_12 (3536->1) |sky130_ef_sc_hd__decap_12 (3536->1)
sky130_fd_sc_hd__decap_4 (3025->1) |sky130_fd_sc_hd__decap_4 (3025->1)
sky130_fd_sc_hd__dfstp_4 (15) |sky130_fd_sc_hd__dfstp_4 (15)
sky130_fd_sc_hd__dfrtp_4 (196) |sky130_fd_sc_hd__dfrtp_4 (196)
sky130_fd_sc_hd__dfrtp_1 (256) |sky130_fd_sc_hd__dfrtp_1 (256)
sky130_fd_sc_hd__mux2_1 (757) |sky130_fd_sc_hd__mux2_1 (757)
sky130_fd_sc_hd__a211o_1 (50) |sky130_fd_sc_hd__a211o_1 (50)
sky130_fd_sc_hd__decap_6 (1323->1) |sky130_fd_sc_hd__decap_6 (1323->1)
sky130_fd_sc_hd__and3b_4 (17) |sky130_fd_sc_hd__and3b_4 (17)
sky130_fd_sc_hd__nand2b_2 (6) |sky130_fd_sc_hd__nand2b_2 (6)
sky130_fd_sc_hd__and2b_4 (13) |sky130_fd_sc_hd__and2b_4 (13)
sky130_fd_sc_hd__dlygate4sd3_1 (1544) |sky130_fd_sc_hd__dlygate4sd3_1 (1544)
sky130_fd_sc_hd__decap_8 (1671->1) |sky130_fd_sc_hd__decap_8 (1671->1)
sky130_fd_sc_hd__diode_2 (207->135) |sky130_fd_sc_hd__diode_2 (207->135)
sky130_fd_sc_hd__o211a_1 (43) |sky130_fd_sc_hd__o211a_1 (43)
sky130_fd_sc_hd__a31o_1 (29) |sky130_fd_sc_hd__a31o_1 (29)
sky130_fd_sc_hd__o221a_1 (41) |sky130_fd_sc_hd__o221a_1 (41)
sky130_fd_sc_hd__dfrtp_2 (121) |sky130_fd_sc_hd__dfrtp_2 (121)
sky130_fd_sc_hd__inv_2 (84) |sky130_fd_sc_hd__inv_2 (84)
sky130_fd_sc_hd__nor3_1 (24) |sky130_fd_sc_hd__nor3_1 (24)
sky130_fd_sc_hd__decap_3 (1106->1) |sky130_fd_sc_hd__decap_3 (1106->1)
sky130_fd_sc_hd__and2_2 (66) |sky130_fd_sc_hd__and2_2 (66)
sky130_fd_sc_hd__nand2_8 (46) |sky130_fd_sc_hd__nand2_8 (46)
sky130_fd_sc_hd__a21oi_1 (38) |sky130_fd_sc_hd__a21oi_1 (38)
sky130_fd_sc_hd__a221o_1 (333) |sky130_fd_sc_hd__a221o_1 (333)
sky130_fd_sc_hd__o2111a_1 (24) |sky130_fd_sc_hd__o2111a_1 (24)
sky130_fd_sc_hd__dfstp_2 (71) |sky130_fd_sc_hd__dfstp_2 (71)
sky130_fd_sc_hd__a22o_2 (22) |sky130_fd_sc_hd__a22o_2 (22)
sky130_fd_sc_hd__clkbuf_8 (42) |sky130_fd_sc_hd__clkbuf_8 (42)
sky130_fd_sc_hd__buf_12 (231) |sky130_fd_sc_hd__buf_12 (231)
sky130_fd_sc_hd__clkbuf_1 (125) |sky130_fd_sc_hd__clkbuf_1 (125)
sky130_fd_sc_hd__buf_4 (14) |sky130_fd_sc_hd__buf_4 (14)
sky130_fd_sc_hd__and2_1 (90) |sky130_fd_sc_hd__and2_1 (90)
sky130_fd_sc_hd__a22o_1 (375) |sky130_fd_sc_hd__a22o_1 (375)
sky130_fd_sc_hd__and2_4 (53) |sky130_fd_sc_hd__and2_4 (53)
sky130_fd_sc_hd__nand4_1 (9) |sky130_fd_sc_hd__nand4_1 (9)
sky130_fd_sc_hd__and3_1 (83) |sky130_fd_sc_hd__and3_1 (83)
sky130_fd_sc_hd__nor4_1 (50) |sky130_fd_sc_hd__nor4_1 (50)
sky130_fd_sc_hd__nand2_1 (99) |sky130_fd_sc_hd__nand2_1 (99)
sky130_fd_sc_hd__o22a_1 (57) |sky130_fd_sc_hd__o22a_1 (57)
sky130_fd_sc_hd__o21a_1 (32) |sky130_fd_sc_hd__o21a_1 (32)
sky130_fd_sc_hd__o2bb2a_1 (14) |sky130_fd_sc_hd__o2bb2a_1 (14)
sky130_fd_sc_hd__nor2_4 (43) |sky130_fd_sc_hd__nor2_4 (43)
sky130_fd_sc_hd__nor2_8 (76) |sky130_fd_sc_hd__nor2_8 (76)
sky130_fd_sc_hd__and4_1 (58) |sky130_fd_sc_hd__and4_1 (58)
sky130_fd_sc_hd__and3_4 (57) |sky130_fd_sc_hd__and3_4 (57)
sky130_fd_sc_hd__nand2_2 (19) |sky130_fd_sc_hd__nand2_2 (19)
sky130_fd_sc_hd__clkbuf_16 (100) |sky130_fd_sc_hd__clkbuf_16 (100)
sky130_fd_sc_hd__nor2_1 (79) |sky130_fd_sc_hd__nor2_1 (79)
sky130_fd_sc_hd__nor2_2 (23) |sky130_fd_sc_hd__nor2_2 (23)
sky130_fd_sc_hd__and4b_1 (17) |sky130_fd_sc_hd__and4b_1 (17)
sky130_fd_sc_hd__clkbuf_4 (15) |sky130_fd_sc_hd__clkbuf_4 (15)
sky130_fd_sc_hd__nand2_4 (28) |sky130_fd_sc_hd__nand2_4 (28)
sky130_fd_sc_hd__a221o_2 (24) |sky130_fd_sc_hd__a221o_2 (24)
sky130_fd_sc_hd__and3b_2 (3) |sky130_fd_sc_hd__and3b_2 (3)
sky130_fd_sc_hd__and2b_1 (10) |sky130_fd_sc_hd__and2b_1 (10)
sky130_fd_sc_hd__and3_2 (6) |sky130_fd_sc_hd__and3_2 (6)
sky130_fd_sc_hd__o31a_4 (1) |sky130_fd_sc_hd__o31a_4 (1)
sky130_fd_sc_hd__a32o_1 (11) |sky130_fd_sc_hd__a32o_1 (11)
sky130_fd_sc_hd__buf_8 (52) |sky130_fd_sc_hd__buf_8 (52)
sky130_fd_sc_hd__and4bb_1 (5) |sky130_fd_sc_hd__and4bb_1 (5)
sky130_fd_sc_hd__a21o_1 (48) |sky130_fd_sc_hd__a21o_1 (48)
sky130_fd_sc_hd__o21ai_1 (14) |sky130_fd_sc_hd__o21ai_1 (14)
sky130_fd_sc_hd__a41o_1 (3) |sky130_fd_sc_hd__a41o_1 (3)
sky130_fd_sc_hd__a2111o_1 (16) |sky130_fd_sc_hd__a2111o_1 (16)
sky130_fd_sc_hd__nand2b_1 (18) |sky130_fd_sc_hd__nand2b_1 (18)
sky130_fd_sc_hd__a2111oi_1 (2) |sky130_fd_sc_hd__a2111oi_1 (2)
sky130_fd_sc_hd__clkbuf_2 (35) |sky130_fd_sc_hd__clkbuf_2 (35)
sky130_fd_sc_hd__dfstp_1 (70) |sky130_fd_sc_hd__dfstp_1 (70)
sky130_fd_sc_hd__o41a_1 (5) |sky130_fd_sc_hd__o41a_1 (5)
sky130_fd_sc_hd__mux2_8 (9) |sky130_fd_sc_hd__mux2_8 (9)
sky130_fd_sc_hd__buf_6 (56) |sky130_fd_sc_hd__buf_6 (56)
sky130_fd_sc_hd__o21ai_2 (1) |sky130_fd_sc_hd__o21ai_2 (1)
sky130_fd_sc_hd__clkinv_2 (9) |sky130_fd_sc_hd__clkinv_2 (9)
sky130_fd_sc_hd__a311o_1 (3) |sky130_fd_sc_hd__a311o_1 (3)
sky130_fd_sc_hd__o2111ai_1 (1) |sky130_fd_sc_hd__o2111ai_1 (1)
sky130_fd_sc_hd__o32a_1 (13) |sky130_fd_sc_hd__o32a_1 (13)
sky130_fd_sc_hd__nand3_1 (17) |sky130_fd_sc_hd__nand3_1 (17)
sky130_fd_sc_hd__nor4_4 (3) |sky130_fd_sc_hd__nor4_4 (3)
sky130_fd_sc_hd__dlymetal6s2s_1 (17) |sky130_fd_sc_hd__dlymetal6s2s_1 (17)
sky130_fd_sc_hd__and2b_2 (10) |sky130_fd_sc_hd__and2b_2 (10)
sky130_fd_sc_hd__mux2_2 (16) |sky130_fd_sc_hd__mux2_2 (16)
sky130_fd_sc_hd__nand3_4 (8) |sky130_fd_sc_hd__nand3_4 (8)
sky130_fd_sc_hd__and3b_1 (8) |sky130_fd_sc_hd__and3b_1 (8)
sky130_fd_sc_hd__nand2b_4 (5) |sky130_fd_sc_hd__nand2b_4 (5)
sky130_fd_sc_hd__a21boi_1 (3) |sky130_fd_sc_hd__a21boi_1 (3)
sky130_fd_sc_hd__nor3_2 (6) |sky130_fd_sc_hd__nor3_2 (6)
sky130_fd_sc_hd__dfxtp_1 (32) |sky130_fd_sc_hd__dfxtp_1 (32)
sky130_fd_sc_hd__buf_2 (16) |sky130_fd_sc_hd__buf_2 (16)
sky130_fd_sc_hd__o31a_2 (1) |sky130_fd_sc_hd__o31a_2 (1)
sky130_fd_sc_hd__o21a_4 (1) |sky130_fd_sc_hd__o21a_4 (1)
sky130_fd_sc_hd__dfrtn_1 (9) |sky130_fd_sc_hd__dfrtn_1 (9)
sky130_fd_sc_hd__mux2_4 (6) |sky130_fd_sc_hd__mux2_4 (6)
sky130_fd_sc_hd__a31oi_1 (2) |sky130_fd_sc_hd__a31oi_1 (2)
sky130_fd_sc_hd__o211a_2 (2) |sky130_fd_sc_hd__o211a_2 (2)
sky130_fd_sc_hd__nand4b_1 (3) |sky130_fd_sc_hd__nand4b_1 (3)
sky130_fd_sc_hd__nand3b_4 (2) |sky130_fd_sc_hd__nand3b_4 (2)
sky130_fd_sc_hd__o21ba_1 (7) |sky130_fd_sc_hd__o21ba_1 (7)
sky130_fd_sc_hd__a31o_2 (1) |sky130_fd_sc_hd__a31o_2 (1)
sky130_fd_sc_hd__a2bb2o_1 (4) |sky130_fd_sc_hd__a2bb2o_1 (4)
sky130_fd_sc_hd__nor4_2 (2) |sky130_fd_sc_hd__nor4_2 (2)
sky130_fd_sc_hd__and4b_2 (4) |sky130_fd_sc_hd__and4b_2 (4)
sky130_fd_sc_hd__nand4_2 (3) |sky130_fd_sc_hd__nand4_2 (3)
sky130_fd_sc_hd__a211o_2 (2) |sky130_fd_sc_hd__a211o_2 (2)
sky130_fd_sc_hd__xnor2_1 (4) |sky130_fd_sc_hd__xnor2_1 (4)
sky130_fd_sc_hd__o311a_1 (8) |sky130_fd_sc_hd__o311a_1 (8)
sky130_fd_sc_hd__a2111o_2 (5) |sky130_fd_sc_hd__a2111o_2 (5)
sky130_fd_sc_hd__a21o_2 (1) |sky130_fd_sc_hd__a21o_2 (1)
sky130_fd_sc_hd__conb_1 (1) |sky130_fd_sc_hd__conb_1 (1)
sky130_fd_sc_hd__nand4b_4 (2) |sky130_fd_sc_hd__nand4b_4 (2)
sky130_fd_sc_hd__nand3_2 (10) |sky130_fd_sc_hd__nand3_2 (10)
sky130_fd_sc_hd__a311oi_2 (1) |sky130_fd_sc_hd__a311oi_2 (1)
sky130_fd_sc_hd__xor2_1 (1) |sky130_fd_sc_hd__xor2_1 (1)
sky130_fd_sc_hd__o221a_4 (3) |sky130_fd_sc_hd__o221a_4 (3)
sky130_fd_sc_hd__a211o_4 (1) |sky130_fd_sc_hd__a211o_4 (1)
sky130_fd_sc_hd__o31a_1 (4) |sky130_fd_sc_hd__o31a_1 (4)
sky130_fd_sc_hd__xnor2_2 (2) |sky130_fd_sc_hd__xnor2_2 (2)
sky130_fd_sc_hd__o31ai_1 (1) |sky130_fd_sc_hd__o31ai_1 (1)
sky130_fd_sc_hd__a21bo_1 (6) |sky130_fd_sc_hd__a21bo_1 (6)
sky130_fd_sc_hd__a221o_4 (1) |sky130_fd_sc_hd__a221o_4 (1)
sky130_fd_sc_hd__and4b_4 (1) |sky130_fd_sc_hd__and4b_4 (1)
sky130_fd_sc_hd__nor3b_1 (2) |sky130_fd_sc_hd__nor3b_1 (2)
sky130_fd_sc_hd__a21oi_2 (2) |sky130_fd_sc_hd__a21oi_2 (2)
sky130_fd_sc_hd__nor3_4 (2) |sky130_fd_sc_hd__nor3_4 (2)
sky130_fd_sc_hd__a21oi_4 (1) |sky130_fd_sc_hd__a21oi_4 (1)
sky130_fd_sc_hd__a21o_4 (1) |sky130_fd_sc_hd__a21o_4 (1)
sky130_fd_sc_hd__a31oi_4 (1) |sky130_fd_sc_hd__a31oi_4 (1)
sky130_fd_sc_hd__and4_2 (1) |sky130_fd_sc_hd__and4_2 (1)
sky130_fd_sc_hd__o21a_2 (1) |sky130_fd_sc_hd__o21a_2 (1)
sky130_fd_sc_hd__a2111o_4 (1) |sky130_fd_sc_hd__a2111o_4 (1)
sky130_fd_sc_hd__inv_6 (1) |sky130_fd_sc_hd__inv_6 (1)
sky130_fd_sc_hd__a221oi_1 (1) |sky130_fd_sc_hd__a221oi_1 (1)
sky130_fd_sc_hd__and4bb_2 (1) |sky130_fd_sc_hd__and4bb_2 (1)
Number of devices: 6397 |Number of devices: 6397
Number of nets: 6433 |Number of nets: 6433
---------------------------------------------------------------------------------------
Netlists match uniquely.
Subcircuit pins:
Circuit 1: housekeeping |Circuit 2: housekeeping
-------------------------------------------|-------------------------------------------
mgmt_gpio_out[9] |mgmt_gpio_out[9]
mgmt_gpio_out[14] |mgmt_gpio_out[14]
pad_flash_clk |pad_flash_clk
mgmt_gpio_out[15] |mgmt_gpio_out[15]
wb_adr_i[0] |wb_adr_i[0]
spimemio_flash_io1_oeb |spimemio_flash_io1_oeb
spi_enabled |spi_enabled
qspi_enabled |qspi_enabled
pad_flash_io1_di |pad_flash_io1_di
mgmt_gpio_in[3] |mgmt_gpio_in[3]
mgmt_gpio_in[37] |mgmt_gpio_in[37]
trap |trap
mgmt_gpio_in[34] |mgmt_gpio_in[34]
mgmt_gpio_in[2] |mgmt_gpio_in[2]
mgmt_gpio_in[18] |mgmt_gpio_in[18]
mgmt_gpio_in[35] |mgmt_gpio_in[35]
spimemio_flash_io3_oeb |spimemio_flash_io3_oeb
mgmt_gpio_in[12] |mgmt_gpio_in[12]
mgmt_gpio_in[19] |mgmt_gpio_in[19]
mgmt_gpio_in[11] |mgmt_gpio_in[11]
mgmt_gpio_in[5] |mgmt_gpio_in[5]
mgmt_gpio_in[36] |mgmt_gpio_in[36]
mgmt_gpio_in[7] |mgmt_gpio_in[7]
mgmt_gpio_in[0] |mgmt_gpio_in[0]
mask_rev_in[9] |mask_rev_in[9]
mask_rev_in[28] |mask_rev_in[28]
mask_rev_in[18] |mask_rev_in[18]
mask_rev_in[14] |mask_rev_in[14]
mgmt_gpio_in[27] |mgmt_gpio_in[27]
mask_rev_in[12] |mask_rev_in[12]
spimemio_flash_io0_do |spimemio_flash_io0_do
mask_rev_in[4] |mask_rev_in[4]
spimemio_flash_csb |spimemio_flash_csb
mgmt_gpio_in[33] |mgmt_gpio_in[33]
spimemio_flash_clk |spimemio_flash_clk
mgmt_gpio_in[22] |mgmt_gpio_in[22]
mgmt_gpio_in[31] |mgmt_gpio_in[31]
mgmt_gpio_in[21] |mgmt_gpio_in[21]
mgmt_gpio_in[20] |mgmt_gpio_in[20]
mgmt_gpio_in[10] |mgmt_gpio_in[10]
mgmt_gpio_in[1] |mgmt_gpio_in[1]
mgmt_gpio_in[28] |mgmt_gpio_in[28]
mgmt_gpio_in[17] |mgmt_gpio_in[17]
mask_rev_in[7] |mask_rev_in[7]
mask_rev_in[26] |mask_rev_in[26]
usr2_vdd_pwrgood |usr2_vdd_pwrgood
mask_rev_in[25] |mask_rev_in[25]
mask_rev_in[17] |mask_rev_in[17]
mgmt_gpio_in[25] |mgmt_gpio_in[25]
mask_rev_in[24] |mask_rev_in[24]
mask_rev_in[10] |mask_rev_in[10]
mgmt_gpio_in[23] |mgmt_gpio_in[23]
mgmt_gpio_in[8] |mgmt_gpio_in[8]
spimemio_flash_io2_do |spimemio_flash_io2_do
spimemio_flash_io3_do |spimemio_flash_io3_do
mask_rev_in[20] |mask_rev_in[20]
spi_csb |spi_csb
mask_rev_in[27] |mask_rev_in[27]
mask_rev_in[16] |mask_rev_in[16]
mask_rev_in[6] |mask_rev_in[6]
usr2_vcc_pwrgood |usr2_vcc_pwrgood
mask_rev_in[11] |mask_rev_in[11]
usr1_vdd_pwrgood |usr1_vdd_pwrgood
mask_rev_in[0] |mask_rev_in[0]
mgmt_gpio_in[9] |mgmt_gpio_in[9]
spi_sdoenb |spi_sdoenb
spi_sdo |spi_sdo
spi_sck |spi_sck
spimemio_flash_io2_oeb |spimemio_flash_io2_oeb
wb_adr_i[1] |wb_adr_i[1]
wb_adr_i[20] |wb_adr_i[20]
wb_adr_i[23] |wb_adr_i[23]
wb_adr_i[22] |wb_adr_i[22]
debug_mode |debug_mode
wb_adr_i[2] |wb_adr_i[2]
wb_adr_i[3] |wb_adr_i[3]
wb_adr_i[4] |wb_adr_i[4]
wb_adr_i[5] |wb_adr_i[5]
wb_adr_i[6] |wb_adr_i[6]
wb_adr_i[7] |wb_adr_i[7]
mgmt_gpio_in[30] |mgmt_gpio_in[30]
spimemio_flash_io1_do |spimemio_flash_io1_do
spimemio_flash_io0_oeb |spimemio_flash_io0_oeb
mgmt_gpio_in[24] |mgmt_gpio_in[24]
usr1_vcc_pwrgood |usr1_vcc_pwrgood
wb_rstn_i |wb_rstn_i
wb_dat_i[9] |wb_dat_i[9]
wb_dat_i[17] |wb_dat_i[17]
mask_rev_in[23] |mask_rev_in[23]
mask_rev_in[3] |mask_rev_in[3]
mask_rev_in[22] |mask_rev_in[22]
mask_rev_in[31] |mask_rev_in[31]
mask_rev_in[21] |mask_rev_in[21]
mask_rev_in[30] |mask_rev_in[30]
mask_rev_in[1] |mask_rev_in[1]
mgmt_gpio_in[6] |mgmt_gpio_in[6]
mask_rev_in[29] |mask_rev_in[29]
mask_rev_in[19] |mask_rev_in[19]
mgmt_gpio_in[29] |mgmt_gpio_in[29]
mask_rev_in[8] |mask_rev_in[8]
ser_tx |ser_tx
mask_rev_in[13] |mask_rev_in[13]
mgmt_gpio_in[26] |mgmt_gpio_in[26]
mgmt_gpio_in[16] |mgmt_gpio_in[16]
mask_rev_in[2] |mask_rev_in[2]
mask_rev_in[15] |mask_rev_in[15]
porb |porb
mgmt_gpio_in[15] |mgmt_gpio_in[15]
mask_rev_in[5] |mask_rev_in[5]
mgmt_gpio_in[14] |mgmt_gpio_in[14]
pad_flash_io0_di |pad_flash_io0_di
mgmt_gpio_in[13] |mgmt_gpio_in[13]
mgmt_gpio_in[32] |mgmt_gpio_in[32]
debug_out |debug_out
debug_oeb |debug_oeb
wb_adr_i[28] |wb_adr_i[28]
wb_adr_i[27] |wb_adr_i[27]
wb_dat_i[16] |wb_dat_i[16]
wb_dat_i[18] |wb_dat_i[18]
wb_adr_i[26] |wb_adr_i[26]
wb_dat_i[25] |wb_dat_i[25]
wb_adr_i[25] |wb_adr_i[25]
wb_dat_i[26] |wb_dat_i[26]
wb_dat_i[24] |wb_dat_i[24]
wb_adr_i[24] |wb_adr_i[24]
wb_dat_i[7] |wb_dat_i[7]
wb_dat_i[6] |wb_dat_i[6]
wb_dat_i[5] |wb_dat_i[5]
wb_dat_i[4] |wb_dat_i[4]
wb_dat_i[3] |wb_dat_i[3]
wb_dat_i[11] |wb_dat_i[11]
wb_dat_i[12] |wb_dat_i[12]
wb_dat_i[13] |wb_dat_i[13]
wb_dat_i[14] |wb_dat_i[14]
wb_dat_i[15] |wb_dat_i[15]
wb_adr_i[31] |wb_adr_i[31]
wb_dat_i[8] |wb_dat_i[8]
wb_dat_i[10] |wb_dat_i[10]
wb_adr_i[30] |wb_adr_i[30]
wb_sel_i[0] |wb_sel_i[0]
wb_dat_i[1] |wb_dat_i[1]
wb_dat_i[0] |wb_dat_i[0]
wb_dat_i[2] |wb_dat_i[2]
wb_dat_i[27] |wb_dat_i[27]
wb_dat_i[28] |wb_dat_i[28]
wb_dat_i[29] |wb_dat_i[29]
wb_dat_i[30] |wb_dat_i[30]
wb_dat_i[31] |wb_dat_i[31]
wb_dat_i[23] |wb_dat_i[23]
wb_dat_i[22] |wb_dat_i[22]
wb_dat_i[21] |wb_dat_i[21]
wb_dat_i[20] |wb_dat_i[20]
wb_dat_i[19] |wb_dat_i[19]
wb_cyc_i |wb_cyc_i
wb_adr_i[29] |wb_adr_i[29]
wb_adr_i[9] |wb_adr_i[9]
uart_enabled |uart_enabled
wb_adr_i[19] |wb_adr_i[19]
wb_adr_i[18] |wb_adr_i[18]
wb_adr_i[8] |wb_adr_i[8]
wb_adr_i[13] |wb_adr_i[13]
wb_adr_i[17] |wb_adr_i[17]
wb_sel_i[3] |wb_sel_i[3]
wb_adr_i[12] |wb_adr_i[12]
wb_adr_i[16] |wb_adr_i[16]
wb_sel_i[2] |wb_sel_i[2]
wb_adr_i[11] |wb_adr_i[11]
wb_adr_i[15] |wb_adr_i[15]
wb_sel_i[1] |wb_sel_i[1]
wb_adr_i[10] |wb_adr_i[10]
wb_adr_i[14] |wb_adr_i[14]
wb_stb_i |wb_stb_i
wb_we_i |wb_we_i
wb_adr_i[21] |wb_adr_i[21]
pll_trim[10] |pll_trim[10]
pll_trim[21] |pll_trim[21]
pll_trim[6] |pll_trim[6]
pll90_sel[2] |pll90_sel[2]
pll_trim[15] |pll_trim[15]
pll_trim[14] |pll_trim[14]
pll_trim[13] |pll_trim[13]
pll_div[2] |pll_div[2]
pll_trim[9] |pll_trim[9]
pll_trim[22] |pll_trim[22]
pll_trim[12] |pll_trim[12]
pll_div[1] |pll_div[1]
pll_trim[8] |pll_trim[8]
pll_trim[11] |pll_trim[11]
pll_div[0] |pll_div[0]
pll_trim[7] |pll_trim[7]
pll_trim[20] |pll_trim[20]
pll_dco_ena |pll_dco_ena
pll_trim[1] |pll_trim[1]
pll_trim[0] |pll_trim[0]
pll_bypass |pll_bypass
pll_trim[5] |pll_trim[5]
pll_trim[19] |pll_trim[19]
pll_sel[2] |pll_sel[2]
pll_trim[4] |pll_trim[4]
pll_trim[18] |pll_trim[18]
pll_trim[3] |pll_trim[3]
pwr_ctrl_out[3] |pwr_ctrl_out[3]
pll_sel[1] |pll_sel[1]
pll90_sel[1] |pll90_sel[1]
pll_trim[17] |pll_trim[17]
pll_sel[0] |pll_sel[0]
pll90_sel[0] |pll90_sel[0]
pll_trim[2] |pll_trim[2]
pll_trim[16] |pll_trim[16]
pll_ena |pll_ena
pll_trim[25] |pll_trim[25]
pll_div[4] |pll_div[4]
pwr_ctrl_out[1] |pwr_ctrl_out[1]
pwr_ctrl_out[2] |pwr_ctrl_out[2]
pll_trim[24] |pll_trim[24]
pll_div[3] |pll_div[3]
pwr_ctrl_out[0] |pwr_ctrl_out[0]
pll_trim[23] |pll_trim[23]
serial_clock |serial_clock
pad_flash_io0_ieb |pad_flash_io0_ieb
serial_data_2 |serial_data_2
serial_data_1 |serial_data_1
reset |reset
mgmt_gpio_oeb[16] |mgmt_gpio_oeb[16]
mgmt_gpio_out[32] |mgmt_gpio_out[32]
mgmt_gpio_out[35] |mgmt_gpio_out[35]
pad_flash_io1_ieb |pad_flash_io1_ieb
mgmt_gpio_in[4] |mgmt_gpio_in[4]
pad_flash_io0_do |pad_flash_io0_do
mgmt_gpio_out[37] |mgmt_gpio_out[37]
mgmt_gpio_out[36] |mgmt_gpio_out[36]
pad_flash_csb_oeb |pad_flash_csb_oeb
spimemio_flash_io0_di |spimemio_flash_io0_di
spi_sdi |spi_sdi
serial_resetn |serial_resetn
serial_load |serial_load
wb_ack_o |wb_ack_o
ser_rx |ser_rx
mgmt_gpio_oeb[1] |mgmt_gpio_oeb[1]
mgmt_gpio_oeb[0] |mgmt_gpio_oeb[0]
irq[2] |irq[2]
spimemio_flash_io2_di |spimemio_flash_io2_di
irq[1] |irq[1]
spimemio_flash_io1_di |spimemio_flash_io1_di
irq[0] |irq[0]
debug_in |debug_in
wb_dat_o[22] |wb_dat_o[22]
wb_dat_o[19] |wb_dat_o[19]
wb_dat_o[23] |wb_dat_o[23]
wb_dat_o[21] |wb_dat_o[21]
wb_dat_o[30] |wb_dat_o[30]
wb_dat_o[18] |wb_dat_o[18]
wb_dat_o[10] |wb_dat_o[10]
wb_dat_o[8] |wb_dat_o[8]
wb_dat_o[11] |wb_dat_o[11]
wb_dat_o[6] |wb_dat_o[6]
wb_dat_o[7] |wb_dat_o[7]
wb_dat_o[5] |wb_dat_o[5]
wb_dat_o[9] |wb_dat_o[9]
wb_dat_o[13] |wb_dat_o[13]
wb_dat_o[15] |wb_dat_o[15]
wb_dat_o[14] |wb_dat_o[14]
wb_dat_o[17] |wb_dat_o[17]
wb_dat_o[12] |wb_dat_o[12]
wb_dat_o[4] |wb_dat_o[4]
wb_dat_o[16] |wb_dat_o[16]
wb_dat_o[26] |wb_dat_o[26]
wb_dat_o[2] |wb_dat_o[2]
wb_dat_o[0] |wb_dat_o[0]
wb_dat_o[24] |wb_dat_o[24]
wb_dat_o[20] |wb_dat_o[20]
wb_dat_o[28] |wb_dat_o[28]
wb_dat_o[27] |wb_dat_o[27]
wb_dat_o[31] |wb_dat_o[31]
wb_dat_o[29] |wb_dat_o[29]
wb_dat_o[25] |wb_dat_o[25]
wb_dat_o[1] |wb_dat_o[1]
wb_dat_o[3] |wb_dat_o[3]
mgmt_gpio_oeb[19] |mgmt_gpio_oeb[19]
mgmt_gpio_oeb[4] |mgmt_gpio_oeb[4]
mgmt_gpio_out[13] |mgmt_gpio_out[13]
pad_flash_csb |pad_flash_csb
mgmt_gpio_oeb[37] |mgmt_gpio_oeb[37]
pad_flash_clk_oeb |pad_flash_clk_oeb
mgmt_gpio_out[33] |mgmt_gpio_out[33]
mgmt_gpio_oeb[36] |mgmt_gpio_oeb[36]
mgmt_gpio_out[8] |mgmt_gpio_out[8]
mgmt_gpio_out[10] |mgmt_gpio_out[10]
mgmt_gpio_oeb[35] |mgmt_gpio_oeb[35]
mgmt_gpio_out[0] |mgmt_gpio_out[0]
mgmt_gpio_out[6] |mgmt_gpio_out[6]
mgmt_gpio_out[1] |mgmt_gpio_out[1]
mgmt_gpio_oeb[10] |mgmt_gpio_oeb[10]
mgmt_gpio_oeb[17] |mgmt_gpio_oeb[17]
mgmt_gpio_oeb[20] |mgmt_gpio_oeb[20]
mgmt_gpio_oeb[29] |mgmt_gpio_oeb[29]
mgmt_gpio_oeb[3] |mgmt_gpio_oeb[3]
mgmt_gpio_oeb[6] |mgmt_gpio_oeb[6]
mgmt_gpio_oeb[8] |mgmt_gpio_oeb[8]
mgmt_gpio_oeb[32] |mgmt_gpio_oeb[32]
mgmt_gpio_oeb[33] |mgmt_gpio_oeb[33]
mgmt_gpio_oeb[34] |mgmt_gpio_oeb[34]
pad_flash_io1_do |pad_flash_io1_do
mgmt_gpio_oeb[11] |mgmt_gpio_oeb[11]
mgmt_gpio_oeb[12] |mgmt_gpio_oeb[12]
mgmt_gpio_oeb[13] |mgmt_gpio_oeb[13]
mgmt_gpio_oeb[14] |mgmt_gpio_oeb[14]
mgmt_gpio_oeb[15] |mgmt_gpio_oeb[15]
mgmt_gpio_oeb[18] |mgmt_gpio_oeb[18]
mgmt_gpio_oeb[21] |mgmt_gpio_oeb[21]
mgmt_gpio_oeb[22] |mgmt_gpio_oeb[22]
mgmt_gpio_oeb[23] |mgmt_gpio_oeb[23]
mgmt_gpio_oeb[24] |mgmt_gpio_oeb[24]
mgmt_gpio_oeb[25] |mgmt_gpio_oeb[25]
mgmt_gpio_oeb[26] |mgmt_gpio_oeb[26]
mgmt_gpio_oeb[27] |mgmt_gpio_oeb[27]
mgmt_gpio_oeb[28] |mgmt_gpio_oeb[28]
mgmt_gpio_oeb[2] |mgmt_gpio_oeb[2]
mgmt_gpio_oeb[30] |mgmt_gpio_oeb[30]
mgmt_gpio_oeb[31] |mgmt_gpio_oeb[31]
mgmt_gpio_oeb[5] |mgmt_gpio_oeb[5]
mgmt_gpio_oeb[7] |mgmt_gpio_oeb[7]
mgmt_gpio_oeb[9] |mgmt_gpio_oeb[9]
pad_flash_io0_oeb |pad_flash_io0_oeb
pad_flash_io1_oeb |pad_flash_io1_oeb
mgmt_gpio_out[11] |mgmt_gpio_out[11]
mgmt_gpio_out[12] |mgmt_gpio_out[12]
mgmt_gpio_out[4] |mgmt_gpio_out[4]
mgmt_gpio_out[3] |mgmt_gpio_out[3]
mgmt_gpio_out[7] |mgmt_gpio_out[7]
mgmt_gpio_out[16] |mgmt_gpio_out[16]
mgmt_gpio_out[17] |mgmt_gpio_out[17]
mgmt_gpio_out[19] |mgmt_gpio_out[19]
mgmt_gpio_out[18] |mgmt_gpio_out[18]
mgmt_gpio_out[24] |mgmt_gpio_out[24]
mgmt_gpio_out[20] |mgmt_gpio_out[20]
mgmt_gpio_out[25] |mgmt_gpio_out[25]
mgmt_gpio_out[26] |mgmt_gpio_out[26]
mgmt_gpio_out[23] |mgmt_gpio_out[23]
mgmt_gpio_out[22] |mgmt_gpio_out[22]
mgmt_gpio_out[21] |mgmt_gpio_out[21]
mgmt_gpio_out[28] |mgmt_gpio_out[28]
mgmt_gpio_out[2] |mgmt_gpio_out[2]
mgmt_gpio_out[27] |mgmt_gpio_out[27]
mgmt_gpio_out[31] |mgmt_gpio_out[31]
mgmt_gpio_out[30] |mgmt_gpio_out[30]
mgmt_gpio_out[29] |mgmt_gpio_out[29]
mgmt_gpio_out[34] |mgmt_gpio_out[34]
mgmt_gpio_out[5] |mgmt_gpio_out[5]
spimemio_flash_io3_di |spimemio_flash_io3_di
wb_clk_i |wb_clk_i
user_clock |user_clock
VGND |VGND
VPWR |VPWR
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes housekeeping and housekeeping are equivalent.
Circuit 2 cell buff_flash_clkrst is a black box; will not flatten Circuit 1
Class buff_flash_clkrst (0): Merged 29 parallel devices.
Subcircuit pins:
Circuit 1: buff_flash_clkrst |Circuit 2: buff_flash_clkrst
-------------------------------------------|-------------------------------------------
VPWR |VPWR
in_n[0] |in_n[0]
in_n[10] |in_n[10]
in_n[11] |in_n[11]
in_n[1] |in_n[1]
in_n[2] |in_n[2]
in_n[3] |in_n[3]
in_n[4] |in_n[4]
in_n[5] |in_n[5]
in_n[6] |in_n[6]
in_n[7] |in_n[7]
in_n[8] |in_n[8]
in_n[9] |in_n[9]
in_s[0] |in_s[0]
in_s[1] |in_s[1]
in_s[2] |in_s[2]
out_n[0] |out_n[0]
out_n[1] |out_n[1]
out_n[2] |out_n[2]
out_s[0] |out_s[0]
out_s[10] |out_s[10]
out_s[11] |out_s[11]
out_s[1] |out_s[1]
out_s[2] |out_s[2]
out_s[3] |out_s[3]
out_s[4] |out_s[4]
out_s[5] |out_s[5]
out_s[6] |out_s[6]
out_s[7] |out_s[7]
out_s[8] |out_s[8]
out_s[9] |out_s[9]
VGND |VGND
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes buff_flash_clkrst and buff_flash_clkrst are equivalent.
Class caravan (0): Merged 26 parallel devices.
Class caravan (1): Merged 26 parallel devices.
Subcircuit summary:
Circuit 1: caravan |Circuit 2: caravan
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__dfrtp_4 (351) |sky130_fd_sc_hd__dfrtp_4 (351)
sky130_fd_sc_hd__nand2b_2 (378) |sky130_fd_sc_hd__nand2b_2 (378)
sky130_fd_sc_hd__dfbbn_2 (351) |sky130_fd_sc_hd__dfbbn_2 (351)
sky130_fd_sc_hd__inv_2 (432) |sky130_fd_sc_hd__inv_2 (432)
sky130_fd_sc_hd__buf_16 (513) |sky130_fd_sc_hd__buf_16 (513)
sky130_fd_sc_hd__mux2_4 (27) |sky130_fd_sc_hd__mux2_4 (27)
sky130_fd_sc_hd__clkbuf_16 (216) |sky130_fd_sc_hd__clkbuf_16 (216)
sky130_fd_sc_hd__and2_0 (27) |sky130_fd_sc_hd__and2_0 (27)
sky130_fd_sc_hd__dlygate4sd3_1 (351) |sky130_fd_sc_hd__dlygate4sd3_1 (351)
sky130_fd_sc_hd__diode_2 (1053->621) |sky130_fd_sc_hd__diode_2 (1053->621)
sky130_fd_sc_hd__decap_3 (1134->1) |sky130_fd_sc_hd__decap_3 (1134->1)
sky130_fd_sc_hd__conb_1 (54) |sky130_fd_sc_hd__conb_1 (54)
sky130_fd_sc_hd__buf_2 (432) |sky130_fd_sc_hd__buf_2 (432)
sky130_fd_sc_hd__or2_0 (351) |sky130_fd_sc_hd__or2_0 (351)
sky130_fd_sc_hd__nand2_2 (54) |sky130_fd_sc_hd__nand2_2 (54)
sky130_fd_sc_hd__nor2_2 (54) |sky130_fd_sc_hd__nor2_2 (54)
gpio_logic_high (27) |gpio_logic_high (27)
sky130_fd_sc_hd__and2_2 (27) |sky130_fd_sc_hd__and2_2 (27)
sky130_fd_sc_hd__o21ai_4 (27) |sky130_fd_sc_hd__o21ai_4 (27)
sky130_fd_sc_hd__o21ai_2 (27) |sky130_fd_sc_hd__o21ai_2 (27)
sky130_fd_sc_hd__and2b_2 (27) |sky130_fd_sc_hd__and2b_2 (27)
sky130_fd_sc_hd__dfrtp_2 (27) |sky130_fd_sc_hd__dfrtp_2 (27)
sky130_fd_sc_hd__and3b_2 (27) |sky130_fd_sc_hd__and3b_2 (27)
gpio_defaults_block_0403 (24) |gpio_defaults_block_0403 (24)
digital_pll (1) |digital_pll (1)
chip_io_alt (1) |chip_io_alt (1)
mgmt_core_wrapper (1) |mgmt_core_wrapper (1)
simple_por (1) |simple_por (1)
caravel_clocking (1) |caravel_clocking (1)
gpio_defaults_block_1803 (2) |gpio_defaults_block_1803 (2)
spare_logic_block (4) |spare_logic_block (4)
user_id_programming (1) |user_id_programming (1)
gpio_defaults_block_0801 (1) |gpio_defaults_block_0801 (1)
gpio_signal_buffering_alt (1) |gpio_signal_buffering_alt (1)
mgmt_protect (1) |mgmt_protect (1)
xres_buf (1) |xres_buf (1)
housekeeping (1) |housekeeping (1)
buff_flash_clkrst (1) |buff_flash_clkrst (1)
(no matching element) |user_analog_project_wrapper (1)
Number of devices: 4444 **Mismatch** |Number of devices: 4445 **Mismatch**
Number of nets: 6526 **Mismatch** |Number of nets: 6531 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: caravan |Circuit 2: caravan
---------------------------------------------------------------------------------------
Net: padframe/mprj_io_analog_en[14] |Net: clock_core
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/in_s[2] = 1
chip_io_alt/mprj_io_analog_en[14] = 1 | chip_io_alt/clock_core = 1
|
Net: padframe/mprj_io_analog_pol[14] |Net: flash_io1_di
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/in_s[1] = 1
chip_io_alt/mprj_io_analog_pol[14] = 1 | chip_io_alt/flash_io1_di_core = 1
|
Net: padframe/mprj_io_analog_sel[14] |Net: flash_io0_di
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/in_s[0] = 1
chip_io_alt/mprj_io_analog_sel[14] = 1 | chip_io_alt/flash_io0_di_core = 1
|
Net: padframe/mprj_io_dm[42] |Net: flash_clk_frame_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[9] = 1
chip_io_alt/mprj_io_dm[42] = 1 | chip_io_alt/flash_clk_core = 1
|
Net: padframe/mprj_io_dm[43] |Net: flash_csb_frame_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[8] = 1
chip_io_alt/mprj_io_dm[43] = 1 | chip_io_alt/flash_csb_core = 1
|
Net: padframe/mprj_io_dm[44] |Net: flash_clk_oeb_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[7] = 1
chip_io_alt/mprj_io_dm[44] = 1 | chip_io_alt/flash_clk_oeb_core = 1
|
Net: padframe/mprj_io_holdover[14] |Net: flash_csb_oeb_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[6] = 1
chip_io_alt/mprj_io_holdover[14] = 1 | chip_io_alt/flash_csb_oeb_core = 1
|
Net: padframe/mprj_io_ib_mode_sel[14] |Net: flash_io0_oeb_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[5] = 1
chip_io_alt/mprj_io_ib_mode_sel[14] = 1 | chip_io_alt/flash_io0_oeb_core = 1
|
Net: padframe/mprj_io_inp_dis[14] |Net: flash_io1_oeb_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[4] = 1
chip_io_alt/mprj_io_inp_dis[14] = 1 | chip_io_alt/flash_io1_oeb_core = 1
|
Net: padframe/mprj_io_out[14] |Net: flash_io0_ieb_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[3] = 1
chip_io_alt/mprj_io_out[14] = 1 | chip_io_alt/flash_io0_ieb_core = 1
|
Net: padframe/mprj_io_oeb[14] |Net: flash_io1_ieb_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[2] = 1
chip_io_alt/mprj_io_oeb[14] = 1 | chip_io_alt/flash_io1_ieb_core = 1
|
Net: padframe/mprj_io_slow_sel[14] |Net: flash_io0_do_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[1] = 1
chip_io_alt/mprj_io_slow_sel[14] = 1 | chip_io_alt/flash_io0_do_core = 1
|
Net: padframe/mprj_io_vtrip_sel[14] |Net: flash_io1_do_buf
sky130_fd_sc_hd__buf_16/X = 1 | buff_flash_clkrst/out_s[0] = 1
chip_io_alt/mprj_io_vtrip_sel[14] = 1 | chip_io_alt/flash_io1_do_core = 1
|
Net: mprj/io_oeb[14] |Net: \mprj_io_one[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[0] = 1
|
Net: mprj/io_oeb[5] |Net: \mprj_io_analog_en[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_en[0] = 1
|
Net: mprj/io_oeb[23] |Net: \mprj_io_analog_pol[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_pol[0] = 1
|
Net: mprj/io_oeb[12] |Net: \mprj_io_analog_sel[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_sel[0] = 1
|
Net: mprj/io_oeb[3] |Net: \mprj_io_holdover[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_holdover[0] = 1
|
Net: mprj/io_oeb[21] |Net: \mprj_io_ib_mode_sel[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_ib_mode_sel[0] = 1
|
Net: mprj/io_oeb[10] |Net: \mprj_io_inp_dis[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_inp_dis[0] = 1
|
Net: mprj/io_oeb[8] |Net: \mprj_io_out[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_out[0] = 1
|
Net: mprj/io_oeb[19] |Net: \mprj_io_oeb[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_oeb[0] = 1
|
Net: mprj/io_oeb[17] |Net: \mprj_io_slow_sel[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_slow_sel[0] = 1
|
Net: mprj/io_oeb[15] |Net: \mprj_io_vtrip_sel[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_vtrip_sel[0] = 1
|
Net: mprj/io_oeb[6] |Net: \user_io_in[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | user_analog_project_wrapper/io_in[0] = 1
|
Net: mprj/io_oeb[13] |Net: \mprj_io_dm[2]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[2] = 1
|
Net: mprj/io_oeb[4] |Net: \mprj_io_dm[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[1] = 1
|
Net: mprj/io_oeb[22] |Net: \mprj_io_dm[0]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[0] = 1
|
Net: mprj/io_oeb[11] |Net: \mprj_io_one[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[1] = 1
|
Net: mprj/io_oeb[2] |Net: \mprj_io_analog_en[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_en[1] = 1
|
Net: mprj/io_oeb[20] |Net: \mprj_io_analog_pol[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_pol[1] = 1
|
Net: mprj/io_oeb[9] |Net: \mprj_io_analog_sel[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_sel[1] = 1
|
Net: mprj/io_oeb[18] |Net: \mprj_io_holdover[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_holdover[1] = 1
|
Net: mprj/io_oeb[16] |Net: \mprj_io_ib_mode_sel[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_ib_mode_sel[1] = 1
|
Net: mprj/io_oeb[7] |Net: \mprj_io_inp_dis[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_inp_dis[1] = 1
|
Net: mprj/io_oeb[24] |Net: \mprj_io_out[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_out[1] = 1
|
Net: mprj/io_oeb[0] |Net: \mprj_io_oeb[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_oeb[1] = 1
|
Net: mprj/io_oeb[25] |Net: \mprj_io_slow_sel[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_slow_sel[1] = 1
|
Net: mprj/io_oeb[1] |Net: \mprj_io_vtrip_sel[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_vtrip_sel[1] = 1
|
Net: mprj/io_oeb[26] |Net: \user_io_in[1]
sky130_fd_sc_hd__mux2_4/A0 = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | user_analog_project_wrapper/io_in[1] = 1
|
Net: mprj/io_out[14] |Net: \mprj_io_dm[5]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[5] = 1
|
Net: mprj/io_out[5] |Net: \mprj_io_dm[4]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[4] = 1
|
Net: mprj/io_out[24] |Net: \mprj_io_dm[3]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[3] = 1
|
Net: mprj/io_out[23] |Net: \mprj_io_one[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[24] = 1
|
Net: mprj/io_out[12] |Net: \mprj_io_analog_en[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_en[24] = 1
|
Net: mprj/io_out[3] |Net: \mprj_io_analog_pol[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_pol[24] = 1
|
Net: mprj/io_out[21] |Net: \mprj_io_analog_sel[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_sel[24] = 1
|
Net: mprj/io_out[10] |Net: \mprj_io_holdover[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_holdover[24] = 1
|
Net: mprj/io_out[8] |Net: \mprj_io_ib_mode_sel[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_ib_mode_sel[24] = 1
|
Net: mprj/io_out[19] |Net: \mprj_io_inp_dis[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_inp_dis[24] = 1
|
Net: mprj/io_out[17] |Net: \mprj_io_out[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_out[24] = 1
|
Net: mprj/io_out[0] |Net: \mprj_io_oeb[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_oeb[24] = 1
|
Net: mprj/io_out[15] |Net: \mprj_io_slow_sel[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_slow_sel[24] = 1
|
Net: mprj/io_out[6] |Net: \mprj_io_vtrip_sel[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_vtrip_sel[24] = 1
|
Net: mprj/io_out[25] |Net: \user_io_in[24]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | user_analog_project_wrapper/io_in[24] =
|
Net: mprj/io_out[13] |Net: \mprj_io_dm[74]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[74] = 1
|
Net: mprj/io_out[4] |Net: \mprj_io_dm[73]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[73] = 1
|
Net: mprj/io_out[22] |Net: \mprj_io_dm[72]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_dm[72] = 1
|
Net: mprj/io_out[11] |Net: \mprj_io_one[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[25] = 1
|
Net: mprj/io_out[2] |Net: \mprj_io_analog_en[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_en[25] = 1
|
Net: mprj/io_out[20] |Net: \mprj_io_analog_pol[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_pol[25] = 1
|
Net: mprj/io_out[9] |Net: \mprj_io_analog_sel[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_analog_sel[25] = 1
|
Net: mprj/io_out[18] |Net: \mprj_io_holdover[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_holdover[25] = 1
|
Net: mprj/io_out[1] |Net: \mprj_io_ib_mode_sel[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_ib_mode_sel[25] = 1
|
Net: mprj/io_out[16] |Net: \mprj_io_inp_dis[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_inp_dis[25] = 1
|
Net: mprj/io_out[7] |Net: \mprj_io_out[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_out[25] = 1
|
Net: mprj/io_out[26] |Net: \mprj_io_oeb[25]
sky130_fd_sc_hd__nand2b_2/B = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_oeb[25] = 1
|
Net: padframe/clock_core |Net: \mprj_io_slow_sel[25]
chip_io_alt/clock_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/in_s[2] = 1 | chip_io_alt/mprj_io_slow_sel[25] = 1
|
Net: padframe/por |Net: \mprj_io_vtrip_sel[25]
chip_io_alt/por = 1 | sky130_fd_sc_hd__buf_16/X = 1
mgmt_core_wrapper/por_l_out = 1 | chip_io_alt/mprj_io_vtrip_sel[25] = 1
|
Net: padframe/flash_io0_di_core |Net: \user_io_in[25]
chip_io_alt/flash_io0_di_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/in_s[0] = 1 | user_analog_project_wrapper/io_in[25] =
|
Net: padframe/flash_io0_do_core |Net: \mprj_io_dm[77]
chip_io_alt/flash_io0_do_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/out_s[1] = 1 | chip_io_alt/mprj_io_dm[77] = 1
|
Net: padframe/flash_io0_ieb_core |Net: \mprj_io_dm[76]
chip_io_alt/flash_io0_ieb_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/out_s[3] = 1 | chip_io_alt/mprj_io_dm[76] = 1
|
Net: padframe/flash_io0_oeb_core |Net: \mprj_io_dm[75]
chip_io_alt/flash_io0_oeb_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/out_s[5] = 1 | chip_io_alt/mprj_io_dm[75] = 1
|
Net: padframe/flash_io1_di_core |Net: \mprj_io_one[26]
chip_io_alt/flash_io1_di_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/in_s[1] = 1 | chip_io_alt/mprj_io_one[26] = 1
|
Net: padframe/flash_io1_do_core |Net: \mprj_io_analog_en[26]
chip_io_alt/flash_io1_do_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/out_s[0] = 1 | chip_io_alt/mprj_io_analog_en[26] = 1
|
Net: padframe/flash_io1_ieb_core |Net: \mprj_io_analog_pol[26]
chip_io_alt/flash_io1_ieb_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/out_s[2] = 1 | chip_io_alt/mprj_io_analog_pol[26] = 1
|
Net: padframe/flash_io1_oeb_core |Net: \mprj_io_analog_sel[26]
chip_io_alt/flash_io1_oeb_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
buff_flash_clkrst/out_s[4] = 1 | chip_io_alt/mprj_io_analog_sel[26] = 1
|
Net: soc/gpio_in_pad |Net: \mprj_io_holdover[26]
chip_io_alt/gpio_in_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
mgmt_core_wrapper/gpio_in_pad = 1 | chip_io_alt/mprj_io_holdover[26] = 1
|
Net: soc/gpio_inenb_pad |Net: \mprj_io_ib_mode_sel[26]
chip_io_alt/gpio_inenb_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
mgmt_core_wrapper/gpio_inenb_pad = 1 | chip_io_alt/mprj_io_ib_mode_sel[26] = 1
|
Net: soc/gpio_mode0_pad |Net: \mprj_io_inp_dis[26]
chip_io_alt/gpio_mode0_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
mgmt_core_wrapper/gpio_mode0_pad = 1 | chip_io_alt/mprj_io_inp_dis[26] = 1
|
Net: soc/gpio_out_pad |Net: \mprj_io_out[26]
chip_io_alt/gpio_out_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
mgmt_core_wrapper/gpio_out_pad = 1 | chip_io_alt/mprj_io_out[26] = 1
|
Net: soc/gpio_outenb_pad |Net: \mprj_io_oeb[26]
chip_io_alt/gpio_outenb_core = 1 | sky130_fd_sc_hd__buf_16/X = 1
mgmt_core_wrapper/gpio_outenb_pad = 1 | chip_io_alt/mprj_io_oeb[26] = 1
|
Net: padframe/mprj_io_analog_en[0] |Net: \mprj_io_slow_sel[26]
chip_io_alt/mprj_io_analog_en[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[26] = 1
|
Net: padframe/mprj_io_analog_pol[0] |Net: \mprj_io_vtrip_sel[26]
chip_io_alt/mprj_io_analog_pol[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[26] = 1
|
Net: padframe/mprj_io_analog_sel[0] |Net: \user_io_in[26]
chip_io_alt/mprj_io_analog_sel[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[26] =
|
Net: padframe/mprj_io_dm[0] |Net: \mprj_io_dm[80]
chip_io_alt/mprj_io_dm[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[80] = 1
|
Net: padframe/mprj_io_dm[1] |Net: \mprj_io_dm[79]
chip_io_alt/mprj_io_dm[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[79] = 1
|
Net: padframe/mprj_io_dm[2] |Net: \mprj_io_dm[78]
chip_io_alt/mprj_io_dm[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[78] = 1
|
Net: padframe/mprj_io_holdover[0] |Net: \mprj_io_analog_en[8]
chip_io_alt/mprj_io_holdover[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[8] = 1
|
Net: padframe/mprj_io_ib_mode_sel[0] |Net: \mprj_io_analog_pol[8]
chip_io_alt/mprj_io_ib_mode_sel[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[8] = 1
|
Net: padframe/mprj_io_inp_dis[0] |Net: \mprj_io_analog_sel[8]
chip_io_alt/mprj_io_inp_dis[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[8] = 1
|
Net: padframe/mprj_io_oeb[0] |Net: \mprj_io_holdover[8]
chip_io_alt/mprj_io_oeb[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[8] = 1
|
Net: padframe/mprj_io_out[0] |Net: \mprj_io_ib_mode_sel[8]
chip_io_alt/mprj_io_out[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[8] = 1
|
Net: padframe/mprj_io_slow_sel[0] |Net: \mprj_io_inp_dis[8]
chip_io_alt/mprj_io_slow_sel[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[8] = 1
|
Net: padframe/mprj_io_vtrip_sel[0] |Net: \mprj_io_out[8]
chip_io_alt/mprj_io_vtrip_sel[0] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[8] = 1
|
Net: padframe/mprj_io_analog_en[10] |Net: \mprj_io_oeb[8]
chip_io_alt/mprj_io_analog_en[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[8] = 1
|
Net: padframe/mprj_io_analog_pol[10] |Net: \mprj_io_slow_sel[8]
chip_io_alt/mprj_io_analog_pol[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[8] = 1
|
Net: padframe/mprj_io_analog_sel[10] |Net: \mprj_io_vtrip_sel[8]
chip_io_alt/mprj_io_analog_sel[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[8] = 1
|
Net: padframe/mprj_io_dm[30] |Net: \user_io_in[8]
chip_io_alt/mprj_io_dm[30] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[8] = 1
|
Net: padframe/mprj_io_dm[31] |Net: \mprj_io_dm[26]
chip_io_alt/mprj_io_dm[31] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[26] = 1
|
Net: padframe/mprj_io_dm[32] |Net: \mprj_io_dm[25]
chip_io_alt/mprj_io_dm[32] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[25] = 1
|
Net: padframe/mprj_io_holdover[10] |Net: \mprj_io_dm[24]
chip_io_alt/mprj_io_holdover[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[24] = 1
|
Net: padframe/mprj_io_ib_mode_sel[10] |Net: \mprj_io_analog_en[9]
chip_io_alt/mprj_io_ib_mode_sel[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[9] = 1
|
Net: padframe/mprj_io_inp_dis[10] |Net: \mprj_io_analog_pol[9]
chip_io_alt/mprj_io_inp_dis[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[9] = 1
|
Net: padframe/mprj_io_oeb[10] |Net: \mprj_io_analog_sel[9]
chip_io_alt/mprj_io_oeb[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[9] = 1
|
Net: padframe/mprj_io_out[10] |Net: \mprj_io_holdover[9]
chip_io_alt/mprj_io_out[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[9] = 1
|
Net: padframe/mprj_io_slow_sel[10] |Net: \mprj_io_ib_mode_sel[9]
chip_io_alt/mprj_io_slow_sel[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[9] = 1
|
Net: padframe/mprj_io_vtrip_sel[10] |Net: \mprj_io_inp_dis[9]
chip_io_alt/mprj_io_vtrip_sel[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[9] = 1
|
Net: padframe/mprj_io_analog_en[11] |Net: \mprj_io_out[9]
chip_io_alt/mprj_io_analog_en[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[9] = 1
|
Net: padframe/mprj_io_analog_pol[11] |Net: \mprj_io_oeb[9]
chip_io_alt/mprj_io_analog_pol[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[9] = 1
|
Net: padframe/mprj_io_analog_sel[11] |Net: \mprj_io_slow_sel[9]
chip_io_alt/mprj_io_analog_sel[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[9] = 1
|
Net: padframe/mprj_io_dm[33] |Net: \mprj_io_vtrip_sel[9]
chip_io_alt/mprj_io_dm[33] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[9] = 1
|
Net: padframe/mprj_io_dm[34] |Net: \user_io_in[9]
chip_io_alt/mprj_io_dm[34] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[9] = 1
|
Net: padframe/mprj_io_dm[35] |Net: \mprj_io_dm[29]
chip_io_alt/mprj_io_dm[35] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[29] = 1
|
Net: padframe/mprj_io_holdover[11] |Net: \mprj_io_dm[28]
chip_io_alt/mprj_io_holdover[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[28] = 1
|
Net: padframe/mprj_io_ib_mode_sel[11] |Net: \mprj_io_dm[27]
chip_io_alt/mprj_io_ib_mode_sel[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[27] = 1
|
Net: padframe/mprj_io_inp_dis[11] |Net: \mprj_io_analog_en[10]
chip_io_alt/mprj_io_inp_dis[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[10] = 1
|
Net: padframe/mprj_io_oeb[11] |Net: \mprj_io_analog_pol[10]
chip_io_alt/mprj_io_oeb[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[10] = 1
|
Net: padframe/mprj_io_out[11] |Net: \mprj_io_analog_sel[10]
chip_io_alt/mprj_io_out[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[10] = 1
|
Net: padframe/mprj_io_slow_sel[11] |Net: \mprj_io_holdover[10]
chip_io_alt/mprj_io_slow_sel[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[10] = 1
|
Net: padframe/mprj_io_vtrip_sel[11] |Net: \mprj_io_ib_mode_sel[10]
chip_io_alt/mprj_io_vtrip_sel[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[10] = 1
|
Net: padframe/mprj_io_analog_en[12] |Net: \mprj_io_inp_dis[10]
chip_io_alt/mprj_io_analog_en[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[10] = 1
|
Net: padframe/mprj_io_analog_pol[12] |Net: \mprj_io_out[10]
chip_io_alt/mprj_io_analog_pol[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[10] = 1
|
Net: padframe/mprj_io_analog_sel[12] |Net: \mprj_io_oeb[10]
chip_io_alt/mprj_io_analog_sel[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[10] = 1
|
Net: padframe/mprj_io_dm[36] |Net: \mprj_io_slow_sel[10]
chip_io_alt/mprj_io_dm[36] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[10] = 1
|
Net: padframe/mprj_io_dm[37] |Net: \mprj_io_vtrip_sel[10]
chip_io_alt/mprj_io_dm[37] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[10] = 1
|
Net: padframe/mprj_io_dm[38] |Net: \user_io_in[10]
chip_io_alt/mprj_io_dm[38] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[10] =
|
Net: padframe/mprj_io_holdover[12] |Net: \mprj_io_dm[32]
chip_io_alt/mprj_io_holdover[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[32] = 1
|
Net: padframe/mprj_io_ib_mode_sel[12] |Net: \mprj_io_dm[31]
chip_io_alt/mprj_io_ib_mode_sel[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[31] = 1
|
Net: padframe/mprj_io_inp_dis[12] |Net: \mprj_io_dm[30]
chip_io_alt/mprj_io_inp_dis[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[30] = 1
|
Net: padframe/mprj_io_oeb[12] |Net: \mprj_io_analog_en[11]
chip_io_alt/mprj_io_oeb[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[11] = 1
|
Net: padframe/mprj_io_out[12] |Net: \mprj_io_analog_pol[11]
chip_io_alt/mprj_io_out[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[11] = 1
|
Net: padframe/mprj_io_slow_sel[12] |Net: \mprj_io_analog_sel[11]
chip_io_alt/mprj_io_slow_sel[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[11] = 1
|
Net: padframe/mprj_io_vtrip_sel[12] |Net: \mprj_io_holdover[11]
chip_io_alt/mprj_io_vtrip_sel[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[11] = 1
|
Net: padframe/mprj_io_analog_en[13] |Net: \mprj_io_ib_mode_sel[11]
chip_io_alt/mprj_io_analog_en[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[11] = 1
|
Net: padframe/mprj_io_analog_pol[13] |Net: \mprj_io_inp_dis[11]
chip_io_alt/mprj_io_analog_pol[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[11] = 1
|
Net: padframe/mprj_io_analog_sel[13] |Net: \mprj_io_out[11]
chip_io_alt/mprj_io_analog_sel[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[11] = 1
|
Net: padframe/mprj_io_dm[39] |Net: \mprj_io_oeb[11]
chip_io_alt/mprj_io_dm[39] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[11] = 1
|
Net: padframe/mprj_io_dm[40] |Net: \mprj_io_slow_sel[11]
chip_io_alt/mprj_io_dm[40] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[11] = 1
|
Net: padframe/mprj_io_dm[41] |Net: \mprj_io_vtrip_sel[11]
chip_io_alt/mprj_io_dm[41] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[11] = 1
|
Net: padframe/mprj_io_holdover[13] |Net: \user_io_in[11]
chip_io_alt/mprj_io_holdover[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[11] =
|
Net: padframe/mprj_io_ib_mode_sel[13] |Net: \mprj_io_dm[35]
chip_io_alt/mprj_io_ib_mode_sel[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[35] = 1
|
Net: padframe/mprj_io_inp_dis[13] |Net: \mprj_io_dm[34]
chip_io_alt/mprj_io_inp_dis[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[34] = 1
|
Net: padframe/mprj_io_oeb[13] |Net: \mprj_io_dm[33]
chip_io_alt/mprj_io_oeb[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[33] = 1
|
Net: padframe/mprj_io_out[13] |Net: \mprj_io_analog_en[12]
chip_io_alt/mprj_io_out[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[12] = 1
|
Net: padframe/mprj_io_slow_sel[13] |Net: \mprj_io_analog_pol[12]
chip_io_alt/mprj_io_slow_sel[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[12] = 1
|
Net: padframe/mprj_io_vtrip_sel[13] |Net: \mprj_io_analog_sel[12]
chip_io_alt/mprj_io_vtrip_sel[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[12] = 1
|
Net: padframe/mprj_io_analog_en[1] |Net: \mprj_io_holdover[12]
chip_io_alt/mprj_io_analog_en[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[12] = 1
|
Net: padframe/mprj_io_analog_pol[1] |Net: \mprj_io_ib_mode_sel[12]
chip_io_alt/mprj_io_analog_pol[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[12] = 1
|
Net: padframe/mprj_io_analog_sel[1] |Net: \mprj_io_inp_dis[12]
chip_io_alt/mprj_io_analog_sel[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[12] = 1
|
Net: padframe/mprj_io_dm[3] |Net: \mprj_io_out[12]
chip_io_alt/mprj_io_dm[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[12] = 1
|
Net: padframe/mprj_io_dm[4] |Net: \mprj_io_oeb[12]
chip_io_alt/mprj_io_dm[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[12] = 1
|
Net: padframe/mprj_io_dm[5] |Net: \mprj_io_slow_sel[12]
chip_io_alt/mprj_io_dm[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[12] = 1
|
Net: padframe/mprj_io_holdover[1] |Net: \mprj_io_vtrip_sel[12]
chip_io_alt/mprj_io_holdover[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[12] = 1
|
Net: padframe/mprj_io_ib_mode_sel[1] |Net: \user_io_in[12]
chip_io_alt/mprj_io_ib_mode_sel[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[12] =
|
Net: padframe/mprj_io_inp_dis[1] |Net: \mprj_io_dm[38]
chip_io_alt/mprj_io_inp_dis[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[38] = 1
|
Net: padframe/mprj_io_oeb[1] |Net: \mprj_io_dm[37]
chip_io_alt/mprj_io_oeb[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[37] = 1
|
Net: padframe/mprj_io_out[1] |Net: \mprj_io_dm[36]
chip_io_alt/mprj_io_out[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[36] = 1
|
Net: padframe/mprj_io_slow_sel[1] |Net: \mprj_io_analog_en[13]
chip_io_alt/mprj_io_slow_sel[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[13] = 1
|
Net: padframe/mprj_io_vtrip_sel[1] |Net: \mprj_io_analog_pol[13]
chip_io_alt/mprj_io_vtrip_sel[1] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[13] = 1
|
Net: padframe/mprj_io_analog_en[2] |Net: \mprj_io_analog_sel[13]
chip_io_alt/mprj_io_analog_en[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[13] = 1
|
Net: padframe/mprj_io_analog_pol[2] |Net: \mprj_io_holdover[13]
chip_io_alt/mprj_io_analog_pol[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[13] = 1
|
Net: padframe/mprj_io_analog_sel[2] |Net: \mprj_io_ib_mode_sel[13]
chip_io_alt/mprj_io_analog_sel[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[13] = 1
|
Net: padframe/mprj_io_dm[6] |Net: \mprj_io_inp_dis[13]
chip_io_alt/mprj_io_dm[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[13] = 1
|
Net: padframe/mprj_io_dm[7] |Net: \mprj_io_out[13]
chip_io_alt/mprj_io_dm[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[13] = 1
|
Net: padframe/mprj_io_dm[8] |Net: \mprj_io_oeb[13]
chip_io_alt/mprj_io_dm[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[13] = 1
|
Net: padframe/mprj_io_holdover[2] |Net: \mprj_io_slow_sel[13]
chip_io_alt/mprj_io_holdover[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[13] = 1
|
Net: padframe/mprj_io_ib_mode_sel[2] |Net: \mprj_io_vtrip_sel[13]
chip_io_alt/mprj_io_ib_mode_sel[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[13] = 1
|
Net: padframe/mprj_io_inp_dis[2] |Net: \user_io_in[13]
chip_io_alt/mprj_io_inp_dis[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[13] =
|
Net: padframe/mprj_io_oeb[2] |Net: \mprj_io_dm[41]
chip_io_alt/mprj_io_oeb[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[41] = 1
|
Net: padframe/mprj_io_out[2] |Net: \mprj_io_dm[40]
chip_io_alt/mprj_io_out[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[40] = 1
|
Net: padframe/mprj_io_slow_sel[2] |Net: \mprj_io_dm[39]
chip_io_alt/mprj_io_slow_sel[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[39] = 1
|
Net: padframe/mprj_io_vtrip_sel[2] |Net: \mprj_io_analog_en[2]
chip_io_alt/mprj_io_vtrip_sel[2] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[2] = 1
|
Net: padframe/mprj_io_analog_en[3] |Net: \mprj_io_analog_pol[2]
chip_io_alt/mprj_io_analog_en[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[2] = 1
|
Net: padframe/mprj_io_analog_pol[3] |Net: \mprj_io_analog_sel[2]
chip_io_alt/mprj_io_analog_pol[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[2] = 1
|
Net: padframe/mprj_io_analog_sel[3] |Net: \mprj_io_holdover[2]
chip_io_alt/mprj_io_analog_sel[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[2] = 1
|
Net: padframe/mprj_io_dm[10] |Net: \mprj_io_ib_mode_sel[2]
chip_io_alt/mprj_io_dm[10] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[2] = 1
|
Net: padframe/mprj_io_dm[11] |Net: \mprj_io_inp_dis[2]
chip_io_alt/mprj_io_dm[11] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[2] = 1
|
Net: padframe/mprj_io_dm[9] |Net: \mprj_io_out[2]
chip_io_alt/mprj_io_dm[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[2] = 1
|
Net: padframe/mprj_io_holdover[3] |Net: \mprj_io_oeb[2]
chip_io_alt/mprj_io_holdover[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[2] = 1
|
Net: padframe/mprj_io_ib_mode_sel[3] |Net: \mprj_io_slow_sel[2]
chip_io_alt/mprj_io_ib_mode_sel[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[2] = 1
|
Net: padframe/mprj_io_inp_dis[3] |Net: \mprj_io_vtrip_sel[2]
chip_io_alt/mprj_io_inp_dis[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[2] = 1
|
Net: padframe/mprj_io_oeb[3] |Net: \user_io_in[2]
chip_io_alt/mprj_io_oeb[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[2] = 1
|
Net: padframe/mprj_io_out[3] |Net: \mprj_io_dm[8]
chip_io_alt/mprj_io_out[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[8] = 1
|
Net: padframe/mprj_io_slow_sel[3] |Net: \mprj_io_dm[7]
chip_io_alt/mprj_io_slow_sel[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[7] = 1
|
Net: padframe/mprj_io_vtrip_sel[3] |Net: \mprj_io_dm[6]
chip_io_alt/mprj_io_vtrip_sel[3] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[6] = 1
|
Net: padframe/mprj_io_analog_en[4] |Net: \mprj_io_analog_en[3]
chip_io_alt/mprj_io_analog_en[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[3] = 1
|
Net: padframe/mprj_io_analog_pol[4] |Net: \mprj_io_analog_pol[3]
chip_io_alt/mprj_io_analog_pol[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[3] = 1
|
Net: padframe/mprj_io_analog_sel[4] |Net: \mprj_io_analog_sel[3]
chip_io_alt/mprj_io_analog_sel[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[3] = 1
|
Net: padframe/mprj_io_dm[12] |Net: \mprj_io_holdover[3]
chip_io_alt/mprj_io_dm[12] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[3] = 1
|
Net: padframe/mprj_io_dm[13] |Net: \mprj_io_ib_mode_sel[3]
chip_io_alt/mprj_io_dm[13] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[3] = 1
|
Net: padframe/mprj_io_dm[14] |Net: \mprj_io_inp_dis[3]
chip_io_alt/mprj_io_dm[14] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[3] = 1
|
Net: padframe/mprj_io_holdover[4] |Net: \mprj_io_out[3]
chip_io_alt/mprj_io_holdover[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[3] = 1
|
Net: padframe/mprj_io_ib_mode_sel[4] |Net: \mprj_io_oeb[3]
chip_io_alt/mprj_io_ib_mode_sel[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[3] = 1
|
Net: padframe/mprj_io_inp_dis[4] |Net: \mprj_io_slow_sel[3]
chip_io_alt/mprj_io_inp_dis[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[3] = 1
|
Net: padframe/mprj_io_oeb[4] |Net: \mprj_io_vtrip_sel[3]
chip_io_alt/mprj_io_oeb[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[3] = 1
|
Net: padframe/mprj_io_out[4] |Net: \user_io_in[3]
chip_io_alt/mprj_io_out[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[3] = 1
|
Net: padframe/mprj_io_slow_sel[4] |Net: \mprj_io_dm[11]
chip_io_alt/mprj_io_slow_sel[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[11] = 1
|
Net: padframe/mprj_io_vtrip_sel[4] |Net: \mprj_io_dm[10]
chip_io_alt/mprj_io_vtrip_sel[4] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[10] = 1
|
Net: padframe/mprj_io_analog_en[5] |Net: \mprj_io_dm[9]
chip_io_alt/mprj_io_analog_en[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[9] = 1
|
Net: padframe/mprj_io_analog_pol[5] |Net: \mprj_io_analog_en[4]
chip_io_alt/mprj_io_analog_pol[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[4] = 1
|
Net: padframe/mprj_io_analog_sel[5] |Net: \mprj_io_analog_pol[4]
chip_io_alt/mprj_io_analog_sel[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[4] = 1
|
Net: padframe/mprj_io_dm[15] |Net: \mprj_io_analog_sel[4]
chip_io_alt/mprj_io_dm[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[4] = 1
|
Net: padframe/mprj_io_dm[16] |Net: \mprj_io_holdover[4]
chip_io_alt/mprj_io_dm[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[4] = 1
|
Net: padframe/mprj_io_dm[17] |Net: \mprj_io_ib_mode_sel[4]
chip_io_alt/mprj_io_dm[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[4] = 1
|
Net: padframe/mprj_io_holdover[5] |Net: \mprj_io_inp_dis[4]
chip_io_alt/mprj_io_holdover[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[4] = 1
|
Net: padframe/mprj_io_ib_mode_sel[5] |Net: \mprj_io_out[4]
chip_io_alt/mprj_io_ib_mode_sel[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[4] = 1
|
Net: padframe/mprj_io_inp_dis[5] |Net: \mprj_io_oeb[4]
chip_io_alt/mprj_io_inp_dis[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[4] = 1
|
Net: padframe/mprj_io_oeb[5] |Net: \mprj_io_slow_sel[4]
chip_io_alt/mprj_io_oeb[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[4] = 1
|
Net: padframe/mprj_io_out[5] |Net: \mprj_io_vtrip_sel[4]
chip_io_alt/mprj_io_out[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[4] = 1
|
Net: padframe/mprj_io_slow_sel[5] |Net: \user_io_in[4]
chip_io_alt/mprj_io_slow_sel[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[4] = 1
|
Net: padframe/mprj_io_vtrip_sel[5] |Net: \mprj_io_dm[14]
chip_io_alt/mprj_io_vtrip_sel[5] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[14] = 1
|
Net: padframe/mprj_io_analog_en[6] |Net: \mprj_io_dm[13]
chip_io_alt/mprj_io_analog_en[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[13] = 1
|
Net: padframe/mprj_io_analog_pol[6] |Net: \mprj_io_dm[12]
chip_io_alt/mprj_io_analog_pol[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[12] = 1
|
Net: padframe/mprj_io_analog_sel[6] |Net: \mprj_io_analog_en[5]
chip_io_alt/mprj_io_analog_sel[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[5] = 1
|
Net: padframe/mprj_io_dm[18] |Net: \mprj_io_analog_pol[5]
chip_io_alt/mprj_io_dm[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[5] = 1
|
Net: padframe/mprj_io_dm[19] |Net: \mprj_io_analog_sel[5]
chip_io_alt/mprj_io_dm[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[5] = 1
|
Net: padframe/mprj_io_dm[20] |Net: \mprj_io_holdover[5]
chip_io_alt/mprj_io_dm[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[5] = 1
|
Net: padframe/mprj_io_holdover[6] |Net: \mprj_io_ib_mode_sel[5]
chip_io_alt/mprj_io_holdover[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[5] = 1
|
Net: padframe/mprj_io_ib_mode_sel[6] |Net: \mprj_io_inp_dis[5]
chip_io_alt/mprj_io_ib_mode_sel[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[5] = 1
|
Net: padframe/mprj_io_inp_dis[6] |Net: \mprj_io_out[5]
chip_io_alt/mprj_io_inp_dis[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[5] = 1
|
Net: padframe/mprj_io_oeb[6] |Net: \mprj_io_oeb[5]
chip_io_alt/mprj_io_oeb[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[5] = 1
|
Net: padframe/mprj_io_out[6] |Net: \mprj_io_slow_sel[5]
chip_io_alt/mprj_io_out[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[5] = 1
|
Net: padframe/mprj_io_slow_sel[6] |Net: \mprj_io_vtrip_sel[5]
chip_io_alt/mprj_io_slow_sel[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[5] = 1
|
Net: padframe/mprj_io_vtrip_sel[6] |Net: \user_io_in[5]
chip_io_alt/mprj_io_vtrip_sel[6] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[5] = 1
|
Net: padframe/mprj_io_analog_en[7] |Net: \mprj_io_dm[17]
chip_io_alt/mprj_io_analog_en[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[17] = 1
|
Net: padframe/mprj_io_analog_pol[7] |Net: \mprj_io_dm[16]
chip_io_alt/mprj_io_analog_pol[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[16] = 1
|
Net: padframe/mprj_io_analog_sel[7] |Net: \mprj_io_dm[15]
chip_io_alt/mprj_io_analog_sel[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[15] = 1
|
Net: padframe/mprj_io_dm[21] |Net: \mprj_io_analog_en[6]
chip_io_alt/mprj_io_dm[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[6] = 1
|
Net: padframe/mprj_io_dm[22] |Net: \mprj_io_analog_pol[6]
chip_io_alt/mprj_io_dm[22] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[6] = 1
|
Net: padframe/mprj_io_dm[23] |Net: \mprj_io_analog_sel[6]
chip_io_alt/mprj_io_dm[23] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[6] = 1
|
Net: padframe/mprj_io_holdover[7] |Net: \mprj_io_holdover[6]
chip_io_alt/mprj_io_holdover[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[6] = 1
|
Net: padframe/mprj_io_ib_mode_sel[7] |Net: \mprj_io_ib_mode_sel[6]
chip_io_alt/mprj_io_ib_mode_sel[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[6] = 1
|
Net: padframe/mprj_io_inp_dis[7] |Net: \mprj_io_inp_dis[6]
chip_io_alt/mprj_io_inp_dis[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[6] = 1
|
Net: padframe/mprj_io_oeb[7] |Net: \mprj_io_out[6]
chip_io_alt/mprj_io_oeb[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[6] = 1
|
Net: padframe/mprj_io_out[7] |Net: \mprj_io_oeb[6]
chip_io_alt/mprj_io_out[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[6] = 1
|
Net: padframe/mprj_io_slow_sel[7] |Net: \mprj_io_slow_sel[6]
chip_io_alt/mprj_io_slow_sel[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[6] = 1
|
Net: padframe/mprj_io_vtrip_sel[7] |Net: \mprj_io_vtrip_sel[6]
chip_io_alt/mprj_io_vtrip_sel[7] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[6] = 1
|
Net: padframe/mprj_io_analog_en[8] |Net: \user_io_in[6]
chip_io_alt/mprj_io_analog_en[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[6] = 1
|
Net: padframe/mprj_io_analog_pol[8] |Net: \mprj_io_dm[20]
chip_io_alt/mprj_io_analog_pol[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[20] = 1
|
Net: padframe/mprj_io_analog_sel[8] |Net: \mprj_io_dm[19]
chip_io_alt/mprj_io_analog_sel[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[19] = 1
|
Net: padframe/mprj_io_dm[24] |Net: \mprj_io_dm[18]
chip_io_alt/mprj_io_dm[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[18] = 1
|
Net: padframe/mprj_io_dm[25] |Net: \mprj_io_analog_en[7]
chip_io_alt/mprj_io_dm[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[7] = 1
|
Net: padframe/mprj_io_dm[26] |Net: \mprj_io_analog_pol[7]
chip_io_alt/mprj_io_dm[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[7] = 1
|
Net: padframe/mprj_io_holdover[8] |Net: \mprj_io_analog_sel[7]
chip_io_alt/mprj_io_holdover[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[7] = 1
|
Net: padframe/mprj_io_ib_mode_sel[8] |Net: \mprj_io_holdover[7]
chip_io_alt/mprj_io_ib_mode_sel[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[7] = 1
|
Net: padframe/mprj_io_inp_dis[8] |Net: \mprj_io_ib_mode_sel[7]
chip_io_alt/mprj_io_inp_dis[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[7] = 1
|
Net: padframe/mprj_io_oeb[8] |Net: \mprj_io_inp_dis[7]
chip_io_alt/mprj_io_oeb[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[7] = 1
|
Net: padframe/mprj_io_out[8] |Net: \mprj_io_out[7]
chip_io_alt/mprj_io_out[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[7] = 1
|
Net: padframe/mprj_io_slow_sel[8] |Net: \mprj_io_oeb[7]
chip_io_alt/mprj_io_slow_sel[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[7] = 1
|
Net: padframe/mprj_io_vtrip_sel[8] |Net: \mprj_io_slow_sel[7]
chip_io_alt/mprj_io_vtrip_sel[8] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[7] = 1
|
Net: padframe/mprj_io_analog_en[9] |Net: \mprj_io_vtrip_sel[7]
chip_io_alt/mprj_io_analog_en[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[7] = 1
|
Net: padframe/mprj_io_analog_pol[9] |Net: \user_io_in[7]
chip_io_alt/mprj_io_analog_pol[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[7] = 1
|
Net: padframe/mprj_io_analog_sel[9] |Net: \mprj_io_dm[23]
chip_io_alt/mprj_io_analog_sel[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[23] = 1
|
Net: padframe/mprj_io_dm[27] |Net: \mprj_io_dm[22]
chip_io_alt/mprj_io_dm[27] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[22] = 1
|
Net: padframe/mprj_io_dm[28] |Net: \mprj_io_dm[21]
chip_io_alt/mprj_io_dm[28] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[21] = 1
|
Net: padframe/mprj_io_dm[29] |Net: \mprj_io_analog_en[14]
chip_io_alt/mprj_io_dm[29] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[14] = 1
|
Net: padframe/mprj_io_holdover[9] |Net: \mprj_io_analog_pol[14]
chip_io_alt/mprj_io_holdover[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[14] = 1
|
Net: padframe/mprj_io_ib_mode_sel[9] |Net: \mprj_io_analog_sel[14]
chip_io_alt/mprj_io_ib_mode_sel[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[14] = 1
|
Net: padframe/mprj_io_inp_dis[9] |Net: \mprj_io_holdover[14]
chip_io_alt/mprj_io_inp_dis[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[14] = 1
|
Net: padframe/mprj_io_oeb[9] |Net: \mprj_io_ib_mode_sel[14]
chip_io_alt/mprj_io_oeb[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[14] = 1
|
Net: padframe/mprj_io_out[9] |Net: \mprj_io_inp_dis[14]
chip_io_alt/mprj_io_out[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[14] = 1
|
Net: padframe/mprj_io_slow_sel[9] |Net: \mprj_io_out[14]
chip_io_alt/mprj_io_slow_sel[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[14] = 1
|
Net: padframe/mprj_io_vtrip_sel[9] |Net: \mprj_io_oeb[14]
chip_io_alt/mprj_io_vtrip_sel[9] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[14] = 1
|
Net: padframe/mprj_io_analog_en[24] |Net: \mprj_io_slow_sel[14]
chip_io_alt/mprj_io_analog_en[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[14] = 1
|
Net: padframe/mprj_io_analog_pol[24] |Net: \mprj_io_vtrip_sel[14]
chip_io_alt/mprj_io_analog_pol[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[14] = 1
|
Net: padframe/mprj_io_analog_sel[24] |Net: \user_io_in[14]
chip_io_alt/mprj_io_analog_sel[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[14] =
|
Net: padframe/mprj_io_dm[72] |Net: \mprj_io_dm[44]
chip_io_alt/mprj_io_dm[72] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[44] = 1
|
Net: padframe/mprj_io_dm[73] |Net: \mprj_io_dm[43]
chip_io_alt/mprj_io_dm[73] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[43] = 1
|
Net: padframe/mprj_io_dm[74] |Net: \mprj_io_dm[42]
chip_io_alt/mprj_io_dm[74] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[42] = 1
|
Net: padframe/mprj_io_holdover[24] |Net: \mprj_io_analog_en[15]
chip_io_alt/mprj_io_holdover[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[15] = 1
|
Net: padframe/mprj_io_ib_mode_sel[24] |Net: \mprj_io_analog_pol[15]
chip_io_alt/mprj_io_ib_mode_sel[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[15] = 1
|
Net: padframe/mprj_io_inp_dis[24] |Net: \mprj_io_analog_sel[15]
chip_io_alt/mprj_io_inp_dis[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[15] = 1
|
Net: padframe/mprj_io_oeb[24] |Net: \mprj_io_holdover[15]
chip_io_alt/mprj_io_oeb[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[15] = 1
|
Net: padframe/mprj_io_out[24] |Net: \mprj_io_ib_mode_sel[15]
chip_io_alt/mprj_io_out[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[15] = 1
|
Net: padframe/mprj_io_slow_sel[24] |Net: \mprj_io_inp_dis[15]
chip_io_alt/mprj_io_slow_sel[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[15] = 1
|
Net: padframe/mprj_io_vtrip_sel[24] |Net: \mprj_io_out[15]
chip_io_alt/mprj_io_vtrip_sel[24] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[15] = 1
|
Net: padframe/mprj_io_analog_en[25] |Net: \mprj_io_oeb[15]
chip_io_alt/mprj_io_analog_en[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[15] = 1
|
Net: padframe/mprj_io_analog_pol[25] |Net: \mprj_io_slow_sel[15]
chip_io_alt/mprj_io_analog_pol[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[15] = 1
|
Net: padframe/mprj_io_analog_sel[25] |Net: \mprj_io_vtrip_sel[15]
chip_io_alt/mprj_io_analog_sel[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[15] = 1
|
Net: padframe/mprj_io_dm[75] |Net: \user_io_in[15]
chip_io_alt/mprj_io_dm[75] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[15] =
|
Net: padframe/mprj_io_dm[76] |Net: \mprj_io_dm[47]
chip_io_alt/mprj_io_dm[76] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[47] = 1
|
Net: padframe/mprj_io_dm[77] |Net: \mprj_io_dm[46]
chip_io_alt/mprj_io_dm[77] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[46] = 1
|
Net: padframe/mprj_io_holdover[25] |Net: \mprj_io_dm[45]
chip_io_alt/mprj_io_holdover[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[45] = 1
|
Net: padframe/mprj_io_ib_mode_sel[25] |Net: \mprj_io_analog_en[16]
chip_io_alt/mprj_io_ib_mode_sel[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[16] = 1
|
Net: padframe/mprj_io_inp_dis[25] |Net: \mprj_io_analog_pol[16]
chip_io_alt/mprj_io_inp_dis[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[16] = 1
|
Net: padframe/mprj_io_oeb[25] |Net: \mprj_io_analog_sel[16]
chip_io_alt/mprj_io_oeb[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[16] = 1
|
Net: padframe/mprj_io_out[25] |Net: \mprj_io_holdover[16]
chip_io_alt/mprj_io_out[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[16] = 1
|
Net: padframe/mprj_io_slow_sel[25] |Net: \mprj_io_ib_mode_sel[16]
chip_io_alt/mprj_io_slow_sel[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[16] = 1
|
Net: padframe/mprj_io_vtrip_sel[25] |Net: \mprj_io_inp_dis[16]
chip_io_alt/mprj_io_vtrip_sel[25] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[16] = 1
|
Net: padframe/mprj_io_analog_en[26] |Net: \mprj_io_out[16]
chip_io_alt/mprj_io_analog_en[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[16] = 1
|
Net: padframe/mprj_io_analog_pol[26] |Net: \mprj_io_oeb[16]
chip_io_alt/mprj_io_analog_pol[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[16] = 1
|
Net: padframe/mprj_io_analog_sel[26] |Net: \mprj_io_slow_sel[16]
chip_io_alt/mprj_io_analog_sel[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[16] = 1
|
Net: padframe/mprj_io_dm[78] |Net: \mprj_io_vtrip_sel[16]
chip_io_alt/mprj_io_dm[78] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[16] = 1
|
Net: padframe/mprj_io_dm[79] |Net: \user_io_in[16]
chip_io_alt/mprj_io_dm[79] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[16] =
|
Net: padframe/mprj_io_dm[80] |Net: \mprj_io_dm[50]
chip_io_alt/mprj_io_dm[80] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[50] = 1
|
Net: padframe/mprj_io_holdover[26] |Net: \mprj_io_dm[49]
chip_io_alt/mprj_io_holdover[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[49] = 1
|
Net: padframe/mprj_io_ib_mode_sel[26] |Net: \mprj_io_dm[48]
chip_io_alt/mprj_io_ib_mode_sel[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[48] = 1
|
Net: padframe/mprj_io_inp_dis[26] |Net: \mprj_io_analog_en[17]
chip_io_alt/mprj_io_inp_dis[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[17] = 1
|
Net: padframe/mprj_io_oeb[26] |Net: \mprj_io_analog_pol[17]
chip_io_alt/mprj_io_oeb[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[17] = 1
|
Net: padframe/mprj_io_out[26] |Net: \mprj_io_analog_sel[17]
chip_io_alt/mprj_io_out[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[17] = 1
|
Net: padframe/mprj_io_slow_sel[26] |Net: \mprj_io_holdover[17]
chip_io_alt/mprj_io_slow_sel[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[17] = 1
|
Net: padframe/mprj_io_vtrip_sel[26] |Net: \mprj_io_ib_mode_sel[17]
chip_io_alt/mprj_io_vtrip_sel[26] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[17] = 1
|
Net: padframe/mprj_io_analog_en[15] |Net: \mprj_io_inp_dis[17]
chip_io_alt/mprj_io_analog_en[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[17] = 1
|
Net: padframe/mprj_io_analog_pol[15] |Net: \mprj_io_out[17]
chip_io_alt/mprj_io_analog_pol[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[17] = 1
|
Net: padframe/mprj_io_analog_sel[15] |Net: \mprj_io_oeb[17]
chip_io_alt/mprj_io_analog_sel[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[17] = 1
|
Net: padframe/mprj_io_dm[45] |Net: \mprj_io_slow_sel[17]
chip_io_alt/mprj_io_dm[45] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[17] = 1
|
Net: padframe/mprj_io_dm[46] |Net: \mprj_io_vtrip_sel[17]
chip_io_alt/mprj_io_dm[46] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[17] = 1
|
Net: padframe/mprj_io_dm[47] |Net: \user_io_in[17]
chip_io_alt/mprj_io_dm[47] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[17] =
|
Net: padframe/mprj_io_holdover[15] |Net: \mprj_io_dm[53]
chip_io_alt/mprj_io_holdover[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[53] = 1
|
Net: padframe/mprj_io_ib_mode_sel[15] |Net: \mprj_io_dm[52]
chip_io_alt/mprj_io_ib_mode_sel[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[52] = 1
|
Net: padframe/mprj_io_inp_dis[15] |Net: \mprj_io_dm[51]
chip_io_alt/mprj_io_inp_dis[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[51] = 1
|
Net: padframe/mprj_io_oeb[15] |Net: \mprj_io_analog_en[18]
chip_io_alt/mprj_io_oeb[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[18] = 1
|
Net: padframe/mprj_io_out[15] |Net: \mprj_io_analog_pol[18]
chip_io_alt/mprj_io_out[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[18] = 1
|
Net: padframe/mprj_io_slow_sel[15] |Net: \mprj_io_analog_sel[18]
chip_io_alt/mprj_io_slow_sel[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[18] = 1
|
Net: padframe/mprj_io_vtrip_sel[15] |Net: \mprj_io_holdover[18]
chip_io_alt/mprj_io_vtrip_sel[15] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[18] = 1
|
Net: padframe/mprj_io_analog_en[16] |Net: \mprj_io_ib_mode_sel[18]
chip_io_alt/mprj_io_analog_en[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[18] = 1
|
Net: padframe/mprj_io_analog_pol[16] |Net: \mprj_io_inp_dis[18]
chip_io_alt/mprj_io_analog_pol[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[18] = 1
|
Net: padframe/mprj_io_analog_sel[16] |Net: \mprj_io_out[18]
chip_io_alt/mprj_io_analog_sel[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[18] = 1
|
Net: padframe/mprj_io_dm[48] |Net: \mprj_io_oeb[18]
chip_io_alt/mprj_io_dm[48] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[18] = 1
|
Net: padframe/mprj_io_dm[49] |Net: \mprj_io_slow_sel[18]
chip_io_alt/mprj_io_dm[49] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[18] = 1
|
Net: padframe/mprj_io_dm[50] |Net: \mprj_io_vtrip_sel[18]
chip_io_alt/mprj_io_dm[50] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[18] = 1
|
Net: padframe/mprj_io_holdover[16] |Net: \user_io_in[18]
chip_io_alt/mprj_io_holdover[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[18] =
|
Net: padframe/mprj_io_ib_mode_sel[16] |Net: \mprj_io_dm[56]
chip_io_alt/mprj_io_ib_mode_sel[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[56] = 1
|
Net: padframe/mprj_io_inp_dis[16] |Net: \mprj_io_dm[55]
chip_io_alt/mprj_io_inp_dis[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[55] = 1
|
Net: padframe/mprj_io_oeb[16] |Net: \mprj_io_dm[54]
chip_io_alt/mprj_io_oeb[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[54] = 1
|
Net: padframe/mprj_io_out[16] |Net: \mprj_io_analog_en[19]
chip_io_alt/mprj_io_out[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[19] = 1
|
Net: padframe/mprj_io_slow_sel[16] |Net: \mprj_io_analog_pol[19]
chip_io_alt/mprj_io_slow_sel[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[19] = 1
|
Net: padframe/mprj_io_vtrip_sel[16] |Net: \mprj_io_analog_sel[19]
chip_io_alt/mprj_io_vtrip_sel[16] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[19] = 1
|
Net: padframe/mprj_io_analog_en[17] |Net: \mprj_io_holdover[19]
chip_io_alt/mprj_io_analog_en[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[19] = 1
|
Net: padframe/mprj_io_analog_pol[17] |Net: \mprj_io_ib_mode_sel[19]
chip_io_alt/mprj_io_analog_pol[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[19] = 1
|
Net: padframe/mprj_io_analog_sel[17] |Net: \mprj_io_inp_dis[19]
chip_io_alt/mprj_io_analog_sel[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[19] = 1
|
Net: padframe/mprj_io_dm[51] |Net: \mprj_io_out[19]
chip_io_alt/mprj_io_dm[51] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[19] = 1
|
Net: padframe/mprj_io_dm[52] |Net: \mprj_io_oeb[19]
chip_io_alt/mprj_io_dm[52] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[19] = 1
|
Net: padframe/mprj_io_dm[53] |Net: \mprj_io_slow_sel[19]
chip_io_alt/mprj_io_dm[53] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[19] = 1
|
Net: padframe/mprj_io_holdover[17] |Net: \mprj_io_vtrip_sel[19]
chip_io_alt/mprj_io_holdover[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[19] = 1
|
Net: padframe/mprj_io_ib_mode_sel[17] |Net: \user_io_in[19]
chip_io_alt/mprj_io_ib_mode_sel[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[19] =
|
Net: padframe/mprj_io_inp_dis[17] |Net: \mprj_io_dm[59]
chip_io_alt/mprj_io_inp_dis[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[59] = 1
|
Net: padframe/mprj_io_oeb[17] |Net: \mprj_io_dm[58]
chip_io_alt/mprj_io_oeb[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[58] = 1
|
Net: padframe/mprj_io_out[17] |Net: \mprj_io_dm[57]
chip_io_alt/mprj_io_out[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[57] = 1
|
Net: padframe/mprj_io_slow_sel[17] |Net: \mprj_io_analog_en[20]
chip_io_alt/mprj_io_slow_sel[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[20] = 1
|
Net: padframe/mprj_io_vtrip_sel[17] |Net: \mprj_io_analog_pol[20]
chip_io_alt/mprj_io_vtrip_sel[17] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[20] = 1
|
Net: padframe/mprj_io_analog_en[18] |Net: \mprj_io_analog_sel[20]
chip_io_alt/mprj_io_analog_en[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[20] = 1
|
Net: padframe/mprj_io_analog_pol[18] |Net: \mprj_io_holdover[20]
chip_io_alt/mprj_io_analog_pol[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[20] = 1
|
Net: padframe/mprj_io_analog_sel[18] |Net: \mprj_io_ib_mode_sel[20]
chip_io_alt/mprj_io_analog_sel[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[20] = 1
|
Net: padframe/mprj_io_dm[54] |Net: \mprj_io_inp_dis[20]
chip_io_alt/mprj_io_dm[54] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[20] = 1
|
Net: padframe/mprj_io_dm[55] |Net: \mprj_io_out[20]
chip_io_alt/mprj_io_dm[55] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[20] = 1
|
Net: padframe/mprj_io_dm[56] |Net: \mprj_io_oeb[20]
chip_io_alt/mprj_io_dm[56] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[20] = 1
|
Net: padframe/mprj_io_holdover[18] |Net: \mprj_io_slow_sel[20]
chip_io_alt/mprj_io_holdover[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[20] = 1
|
Net: padframe/mprj_io_ib_mode_sel[18] |Net: \mprj_io_vtrip_sel[20]
chip_io_alt/mprj_io_ib_mode_sel[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[20] = 1
|
Net: padframe/mprj_io_inp_dis[18] |Net: \user_io_in[20]
chip_io_alt/mprj_io_inp_dis[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[20] =
|
Net: padframe/mprj_io_oeb[18] |Net: \mprj_io_dm[62]
chip_io_alt/mprj_io_oeb[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[62] = 1
|
Net: padframe/mprj_io_out[18] |Net: \mprj_io_dm[61]
chip_io_alt/mprj_io_out[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[61] = 1
|
Net: padframe/mprj_io_slow_sel[18] |Net: \mprj_io_dm[60]
chip_io_alt/mprj_io_slow_sel[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[60] = 1
|
Net: padframe/mprj_io_vtrip_sel[18] |Net: \mprj_io_analog_en[21]
chip_io_alt/mprj_io_vtrip_sel[18] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[21] = 1
|
Net: padframe/mprj_io_analog_en[19] |Net: \mprj_io_analog_pol[21]
chip_io_alt/mprj_io_analog_en[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[21] = 1
|
Net: padframe/mprj_io_analog_pol[19] |Net: \mprj_io_analog_sel[21]
chip_io_alt/mprj_io_analog_pol[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[21] = 1
|
Net: padframe/mprj_io_analog_sel[19] |Net: \mprj_io_holdover[21]
chip_io_alt/mprj_io_analog_sel[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[21] = 1
|
Net: padframe/mprj_io_dm[57] |Net: \mprj_io_ib_mode_sel[21]
chip_io_alt/mprj_io_dm[57] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[21] = 1
|
Net: padframe/mprj_io_dm[58] |Net: \mprj_io_inp_dis[21]
chip_io_alt/mprj_io_dm[58] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[21] = 1
|
Net: padframe/mprj_io_dm[59] |Net: \mprj_io_out[21]
chip_io_alt/mprj_io_dm[59] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[21] = 1
|
Net: padframe/mprj_io_holdover[19] |Net: \mprj_io_oeb[21]
chip_io_alt/mprj_io_holdover[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[21] = 1
|
Net: padframe/mprj_io_ib_mode_sel[19] |Net: \mprj_io_slow_sel[21]
chip_io_alt/mprj_io_ib_mode_sel[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[21] = 1
|
Net: padframe/mprj_io_inp_dis[19] |Net: \mprj_io_vtrip_sel[21]
chip_io_alt/mprj_io_inp_dis[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[21] = 1
|
Net: padframe/mprj_io_oeb[19] |Net: \user_io_in[21]
chip_io_alt/mprj_io_oeb[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[21] =
|
Net: padframe/mprj_io_out[19] |Net: \mprj_io_dm[65]
chip_io_alt/mprj_io_out[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[65] = 1
|
Net: padframe/mprj_io_slow_sel[19] |Net: \mprj_io_dm[64]
chip_io_alt/mprj_io_slow_sel[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[64] = 1
|
Net: padframe/mprj_io_vtrip_sel[19] |Net: \mprj_io_dm[63]
chip_io_alt/mprj_io_vtrip_sel[19] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[63] = 1
|
Net: padframe/mprj_io_analog_en[20] |Net: \mprj_io_analog_en[22]
chip_io_alt/mprj_io_analog_en[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[22] = 1
|
Net: padframe/mprj_io_analog_pol[20] |Net: \mprj_io_analog_pol[22]
chip_io_alt/mprj_io_analog_pol[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[22] = 1
|
Net: padframe/mprj_io_analog_sel[20] |Net: \mprj_io_analog_sel[22]
chip_io_alt/mprj_io_analog_sel[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[22] = 1
|
Net: padframe/mprj_io_dm[60] |Net: \mprj_io_holdover[22]
chip_io_alt/mprj_io_dm[60] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[22] = 1
|
Net: padframe/mprj_io_dm[61] |Net: \mprj_io_ib_mode_sel[22]
chip_io_alt/mprj_io_dm[61] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[22] = 1
|
Net: padframe/mprj_io_dm[62] |Net: \mprj_io_inp_dis[22]
chip_io_alt/mprj_io_dm[62] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[22] = 1
|
Net: padframe/mprj_io_holdover[20] |Net: \mprj_io_out[22]
chip_io_alt/mprj_io_holdover[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[22] = 1
|
Net: padframe/mprj_io_ib_mode_sel[20] |Net: \mprj_io_oeb[22]
chip_io_alt/mprj_io_ib_mode_sel[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[22] = 1
|
Net: padframe/mprj_io_inp_dis[20] |Net: \mprj_io_slow_sel[22]
chip_io_alt/mprj_io_inp_dis[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[22] = 1
|
Net: padframe/mprj_io_oeb[20] |Net: \mprj_io_vtrip_sel[22]
chip_io_alt/mprj_io_oeb[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[22] = 1
|
Net: padframe/mprj_io_out[20] |Net: \user_io_in[22]
chip_io_alt/mprj_io_out[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[22] =
|
Net: padframe/mprj_io_slow_sel[20] |Net: \mprj_io_dm[68]
chip_io_alt/mprj_io_slow_sel[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[68] = 1
|
Net: padframe/mprj_io_vtrip_sel[20] |Net: \mprj_io_dm[67]
chip_io_alt/mprj_io_vtrip_sel[20] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[67] = 1
|
Net: padframe/mprj_io_analog_en[21] |Net: \mprj_io_dm[66]
chip_io_alt/mprj_io_analog_en[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[66] = 1
|
Net: padframe/mprj_io_analog_pol[21] |Net: \mprj_io_analog_en[23]
chip_io_alt/mprj_io_analog_pol[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_en[23] = 1
|
Net: padframe/mprj_io_analog_sel[21] |Net: \mprj_io_analog_pol[23]
chip_io_alt/mprj_io_analog_sel[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_pol[23] = 1
|
Net: padframe/mprj_io_dm[63] |Net: \mprj_io_analog_sel[23]
chip_io_alt/mprj_io_dm[63] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_analog_sel[23] = 1
|
Net: padframe/mprj_io_dm[64] |Net: \mprj_io_holdover[23]
chip_io_alt/mprj_io_dm[64] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_holdover[23] = 1
|
Net: padframe/mprj_io_dm[65] |Net: \mprj_io_ib_mode_sel[23]
chip_io_alt/mprj_io_dm[65] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_ib_mode_sel[23] = 1
|
Net: padframe/mprj_io_holdover[21] |Net: \mprj_io_inp_dis[23]
chip_io_alt/mprj_io_holdover[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_inp_dis[23] = 1
|
Net: padframe/mprj_io_ib_mode_sel[21] |Net: \mprj_io_out[23]
chip_io_alt/mprj_io_ib_mode_sel[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_out[23] = 1
|
Net: padframe/mprj_io_inp_dis[21] |Net: \mprj_io_oeb[23]
chip_io_alt/mprj_io_inp_dis[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_oeb[23] = 1
|
Net: padframe/mprj_io_oeb[21] |Net: \mprj_io_slow_sel[23]
chip_io_alt/mprj_io_oeb[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_slow_sel[23] = 1
|
Net: padframe/mprj_io_out[21] |Net: \mprj_io_vtrip_sel[23]
chip_io_alt/mprj_io_out[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_vtrip_sel[23] = 1
|
Net: padframe/mprj_io_slow_sel[21] |Net: \user_io_in[23]
chip_io_alt/mprj_io_slow_sel[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/io_in[23] =
|
Net: padframe/mprj_io_vtrip_sel[21] |Net: \mprj_io_dm[71]
chip_io_alt/mprj_io_vtrip_sel[21] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[71] = 1
|
Net: padframe/mprj_io_analog_en[22] |Net: \mprj_io_dm[70]
chip_io_alt/mprj_io_analog_en[22] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[70] = 1
|
Net: padframe/mprj_io_analog_pol[22] |Net: \mprj_io_dm[69]
chip_io_alt/mprj_io_analog_pol[22] = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__buf_16/X = 1 | chip_io_alt/mprj_io_dm[69] = 1
|
Net: padframe/mprj_io_analog_sel[22] |Net: mprj_vcc_pwrgood
chip_io_alt/mprj_io_analog_sel[22] = 1 | housekeeping/usr1_vcc_pwrgood = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/user1_vcc_powergood = 1
|
Net: padframe/mprj_io_dm[66] |Net: mprj_vdd_pwrgood
chip_io_alt/mprj_io_dm[66] = 1 | housekeeping/usr1_vdd_pwrgood = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/user1_vdd_powergood = 1
|
Net: padframe/mprj_io_dm[67] |Net: mprj2_vcc_pwrgood
chip_io_alt/mprj_io_dm[67] = 1 | housekeeping/usr2_vcc_pwrgood = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/user2_vcc_powergood = 1
|
Net: padframe/mprj_io_dm[68] |Net: mprj2_vdd_pwrgood
chip_io_alt/mprj_io_dm[68] = 1 | housekeeping/usr2_vdd_pwrgood = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/user2_vdd_powergood = 1
|
Net: padframe/mprj_io_holdover[22] |Net: clk_passthru
chip_io_alt/mprj_io_holdover[22] = 1 | mgmt_protect/caravel_clk = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_core_wrapper/clk_out = 1
|
Net: padframe/mprj_io_ib_mode_sel[22] |Net: resetn_passthru
chip_io_alt/mprj_io_ib_mode_sel[22] = 1 | mgmt_protect/caravel_rstn = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_core_wrapper/resetn_out = 1
|
Net: padframe/mprj_io_inp_dis[22] |Net: mprj_ack_i_core
chip_io_alt/mprj_io_inp_dis[22] = 1 | mgmt_protect/mprj_ack_i_core = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_core_wrapper/mprj_ack_i = 1
|
Net: padframe/mprj_io_oeb[22] |Net: mprj_ack_i_user
chip_io_alt/mprj_io_oeb[22] = 1 | mgmt_protect/mprj_ack_i_user = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/wbs_ack_o =
|
Net: padframe/mprj_io_out[22] |Net: mprj_cyc_o_core
chip_io_alt/mprj_io_out[22] = 1 | mgmt_protect/mprj_cyc_o_core = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_core_wrapper/mprj_cyc_o = 1
|
Net: padframe/mprj_io_slow_sel[22] |Net: mprj_cyc_o_user
chip_io_alt/mprj_io_slow_sel[22] = 1 | mgmt_protect/mprj_cyc_o_user = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/wbs_cyc_i =
|
Net: padframe/mprj_io_vtrip_sel[22] |Net: mprj_iena_wb
chip_io_alt/mprj_io_vtrip_sel[22] = 1 | mgmt_protect/mprj_iena_wb = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_core_wrapper/mprj_wb_iena = 1
|
Net: padframe/mprj_io_analog_en[23] |Net: mprj_stb_o_core
chip_io_alt/mprj_io_analog_en[23] = 1 | mgmt_protect/mprj_stb_o_core = 1
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_core_wrapper/mprj_stb_o = 1
|
Net: padframe/mprj_io_analog_pol[23] |Net: mprj_stb_o_user
chip_io_alt/mprj_io_analog_pol[23] = 1 | mgmt_protect/mprj_stb_o_user = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/wbs_stb_i =
|
Net: padframe/mprj_io_analog_sel[23] |Net: mprj_we_o_user
chip_io_alt/mprj_io_analog_sel[23] = 1 | mgmt_protect/mprj_we_o_user = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/wbs_we_i = 1
|
Net: padframe/mprj_io_dm[69] |Net: mprj_clock
chip_io_alt/mprj_io_dm[69] = 1 | mgmt_protect/user_clock = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/wb_clk_i = 1
|
Net: padframe/mprj_io_dm[70] |Net: mprj_clock2
chip_io_alt/mprj_io_dm[70] = 1 | mgmt_protect/user_clock2 = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/user_clock2
|
Net: padframe/mprj_io_dm[71] |Net: mprj_reset
chip_io_alt/mprj_io_dm[71] = 1 | mgmt_protect/user_reset = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/wb_rst_i = 1
|
Net: padframe/mprj_io_holdover[23] |Net: \la_data_in_user[127]
chip_io_alt/mprj_io_holdover[23] = 1 | mgmt_protect/la_data_in_core[127] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_ib_mode_sel[23] |Net: \la_data_in_user[126]
chip_io_alt/mprj_io_ib_mode_sel[23] = 1 | mgmt_protect/la_data_in_core[126] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_inp_dis[23] |Net: \la_data_in_user[125]
chip_io_alt/mprj_io_inp_dis[23] = 1 | mgmt_protect/la_data_in_core[125] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_oeb[23] |Net: \la_data_in_user[124]
chip_io_alt/mprj_io_oeb[23] = 1 | mgmt_protect/la_data_in_core[124] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_out[23] |Net: \la_data_in_user[123]
chip_io_alt/mprj_io_out[23] = 1 | mgmt_protect/la_data_in_core[123] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_slow_sel[23] |Net: \la_data_in_user[122]
chip_io_alt/mprj_io_slow_sel[23] = 1 | mgmt_protect/la_data_in_core[122] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_vtrip_sel[23] |Net: \la_data_in_user[121]
chip_io_alt/mprj_io_vtrip_sel[23] = 1 | mgmt_protect/la_data_in_core[121] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: rstb_level/A |Net: \la_data_in_user[120]
chip_io_alt/resetb_core_h = 1 | mgmt_protect/la_data_in_core[120] = 1
xres_buf/A = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: mprj/vdda1 |Net: \la_data_in_user[119]
chip_io_alt/vdda1 = 1 | mgmt_protect/la_data_in_core[119] = 1
mgmt_protect/vdda1 = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: mprj/vccd2 |Net: \la_data_in_user[118]
chip_io_alt/vccd2 = 1 | mgmt_protect/la_data_in_core[118] = 1
mgmt_protect/vccd2 = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: mprj/vdda2 |Net: \la_data_in_user[117]
chip_io_alt/vdda2 = 1 | mgmt_protect/la_data_in_core[117] = 1
mgmt_protect/vdda2 = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/flash_csb_core |Net: \la_data_in_user[116]
chip_io_alt/flash_csb_core = 1 | mgmt_protect/la_data_in_core[116] = 1
buff_flash_clkrst/out_s[8] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/flash_clk_oeb_core |Net: \la_data_in_user[115]
chip_io_alt/flash_clk_oeb_core = 1 | mgmt_protect/la_data_in_core[115] = 1
buff_flash_clkrst/out_s[7] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/flash_clk_core |Net: \la_data_in_user[114]
chip_io_alt/flash_clk_core = 1 | mgmt_protect/la_data_in_core[114] = 1
buff_flash_clkrst/out_s[9] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/flash_csb_oeb_core |Net: \la_data_in_user[113]
chip_io_alt/flash_csb_oeb_core = 1 | mgmt_protect/la_data_in_core[113] = 1
buff_flash_clkrst/out_s[6] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_one[0] |Net: \la_data_in_user[112]
chip_io_alt/mprj_io_one[0] = 1 | mgmt_protect/la_data_in_core[112] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_one[1] |Net: \la_data_in_user[111]
chip_io_alt/mprj_io_one[1] = 1 | mgmt_protect/la_data_in_core[111] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_one[24] |Net: \la_data_in_user[110]
chip_io_alt/mprj_io_one[24] = 1 | mgmt_protect/la_data_in_core[110] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_one[25] |Net: \la_data_in_user[109]
chip_io_alt/mprj_io_one[25] = 1 | mgmt_protect/la_data_in_core[109] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: padframe/mprj_io_one[26] |Net: \la_data_in_user[108]
chip_io_alt/mprj_io_one[26] = 1 | mgmt_protect/la_data_in_core[108] = 1
sky130_fd_sc_hd__buf_16/X = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: por/porb_h |Net: \la_data_in_user[107]
chip_io_alt/porb_h = 1 | mgmt_protect/la_data_in_core[107] = 1
simple_por/porb_h = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/gpio_mode1_pad |Net: \la_data_in_user[106]
chip_io_alt/gpio_mode1_core = 1 | mgmt_protect/la_data_in_core[106] = 1
mgmt_core_wrapper/gpio_mode1_pad = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: mprj/vssd2 |Net: \la_data_in_user[105]
chip_io_alt/vssd2 = 1 | mgmt_protect/la_data_in_core[105] = 1
mgmt_protect/vssd2 = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: mprj/vssa2 |Net: \la_data_in_user[104]
chip_io_alt/vssa2 = 1 | mgmt_protect/la_data_in_core[104] = 1
mgmt_protect/vssa2 = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: mprj/vssa1 |Net: \la_data_in_user[103]
chip_io_alt/vssa1 = 1 | mgmt_protect/la_data_in_core[103] = 1
mgmt_protect/vssa1 = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/clk_out |Net: \la_data_in_user[102]
mgmt_core_wrapper/clk_out = 1 | mgmt_protect/la_data_in_core[102] = 1
mgmt_protect/caravel_clk = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/irq[0] |Net: \la_data_in_user[101]
mgmt_core_wrapper/irq[0] = 1 | mgmt_protect/la_data_in_core[101] = 1
mgmt_protect/user_irq[0] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/irq[1] |Net: \la_data_in_user[100]
mgmt_core_wrapper/irq[1] = 1 | mgmt_protect/la_data_in_core[100] = 1
mgmt_protect/user_irq[1] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/irq[2] |Net: \la_data_in_user[99]
mgmt_core_wrapper/irq[2] = 1 | mgmt_protect/la_data_in_core[99] = 1
mgmt_protect/user_irq[2] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[0] |Net: \la_data_in_user[98]
mgmt_core_wrapper/la_iena[0] = 1 | mgmt_protect/la_data_in_core[98] = 1
mgmt_protect/la_iena_mprj[0] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[100] |Net: \la_data_in_user[97]
mgmt_core_wrapper/la_iena[100] = 1 | mgmt_protect/la_data_in_core[97] = 1
mgmt_protect/la_iena_mprj[100] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[101] |Net: \la_data_in_user[96]
mgmt_core_wrapper/la_iena[101] = 1 | mgmt_protect/la_data_in_core[96] = 1
mgmt_protect/la_iena_mprj[101] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[102] |Net: \la_data_in_user[95]
mgmt_core_wrapper/la_iena[102] = 1 | mgmt_protect/la_data_in_core[95] = 1
mgmt_protect/la_iena_mprj[102] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[103] |Net: \la_data_in_user[94]
mgmt_core_wrapper/la_iena[103] = 1 | mgmt_protect/la_data_in_core[94] = 1
mgmt_protect/la_iena_mprj[103] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[104] |Net: \la_data_in_user[93]
mgmt_core_wrapper/la_iena[104] = 1 | mgmt_protect/la_data_in_core[93] = 1
mgmt_protect/la_iena_mprj[104] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[105] |Net: \la_data_in_user[92]
mgmt_core_wrapper/la_iena[105] = 1 | mgmt_protect/la_data_in_core[92] = 1
mgmt_protect/la_iena_mprj[105] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[106] |Net: \la_data_in_user[91]
mgmt_core_wrapper/la_iena[106] = 1 | mgmt_protect/la_data_in_core[91] = 1
mgmt_protect/la_iena_mprj[106] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[107] |Net: \la_data_in_user[90]
mgmt_core_wrapper/la_iena[107] = 1 | mgmt_protect/la_data_in_core[90] = 1
mgmt_protect/la_iena_mprj[107] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[108] |Net: \la_data_in_user[89]
mgmt_core_wrapper/la_iena[108] = 1 | mgmt_protect/la_data_in_core[89] = 1
mgmt_protect/la_iena_mprj[108] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[109] |Net: \la_data_in_user[88]
mgmt_core_wrapper/la_iena[109] = 1 | mgmt_protect/la_data_in_core[88] = 1
mgmt_protect/la_iena_mprj[109] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[10] |Net: \la_data_in_user[87]
mgmt_core_wrapper/la_iena[10] = 1 | mgmt_protect/la_data_in_core[87] = 1
mgmt_protect/la_iena_mprj[10] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[110] |Net: \la_data_in_user[86]
mgmt_core_wrapper/la_iena[110] = 1 | mgmt_protect/la_data_in_core[86] = 1
mgmt_protect/la_iena_mprj[110] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[111] |Net: \la_data_in_user[85]
mgmt_core_wrapper/la_iena[111] = 1 | mgmt_protect/la_data_in_core[85] = 1
mgmt_protect/la_iena_mprj[111] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[112] |Net: \la_data_in_user[84]
mgmt_core_wrapper/la_iena[112] = 1 | mgmt_protect/la_data_in_core[84] = 1
mgmt_protect/la_iena_mprj[112] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[113] |Net: \la_data_in_user[83]
mgmt_core_wrapper/la_iena[113] = 1 | mgmt_protect/la_data_in_core[83] = 1
mgmt_protect/la_iena_mprj[113] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[114] |Net: \la_data_in_user[82]
mgmt_core_wrapper/la_iena[114] = 1 | mgmt_protect/la_data_in_core[82] = 1
mgmt_protect/la_iena_mprj[114] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[115] |Net: \la_data_in_user[81]
mgmt_core_wrapper/la_iena[115] = 1 | mgmt_protect/la_data_in_core[81] = 1
mgmt_protect/la_iena_mprj[115] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[116] |Net: \la_data_in_user[80]
mgmt_core_wrapper/la_iena[116] = 1 | mgmt_protect/la_data_in_core[80] = 1
mgmt_protect/la_iena_mprj[116] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[117] |Net: \la_data_in_user[79]
mgmt_core_wrapper/la_iena[117] = 1 | mgmt_protect/la_data_in_core[79] = 1
mgmt_protect/la_iena_mprj[117] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[118] |Net: \la_data_in_user[78]
mgmt_core_wrapper/la_iena[118] = 1 | mgmt_protect/la_data_in_core[78] = 1
mgmt_protect/la_iena_mprj[118] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[119] |Net: \la_data_in_user[77]
mgmt_core_wrapper/la_iena[119] = 1 | mgmt_protect/la_data_in_core[77] = 1
mgmt_protect/la_iena_mprj[119] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[11] |Net: \la_data_in_user[76]
mgmt_core_wrapper/la_iena[11] = 1 | mgmt_protect/la_data_in_core[76] = 1
mgmt_protect/la_iena_mprj[11] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[120] |Net: \la_data_in_user[75]
mgmt_core_wrapper/la_iena[120] = 1 | mgmt_protect/la_data_in_core[75] = 1
mgmt_protect/la_iena_mprj[120] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[121] |Net: \la_data_in_user[74]
mgmt_core_wrapper/la_iena[121] = 1 | mgmt_protect/la_data_in_core[74] = 1
mgmt_protect/la_iena_mprj[121] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[122] |Net: \la_data_in_user[73]
mgmt_core_wrapper/la_iena[122] = 1 | mgmt_protect/la_data_in_core[73] = 1
mgmt_protect/la_iena_mprj[122] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[123] |Net: \la_data_in_user[72]
mgmt_core_wrapper/la_iena[123] = 1 | mgmt_protect/la_data_in_core[72] = 1
mgmt_protect/la_iena_mprj[123] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[124] |Net: \la_data_in_user[71]
mgmt_core_wrapper/la_iena[124] = 1 | mgmt_protect/la_data_in_core[71] = 1
mgmt_protect/la_iena_mprj[124] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[125] |Net: \la_data_in_user[70]
mgmt_core_wrapper/la_iena[125] = 1 | mgmt_protect/la_data_in_core[70] = 1
mgmt_protect/la_iena_mprj[125] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[126] |Net: \la_data_in_user[69]
mgmt_core_wrapper/la_iena[126] = 1 | mgmt_protect/la_data_in_core[69] = 1
mgmt_protect/la_iena_mprj[126] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[127] |Net: \la_data_in_user[68]
mgmt_core_wrapper/la_iena[127] = 1 | mgmt_protect/la_data_in_core[68] = 1
mgmt_protect/la_iena_mprj[127] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[12] |Net: \la_data_in_user[67]
mgmt_core_wrapper/la_iena[12] = 1 | mgmt_protect/la_data_in_core[67] = 1
mgmt_protect/la_iena_mprj[12] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[13] |Net: \la_data_in_user[66]
mgmt_core_wrapper/la_iena[13] = 1 | mgmt_protect/la_data_in_core[66] = 1
mgmt_protect/la_iena_mprj[13] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[14] |Net: \la_data_in_user[65]
mgmt_core_wrapper/la_iena[14] = 1 | mgmt_protect/la_data_in_core[65] = 1
mgmt_protect/la_iena_mprj[14] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[15] |Net: \la_data_in_user[64]
mgmt_core_wrapper/la_iena[15] = 1 | mgmt_protect/la_data_in_core[64] = 1
mgmt_protect/la_iena_mprj[15] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[16] |Net: \la_data_in_user[63]
mgmt_core_wrapper/la_iena[16] = 1 | mgmt_protect/la_data_in_core[63] = 1
mgmt_protect/la_iena_mprj[16] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[17] |Net: \la_data_in_user[62]
mgmt_core_wrapper/la_iena[17] = 1 | mgmt_protect/la_data_in_core[62] = 1
mgmt_protect/la_iena_mprj[17] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[18] |Net: \la_data_in_user[61]
mgmt_core_wrapper/la_iena[18] = 1 | mgmt_protect/la_data_in_core[61] = 1
mgmt_protect/la_iena_mprj[18] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[19] |Net: \la_data_in_user[60]
mgmt_core_wrapper/la_iena[19] = 1 | mgmt_protect/la_data_in_core[60] = 1
mgmt_protect/la_iena_mprj[19] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[1] |Net: \la_data_in_user[59]
mgmt_core_wrapper/la_iena[1] = 1 | mgmt_protect/la_data_in_core[59] = 1
mgmt_protect/la_iena_mprj[1] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[20] |Net: \la_data_in_user[58]
mgmt_core_wrapper/la_iena[20] = 1 | mgmt_protect/la_data_in_core[58] = 1
mgmt_protect/la_iena_mprj[20] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[21] |Net: \la_data_in_user[57]
mgmt_core_wrapper/la_iena[21] = 1 | mgmt_protect/la_data_in_core[57] = 1
mgmt_protect/la_iena_mprj[21] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[22] |Net: \la_data_in_user[56]
mgmt_core_wrapper/la_iena[22] = 1 | mgmt_protect/la_data_in_core[56] = 1
mgmt_protect/la_iena_mprj[22] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[23] |Net: \la_data_in_user[55]
mgmt_core_wrapper/la_iena[23] = 1 | mgmt_protect/la_data_in_core[55] = 1
mgmt_protect/la_iena_mprj[23] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[24] |Net: \la_data_in_user[54]
mgmt_core_wrapper/la_iena[24] = 1 | mgmt_protect/la_data_in_core[54] = 1
mgmt_protect/la_iena_mprj[24] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[25] |Net: \la_data_in_user[53]
mgmt_core_wrapper/la_iena[25] = 1 | mgmt_protect/la_data_in_core[53] = 1
mgmt_protect/la_iena_mprj[25] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[26] |Net: \la_data_in_user[52]
mgmt_core_wrapper/la_iena[26] = 1 | mgmt_protect/la_data_in_core[52] = 1
mgmt_protect/la_iena_mprj[26] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[27] |Net: \la_data_in_user[51]
mgmt_core_wrapper/la_iena[27] = 1 | mgmt_protect/la_data_in_core[51] = 1
mgmt_protect/la_iena_mprj[27] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[28] |Net: \la_data_in_user[50]
mgmt_core_wrapper/la_iena[28] = 1 | mgmt_protect/la_data_in_core[50] = 1
mgmt_protect/la_iena_mprj[28] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[29] |Net: \la_data_in_user[49]
mgmt_core_wrapper/la_iena[29] = 1 | mgmt_protect/la_data_in_core[49] = 1
mgmt_protect/la_iena_mprj[29] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[2] |Net: \la_data_in_user[48]
mgmt_core_wrapper/la_iena[2] = 1 | mgmt_protect/la_data_in_core[48] = 1
mgmt_protect/la_iena_mprj[2] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[30] |Net: \la_data_in_user[47]
mgmt_core_wrapper/la_iena[30] = 1 | mgmt_protect/la_data_in_core[47] = 1
mgmt_protect/la_iena_mprj[30] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[31] |Net: \la_data_in_user[46]
mgmt_core_wrapper/la_iena[31] = 1 | mgmt_protect/la_data_in_core[46] = 1
mgmt_protect/la_iena_mprj[31] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[32] |Net: \la_data_in_user[45]
mgmt_core_wrapper/la_iena[32] = 1 | mgmt_protect/la_data_in_core[45] = 1
mgmt_protect/la_iena_mprj[32] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[33] |Net: \la_data_in_user[44]
mgmt_core_wrapper/la_iena[33] = 1 | mgmt_protect/la_data_in_core[44] = 1
mgmt_protect/la_iena_mprj[33] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[34] |Net: \la_data_in_user[43]
mgmt_core_wrapper/la_iena[34] = 1 | mgmt_protect/la_data_in_core[43] = 1
mgmt_protect/la_iena_mprj[34] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[35] |Net: \la_data_in_user[42]
mgmt_core_wrapper/la_iena[35] = 1 | mgmt_protect/la_data_in_core[42] = 1
mgmt_protect/la_iena_mprj[35] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[36] |Net: \la_data_in_user[41]
mgmt_core_wrapper/la_iena[36] = 1 | mgmt_protect/la_data_in_core[41] = 1
mgmt_protect/la_iena_mprj[36] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[37] |Net: \la_data_in_user[40]
mgmt_core_wrapper/la_iena[37] = 1 | mgmt_protect/la_data_in_core[40] = 1
mgmt_protect/la_iena_mprj[37] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[38] |Net: \la_data_in_user[39]
mgmt_core_wrapper/la_iena[38] = 1 | mgmt_protect/la_data_in_core[39] = 1
mgmt_protect/la_iena_mprj[38] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[39] |Net: \la_data_in_user[38]
mgmt_core_wrapper/la_iena[39] = 1 | mgmt_protect/la_data_in_core[38] = 1
mgmt_protect/la_iena_mprj[39] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[3] |Net: \la_data_in_user[37]
mgmt_core_wrapper/la_iena[3] = 1 | mgmt_protect/la_data_in_core[37] = 1
mgmt_protect/la_iena_mprj[3] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[40] |Net: \la_data_in_user[36]
mgmt_core_wrapper/la_iena[40] = 1 | mgmt_protect/la_data_in_core[36] = 1
mgmt_protect/la_iena_mprj[40] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[41] |Net: \la_data_in_user[35]
mgmt_core_wrapper/la_iena[41] = 1 | mgmt_protect/la_data_in_core[35] = 1
mgmt_protect/la_iena_mprj[41] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[42] |Net: \la_data_in_user[34]
mgmt_core_wrapper/la_iena[42] = 1 | mgmt_protect/la_data_in_core[34] = 1
mgmt_protect/la_iena_mprj[42] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[43] |Net: \la_data_in_user[33]
mgmt_core_wrapper/la_iena[43] = 1 | mgmt_protect/la_data_in_core[33] = 1
mgmt_protect/la_iena_mprj[43] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[44] |Net: \la_data_in_user[32]
mgmt_core_wrapper/la_iena[44] = 1 | mgmt_protect/la_data_in_core[32] = 1
mgmt_protect/la_iena_mprj[44] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[45] |Net: \la_data_in_user[31]
mgmt_core_wrapper/la_iena[45] = 1 | mgmt_protect/la_data_in_core[31] = 1
mgmt_protect/la_iena_mprj[45] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[46] |Net: \la_data_in_user[30]
mgmt_core_wrapper/la_iena[46] = 1 | mgmt_protect/la_data_in_core[30] = 1
mgmt_protect/la_iena_mprj[46] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[47] |Net: \la_data_in_user[29]
mgmt_core_wrapper/la_iena[47] = 1 | mgmt_protect/la_data_in_core[29] = 1
mgmt_protect/la_iena_mprj[47] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[48] |Net: \la_data_in_user[28]
mgmt_core_wrapper/la_iena[48] = 1 | mgmt_protect/la_data_in_core[28] = 1
mgmt_protect/la_iena_mprj[48] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[49] |Net: \la_data_in_user[27]
mgmt_core_wrapper/la_iena[49] = 1 | mgmt_protect/la_data_in_core[27] = 1
mgmt_protect/la_iena_mprj[49] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[4] |Net: \la_data_in_user[26]
mgmt_core_wrapper/la_iena[4] = 1 | mgmt_protect/la_data_in_core[26] = 1
mgmt_protect/la_iena_mprj[4] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[50] |Net: \la_data_in_user[25]
mgmt_core_wrapper/la_iena[50] = 1 | mgmt_protect/la_data_in_core[25] = 1
mgmt_protect/la_iena_mprj[50] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[51] |Net: \la_data_in_user[24]
mgmt_core_wrapper/la_iena[51] = 1 | mgmt_protect/la_data_in_core[24] = 1
mgmt_protect/la_iena_mprj[51] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[52] |Net: \la_data_in_user[23]
mgmt_core_wrapper/la_iena[52] = 1 | mgmt_protect/la_data_in_core[23] = 1
mgmt_protect/la_iena_mprj[52] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[53] |Net: \la_data_in_user[22]
mgmt_core_wrapper/la_iena[53] = 1 | mgmt_protect/la_data_in_core[22] = 1
mgmt_protect/la_iena_mprj[53] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[54] |Net: \la_data_in_user[21]
mgmt_core_wrapper/la_iena[54] = 1 | mgmt_protect/la_data_in_core[21] = 1
mgmt_protect/la_iena_mprj[54] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[55] |Net: \la_data_in_user[20]
mgmt_core_wrapper/la_iena[55] = 1 | mgmt_protect/la_data_in_core[20] = 1
mgmt_protect/la_iena_mprj[55] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[56] |Net: \la_data_in_user[19]
mgmt_core_wrapper/la_iena[56] = 1 | mgmt_protect/la_data_in_core[19] = 1
mgmt_protect/la_iena_mprj[56] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[57] |Net: \la_data_in_user[18]
mgmt_core_wrapper/la_iena[57] = 1 | mgmt_protect/la_data_in_core[18] = 1
mgmt_protect/la_iena_mprj[57] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[58] |Net: \la_data_in_user[17]
mgmt_core_wrapper/la_iena[58] = 1 | mgmt_protect/la_data_in_core[17] = 1
mgmt_protect/la_iena_mprj[58] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[59] |Net: \la_data_in_user[16]
mgmt_core_wrapper/la_iena[59] = 1 | mgmt_protect/la_data_in_core[16] = 1
mgmt_protect/la_iena_mprj[59] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[5] |Net: \la_data_in_user[15]
mgmt_core_wrapper/la_iena[5] = 1 | mgmt_protect/la_data_in_core[15] = 1
mgmt_protect/la_iena_mprj[5] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[60] |Net: \la_data_in_user[14]
mgmt_core_wrapper/la_iena[60] = 1 | mgmt_protect/la_data_in_core[14] = 1
mgmt_protect/la_iena_mprj[60] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[61] |Net: \la_data_in_user[13]
mgmt_core_wrapper/la_iena[61] = 1 | mgmt_protect/la_data_in_core[13] = 1
mgmt_protect/la_iena_mprj[61] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[62] |Net: \la_data_in_user[12]
mgmt_core_wrapper/la_iena[62] = 1 | mgmt_protect/la_data_in_core[12] = 1
mgmt_protect/la_iena_mprj[62] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[63] |Net: \la_data_in_user[11]
mgmt_core_wrapper/la_iena[63] = 1 | mgmt_protect/la_data_in_core[11] = 1
mgmt_protect/la_iena_mprj[63] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[64] |Net: \la_data_in_user[10]
mgmt_core_wrapper/la_iena[64] = 1 | mgmt_protect/la_data_in_core[10] = 1
mgmt_protect/la_iena_mprj[64] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[65] |Net: \la_data_in_user[9]
mgmt_core_wrapper/la_iena[65] = 1 | mgmt_protect/la_data_in_core[9] = 1
mgmt_protect/la_iena_mprj[65] = 1 | user_analog_project_wrapper/la_data_in[9
|
Net: soc/la_iena[66] |Net: \la_data_in_user[8]
mgmt_core_wrapper/la_iena[66] = 1 | mgmt_protect/la_data_in_core[8] = 1
mgmt_protect/la_iena_mprj[66] = 1 | user_analog_project_wrapper/la_data_in[8
|
Net: soc/la_iena[67] |Net: \la_data_in_user[7]
mgmt_core_wrapper/la_iena[67] = 1 | mgmt_protect/la_data_in_core[7] = 1
mgmt_protect/la_iena_mprj[67] = 1 | user_analog_project_wrapper/la_data_in[7
|
Net: soc/la_iena[68] |Net: \la_data_in_user[6]
mgmt_core_wrapper/la_iena[68] = 1 | mgmt_protect/la_data_in_core[6] = 1
mgmt_protect/la_iena_mprj[68] = 1 | user_analog_project_wrapper/la_data_in[6
|
Net: soc/la_iena[69] |Net: \la_data_in_user[5]
mgmt_core_wrapper/la_iena[69] = 1 | mgmt_protect/la_data_in_core[5] = 1
mgmt_protect/la_iena_mprj[69] = 1 | user_analog_project_wrapper/la_data_in[5
|
Net: soc/la_iena[6] |Net: \la_data_in_user[4]
mgmt_core_wrapper/la_iena[6] = 1 | mgmt_protect/la_data_in_core[4] = 1
mgmt_protect/la_iena_mprj[6] = 1 | user_analog_project_wrapper/la_data_in[4
|
Net: soc/la_iena[70] |Net: \la_data_in_user[3]
mgmt_core_wrapper/la_iena[70] = 1 | mgmt_protect/la_data_in_core[3] = 1
mgmt_protect/la_iena_mprj[70] = 1 | user_analog_project_wrapper/la_data_in[3
|
Net: soc/la_iena[71] |Net: \la_data_in_user[2]
mgmt_core_wrapper/la_iena[71] = 1 | mgmt_protect/la_data_in_core[2] = 1
mgmt_protect/la_iena_mprj[71] = 1 | user_analog_project_wrapper/la_data_in[2
|
Net: soc/la_iena[72] |Net: \la_data_in_user[1]
mgmt_core_wrapper/la_iena[72] = 1 | mgmt_protect/la_data_in_core[1] = 1
mgmt_protect/la_iena_mprj[72] = 1 | user_analog_project_wrapper/la_data_in[1
|
Net: soc/la_iena[73] |Net: \la_data_in_user[0]
mgmt_core_wrapper/la_iena[73] = 1 | mgmt_protect/la_data_in_core[0] = 1
mgmt_protect/la_iena_mprj[73] = 1 | user_analog_project_wrapper/la_data_in[0
|
Net: soc/la_iena[74] |Net: \la_data_in_mprj[127]
mgmt_core_wrapper/la_iena[74] = 1 | mgmt_protect/la_data_in_mprj[127] = 1
mgmt_protect/la_iena_mprj[74] = 1 | mgmt_core_wrapper/la_input[127] = 1
|
Net: soc/la_iena[75] |Net: \la_data_in_mprj[126]
mgmt_core_wrapper/la_iena[75] = 1 | mgmt_protect/la_data_in_mprj[126] = 1
mgmt_protect/la_iena_mprj[75] = 1 | mgmt_core_wrapper/la_input[126] = 1
|
Net: soc/la_iena[76] |Net: \la_data_in_mprj[125]
mgmt_core_wrapper/la_iena[76] = 1 | mgmt_protect/la_data_in_mprj[125] = 1
mgmt_protect/la_iena_mprj[76] = 1 | mgmt_core_wrapper/la_input[125] = 1
|
Net: soc/la_iena[77] |Net: \la_data_in_mprj[124]
mgmt_core_wrapper/la_iena[77] = 1 | mgmt_protect/la_data_in_mprj[124] = 1
mgmt_protect/la_iena_mprj[77] = 1 | mgmt_core_wrapper/la_input[124] = 1
|
Net: soc/la_iena[78] |Net: \la_data_in_mprj[123]
mgmt_core_wrapper/la_iena[78] = 1 | mgmt_protect/la_data_in_mprj[123] = 1
mgmt_protect/la_iena_mprj[78] = 1 | mgmt_core_wrapper/la_input[123] = 1
|
Net: soc/la_iena[79] |Net: \la_data_in_mprj[122]
mgmt_core_wrapper/la_iena[79] = 1 | mgmt_protect/la_data_in_mprj[122] = 1
mgmt_protect/la_iena_mprj[79] = 1 | mgmt_core_wrapper/la_input[122] = 1
|
Net: soc/la_iena[7] |Net: \la_data_in_mprj[121]
mgmt_core_wrapper/la_iena[7] = 1 | mgmt_protect/la_data_in_mprj[121] = 1
mgmt_protect/la_iena_mprj[7] = 1 | mgmt_core_wrapper/la_input[121] = 1
|
Net: soc/la_iena[80] |Net: \la_data_in_mprj[120]
mgmt_core_wrapper/la_iena[80] = 1 | mgmt_protect/la_data_in_mprj[120] = 1
mgmt_protect/la_iena_mprj[80] = 1 | mgmt_core_wrapper/la_input[120] = 1
|
Net: soc/la_iena[81] |Net: \la_data_in_mprj[119]
mgmt_core_wrapper/la_iena[81] = 1 | mgmt_protect/la_data_in_mprj[119] = 1
mgmt_protect/la_iena_mprj[81] = 1 | mgmt_core_wrapper/la_input[119] = 1
|
Net: soc/la_iena[82] |Net: \la_data_in_mprj[118]
mgmt_core_wrapper/la_iena[82] = 1 | mgmt_protect/la_data_in_mprj[118] = 1
mgmt_protect/la_iena_mprj[82] = 1 | mgmt_core_wrapper/la_input[118] = 1
|
Net: soc/la_iena[83] |Net: \la_data_in_mprj[117]
mgmt_core_wrapper/la_iena[83] = 1 | mgmt_protect/la_data_in_mprj[117] = 1
mgmt_protect/la_iena_mprj[83] = 1 | mgmt_core_wrapper/la_input[117] = 1
|
Net: soc/la_iena[84] |Net: \la_data_in_mprj[116]
mgmt_core_wrapper/la_iena[84] = 1 | mgmt_protect/la_data_in_mprj[116] = 1
mgmt_protect/la_iena_mprj[84] = 1 | mgmt_core_wrapper/la_input[116] = 1
|
Net: soc/la_iena[85] |Net: \la_data_in_mprj[115]
mgmt_core_wrapper/la_iena[85] = 1 | mgmt_protect/la_data_in_mprj[115] = 1
mgmt_protect/la_iena_mprj[85] = 1 | mgmt_core_wrapper/la_input[115] = 1
|
Net: soc/la_iena[86] |Net: \la_data_in_mprj[114]
mgmt_core_wrapper/la_iena[86] = 1 | mgmt_protect/la_data_in_mprj[114] = 1
mgmt_protect/la_iena_mprj[86] = 1 | mgmt_core_wrapper/la_input[114] = 1
|
Net: soc/la_iena[87] |Net: \la_data_in_mprj[113]
mgmt_core_wrapper/la_iena[87] = 1 | mgmt_protect/la_data_in_mprj[113] = 1
mgmt_protect/la_iena_mprj[87] = 1 | mgmt_core_wrapper/la_input[113] = 1
|
Net: soc/la_iena[88] |Net: \la_data_in_mprj[112]
mgmt_core_wrapper/la_iena[88] = 1 | mgmt_protect/la_data_in_mprj[112] = 1
mgmt_protect/la_iena_mprj[88] = 1 | mgmt_core_wrapper/la_input[112] = 1
|
Net: soc/la_iena[89] |Net: \la_data_in_mprj[111]
mgmt_core_wrapper/la_iena[89] = 1 | mgmt_protect/la_data_in_mprj[111] = 1
mgmt_protect/la_iena_mprj[89] = 1 | mgmt_core_wrapper/la_input[111] = 1
|
Net: soc/la_iena[8] |Net: \la_data_in_mprj[110]
mgmt_core_wrapper/la_iena[8] = 1 | mgmt_protect/la_data_in_mprj[110] = 1
mgmt_protect/la_iena_mprj[8] = 1 | mgmt_core_wrapper/la_input[110] = 1
|
Net: soc/la_iena[90] |Net: \la_data_in_mprj[109]
mgmt_core_wrapper/la_iena[90] = 1 | mgmt_protect/la_data_in_mprj[109] = 1
mgmt_protect/la_iena_mprj[90] = 1 | mgmt_core_wrapper/la_input[109] = 1
|
Net: soc/la_iena[91] |Net: \la_data_in_mprj[108]
mgmt_core_wrapper/la_iena[91] = 1 | mgmt_protect/la_data_in_mprj[108] = 1
mgmt_protect/la_iena_mprj[91] = 1 | mgmt_core_wrapper/la_input[108] = 1
|
Net: soc/la_iena[92] |Net: \la_data_in_mprj[107]
mgmt_core_wrapper/la_iena[92] = 1 | mgmt_protect/la_data_in_mprj[107] = 1
mgmt_protect/la_iena_mprj[92] = 1 | mgmt_core_wrapper/la_input[107] = 1
|
Net: soc/la_iena[93] |Net: \la_data_in_mprj[106]
mgmt_core_wrapper/la_iena[93] = 1 | mgmt_protect/la_data_in_mprj[106] = 1
mgmt_protect/la_iena_mprj[93] = 1 | mgmt_core_wrapper/la_input[106] = 1
|
Net: soc/la_iena[94] |Net: \la_data_in_mprj[105]
mgmt_core_wrapper/la_iena[94] = 1 | mgmt_protect/la_data_in_mprj[105] = 1
mgmt_protect/la_iena_mprj[94] = 1 | mgmt_core_wrapper/la_input[105] = 1
|
Net: soc/la_iena[95] |Net: \la_data_in_mprj[104]
mgmt_core_wrapper/la_iena[95] = 1 | mgmt_protect/la_data_in_mprj[104] = 1
mgmt_protect/la_iena_mprj[95] = 1 | mgmt_core_wrapper/la_input[104] = 1
|
Net: soc/la_iena[96] |Net: \la_data_in_mprj[103]
mgmt_core_wrapper/la_iena[96] = 1 | mgmt_protect/la_data_in_mprj[103] = 1
mgmt_protect/la_iena_mprj[96] = 1 | mgmt_core_wrapper/la_input[103] = 1
|
Net: soc/la_iena[97] |Net: \la_data_in_mprj[102]
mgmt_core_wrapper/la_iena[97] = 1 | mgmt_protect/la_data_in_mprj[102] = 1
mgmt_protect/la_iena_mprj[97] = 1 | mgmt_core_wrapper/la_input[102] = 1
|
Net: soc/la_iena[98] |Net: \la_data_in_mprj[101]
mgmt_core_wrapper/la_iena[98] = 1 | mgmt_protect/la_data_in_mprj[101] = 1
mgmt_protect/la_iena_mprj[98] = 1 | mgmt_core_wrapper/la_input[101] = 1
|
Net: soc/la_iena[99] |Net: \la_data_in_mprj[100]
mgmt_core_wrapper/la_iena[99] = 1 | mgmt_protect/la_data_in_mprj[100] = 1
mgmt_protect/la_iena_mprj[99] = 1 | mgmt_core_wrapper/la_input[100] = 1
|
Net: soc/la_iena[9] |Net: \la_data_in_mprj[99]
mgmt_core_wrapper/la_iena[9] = 1 | mgmt_protect/la_data_in_mprj[99] = 1
mgmt_protect/la_iena_mprj[9] = 1 | mgmt_core_wrapper/la_input[99] = 1
|
Net: soc/la_input[0] |Net: \la_data_in_mprj[98]
mgmt_core_wrapper/la_input[0] = 1 | mgmt_protect/la_data_in_mprj[98] = 1
mgmt_protect/la_data_in_mprj[0] = 1 | mgmt_core_wrapper/la_input[98] = 1
|
Net: soc/la_input[100] |Net: \la_data_in_mprj[97]
mgmt_core_wrapper/la_input[100] = 1 | mgmt_protect/la_data_in_mprj[97] = 1
mgmt_protect/la_data_in_mprj[100] = 1 | mgmt_core_wrapper/la_input[97] = 1
|
Net: soc/la_input[101] |Net: \la_data_in_mprj[96]
mgmt_core_wrapper/la_input[101] = 1 | mgmt_protect/la_data_in_mprj[96] = 1
mgmt_protect/la_data_in_mprj[101] = 1 | mgmt_core_wrapper/la_input[96] = 1
|
Net: soc/la_input[102] |Net: \la_data_in_mprj[95]
mgmt_core_wrapper/la_input[102] = 1 | mgmt_protect/la_data_in_mprj[95] = 1
mgmt_protect/la_data_in_mprj[102] = 1 | mgmt_core_wrapper/la_input[95] = 1
|
Net: soc/la_input[103] |Net: \la_data_in_mprj[94]
mgmt_core_wrapper/la_input[103] = 1 | mgmt_protect/la_data_in_mprj[94] = 1
mgmt_protect/la_data_in_mprj[103] = 1 | mgmt_core_wrapper/la_input[94] = 1
|
Net: soc/la_input[104] |Net: \la_data_in_mprj[93]
mgmt_core_wrapper/la_input[104] = 1 | mgmt_protect/la_data_in_mprj[93] = 1
mgmt_protect/la_data_in_mprj[104] = 1 | mgmt_core_wrapper/la_input[93] = 1
|
Net: soc/la_input[105] |Net: \la_data_in_mprj[92]
mgmt_core_wrapper/la_input[105] = 1 | mgmt_protect/la_data_in_mprj[92] = 1
mgmt_protect/la_data_in_mprj[105] = 1 | mgmt_core_wrapper/la_input[92] = 1
|
Net: soc/la_input[106] |Net: \la_data_in_mprj[91]
mgmt_core_wrapper/la_input[106] = 1 | mgmt_protect/la_data_in_mprj[91] = 1
mgmt_protect/la_data_in_mprj[106] = 1 | mgmt_core_wrapper/la_input[91] = 1
|
Net: soc/la_input[107] |Net: \la_data_in_mprj[90]
mgmt_core_wrapper/la_input[107] = 1 | mgmt_protect/la_data_in_mprj[90] = 1
mgmt_protect/la_data_in_mprj[107] = 1 | mgmt_core_wrapper/la_input[90] = 1
|
Net: soc/la_input[108] |Net: \la_data_in_mprj[89]
mgmt_core_wrapper/la_input[108] = 1 | mgmt_protect/la_data_in_mprj[89] = 1
mgmt_protect/la_data_in_mprj[108] = 1 | mgmt_core_wrapper/la_input[89] = 1
|
Net: soc/la_input[109] |Net: \la_data_in_mprj[88]
mgmt_core_wrapper/la_input[109] = 1 | mgmt_protect/la_data_in_mprj[88] = 1
mgmt_protect/la_data_in_mprj[109] = 1 | mgmt_core_wrapper/la_input[88] = 1
|
Net: soc/la_input[10] |Net: \la_data_in_mprj[87]
mgmt_core_wrapper/la_input[10] = 1 | mgmt_protect/la_data_in_mprj[87] = 1
mgmt_protect/la_data_in_mprj[10] = 1 | mgmt_core_wrapper/la_input[87] = 1
|
Net: soc/la_input[110] |Net: \la_data_in_mprj[86]
mgmt_core_wrapper/la_input[110] = 1 | mgmt_protect/la_data_in_mprj[86] = 1
mgmt_protect/la_data_in_mprj[110] = 1 | mgmt_core_wrapper/la_input[86] = 1
|
Net: soc/la_input[111] |Net: \la_data_in_mprj[85]
mgmt_core_wrapper/la_input[111] = 1 | mgmt_protect/la_data_in_mprj[85] = 1
mgmt_protect/la_data_in_mprj[111] = 1 | mgmt_core_wrapper/la_input[85] = 1
|
Net: soc/la_input[112] |Net: \la_data_in_mprj[84]
mgmt_core_wrapper/la_input[112] = 1 | mgmt_protect/la_data_in_mprj[84] = 1
mgmt_protect/la_data_in_mprj[112] = 1 | mgmt_core_wrapper/la_input[84] = 1
|
Net: soc/la_input[113] |Net: \la_data_in_mprj[83]
mgmt_core_wrapper/la_input[113] = 1 | mgmt_protect/la_data_in_mprj[83] = 1
mgmt_protect/la_data_in_mprj[113] = 1 | mgmt_core_wrapper/la_input[83] = 1
|
Net: soc/la_input[114] |Net: \la_data_in_mprj[82]
mgmt_core_wrapper/la_input[114] = 1 | mgmt_protect/la_data_in_mprj[82] = 1
mgmt_protect/la_data_in_mprj[114] = 1 | mgmt_core_wrapper/la_input[82] = 1
|
Net: soc/la_input[115] |Net: \la_data_in_mprj[81]
mgmt_core_wrapper/la_input[115] = 1 | mgmt_protect/la_data_in_mprj[81] = 1
mgmt_protect/la_data_in_mprj[115] = 1 | mgmt_core_wrapper/la_input[81] = 1
|
Net: soc/la_input[116] |Net: \la_data_in_mprj[80]
mgmt_core_wrapper/la_input[116] = 1 | mgmt_protect/la_data_in_mprj[80] = 1
mgmt_protect/la_data_in_mprj[116] = 1 | mgmt_core_wrapper/la_input[80] = 1
|
Net: soc/la_input[117] |Net: \la_data_in_mprj[79]
mgmt_core_wrapper/la_input[117] = 1 | mgmt_protect/la_data_in_mprj[79] = 1
mgmt_protect/la_data_in_mprj[117] = 1 | mgmt_core_wrapper/la_input[79] = 1
|
Net: soc/la_input[118] |Net: \la_data_in_mprj[78]
mgmt_core_wrapper/la_input[118] = 1 | mgmt_protect/la_data_in_mprj[78] = 1
mgmt_protect/la_data_in_mprj[118] = 1 | mgmt_core_wrapper/la_input[78] = 1
|
Net: soc/la_input[119] |Net: \la_data_in_mprj[77]
mgmt_core_wrapper/la_input[119] = 1 | mgmt_protect/la_data_in_mprj[77] = 1
mgmt_protect/la_data_in_mprj[119] = 1 | mgmt_core_wrapper/la_input[77] = 1
|
Net: soc/la_input[11] |Net: \la_data_in_mprj[76]
mgmt_core_wrapper/la_input[11] = 1 | mgmt_protect/la_data_in_mprj[76] = 1
mgmt_protect/la_data_in_mprj[11] = 1 | mgmt_core_wrapper/la_input[76] = 1
|
Net: soc/la_input[120] |Net: \la_data_in_mprj[75]
mgmt_core_wrapper/la_input[120] = 1 | mgmt_protect/la_data_in_mprj[75] = 1
mgmt_protect/la_data_in_mprj[120] = 1 | mgmt_core_wrapper/la_input[75] = 1
|
Net: soc/la_input[121] |Net: \la_data_in_mprj[74]
mgmt_core_wrapper/la_input[121] = 1 | mgmt_protect/la_data_in_mprj[74] = 1
mgmt_protect/la_data_in_mprj[121] = 1 | mgmt_core_wrapper/la_input[74] = 1
|
Net: soc/la_input[122] |Net: \la_data_in_mprj[73]
mgmt_core_wrapper/la_input[122] = 1 | mgmt_protect/la_data_in_mprj[73] = 1
mgmt_protect/la_data_in_mprj[122] = 1 | mgmt_core_wrapper/la_input[73] = 1
|
Net: soc/la_input[123] |Net: \la_data_in_mprj[72]
mgmt_core_wrapper/la_input[123] = 1 | mgmt_protect/la_data_in_mprj[72] = 1
mgmt_protect/la_data_in_mprj[123] = 1 | mgmt_core_wrapper/la_input[72] = 1
|
Net: soc/la_input[124] |Net: \la_data_in_mprj[71]
mgmt_core_wrapper/la_input[124] = 1 | mgmt_protect/la_data_in_mprj[71] = 1
mgmt_protect/la_data_in_mprj[124] = 1 | mgmt_core_wrapper/la_input[71] = 1
|
Net: soc/la_input[125] |Net: \la_data_in_mprj[70]
mgmt_core_wrapper/la_input[125] = 1 | mgmt_protect/la_data_in_mprj[70] = 1
mgmt_protect/la_data_in_mprj[125] = 1 | mgmt_core_wrapper/la_input[70] = 1
|
Net: soc/la_input[126] |Net: \la_data_in_mprj[69]
mgmt_core_wrapper/la_input[126] = 1 | mgmt_protect/la_data_in_mprj[69] = 1
mgmt_protect/la_data_in_mprj[126] = 1 | mgmt_core_wrapper/la_input[69] = 1
|
Net: soc/la_input[127] |Net: \la_data_in_mprj[68]
mgmt_core_wrapper/la_input[127] = 1 | mgmt_protect/la_data_in_mprj[68] = 1
mgmt_protect/la_data_in_mprj[127] = 1 | mgmt_core_wrapper/la_input[68] = 1
|
Net: soc/la_input[12] |Net: \la_data_in_mprj[67]
mgmt_core_wrapper/la_input[12] = 1 | mgmt_protect/la_data_in_mprj[67] = 1
mgmt_protect/la_data_in_mprj[12] = 1 | mgmt_core_wrapper/la_input[67] = 1
|
Net: soc/la_input[13] |Net: \la_data_in_mprj[66]
mgmt_core_wrapper/la_input[13] = 1 | mgmt_protect/la_data_in_mprj[66] = 1
mgmt_protect/la_data_in_mprj[13] = 1 | mgmt_core_wrapper/la_input[66] = 1
|
Net: soc/la_input[14] |Net: \la_data_in_mprj[65]
mgmt_core_wrapper/la_input[14] = 1 | mgmt_protect/la_data_in_mprj[65] = 1
mgmt_protect/la_data_in_mprj[14] = 1 | mgmt_core_wrapper/la_input[65] = 1
|
Net: soc/la_input[15] |Net: \la_data_in_mprj[64]
mgmt_core_wrapper/la_input[15] = 1 | mgmt_protect/la_data_in_mprj[64] = 1
mgmt_protect/la_data_in_mprj[15] = 1 | mgmt_core_wrapper/la_input[64] = 1
|
Net: soc/la_input[16] |Net: \la_data_in_mprj[63]
mgmt_core_wrapper/la_input[16] = 1 | mgmt_protect/la_data_in_mprj[63] = 1
mgmt_protect/la_data_in_mprj[16] = 1 | mgmt_core_wrapper/la_input[63] = 1
|
Net: soc/la_input[17] |Net: \la_data_in_mprj[62]
mgmt_core_wrapper/la_input[17] = 1 | mgmt_protect/la_data_in_mprj[62] = 1
mgmt_protect/la_data_in_mprj[17] = 1 | mgmt_core_wrapper/la_input[62] = 1
|
Net: soc/la_input[18] |Net: \la_data_in_mprj[61]
mgmt_core_wrapper/la_input[18] = 1 | mgmt_protect/la_data_in_mprj[61] = 1
mgmt_protect/la_data_in_mprj[18] = 1 | mgmt_core_wrapper/la_input[61] = 1
|
Net: soc/la_input[19] |Net: \la_data_in_mprj[60]
mgmt_core_wrapper/la_input[19] = 1 | mgmt_protect/la_data_in_mprj[60] = 1
mgmt_protect/la_data_in_mprj[19] = 1 | mgmt_core_wrapper/la_input[60] = 1
|
Net: soc/la_input[1] |Net: \la_data_in_mprj[59]
mgmt_core_wrapper/la_input[1] = 1 | mgmt_protect/la_data_in_mprj[59] = 1
mgmt_protect/la_data_in_mprj[1] = 1 | mgmt_core_wrapper/la_input[59] = 1
|
Net: soc/la_input[20] |Net: \la_data_in_mprj[58]
mgmt_core_wrapper/la_input[20] = 1 | mgmt_protect/la_data_in_mprj[58] = 1
mgmt_protect/la_data_in_mprj[20] = 1 | mgmt_core_wrapper/la_input[58] = 1
|
Net: soc/la_input[21] |Net: \la_data_in_mprj[57]
mgmt_core_wrapper/la_input[21] = 1 | mgmt_protect/la_data_in_mprj[57] = 1
mgmt_protect/la_data_in_mprj[21] = 1 | mgmt_core_wrapper/la_input[57] = 1
|
Net: soc/la_input[22] |Net: \la_data_in_mprj[56]
mgmt_core_wrapper/la_input[22] = 1 | mgmt_protect/la_data_in_mprj[56] = 1
mgmt_protect/la_data_in_mprj[22] = 1 | mgmt_core_wrapper/la_input[56] = 1
|
Net: soc/la_input[23] |Net: \la_data_in_mprj[55]
mgmt_core_wrapper/la_input[23] = 1 | mgmt_protect/la_data_in_mprj[55] = 1
mgmt_protect/la_data_in_mprj[23] = 1 | mgmt_core_wrapper/la_input[55] = 1
|
Net: soc/la_input[24] |Net: \la_data_in_mprj[54]
mgmt_core_wrapper/la_input[24] = 1 | mgmt_protect/la_data_in_mprj[54] = 1
mgmt_protect/la_data_in_mprj[24] = 1 | mgmt_core_wrapper/la_input[54] = 1
|
Net: soc/la_input[25] |Net: \la_data_in_mprj[53]
mgmt_core_wrapper/la_input[25] = 1 | mgmt_protect/la_data_in_mprj[53] = 1
mgmt_protect/la_data_in_mprj[25] = 1 | mgmt_core_wrapper/la_input[53] = 1
|
Net: soc/la_input[26] |Net: \la_data_in_mprj[52]
mgmt_core_wrapper/la_input[26] = 1 | mgmt_protect/la_data_in_mprj[52] = 1
mgmt_protect/la_data_in_mprj[26] = 1 | mgmt_core_wrapper/la_input[52] = 1
|
Net: soc/la_input[27] |Net: \la_data_in_mprj[51]
mgmt_core_wrapper/la_input[27] = 1 | mgmt_protect/la_data_in_mprj[51] = 1
mgmt_protect/la_data_in_mprj[27] = 1 | mgmt_core_wrapper/la_input[51] = 1
|
Net: soc/la_input[28] |Net: \la_data_in_mprj[50]
mgmt_core_wrapper/la_input[28] = 1 | mgmt_protect/la_data_in_mprj[50] = 1
mgmt_protect/la_data_in_mprj[28] = 1 | mgmt_core_wrapper/la_input[50] = 1
|
Net: soc/la_input[29] |Net: \la_data_in_mprj[49]
mgmt_core_wrapper/la_input[29] = 1 | mgmt_protect/la_data_in_mprj[49] = 1
mgmt_protect/la_data_in_mprj[29] = 1 | mgmt_core_wrapper/la_input[49] = 1
|
Net: soc/la_input[2] |Net: \la_data_in_mprj[48]
mgmt_core_wrapper/la_input[2] = 1 | mgmt_protect/la_data_in_mprj[48] = 1
mgmt_protect/la_data_in_mprj[2] = 1 | mgmt_core_wrapper/la_input[48] = 1
|
Net: soc/la_input[30] |Net: \la_data_in_mprj[47]
mgmt_core_wrapper/la_input[30] = 1 | mgmt_protect/la_data_in_mprj[47] = 1
mgmt_protect/la_data_in_mprj[30] = 1 | mgmt_core_wrapper/la_input[47] = 1
|
Net: soc/la_input[31] |Net: \la_data_in_mprj[46]
mgmt_core_wrapper/la_input[31] = 1 | mgmt_protect/la_data_in_mprj[46] = 1
mgmt_protect/la_data_in_mprj[31] = 1 | mgmt_core_wrapper/la_input[46] = 1
|
Net: soc/la_input[32] |Net: \la_data_in_mprj[45]
mgmt_core_wrapper/la_input[32] = 1 | mgmt_protect/la_data_in_mprj[45] = 1
mgmt_protect/la_data_in_mprj[32] = 1 | mgmt_core_wrapper/la_input[45] = 1
|
Net: soc/la_input[33] |Net: \la_data_in_mprj[44]
mgmt_core_wrapper/la_input[33] = 1 | mgmt_protect/la_data_in_mprj[44] = 1
mgmt_protect/la_data_in_mprj[33] = 1 | mgmt_core_wrapper/la_input[44] = 1
|
Net: soc/la_input[34] |Net: \la_data_in_mprj[43]
mgmt_core_wrapper/la_input[34] = 1 | mgmt_protect/la_data_in_mprj[43] = 1
mgmt_protect/la_data_in_mprj[34] = 1 | mgmt_core_wrapper/la_input[43] = 1
|
Net: soc/la_input[35] |Net: \la_data_in_mprj[42]
mgmt_core_wrapper/la_input[35] = 1 | mgmt_protect/la_data_in_mprj[42] = 1
mgmt_protect/la_data_in_mprj[35] = 1 | mgmt_core_wrapper/la_input[42] = 1
|
Net: soc/la_input[36] |Net: \la_data_in_mprj[41]
mgmt_core_wrapper/la_input[36] = 1 | mgmt_protect/la_data_in_mprj[41] = 1
mgmt_protect/la_data_in_mprj[36] = 1 | mgmt_core_wrapper/la_input[41] = 1
|
Net: soc/la_input[37] |Net: \la_data_in_mprj[40]
mgmt_core_wrapper/la_input[37] = 1 | mgmt_protect/la_data_in_mprj[40] = 1
mgmt_protect/la_data_in_mprj[37] = 1 | mgmt_core_wrapper/la_input[40] = 1
|
Net: soc/la_input[38] |Net: \la_data_in_mprj[39]
mgmt_core_wrapper/la_input[38] = 1 | mgmt_protect/la_data_in_mprj[39] = 1
mgmt_protect/la_data_in_mprj[38] = 1 | mgmt_core_wrapper/la_input[39] = 1
|
Net: soc/la_input[39] |Net: \la_data_in_mprj[38]
mgmt_core_wrapper/la_input[39] = 1 | mgmt_protect/la_data_in_mprj[38] = 1
mgmt_protect/la_data_in_mprj[39] = 1 | mgmt_core_wrapper/la_input[38] = 1
|
Net: soc/la_input[3] |Net: \la_data_in_mprj[37]
mgmt_core_wrapper/la_input[3] = 1 | mgmt_protect/la_data_in_mprj[37] = 1
mgmt_protect/la_data_in_mprj[3] = 1 | mgmt_core_wrapper/la_input[37] = 1
|
Net: soc/la_input[40] |Net: \la_data_in_mprj[36]
mgmt_core_wrapper/la_input[40] = 1 | mgmt_protect/la_data_in_mprj[36] = 1
mgmt_protect/la_data_in_mprj[40] = 1 | mgmt_core_wrapper/la_input[36] = 1
|
Net: soc/la_input[41] |Net: \la_data_in_mprj[35]
mgmt_core_wrapper/la_input[41] = 1 | mgmt_protect/la_data_in_mprj[35] = 1
mgmt_protect/la_data_in_mprj[41] = 1 | mgmt_core_wrapper/la_input[35] = 1
|
Net: soc/la_input[42] |Net: \la_data_in_mprj[34]
mgmt_core_wrapper/la_input[42] = 1 | mgmt_protect/la_data_in_mprj[34] = 1
mgmt_protect/la_data_in_mprj[42] = 1 | mgmt_core_wrapper/la_input[34] = 1
|
Net: soc/la_input[43] |Net: \la_data_in_mprj[33]
mgmt_core_wrapper/la_input[43] = 1 | mgmt_protect/la_data_in_mprj[33] = 1
mgmt_protect/la_data_in_mprj[43] = 1 | mgmt_core_wrapper/la_input[33] = 1
|
Net: soc/la_input[44] |Net: \la_data_in_mprj[32]
mgmt_core_wrapper/la_input[44] = 1 | mgmt_protect/la_data_in_mprj[32] = 1
mgmt_protect/la_data_in_mprj[44] = 1 | mgmt_core_wrapper/la_input[32] = 1
|
Net: soc/la_input[45] |Net: \la_data_in_mprj[31]
mgmt_core_wrapper/la_input[45] = 1 | mgmt_protect/la_data_in_mprj[31] = 1
mgmt_protect/la_data_in_mprj[45] = 1 | mgmt_core_wrapper/la_input[31] = 1
|
Net: soc/la_input[46] |Net: \la_data_in_mprj[30]
mgmt_core_wrapper/la_input[46] = 1 | mgmt_protect/la_data_in_mprj[30] = 1
mgmt_protect/la_data_in_mprj[46] = 1 | mgmt_core_wrapper/la_input[30] = 1
|
Net: soc/la_input[47] |Net: \la_data_in_mprj[29]
mgmt_core_wrapper/la_input[47] = 1 | mgmt_protect/la_data_in_mprj[29] = 1
mgmt_protect/la_data_in_mprj[47] = 1 | mgmt_core_wrapper/la_input[29] = 1
|
Net: soc/la_input[48] |Net: \la_data_in_mprj[28]
mgmt_core_wrapper/la_input[48] = 1 | mgmt_protect/la_data_in_mprj[28] = 1
mgmt_protect/la_data_in_mprj[48] = 1 | mgmt_core_wrapper/la_input[28] = 1
|
Net: soc/la_input[49] |Net: \la_data_in_mprj[27]
mgmt_core_wrapper/la_input[49] = 1 | mgmt_protect/la_data_in_mprj[27] = 1
mgmt_protect/la_data_in_mprj[49] = 1 | mgmt_core_wrapper/la_input[27] = 1
|
Net: soc/la_input[4] |Net: \la_data_in_mprj[26]
mgmt_core_wrapper/la_input[4] = 1 | mgmt_protect/la_data_in_mprj[26] = 1
mgmt_protect/la_data_in_mprj[4] = 1 | mgmt_core_wrapper/la_input[26] = 1
|
Net: soc/la_input[50] |Net: \la_data_in_mprj[25]
mgmt_core_wrapper/la_input[50] = 1 | mgmt_protect/la_data_in_mprj[25] = 1
mgmt_protect/la_data_in_mprj[50] = 1 | mgmt_core_wrapper/la_input[25] = 1
|
Net: soc/la_input[51] |Net: \la_data_in_mprj[24]
mgmt_core_wrapper/la_input[51] = 1 | mgmt_protect/la_data_in_mprj[24] = 1
mgmt_protect/la_data_in_mprj[51] = 1 | mgmt_core_wrapper/la_input[24] = 1
|
Net: soc/la_input[52] |Net: \la_data_in_mprj[23]
mgmt_core_wrapper/la_input[52] = 1 | mgmt_protect/la_data_in_mprj[23] = 1
mgmt_protect/la_data_in_mprj[52] = 1 | mgmt_core_wrapper/la_input[23] = 1
|
Net: soc/la_input[53] |Net: \la_data_in_mprj[22]
mgmt_core_wrapper/la_input[53] = 1 | mgmt_protect/la_data_in_mprj[22] = 1
mgmt_protect/la_data_in_mprj[53] = 1 | mgmt_core_wrapper/la_input[22] = 1
|
Net: soc/la_input[54] |Net: \la_data_in_mprj[21]
mgmt_core_wrapper/la_input[54] = 1 | mgmt_protect/la_data_in_mprj[21] = 1
mgmt_protect/la_data_in_mprj[54] = 1 | mgmt_core_wrapper/la_input[21] = 1
|
Net: soc/la_input[55] |Net: \la_data_in_mprj[20]
mgmt_core_wrapper/la_input[55] = 1 | mgmt_protect/la_data_in_mprj[20] = 1
mgmt_protect/la_data_in_mprj[55] = 1 | mgmt_core_wrapper/la_input[20] = 1
|
Net: soc/la_input[56] |Net: \la_data_in_mprj[19]
mgmt_core_wrapper/la_input[56] = 1 | mgmt_protect/la_data_in_mprj[19] = 1
mgmt_protect/la_data_in_mprj[56] = 1 | mgmt_core_wrapper/la_input[19] = 1
|
Net: soc/la_input[57] |Net: \la_data_in_mprj[18]
mgmt_core_wrapper/la_input[57] = 1 | mgmt_protect/la_data_in_mprj[18] = 1
mgmt_protect/la_data_in_mprj[57] = 1 | mgmt_core_wrapper/la_input[18] = 1
|
Net: soc/la_input[58] |Net: \la_data_in_mprj[17]
mgmt_core_wrapper/la_input[58] = 1 | mgmt_protect/la_data_in_mprj[17] = 1
mgmt_protect/la_data_in_mprj[58] = 1 | mgmt_core_wrapper/la_input[17] = 1
|
Net: soc/la_input[59] |Net: \la_data_in_mprj[16]
mgmt_core_wrapper/la_input[59] = 1 | mgmt_protect/la_data_in_mprj[16] = 1
mgmt_protect/la_data_in_mprj[59] = 1 | mgmt_core_wrapper/la_input[16] = 1
|
Net: soc/la_input[5] |Net: \la_data_in_mprj[15]
mgmt_core_wrapper/la_input[5] = 1 | mgmt_protect/la_data_in_mprj[15] = 1
mgmt_protect/la_data_in_mprj[5] = 1 | mgmt_core_wrapper/la_input[15] = 1
|
Net: soc/la_input[60] |Net: \la_data_in_mprj[14]
mgmt_core_wrapper/la_input[60] = 1 | mgmt_protect/la_data_in_mprj[14] = 1
mgmt_protect/la_data_in_mprj[60] = 1 | mgmt_core_wrapper/la_input[14] = 1
|
Net: soc/la_input[61] |Net: \la_data_in_mprj[13]
mgmt_core_wrapper/la_input[61] = 1 | mgmt_protect/la_data_in_mprj[13] = 1
mgmt_protect/la_data_in_mprj[61] = 1 | mgmt_core_wrapper/la_input[13] = 1
|
Net: soc/la_input[62] |Net: \la_data_in_mprj[12]
mgmt_core_wrapper/la_input[62] = 1 | mgmt_protect/la_data_in_mprj[12] = 1
mgmt_protect/la_data_in_mprj[62] = 1 | mgmt_core_wrapper/la_input[12] = 1
|
Net: soc/la_input[63] |Net: \la_data_in_mprj[11]
mgmt_core_wrapper/la_input[63] = 1 | mgmt_protect/la_data_in_mprj[11] = 1
mgmt_protect/la_data_in_mprj[63] = 1 | mgmt_core_wrapper/la_input[11] = 1
|
Net: soc/la_input[64] |Net: \la_data_in_mprj[10]
mgmt_core_wrapper/la_input[64] = 1 | mgmt_protect/la_data_in_mprj[10] = 1
mgmt_protect/la_data_in_mprj[64] = 1 | mgmt_core_wrapper/la_input[10] = 1
|
Net: soc/la_input[65] |Net: \la_data_in_mprj[9]
mgmt_core_wrapper/la_input[65] = 1 | mgmt_protect/la_data_in_mprj[9] = 1
mgmt_protect/la_data_in_mprj[65] = 1 | mgmt_core_wrapper/la_input[9] = 1
|
Net: soc/la_input[66] |Net: \la_data_in_mprj[8]
mgmt_core_wrapper/la_input[66] = 1 | mgmt_protect/la_data_in_mprj[8] = 1
mgmt_protect/la_data_in_mprj[66] = 1 | mgmt_core_wrapper/la_input[8] = 1
|
Net: soc/la_input[67] |Net: \la_data_in_mprj[7]
mgmt_core_wrapper/la_input[67] = 1 | mgmt_protect/la_data_in_mprj[7] = 1
mgmt_protect/la_data_in_mprj[67] = 1 | mgmt_core_wrapper/la_input[7] = 1
|
Net: soc/la_input[68] |Net: \la_data_in_mprj[6]
mgmt_core_wrapper/la_input[68] = 1 | mgmt_protect/la_data_in_mprj[6] = 1
mgmt_protect/la_data_in_mprj[68] = 1 | mgmt_core_wrapper/la_input[6] = 1
|
Net: soc/la_input[69] |Net: \la_data_in_mprj[5]
mgmt_core_wrapper/la_input[69] = 1 | mgmt_protect/la_data_in_mprj[5] = 1
mgmt_protect/la_data_in_mprj[69] = 1 | mgmt_core_wrapper/la_input[5] = 1
|
Net: soc/la_input[6] |Net: \la_data_in_mprj[4]
mgmt_core_wrapper/la_input[6] = 1 | mgmt_protect/la_data_in_mprj[4] = 1
mgmt_protect/la_data_in_mprj[6] = 1 | mgmt_core_wrapper/la_input[4] = 1
|
Net: soc/la_input[70] |Net: \la_data_in_mprj[3]
mgmt_core_wrapper/la_input[70] = 1 | mgmt_protect/la_data_in_mprj[3] = 1
mgmt_protect/la_data_in_mprj[70] = 1 | mgmt_core_wrapper/la_input[3] = 1
|
Net: soc/la_input[71] |Net: \la_data_in_mprj[2]
mgmt_core_wrapper/la_input[71] = 1 | mgmt_protect/la_data_in_mprj[2] = 1
mgmt_protect/la_data_in_mprj[71] = 1 | mgmt_core_wrapper/la_input[2] = 1
|
Net: soc/la_input[72] |Net: \la_data_in_mprj[1]
mgmt_core_wrapper/la_input[72] = 1 | mgmt_protect/la_data_in_mprj[1] = 1
mgmt_protect/la_data_in_mprj[72] = 1 | mgmt_core_wrapper/la_input[1] = 1
|
Net: soc/la_input[73] |Net: \la_data_in_mprj[0]
mgmt_core_wrapper/la_input[73] = 1 | mgmt_protect/la_data_in_mprj[0] = 1
mgmt_protect/la_data_in_mprj[73] = 1 | mgmt_core_wrapper/la_input[0] = 1
|
Net: soc/la_input[74] |Net: \la_data_out_user[127]
mgmt_core_wrapper/la_input[74] = 1 | mgmt_protect/la_data_out_core[127] = 1
mgmt_protect/la_data_in_mprj[74] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[75] |Net: \la_data_out_user[126]
mgmt_core_wrapper/la_input[75] = 1 | mgmt_protect/la_data_out_core[126] = 1
mgmt_protect/la_data_in_mprj[75] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[76] |Net: \la_data_out_user[125]
mgmt_core_wrapper/la_input[76] = 1 | mgmt_protect/la_data_out_core[125] = 1
mgmt_protect/la_data_in_mprj[76] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[77] |Net: \la_data_out_user[124]
mgmt_core_wrapper/la_input[77] = 1 | mgmt_protect/la_data_out_core[124] = 1
mgmt_protect/la_data_in_mprj[77] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[78] |Net: \la_data_out_user[123]
mgmt_core_wrapper/la_input[78] = 1 | mgmt_protect/la_data_out_core[123] = 1
mgmt_protect/la_data_in_mprj[78] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[79] |Net: \la_data_out_user[122]
mgmt_core_wrapper/la_input[79] = 1 | mgmt_protect/la_data_out_core[122] = 1
mgmt_protect/la_data_in_mprj[79] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[7] |Net: \la_data_out_user[121]
mgmt_core_wrapper/la_input[7] = 1 | mgmt_protect/la_data_out_core[121] = 1
mgmt_protect/la_data_in_mprj[7] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[80] |Net: \la_data_out_user[120]
mgmt_core_wrapper/la_input[80] = 1 | mgmt_protect/la_data_out_core[120] = 1
mgmt_protect/la_data_in_mprj[80] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[81] |Net: \la_data_out_user[119]
mgmt_core_wrapper/la_input[81] = 1 | mgmt_protect/la_data_out_core[119] = 1
mgmt_protect/la_data_in_mprj[81] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[82] |Net: \la_data_out_user[118]
mgmt_core_wrapper/la_input[82] = 1 | mgmt_protect/la_data_out_core[118] = 1
mgmt_protect/la_data_in_mprj[82] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[83] |Net: \la_data_out_user[117]
mgmt_core_wrapper/la_input[83] = 1 | mgmt_protect/la_data_out_core[117] = 1
mgmt_protect/la_data_in_mprj[83] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[84] |Net: \la_data_out_user[116]
mgmt_core_wrapper/la_input[84] = 1 | mgmt_protect/la_data_out_core[116] = 1
mgmt_protect/la_data_in_mprj[84] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[85] |Net: \la_data_out_user[115]
mgmt_core_wrapper/la_input[85] = 1 | mgmt_protect/la_data_out_core[115] = 1
mgmt_protect/la_data_in_mprj[85] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[86] |Net: \la_data_out_user[114]
mgmt_core_wrapper/la_input[86] = 1 | mgmt_protect/la_data_out_core[114] = 1
mgmt_protect/la_data_in_mprj[86] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[87] |Net: \la_data_out_user[113]
mgmt_core_wrapper/la_input[87] = 1 | mgmt_protect/la_data_out_core[113] = 1
mgmt_protect/la_data_in_mprj[87] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[88] |Net: \la_data_out_user[112]
mgmt_core_wrapper/la_input[88] = 1 | mgmt_protect/la_data_out_core[112] = 1
mgmt_protect/la_data_in_mprj[88] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[89] |Net: \la_data_out_user[111]
mgmt_core_wrapper/la_input[89] = 1 | mgmt_protect/la_data_out_core[111] = 1
mgmt_protect/la_data_in_mprj[89] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[8] |Net: \la_data_out_user[110]
mgmt_core_wrapper/la_input[8] = 1 | mgmt_protect/la_data_out_core[110] = 1
mgmt_protect/la_data_in_mprj[8] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[90] |Net: \la_data_out_user[109]
mgmt_core_wrapper/la_input[90] = 1 | mgmt_protect/la_data_out_core[109] = 1
mgmt_protect/la_data_in_mprj[90] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[91] |Net: \la_data_out_user[108]
mgmt_core_wrapper/la_input[91] = 1 | mgmt_protect/la_data_out_core[108] = 1
mgmt_protect/la_data_in_mprj[91] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[92] |Net: \la_data_out_user[107]
mgmt_core_wrapper/la_input[92] = 1 | mgmt_protect/la_data_out_core[107] = 1
mgmt_protect/la_data_in_mprj[92] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[93] |Net: \la_data_out_user[106]
mgmt_core_wrapper/la_input[93] = 1 | mgmt_protect/la_data_out_core[106] = 1
mgmt_protect/la_data_in_mprj[93] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[94] |Net: \la_data_out_user[105]
mgmt_core_wrapper/la_input[94] = 1 | mgmt_protect/la_data_out_core[105] = 1
mgmt_protect/la_data_in_mprj[94] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[95] |Net: \la_data_out_user[104]
mgmt_core_wrapper/la_input[95] = 1 | mgmt_protect/la_data_out_core[104] = 1
mgmt_protect/la_data_in_mprj[95] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[96] |Net: \la_data_out_user[103]
mgmt_core_wrapper/la_input[96] = 1 | mgmt_protect/la_data_out_core[103] = 1
mgmt_protect/la_data_in_mprj[96] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[97] |Net: \la_data_out_user[102]
mgmt_core_wrapper/la_input[97] = 1 | mgmt_protect/la_data_out_core[102] = 1
mgmt_protect/la_data_in_mprj[97] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[98] |Net: \la_data_out_user[101]
mgmt_core_wrapper/la_input[98] = 1 | mgmt_protect/la_data_out_core[101] = 1
mgmt_protect/la_data_in_mprj[98] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[99] |Net: \la_data_out_user[100]
mgmt_core_wrapper/la_input[99] = 1 | mgmt_protect/la_data_out_core[100] = 1
mgmt_protect/la_data_in_mprj[99] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_input[9] |Net: \la_data_out_user[99]
mgmt_core_wrapper/la_input[9] = 1 | mgmt_protect/la_data_out_core[99] = 1
mgmt_protect/la_data_in_mprj[9] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[0] |Net: \la_data_out_user[98]
mgmt_core_wrapper/la_oenb[0] = 1 | mgmt_protect/la_data_out_core[98] = 1
mgmt_protect/la_oenb_mprj[0] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[100] |Net: \la_data_out_user[97]
mgmt_core_wrapper/la_oenb[100] = 1 | mgmt_protect/la_data_out_core[97] = 1
mgmt_protect/la_oenb_mprj[100] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[101] |Net: \la_data_out_user[96]
mgmt_core_wrapper/la_oenb[101] = 1 | mgmt_protect/la_data_out_core[96] = 1
mgmt_protect/la_oenb_mprj[101] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[102] |Net: \la_data_out_user[95]
mgmt_core_wrapper/la_oenb[102] = 1 | mgmt_protect/la_data_out_core[95] = 1
mgmt_protect/la_oenb_mprj[102] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[103] |Net: \la_data_out_user[94]
mgmt_core_wrapper/la_oenb[103] = 1 | mgmt_protect/la_data_out_core[94] = 1
mgmt_protect/la_oenb_mprj[103] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[104] |Net: \la_data_out_user[93]
mgmt_core_wrapper/la_oenb[104] = 1 | mgmt_protect/la_data_out_core[93] = 1
mgmt_protect/la_oenb_mprj[104] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[105] |Net: \la_data_out_user[92]
mgmt_core_wrapper/la_oenb[105] = 1 | mgmt_protect/la_data_out_core[92] = 1
mgmt_protect/la_oenb_mprj[105] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[106] |Net: \la_data_out_user[91]
mgmt_core_wrapper/la_oenb[106] = 1 | mgmt_protect/la_data_out_core[91] = 1
mgmt_protect/la_oenb_mprj[106] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[107] |Net: \la_data_out_user[90]
mgmt_core_wrapper/la_oenb[107] = 1 | mgmt_protect/la_data_out_core[90] = 1
mgmt_protect/la_oenb_mprj[107] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[108] |Net: \la_data_out_user[89]
mgmt_core_wrapper/la_oenb[108] = 1 | mgmt_protect/la_data_out_core[89] = 1
mgmt_protect/la_oenb_mprj[108] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[109] |Net: \la_data_out_user[88]
mgmt_core_wrapper/la_oenb[109] = 1 | mgmt_protect/la_data_out_core[88] = 1
mgmt_protect/la_oenb_mprj[109] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[10] |Net: \la_data_out_user[87]
mgmt_core_wrapper/la_oenb[10] = 1 | mgmt_protect/la_data_out_core[87] = 1
mgmt_protect/la_oenb_mprj[10] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[110] |Net: \la_data_out_user[86]
mgmt_core_wrapper/la_oenb[110] = 1 | mgmt_protect/la_data_out_core[86] = 1
mgmt_protect/la_oenb_mprj[110] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[111] |Net: \la_data_out_user[85]
mgmt_core_wrapper/la_oenb[111] = 1 | mgmt_protect/la_data_out_core[85] = 1
mgmt_protect/la_oenb_mprj[111] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[112] |Net: \la_data_out_user[84]
mgmt_core_wrapper/la_oenb[112] = 1 | mgmt_protect/la_data_out_core[84] = 1
mgmt_protect/la_oenb_mprj[112] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[113] |Net: \la_data_out_user[83]
mgmt_core_wrapper/la_oenb[113] = 1 | mgmt_protect/la_data_out_core[83] = 1
mgmt_protect/la_oenb_mprj[113] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[114] |Net: \la_data_out_user[82]
mgmt_core_wrapper/la_oenb[114] = 1 | mgmt_protect/la_data_out_core[82] = 1
mgmt_protect/la_oenb_mprj[114] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[115] |Net: \la_data_out_user[81]
mgmt_core_wrapper/la_oenb[115] = 1 | mgmt_protect/la_data_out_core[81] = 1
mgmt_protect/la_oenb_mprj[115] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[116] |Net: \la_data_out_user[80]
mgmt_core_wrapper/la_oenb[116] = 1 | mgmt_protect/la_data_out_core[80] = 1
mgmt_protect/la_oenb_mprj[116] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[117] |Net: \la_data_out_user[79]
mgmt_core_wrapper/la_oenb[117] = 1 | mgmt_protect/la_data_out_core[79] = 1
mgmt_protect/la_oenb_mprj[117] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[118] |Net: \la_data_out_user[78]
mgmt_core_wrapper/la_oenb[118] = 1 | mgmt_protect/la_data_out_core[78] = 1
mgmt_protect/la_oenb_mprj[118] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[119] |Net: \la_data_out_user[77]
mgmt_core_wrapper/la_oenb[119] = 1 | mgmt_protect/la_data_out_core[77] = 1
mgmt_protect/la_oenb_mprj[119] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[11] |Net: \la_data_out_user[76]
mgmt_core_wrapper/la_oenb[11] = 1 | mgmt_protect/la_data_out_core[76] = 1
mgmt_protect/la_oenb_mprj[11] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[120] |Net: \la_data_out_user[75]
mgmt_core_wrapper/la_oenb[120] = 1 | mgmt_protect/la_data_out_core[75] = 1
mgmt_protect/la_oenb_mprj[120] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[121] |Net: \la_data_out_user[74]
mgmt_core_wrapper/la_oenb[121] = 1 | mgmt_protect/la_data_out_core[74] = 1
mgmt_protect/la_oenb_mprj[121] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[122] |Net: \la_data_out_user[73]
mgmt_core_wrapper/la_oenb[122] = 1 | mgmt_protect/la_data_out_core[73] = 1
mgmt_protect/la_oenb_mprj[122] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[123] |Net: \la_data_out_user[72]
mgmt_core_wrapper/la_oenb[123] = 1 | mgmt_protect/la_data_out_core[72] = 1
mgmt_protect/la_oenb_mprj[123] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[124] |Net: \la_data_out_user[71]
mgmt_core_wrapper/la_oenb[124] = 1 | mgmt_protect/la_data_out_core[71] = 1
mgmt_protect/la_oenb_mprj[124] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[125] |Net: \la_data_out_user[70]
mgmt_core_wrapper/la_oenb[125] = 1 | mgmt_protect/la_data_out_core[70] = 1
mgmt_protect/la_oenb_mprj[125] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[126] |Net: \la_data_out_user[69]
mgmt_core_wrapper/la_oenb[126] = 1 | mgmt_protect/la_data_out_core[69] = 1
mgmt_protect/la_oenb_mprj[126] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[127] |Net: \la_data_out_user[68]
mgmt_core_wrapper/la_oenb[127] = 1 | mgmt_protect/la_data_out_core[68] = 1
mgmt_protect/la_oenb_mprj[127] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[12] |Net: \la_data_out_user[67]
mgmt_core_wrapper/la_oenb[12] = 1 | mgmt_protect/la_data_out_core[67] = 1
mgmt_protect/la_oenb_mprj[12] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[13] |Net: \la_data_out_user[66]
mgmt_core_wrapper/la_oenb[13] = 1 | mgmt_protect/la_data_out_core[66] = 1
mgmt_protect/la_oenb_mprj[13] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[14] |Net: \la_data_out_user[65]
mgmt_core_wrapper/la_oenb[14] = 1 | mgmt_protect/la_data_out_core[65] = 1
mgmt_protect/la_oenb_mprj[14] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[15] |Net: \la_data_out_user[64]
mgmt_core_wrapper/la_oenb[15] = 1 | mgmt_protect/la_data_out_core[64] = 1
mgmt_protect/la_oenb_mprj[15] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[16] |Net: \la_data_out_user[63]
mgmt_core_wrapper/la_oenb[16] = 1 | mgmt_protect/la_data_out_core[63] = 1
mgmt_protect/la_oenb_mprj[16] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[17] |Net: \la_data_out_user[62]
mgmt_core_wrapper/la_oenb[17] = 1 | mgmt_protect/la_data_out_core[62] = 1
mgmt_protect/la_oenb_mprj[17] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[18] |Net: \la_data_out_user[61]
mgmt_core_wrapper/la_oenb[18] = 1 | mgmt_protect/la_data_out_core[61] = 1
mgmt_protect/la_oenb_mprj[18] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[19] |Net: \la_data_out_user[60]
mgmt_core_wrapper/la_oenb[19] = 1 | mgmt_protect/la_data_out_core[60] = 1
mgmt_protect/la_oenb_mprj[19] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[1] |Net: \la_data_out_user[59]
mgmt_core_wrapper/la_oenb[1] = 1 | mgmt_protect/la_data_out_core[59] = 1
mgmt_protect/la_oenb_mprj[1] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[20] |Net: \la_data_out_user[58]
mgmt_core_wrapper/la_oenb[20] = 1 | mgmt_protect/la_data_out_core[58] = 1
mgmt_protect/la_oenb_mprj[20] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[21] |Net: \la_data_out_user[57]
mgmt_core_wrapper/la_oenb[21] = 1 | mgmt_protect/la_data_out_core[57] = 1
mgmt_protect/la_oenb_mprj[21] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[22] |Net: \la_data_out_user[56]
mgmt_core_wrapper/la_oenb[22] = 1 | mgmt_protect/la_data_out_core[56] = 1
mgmt_protect/la_oenb_mprj[22] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[23] |Net: \la_data_out_user[55]
mgmt_core_wrapper/la_oenb[23] = 1 | mgmt_protect/la_data_out_core[55] = 1
mgmt_protect/la_oenb_mprj[23] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[24] |Net: \la_data_out_user[54]
mgmt_core_wrapper/la_oenb[24] = 1 | mgmt_protect/la_data_out_core[54] = 1
mgmt_protect/la_oenb_mprj[24] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[25] |Net: \la_data_out_user[53]
mgmt_core_wrapper/la_oenb[25] = 1 | mgmt_protect/la_data_out_core[53] = 1
mgmt_protect/la_oenb_mprj[25] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[26] |Net: \la_data_out_user[52]
mgmt_core_wrapper/la_oenb[26] = 1 | mgmt_protect/la_data_out_core[52] = 1
mgmt_protect/la_oenb_mprj[26] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[27] |Net: \la_data_out_user[51]
mgmt_core_wrapper/la_oenb[27] = 1 | mgmt_protect/la_data_out_core[51] = 1
mgmt_protect/la_oenb_mprj[27] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[28] |Net: \la_data_out_user[50]
mgmt_core_wrapper/la_oenb[28] = 1 | mgmt_protect/la_data_out_core[50] = 1
mgmt_protect/la_oenb_mprj[28] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[29] |Net: \la_data_out_user[49]
mgmt_core_wrapper/la_oenb[29] = 1 | mgmt_protect/la_data_out_core[49] = 1
mgmt_protect/la_oenb_mprj[29] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[2] |Net: \la_data_out_user[48]
mgmt_core_wrapper/la_oenb[2] = 1 | mgmt_protect/la_data_out_core[48] = 1
mgmt_protect/la_oenb_mprj[2] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[30] |Net: \la_data_out_user[47]
mgmt_core_wrapper/la_oenb[30] = 1 | mgmt_protect/la_data_out_core[47] = 1
mgmt_protect/la_oenb_mprj[30] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[31] |Net: \la_data_out_user[46]
mgmt_core_wrapper/la_oenb[31] = 1 | mgmt_protect/la_data_out_core[46] = 1
mgmt_protect/la_oenb_mprj[31] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[32] |Net: \la_data_out_user[45]
mgmt_core_wrapper/la_oenb[32] = 1 | mgmt_protect/la_data_out_core[45] = 1
mgmt_protect/la_oenb_mprj[32] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[33] |Net: \la_data_out_user[44]
mgmt_core_wrapper/la_oenb[33] = 1 | mgmt_protect/la_data_out_core[44] = 1
mgmt_protect/la_oenb_mprj[33] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[34] |Net: \la_data_out_user[43]
mgmt_core_wrapper/la_oenb[34] = 1 | mgmt_protect/la_data_out_core[43] = 1
mgmt_protect/la_oenb_mprj[34] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[35] |Net: \la_data_out_user[42]
mgmt_core_wrapper/la_oenb[35] = 1 | mgmt_protect/la_data_out_core[42] = 1
mgmt_protect/la_oenb_mprj[35] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[36] |Net: \la_data_out_user[41]
mgmt_core_wrapper/la_oenb[36] = 1 | mgmt_protect/la_data_out_core[41] = 1
mgmt_protect/la_oenb_mprj[36] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[37] |Net: \la_data_out_user[40]
mgmt_core_wrapper/la_oenb[37] = 1 | mgmt_protect/la_data_out_core[40] = 1
mgmt_protect/la_oenb_mprj[37] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[38] |Net: \la_data_out_user[39]
mgmt_core_wrapper/la_oenb[38] = 1 | mgmt_protect/la_data_out_core[39] = 1
mgmt_protect/la_oenb_mprj[38] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[39] |Net: \la_data_out_user[38]
mgmt_core_wrapper/la_oenb[39] = 1 | mgmt_protect/la_data_out_core[38] = 1
mgmt_protect/la_oenb_mprj[39] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[3] |Net: \la_data_out_user[37]
mgmt_core_wrapper/la_oenb[3] = 1 | mgmt_protect/la_data_out_core[37] = 1
mgmt_protect/la_oenb_mprj[3] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[40] |Net: \la_data_out_user[36]
mgmt_core_wrapper/la_oenb[40] = 1 | mgmt_protect/la_data_out_core[36] = 1
mgmt_protect/la_oenb_mprj[40] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[41] |Net: \la_data_out_user[35]
mgmt_core_wrapper/la_oenb[41] = 1 | mgmt_protect/la_data_out_core[35] = 1
mgmt_protect/la_oenb_mprj[41] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[42] |Net: \la_data_out_user[34]
mgmt_core_wrapper/la_oenb[42] = 1 | mgmt_protect/la_data_out_core[34] = 1
mgmt_protect/la_oenb_mprj[42] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[43] |Net: \la_data_out_user[33]
mgmt_core_wrapper/la_oenb[43] = 1 | mgmt_protect/la_data_out_core[33] = 1
mgmt_protect/la_oenb_mprj[43] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[44] |Net: \la_data_out_user[32]
mgmt_core_wrapper/la_oenb[44] = 1 | mgmt_protect/la_data_out_core[32] = 1
mgmt_protect/la_oenb_mprj[44] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[45] |Net: \la_data_out_user[31]
mgmt_core_wrapper/la_oenb[45] = 1 | mgmt_protect/la_data_out_core[31] = 1
mgmt_protect/la_oenb_mprj[45] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[46] |Net: \la_data_out_user[30]
mgmt_core_wrapper/la_oenb[46] = 1 | mgmt_protect/la_data_out_core[30] = 1
mgmt_protect/la_oenb_mprj[46] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[47] |Net: \la_data_out_user[29]
mgmt_core_wrapper/la_oenb[47] = 1 | mgmt_protect/la_data_out_core[29] = 1
mgmt_protect/la_oenb_mprj[47] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[48] |Net: \la_data_out_user[28]
mgmt_core_wrapper/la_oenb[48] = 1 | mgmt_protect/la_data_out_core[28] = 1
mgmt_protect/la_oenb_mprj[48] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[49] |Net: \la_data_out_user[27]
mgmt_core_wrapper/la_oenb[49] = 1 | mgmt_protect/la_data_out_core[27] = 1
mgmt_protect/la_oenb_mprj[49] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[4] |Net: \la_data_out_user[26]
mgmt_core_wrapper/la_oenb[4] = 1 | mgmt_protect/la_data_out_core[26] = 1
mgmt_protect/la_oenb_mprj[4] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[50] |Net: \la_data_out_user[25]
mgmt_core_wrapper/la_oenb[50] = 1 | mgmt_protect/la_data_out_core[25] = 1
mgmt_protect/la_oenb_mprj[50] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[51] |Net: \la_data_out_user[24]
mgmt_core_wrapper/la_oenb[51] = 1 | mgmt_protect/la_data_out_core[24] = 1
mgmt_protect/la_oenb_mprj[51] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[52] |Net: \la_data_out_user[23]
mgmt_core_wrapper/la_oenb[52] = 1 | mgmt_protect/la_data_out_core[23] = 1
mgmt_protect/la_oenb_mprj[52] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[53] |Net: \la_data_out_user[22]
mgmt_core_wrapper/la_oenb[53] = 1 | mgmt_protect/la_data_out_core[22] = 1
mgmt_protect/la_oenb_mprj[53] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[54] |Net: \la_data_out_user[21]
mgmt_core_wrapper/la_oenb[54] = 1 | mgmt_protect/la_data_out_core[21] = 1
mgmt_protect/la_oenb_mprj[54] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[55] |Net: \la_data_out_user[20]
mgmt_core_wrapper/la_oenb[55] = 1 | mgmt_protect/la_data_out_core[20] = 1
mgmt_protect/la_oenb_mprj[55] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[56] |Net: \la_data_out_user[19]
mgmt_core_wrapper/la_oenb[56] = 1 | mgmt_protect/la_data_out_core[19] = 1
mgmt_protect/la_oenb_mprj[56] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[57] |Net: \la_data_out_user[18]
mgmt_core_wrapper/la_oenb[57] = 1 | mgmt_protect/la_data_out_core[18] = 1
mgmt_protect/la_oenb_mprj[57] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[58] |Net: \la_data_out_user[17]
mgmt_core_wrapper/la_oenb[58] = 1 | mgmt_protect/la_data_out_core[17] = 1
mgmt_protect/la_oenb_mprj[58] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[59] |Net: \la_data_out_user[16]
mgmt_core_wrapper/la_oenb[59] = 1 | mgmt_protect/la_data_out_core[16] = 1
mgmt_protect/la_oenb_mprj[59] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[5] |Net: \la_data_out_user[15]
mgmt_core_wrapper/la_oenb[5] = 1 | mgmt_protect/la_data_out_core[15] = 1
mgmt_protect/la_oenb_mprj[5] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[60] |Net: \la_data_out_user[14]
mgmt_core_wrapper/la_oenb[60] = 1 | mgmt_protect/la_data_out_core[14] = 1
mgmt_protect/la_oenb_mprj[60] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[61] |Net: \la_data_out_user[13]
mgmt_core_wrapper/la_oenb[61] = 1 | mgmt_protect/la_data_out_core[13] = 1
mgmt_protect/la_oenb_mprj[61] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[62] |Net: \la_data_out_user[12]
mgmt_core_wrapper/la_oenb[62] = 1 | mgmt_protect/la_data_out_core[12] = 1
mgmt_protect/la_oenb_mprj[62] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[63] |Net: \la_data_out_user[11]
mgmt_core_wrapper/la_oenb[63] = 1 | mgmt_protect/la_data_out_core[11] = 1
mgmt_protect/la_oenb_mprj[63] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[64] |Net: \la_data_out_user[10]
mgmt_core_wrapper/la_oenb[64] = 1 | mgmt_protect/la_data_out_core[10] = 1
mgmt_protect/la_oenb_mprj[64] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[65] |Net: \la_data_out_user[9]
mgmt_core_wrapper/la_oenb[65] = 1 | mgmt_protect/la_data_out_core[9] = 1
mgmt_protect/la_oenb_mprj[65] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[66] |Net: \la_data_out_user[8]
mgmt_core_wrapper/la_oenb[66] = 1 | mgmt_protect/la_data_out_core[8] = 1
mgmt_protect/la_oenb_mprj[66] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[67] |Net: \la_data_out_user[7]
mgmt_core_wrapper/la_oenb[67] = 1 | mgmt_protect/la_data_out_core[7] = 1
mgmt_protect/la_oenb_mprj[67] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[68] |Net: \la_data_out_user[6]
mgmt_core_wrapper/la_oenb[68] = 1 | mgmt_protect/la_data_out_core[6] = 1
mgmt_protect/la_oenb_mprj[68] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[69] |Net: \la_data_out_user[5]
mgmt_core_wrapper/la_oenb[69] = 1 | mgmt_protect/la_data_out_core[5] = 1
mgmt_protect/la_oenb_mprj[69] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[6] |Net: \la_data_out_user[4]
mgmt_core_wrapper/la_oenb[6] = 1 | mgmt_protect/la_data_out_core[4] = 1
mgmt_protect/la_oenb_mprj[6] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[70] |Net: \la_data_out_user[3]
mgmt_core_wrapper/la_oenb[70] = 1 | mgmt_protect/la_data_out_core[3] = 1
mgmt_protect/la_oenb_mprj[70] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[71] |Net: \la_data_out_user[2]
mgmt_core_wrapper/la_oenb[71] = 1 | mgmt_protect/la_data_out_core[2] = 1
mgmt_protect/la_oenb_mprj[71] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[72] |Net: \la_data_out_user[1]
mgmt_core_wrapper/la_oenb[72] = 1 | mgmt_protect/la_data_out_core[1] = 1
mgmt_protect/la_oenb_mprj[72] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[73] |Net: \la_data_out_user[0]
mgmt_core_wrapper/la_oenb[73] = 1 | mgmt_protect/la_data_out_core[0] = 1
mgmt_protect/la_oenb_mprj[73] = 1 | user_analog_project_wrapper/la_data_out[
|
Net: soc/la_oenb[74] |Net: \la_data_out_mprj[127]
mgmt_core_wrapper/la_oenb[74] = 1 | mgmt_protect/la_data_out_mprj[127] = 1
mgmt_protect/la_oenb_mprj[74] = 1 | mgmt_core_wrapper/la_output[127] = 1
|
Net: soc/la_oenb[75] |Net: \la_data_out_mprj[126]
mgmt_core_wrapper/la_oenb[75] = 1 | mgmt_protect/la_data_out_mprj[126] = 1
mgmt_protect/la_oenb_mprj[75] = 1 | mgmt_core_wrapper/la_output[126] = 1
|
Net: soc/la_oenb[76] |Net: \la_data_out_mprj[125]
mgmt_core_wrapper/la_oenb[76] = 1 | mgmt_protect/la_data_out_mprj[125] = 1
mgmt_protect/la_oenb_mprj[76] = 1 | mgmt_core_wrapper/la_output[125] = 1
|
Net: soc/la_oenb[77] |Net: \la_data_out_mprj[124]
mgmt_core_wrapper/la_oenb[77] = 1 | mgmt_protect/la_data_out_mprj[124] = 1
mgmt_protect/la_oenb_mprj[77] = 1 | mgmt_core_wrapper/la_output[124] = 1
|
Net: soc/la_oenb[78] |Net: \la_data_out_mprj[123]
mgmt_core_wrapper/la_oenb[78] = 1 | mgmt_protect/la_data_out_mprj[123] = 1
mgmt_protect/la_oenb_mprj[78] = 1 | mgmt_core_wrapper/la_output[123] = 1
|
Net: soc/la_oenb[79] |Net: \la_data_out_mprj[122]
mgmt_core_wrapper/la_oenb[79] = 1 | mgmt_protect/la_data_out_mprj[122] = 1
mgmt_protect/la_oenb_mprj[79] = 1 | mgmt_core_wrapper/la_output[122] = 1
|
Net: soc/la_oenb[7] |Net: \la_data_out_mprj[121]
mgmt_core_wrapper/la_oenb[7] = 1 | mgmt_protect/la_data_out_mprj[121] = 1
mgmt_protect/la_oenb_mprj[7] = 1 | mgmt_core_wrapper/la_output[121] = 1
|
Net: soc/la_oenb[80] |Net: \la_data_out_mprj[120]
mgmt_core_wrapper/la_oenb[80] = 1 | mgmt_protect/la_data_out_mprj[120] = 1
mgmt_protect/la_oenb_mprj[80] = 1 | mgmt_core_wrapper/la_output[120] = 1
|
Net: soc/la_oenb[81] |Net: \la_data_out_mprj[119]
mgmt_core_wrapper/la_oenb[81] = 1 | mgmt_protect/la_data_out_mprj[119] = 1
mgmt_protect/la_oenb_mprj[81] = 1 | mgmt_core_wrapper/la_output[119] = 1
|
Net: soc/la_oenb[82] |Net: \la_data_out_mprj[118]
mgmt_core_wrapper/la_oenb[82] = 1 | mgmt_protect/la_data_out_mprj[118] = 1
mgmt_protect/la_oenb_mprj[82] = 1 | mgmt_core_wrapper/la_output[118] = 1
|
Net: soc/la_oenb[83] |Net: \la_data_out_mprj[117]
mgmt_core_wrapper/la_oenb[83] = 1 | mgmt_protect/la_data_out_mprj[117] = 1
mgmt_protect/la_oenb_mprj[83] = 1 | mgmt_core_wrapper/la_output[117] = 1
|
Net: soc/la_oenb[84] |Net: \la_data_out_mprj[116]
mgmt_core_wrapper/la_oenb[84] = 1 | mgmt_protect/la_data_out_mprj[116] = 1
mgmt_protect/la_oenb_mprj[84] = 1 | mgmt_core_wrapper/la_output[116] = 1
|
Net: soc/la_oenb[85] |Net: \la_data_out_mprj[115]
mgmt_core_wrapper/la_oenb[85] = 1 | mgmt_protect/la_data_out_mprj[115] = 1
mgmt_protect/la_oenb_mprj[85] = 1 | mgmt_core_wrapper/la_output[115] = 1
|
Net: soc/la_oenb[86] |Net: \la_data_out_mprj[114]
mgmt_core_wrapper/la_oenb[86] = 1 | mgmt_protect/la_data_out_mprj[114] = 1
mgmt_protect/la_oenb_mprj[86] = 1 | mgmt_core_wrapper/la_output[114] = 1
|
Net: soc/la_oenb[87] |Net: \la_data_out_mprj[113]
mgmt_core_wrapper/la_oenb[87] = 1 | mgmt_protect/la_data_out_mprj[113] = 1
mgmt_protect/la_oenb_mprj[87] = 1 | mgmt_core_wrapper/la_output[113] = 1
|
Net: soc/la_oenb[88] |Net: \la_data_out_mprj[112]
mgmt_core_wrapper/la_oenb[88] = 1 | mgmt_protect/la_data_out_mprj[112] = 1
mgmt_protect/la_oenb_mprj[88] = 1 | mgmt_core_wrapper/la_output[112] = 1
|
Net: soc/la_oenb[89] |Net: \la_data_out_mprj[111]
mgmt_core_wrapper/la_oenb[89] = 1 | mgmt_protect/la_data_out_mprj[111] = 1
mgmt_protect/la_oenb_mprj[89] = 1 | mgmt_core_wrapper/la_output[111] = 1
|
Net: soc/la_oenb[8] |Net: \la_data_out_mprj[110]
mgmt_core_wrapper/la_oenb[8] = 1 | mgmt_protect/la_data_out_mprj[110] = 1
mgmt_protect/la_oenb_mprj[8] = 1 | mgmt_core_wrapper/la_output[110] = 1
|
Net: soc/la_oenb[90] |Net: \la_data_out_mprj[109]
mgmt_core_wrapper/la_oenb[90] = 1 | mgmt_protect/la_data_out_mprj[109] = 1
mgmt_protect/la_oenb_mprj[90] = 1 | mgmt_core_wrapper/la_output[109] = 1
|
Net: soc/la_oenb[91] |Net: \la_data_out_mprj[108]
mgmt_core_wrapper/la_oenb[91] = 1 | mgmt_protect/la_data_out_mprj[108] = 1
mgmt_protect/la_oenb_mprj[91] = 1 | mgmt_core_wrapper/la_output[108] = 1
|
Net: soc/la_oenb[92] |Net: \la_data_out_mprj[107]
mgmt_core_wrapper/la_oenb[92] = 1 | mgmt_protect/la_data_out_mprj[107] = 1
mgmt_protect/la_oenb_mprj[92] = 1 | mgmt_core_wrapper/la_output[107] = 1
|
Net: soc/la_oenb[93] |Net: \la_data_out_mprj[106]
mgmt_core_wrapper/la_oenb[93] = 1 | mgmt_protect/la_data_out_mprj[106] = 1
mgmt_protect/la_oenb_mprj[93] = 1 | mgmt_core_wrapper/la_output[106] = 1
|
Net: soc/la_oenb[94] |Net: \la_data_out_mprj[105]
mgmt_core_wrapper/la_oenb[94] = 1 | mgmt_protect/la_data_out_mprj[105] = 1
mgmt_protect/la_oenb_mprj[94] = 1 | mgmt_core_wrapper/la_output[105] = 1
|
Net: soc/la_oenb[95] |Net: \la_data_out_mprj[104]
mgmt_core_wrapper/la_oenb[95] = 1 | mgmt_protect/la_data_out_mprj[104] = 1
mgmt_protect/la_oenb_mprj[95] = 1 | mgmt_core_wrapper/la_output[104] = 1
|
Net: soc/la_oenb[96] |Net: \la_data_out_mprj[103]
mgmt_core_wrapper/la_oenb[96] = 1 | mgmt_protect/la_data_out_mprj[103] = 1
mgmt_protect/la_oenb_mprj[96] = 1 | mgmt_core_wrapper/la_output[103] = 1
|
Net: soc/la_oenb[97] |Net: \la_data_out_mprj[102]
mgmt_core_wrapper/la_oenb[97] = 1 | mgmt_protect/la_data_out_mprj[102] = 1
mgmt_protect/la_oenb_mprj[97] = 1 | mgmt_core_wrapper/la_output[102] = 1
|
Net: soc/la_oenb[98] |Net: \la_data_out_mprj[101]
mgmt_core_wrapper/la_oenb[98] = 1 | mgmt_protect/la_data_out_mprj[101] = 1
mgmt_protect/la_oenb_mprj[98] = 1 | mgmt_core_wrapper/la_output[101] = 1
|
Net: soc/la_oenb[99] |Net: \la_data_out_mprj[100]
mgmt_core_wrapper/la_oenb[99] = 1 | mgmt_protect/la_data_out_mprj[100] = 1
mgmt_protect/la_oenb_mprj[99] = 1 | mgmt_core_wrapper/la_output[100] = 1
|
Net: soc/la_oenb[9] |Net: \la_data_out_mprj[99]
mgmt_core_wrapper/la_oenb[9] = 1 | mgmt_protect/la_data_out_mprj[99] = 1
mgmt_protect/la_oenb_mprj[9] = 1 | mgmt_core_wrapper/la_output[99] = 1
|
Net: soc/la_output[0] |Net: \la_data_out_mprj[98]
mgmt_core_wrapper/la_output[0] = 1 | mgmt_protect/la_data_out_mprj[98] = 1
mgmt_protect/la_data_out_mprj[0] = 1 | mgmt_core_wrapper/la_output[98] = 1
|
Net: soc/la_output[100] |Net: \la_data_out_mprj[97]
mgmt_core_wrapper/la_output[100] = 1 | mgmt_protect/la_data_out_mprj[97] = 1
mgmt_protect/la_data_out_mprj[100] = 1 | mgmt_core_wrapper/la_output[97] = 1
|
Net: soc/la_output[101] |Net: \la_data_out_mprj[96]
mgmt_core_wrapper/la_output[101] = 1 | mgmt_protect/la_data_out_mprj[96] = 1
mgmt_protect/la_data_out_mprj[101] = 1 | mgmt_core_wrapper/la_output[96] = 1
|
Net: soc/la_output[102] |Net: \la_data_out_mprj[95]
mgmt_core_wrapper/la_output[102] = 1 | mgmt_protect/la_data_out_mprj[95] = 1
mgmt_protect/la_data_out_mprj[102] = 1 | mgmt_core_wrapper/la_output[95] = 1
|
Net: soc/la_output[103] |Net: \la_data_out_mprj[94]
mgmt_core_wrapper/la_output[103] = 1 | mgmt_protect/la_data_out_mprj[94] = 1
mgmt_protect/la_data_out_mprj[103] = 1 | mgmt_core_wrapper/la_output[94] = 1
|
Net: soc/la_output[104] |Net: \la_data_out_mprj[93]
mgmt_core_wrapper/la_output[104] = 1 | mgmt_protect/la_data_out_mprj[93] = 1
mgmt_protect/la_data_out_mprj[104] = 1 | mgmt_core_wrapper/la_output[93] = 1
|
Net: soc/la_output[105] |Net: \la_data_out_mprj[92]
mgmt_core_wrapper/la_output[105] = 1 | mgmt_protect/la_data_out_mprj[92] = 1
mgmt_protect/la_data_out_mprj[105] = 1 | mgmt_core_wrapper/la_output[92] = 1
|
Net: soc/la_output[106] |Net: \la_data_out_mprj[91]
mgmt_core_wrapper/la_output[106] = 1 | mgmt_protect/la_data_out_mprj[91] = 1
mgmt_protect/la_data_out_mprj[106] = 1 | mgmt_core_wrapper/la_output[91] = 1
|
Net: soc/la_output[107] |Net: \la_data_out_mprj[90]
mgmt_core_wrapper/la_output[107] = 1 | mgmt_protect/la_data_out_mprj[90] = 1
mgmt_protect/la_data_out_mprj[107] = 1 | mgmt_core_wrapper/la_output[90] = 1
|
Net: soc/la_output[108] |Net: \la_data_out_mprj[89]
mgmt_core_wrapper/la_output[108] = 1 | mgmt_protect/la_data_out_mprj[89] = 1
mgmt_protect/la_data_out_mprj[108] = 1 | mgmt_core_wrapper/la_output[89] = 1
|
Net: soc/la_output[109] |Net: \la_data_out_mprj[88]
mgmt_core_wrapper/la_output[109] = 1 | mgmt_protect/la_data_out_mprj[88] = 1
mgmt_protect/la_data_out_mprj[109] = 1 | mgmt_core_wrapper/la_output[88] = 1
|
Net: soc/la_output[10] |Net: \la_data_out_mprj[87]
mgmt_core_wrapper/la_output[10] = 1 | mgmt_protect/la_data_out_mprj[87] = 1
mgmt_protect/la_data_out_mprj[10] = 1 | mgmt_core_wrapper/la_output[87] = 1
|
Net: soc/la_output[110] |Net: \la_data_out_mprj[86]
mgmt_core_wrapper/la_output[110] = 1 | mgmt_protect/la_data_out_mprj[86] = 1
mgmt_protect/la_data_out_mprj[110] = 1 | mgmt_core_wrapper/la_output[86] = 1
|
Net: soc/la_output[111] |Net: \la_data_out_mprj[85]
mgmt_core_wrapper/la_output[111] = 1 | mgmt_protect/la_data_out_mprj[85] = 1
mgmt_protect/la_data_out_mprj[111] = 1 | mgmt_core_wrapper/la_output[85] = 1
|
Net: soc/la_output[112] |Net: \la_data_out_mprj[84]
mgmt_core_wrapper/la_output[112] = 1 | mgmt_protect/la_data_out_mprj[84] = 1
mgmt_protect/la_data_out_mprj[112] = 1 | mgmt_core_wrapper/la_output[84] = 1
|
Net: soc/la_output[113] |Net: \la_data_out_mprj[83]
mgmt_core_wrapper/la_output[113] = 1 | mgmt_protect/la_data_out_mprj[83] = 1
mgmt_protect/la_data_out_mprj[113] = 1 | mgmt_core_wrapper/la_output[83] = 1
|
Net: soc/la_output[114] |Net: \la_data_out_mprj[82]
mgmt_core_wrapper/la_output[114] = 1 | mgmt_protect/la_data_out_mprj[82] = 1
mgmt_protect/la_data_out_mprj[114] = 1 | mgmt_core_wrapper/la_output[82] = 1
|
Net: soc/la_output[115] |Net: \la_data_out_mprj[81]
mgmt_core_wrapper/la_output[115] = 1 | mgmt_protect/la_data_out_mprj[81] = 1
mgmt_protect/la_data_out_mprj[115] = 1 | mgmt_core_wrapper/la_output[81] = 1
|
Net: soc/la_output[116] |Net: \la_data_out_mprj[80]
mgmt_core_wrapper/la_output[116] = 1 | mgmt_protect/la_data_out_mprj[80] = 1
mgmt_protect/la_data_out_mprj[116] = 1 | mgmt_core_wrapper/la_output[80] = 1
|
Net: soc/la_output[117] |Net: \la_data_out_mprj[79]
mgmt_core_wrapper/la_output[117] = 1 | mgmt_protect/la_data_out_mprj[79] = 1
mgmt_protect/la_data_out_mprj[117] = 1 | mgmt_core_wrapper/la_output[79] = 1
|
Net: soc/la_output[118] |Net: \la_data_out_mprj[78]
mgmt_core_wrapper/la_output[118] = 1 | mgmt_protect/la_data_out_mprj[78] = 1
mgmt_protect/la_data_out_mprj[118] = 1 | mgmt_core_wrapper/la_output[78] = 1
|
Net: soc/la_output[119] |Net: \la_data_out_mprj[77]
mgmt_core_wrapper/la_output[119] = 1 | mgmt_protect/la_data_out_mprj[77] = 1
mgmt_protect/la_data_out_mprj[119] = 1 | mgmt_core_wrapper/la_output[77] = 1
|
Net: soc/la_output[11] |Net: \la_data_out_mprj[76]
mgmt_core_wrapper/la_output[11] = 1 | mgmt_protect/la_data_out_mprj[76] = 1
mgmt_protect/la_data_out_mprj[11] = 1 | mgmt_core_wrapper/la_output[76] = 1
|
Net: soc/la_output[120] |Net: \la_data_out_mprj[75]
mgmt_core_wrapper/la_output[120] = 1 | mgmt_protect/la_data_out_mprj[75] = 1
mgmt_protect/la_data_out_mprj[120] = 1 | mgmt_core_wrapper/la_output[75] = 1
|
Net: soc/la_output[121] |Net: \la_data_out_mprj[74]
mgmt_core_wrapper/la_output[121] = 1 | mgmt_protect/la_data_out_mprj[74] = 1
mgmt_protect/la_data_out_mprj[121] = 1 | mgmt_core_wrapper/la_output[74] = 1
|
Net: soc/la_output[122] |Net: \la_data_out_mprj[73]
mgmt_core_wrapper/la_output[122] = 1 | mgmt_protect/la_data_out_mprj[73] = 1
mgmt_protect/la_data_out_mprj[122] = 1 | mgmt_core_wrapper/la_output[73] = 1
|
Net: soc/la_output[123] |Net: \la_data_out_mprj[72]
mgmt_core_wrapper/la_output[123] = 1 | mgmt_protect/la_data_out_mprj[72] = 1
mgmt_protect/la_data_out_mprj[123] = 1 | mgmt_core_wrapper/la_output[72] = 1
|
Net: soc/la_output[124] |Net: \la_data_out_mprj[71]
mgmt_core_wrapper/la_output[124] = 1 | mgmt_protect/la_data_out_mprj[71] = 1
mgmt_protect/la_data_out_mprj[124] = 1 | mgmt_core_wrapper/la_output[71] = 1
|
Net: soc/la_output[125] |Net: \la_data_out_mprj[70]
mgmt_core_wrapper/la_output[125] = 1 | mgmt_protect/la_data_out_mprj[70] = 1
mgmt_protect/la_data_out_mprj[125] = 1 | mgmt_core_wrapper/la_output[70] = 1
|
Net: soc/la_output[126] |Net: \la_data_out_mprj[69]
mgmt_core_wrapper/la_output[126] = 1 | mgmt_protect/la_data_out_mprj[69] = 1
mgmt_protect/la_data_out_mprj[126] = 1 | mgmt_core_wrapper/la_output[69] = 1
|
Net: soc/la_output[127] |Net: \la_data_out_mprj[68]
mgmt_core_wrapper/la_output[127] = 1 | mgmt_protect/la_data_out_mprj[68] = 1
mgmt_protect/la_data_out_mprj[127] = 1 | mgmt_core_wrapper/la_output[68] = 1
|
Net: soc/la_output[12] |Net: \la_data_out_mprj[67]
mgmt_core_wrapper/la_output[12] = 1 | mgmt_protect/la_data_out_mprj[67] = 1
mgmt_protect/la_data_out_mprj[12] = 1 | mgmt_core_wrapper/la_output[67] = 1
|
Net: soc/la_output[13] |Net: \la_data_out_mprj[66]
mgmt_core_wrapper/la_output[13] = 1 | mgmt_protect/la_data_out_mprj[66] = 1
mgmt_protect/la_data_out_mprj[13] = 1 | mgmt_core_wrapper/la_output[66] = 1
|
Net: soc/la_output[14] |Net: \la_data_out_mprj[65]
mgmt_core_wrapper/la_output[14] = 1 | mgmt_protect/la_data_out_mprj[65] = 1
mgmt_protect/la_data_out_mprj[14] = 1 | mgmt_core_wrapper/la_output[65] = 1
|
Net: soc/la_output[15] |Net: \la_data_out_mprj[64]
mgmt_core_wrapper/la_output[15] = 1 | mgmt_protect/la_data_out_mprj[64] = 1
mgmt_protect/la_data_out_mprj[15] = 1 | mgmt_core_wrapper/la_output[64] = 1
|
Net: soc/la_output[16] |Net: \la_data_out_mprj[63]
mgmt_core_wrapper/la_output[16] = 1 | mgmt_protect/la_data_out_mprj[63] = 1
mgmt_protect/la_data_out_mprj[16] = 1 | mgmt_core_wrapper/la_output[63] = 1
|
Net: soc/la_output[17] |Net: \la_data_out_mprj[62]
mgmt_core_wrapper/la_output[17] = 1 | mgmt_protect/la_data_out_mprj[62] = 1
mgmt_protect/la_data_out_mprj[17] = 1 | mgmt_core_wrapper/la_output[62] = 1
|
Net: soc/la_output[18] |Net: \la_data_out_mprj[61]
mgmt_core_wrapper/la_output[18] = 1 | mgmt_protect/la_data_out_mprj[61] = 1
mgmt_protect/la_data_out_mprj[18] = 1 | mgmt_core_wrapper/la_output[61] = 1
|
Net: soc/la_output[19] |Net: \la_data_out_mprj[60]
mgmt_core_wrapper/la_output[19] = 1 | mgmt_protect/la_data_out_mprj[60] = 1
mgmt_protect/la_data_out_mprj[19] = 1 | mgmt_core_wrapper/la_output[60] = 1
|
Net: soc/la_output[1] |Net: \la_data_out_mprj[59]
mgmt_core_wrapper/la_output[1] = 1 | mgmt_protect/la_data_out_mprj[59] = 1
mgmt_protect/la_data_out_mprj[1] = 1 | mgmt_core_wrapper/la_output[59] = 1
|
Net: soc/la_output[20] |Net: \la_data_out_mprj[58]
mgmt_core_wrapper/la_output[20] = 1 | mgmt_protect/la_data_out_mprj[58] = 1
mgmt_protect/la_data_out_mprj[20] = 1 | mgmt_core_wrapper/la_output[58] = 1
|
Net: soc/la_output[21] |Net: \la_data_out_mprj[57]
mgmt_core_wrapper/la_output[21] = 1 | mgmt_protect/la_data_out_mprj[57] = 1
mgmt_protect/la_data_out_mprj[21] = 1 | mgmt_core_wrapper/la_output[57] = 1
|
Net: soc/la_output[22] |Net: \la_data_out_mprj[56]
mgmt_core_wrapper/la_output[22] = 1 | mgmt_protect/la_data_out_mprj[56] = 1
mgmt_protect/la_data_out_mprj[22] = 1 | mgmt_core_wrapper/la_output[56] = 1
|
Net: soc/la_output[23] |Net: \la_data_out_mprj[55]
mgmt_core_wrapper/la_output[23] = 1 | mgmt_protect/la_data_out_mprj[55] = 1
mgmt_protect/la_data_out_mprj[23] = 1 | mgmt_core_wrapper/la_output[55] = 1
|
Net: soc/la_output[24] |Net: \la_data_out_mprj[54]
mgmt_core_wrapper/la_output[24] = 1 | mgmt_protect/la_data_out_mprj[54] = 1
mgmt_protect/la_data_out_mprj[24] = 1 | mgmt_core_wrapper/la_output[54] = 1
|
Net: soc/la_output[25] |Net: \la_data_out_mprj[53]
mgmt_core_wrapper/la_output[25] = 1 | mgmt_protect/la_data_out_mprj[53] = 1
mgmt_protect/la_data_out_mprj[25] = 1 | mgmt_core_wrapper/la_output[53] = 1
|
Net: soc/la_output[26] |Net: \la_data_out_mprj[52]
mgmt_core_wrapper/la_output[26] = 1 | mgmt_protect/la_data_out_mprj[52] = 1
mgmt_protect/la_data_out_mprj[26] = 1 | mgmt_core_wrapper/la_output[52] = 1
|
Net: soc/la_output[27] |Net: \la_data_out_mprj[51]
mgmt_core_wrapper/la_output[27] = 1 | mgmt_protect/la_data_out_mprj[51] = 1
mgmt_protect/la_data_out_mprj[27] = 1 | mgmt_core_wrapper/la_output[51] = 1
|
Net: soc/la_output[28] |Net: \la_data_out_mprj[50]
mgmt_core_wrapper/la_output[28] = 1 | mgmt_protect/la_data_out_mprj[50] = 1
mgmt_protect/la_data_out_mprj[28] = 1 | mgmt_core_wrapper/la_output[50] = 1
|
Net: soc/la_output[29] |Net: \la_data_out_mprj[49]
mgmt_core_wrapper/la_output[29] = 1 | mgmt_protect/la_data_out_mprj[49] = 1
mgmt_protect/la_data_out_mprj[29] = 1 | mgmt_core_wrapper/la_output[49] = 1
|
Net: soc/la_output[2] |Net: \la_data_out_mprj[48]
mgmt_core_wrapper/la_output[2] = 1 | mgmt_protect/la_data_out_mprj[48] = 1
mgmt_protect/la_data_out_mprj[2] = 1 | mgmt_core_wrapper/la_output[48] = 1
|
Net: soc/la_output[30] |Net: \la_data_out_mprj[47]
mgmt_core_wrapper/la_output[30] = 1 | mgmt_protect/la_data_out_mprj[47] = 1
mgmt_protect/la_data_out_mprj[30] = 1 | mgmt_core_wrapper/la_output[47] = 1
|
Net: soc/la_output[31] |Net: \la_data_out_mprj[46]
mgmt_core_wrapper/la_output[31] = 1 | mgmt_protect/la_data_out_mprj[46] = 1
mgmt_protect/la_data_out_mprj[31] = 1 | mgmt_core_wrapper/la_output[46] = 1
|
Net: soc/la_output[32] |Net: \la_data_out_mprj[45]
mgmt_core_wrapper/la_output[32] = 1 | mgmt_protect/la_data_out_mprj[45] = 1
mgmt_protect/la_data_out_mprj[32] = 1 | mgmt_core_wrapper/la_output[45] = 1
|
Net: soc/la_output[33] |Net: \la_data_out_mprj[44]
mgmt_core_wrapper/la_output[33] = 1 | mgmt_protect/la_data_out_mprj[44] = 1
mgmt_protect/la_data_out_mprj[33] = 1 | mgmt_core_wrapper/la_output[44] = 1
|
Net: soc/la_output[34] |Net: \la_data_out_mprj[43]
mgmt_core_wrapper/la_output[34] = 1 | mgmt_protect/la_data_out_mprj[43] = 1
mgmt_protect/la_data_out_mprj[34] = 1 | mgmt_core_wrapper/la_output[43] = 1
|
Net: soc/la_output[35] |Net: \la_data_out_mprj[42]
mgmt_core_wrapper/la_output[35] = 1 | mgmt_protect/la_data_out_mprj[42] = 1
mgmt_protect/la_data_out_mprj[35] = 1 | mgmt_core_wrapper/la_output[42] = 1
|
Net: soc/la_output[36] |Net: \la_data_out_mprj[41]
mgmt_core_wrapper/la_output[36] = 1 | mgmt_protect/la_data_out_mprj[41] = 1
mgmt_protect/la_data_out_mprj[36] = 1 | mgmt_core_wrapper/la_output[41] = 1
|
Net: soc/la_output[37] |Net: \la_data_out_mprj[40]
mgmt_core_wrapper/la_output[37] = 1 | mgmt_protect/la_data_out_mprj[40] = 1
mgmt_protect/la_data_out_mprj[37] = 1 | mgmt_core_wrapper/la_output[40] = 1
|
Net: soc/la_output[38] |Net: \la_data_out_mprj[39]
mgmt_core_wrapper/la_output[38] = 1 | mgmt_protect/la_data_out_mprj[39] = 1
mgmt_protect/la_data_out_mprj[38] = 1 | mgmt_core_wrapper/la_output[39] = 1
|
Net: soc/la_output[39] |Net: \la_data_out_mprj[38]
mgmt_core_wrapper/la_output[39] = 1 | mgmt_protect/la_data_out_mprj[38] = 1
mgmt_protect/la_data_out_mprj[39] = 1 | mgmt_core_wrapper/la_output[38] = 1
|
Net: soc/la_output[3] |Net: \la_data_out_mprj[37]
mgmt_core_wrapper/la_output[3] = 1 | mgmt_protect/la_data_out_mprj[37] = 1
mgmt_protect/la_data_out_mprj[3] = 1 | mgmt_core_wrapper/la_output[37] = 1
|
Net: soc/la_output[40] |Net: \la_data_out_mprj[36]
mgmt_core_wrapper/la_output[40] = 1 | mgmt_protect/la_data_out_mprj[36] = 1
mgmt_protect/la_data_out_mprj[40] = 1 | mgmt_core_wrapper/la_output[36] = 1
|
Net: soc/la_output[41] |Net: \la_data_out_mprj[35]
mgmt_core_wrapper/la_output[41] = 1 | mgmt_protect/la_data_out_mprj[35] = 1
mgmt_protect/la_data_out_mprj[41] = 1 | mgmt_core_wrapper/la_output[35] = 1
|
Net: soc/la_output[42] |Net: \la_data_out_mprj[34]
mgmt_core_wrapper/la_output[42] = 1 | mgmt_protect/la_data_out_mprj[34] = 1
mgmt_protect/la_data_out_mprj[42] = 1 | mgmt_core_wrapper/la_output[34] = 1
|
Net: soc/la_output[43] |Net: \la_data_out_mprj[33]
mgmt_core_wrapper/la_output[43] = 1 | mgmt_protect/la_data_out_mprj[33] = 1
mgmt_protect/la_data_out_mprj[43] = 1 | mgmt_core_wrapper/la_output[33] = 1
|
Net: soc/la_output[44] |Net: \la_data_out_mprj[32]
mgmt_core_wrapper/la_output[44] = 1 | mgmt_protect/la_data_out_mprj[32] = 1
mgmt_protect/la_data_out_mprj[44] = 1 | mgmt_core_wrapper/la_output[32] = 1
|
Net: soc/la_output[45] |Net: \la_data_out_mprj[31]
mgmt_core_wrapper/la_output[45] = 1 | mgmt_protect/la_data_out_mprj[31] = 1
mgmt_protect/la_data_out_mprj[45] = 1 | mgmt_core_wrapper/la_output[31] = 1
|
Net: soc/la_output[46] |Net: \la_data_out_mprj[30]
mgmt_core_wrapper/la_output[46] = 1 | mgmt_protect/la_data_out_mprj[30] = 1
mgmt_protect/la_data_out_mprj[46] = 1 | mgmt_core_wrapper/la_output[30] = 1
|
Net: soc/la_output[47] |Net: \la_data_out_mprj[29]
mgmt_core_wrapper/la_output[47] = 1 | mgmt_protect/la_data_out_mprj[29] = 1
mgmt_protect/la_data_out_mprj[47] = 1 | mgmt_core_wrapper/la_output[29] = 1
|
Net: soc/la_output[48] |Net: \la_data_out_mprj[28]
mgmt_core_wrapper/la_output[48] = 1 | mgmt_protect/la_data_out_mprj[28] = 1
mgmt_protect/la_data_out_mprj[48] = 1 | mgmt_core_wrapper/la_output[28] = 1
|
Net: soc/la_output[49] |Net: \la_data_out_mprj[27]
mgmt_core_wrapper/la_output[49] = 1 | mgmt_protect/la_data_out_mprj[27] = 1
mgmt_protect/la_data_out_mprj[49] = 1 | mgmt_core_wrapper/la_output[27] = 1
|
Net: soc/la_output[4] |Net: \la_data_out_mprj[26]
mgmt_core_wrapper/la_output[4] = 1 | mgmt_protect/la_data_out_mprj[26] = 1
mgmt_protect/la_data_out_mprj[4] = 1 | mgmt_core_wrapper/la_output[26] = 1
|
Net: soc/la_output[50] |Net: \la_data_out_mprj[25]
mgmt_core_wrapper/la_output[50] = 1 | mgmt_protect/la_data_out_mprj[25] = 1
mgmt_protect/la_data_out_mprj[50] = 1 | mgmt_core_wrapper/la_output[25] = 1
|
Net: soc/la_output[51] |Net: \la_data_out_mprj[24]
mgmt_core_wrapper/la_output[51] = 1 | mgmt_protect/la_data_out_mprj[24] = 1
mgmt_protect/la_data_out_mprj[51] = 1 | mgmt_core_wrapper/la_output[24] = 1
|
Net: soc/la_output[52] |Net: \la_data_out_mprj[23]
mgmt_core_wrapper/la_output[52] = 1 | mgmt_protect/la_data_out_mprj[23] = 1
mgmt_protect/la_data_out_mprj[52] = 1 | mgmt_core_wrapper/la_output[23] = 1
|
Net: soc/la_output[53] |Net: \la_data_out_mprj[22]
mgmt_core_wrapper/la_output[53] = 1 | mgmt_protect/la_data_out_mprj[22] = 1
mgmt_protect/la_data_out_mprj[53] = 1 | mgmt_core_wrapper/la_output[22] = 1
|
Net: soc/la_output[54] |Net: \la_data_out_mprj[21]
mgmt_core_wrapper/la_output[54] = 1 | mgmt_protect/la_data_out_mprj[21] = 1
mgmt_protect/la_data_out_mprj[54] = 1 | mgmt_core_wrapper/la_output[21] = 1
|
Net: soc/la_output[55] |Net: \la_data_out_mprj[20]
mgmt_core_wrapper/la_output[55] = 1 | mgmt_protect/la_data_out_mprj[20] = 1
mgmt_protect/la_data_out_mprj[55] = 1 | mgmt_core_wrapper/la_output[20] = 1
|
Net: soc/la_output[56] |Net: \la_data_out_mprj[19]
mgmt_core_wrapper/la_output[56] = 1 | mgmt_protect/la_data_out_mprj[19] = 1
mgmt_protect/la_data_out_mprj[56] = 1 | mgmt_core_wrapper/la_output[19] = 1
|
Net: soc/la_output[57] |Net: \la_data_out_mprj[18]
mgmt_core_wrapper/la_output[57] = 1 | mgmt_protect/la_data_out_mprj[18] = 1
mgmt_protect/la_data_out_mprj[57] = 1 | mgmt_core_wrapper/la_output[18] = 1
|
Net: soc/la_output[58] |Net: \la_data_out_mprj[17]
mgmt_core_wrapper/la_output[58] = 1 | mgmt_protect/la_data_out_mprj[17] = 1
mgmt_protect/la_data_out_mprj[58] = 1 | mgmt_core_wrapper/la_output[17] = 1
|
Net: soc/la_output[59] |Net: \la_data_out_mprj[16]
mgmt_core_wrapper/la_output[59] = 1 | mgmt_protect/la_data_out_mprj[16] = 1
mgmt_protect/la_data_out_mprj[59] = 1 | mgmt_core_wrapper/la_output[16] = 1
|
Net: soc/la_output[5] |Net: \la_data_out_mprj[15]
mgmt_core_wrapper/la_output[5] = 1 | mgmt_protect/la_data_out_mprj[15] = 1
mgmt_protect/la_data_out_mprj[5] = 1 | mgmt_core_wrapper/la_output[15] = 1
|
Net: soc/la_output[60] |Net: \la_data_out_mprj[14]
mgmt_core_wrapper/la_output[60] = 1 | mgmt_protect/la_data_out_mprj[14] = 1
mgmt_protect/la_data_out_mprj[60] = 1 | mgmt_core_wrapper/la_output[14] = 1
|
Net: soc/la_output[61] |Net: \la_data_out_mprj[13]
mgmt_core_wrapper/la_output[61] = 1 | mgmt_protect/la_data_out_mprj[13] = 1
mgmt_protect/la_data_out_mprj[61] = 1 | mgmt_core_wrapper/la_output[13] = 1
|
Net: soc/la_output[62] |Net: \la_data_out_mprj[12]
mgmt_core_wrapper/la_output[62] = 1 | mgmt_protect/la_data_out_mprj[12] = 1
mgmt_protect/la_data_out_mprj[62] = 1 | mgmt_core_wrapper/la_output[12] = 1
|
Net: soc/la_output[63] |Net: \la_data_out_mprj[11]
mgmt_core_wrapper/la_output[63] = 1 | mgmt_protect/la_data_out_mprj[11] = 1
mgmt_protect/la_data_out_mprj[63] = 1 | mgmt_core_wrapper/la_output[11] = 1
|
Net: soc/la_output[64] |Net: \la_data_out_mprj[10]
mgmt_core_wrapper/la_output[64] = 1 | mgmt_protect/la_data_out_mprj[10] = 1
mgmt_protect/la_data_out_mprj[64] = 1 | mgmt_core_wrapper/la_output[10] = 1
|
Net: soc/la_output[65] |Net: \la_data_out_mprj[9]
mgmt_core_wrapper/la_output[65] = 1 | mgmt_protect/la_data_out_mprj[9] = 1
mgmt_protect/la_data_out_mprj[65] = 1 | mgmt_core_wrapper/la_output[9] = 1
|
Net: soc/la_output[66] |Net: \la_data_out_mprj[8]
mgmt_core_wrapper/la_output[66] = 1 | mgmt_protect/la_data_out_mprj[8] = 1
mgmt_protect/la_data_out_mprj[66] = 1 | mgmt_core_wrapper/la_output[8] = 1
|
Net: soc/la_output[67] |Net: \la_data_out_mprj[7]
mgmt_core_wrapper/la_output[67] = 1 | mgmt_protect/la_data_out_mprj[7] = 1
mgmt_protect/la_data_out_mprj[67] = 1 | mgmt_core_wrapper/la_output[7] = 1
|
Net: soc/la_output[68] |Net: \la_data_out_mprj[6]
mgmt_core_wrapper/la_output[68] = 1 | mgmt_protect/la_data_out_mprj[6] = 1
mgmt_protect/la_data_out_mprj[68] = 1 | mgmt_core_wrapper/la_output[6] = 1
|
Net: soc/la_output[69] |Net: \la_data_out_mprj[5]
mgmt_core_wrapper/la_output[69] = 1 | mgmt_protect/la_data_out_mprj[5] = 1
mgmt_protect/la_data_out_mprj[69] = 1 | mgmt_core_wrapper/la_output[5] = 1
|
Net: soc/la_output[6] |Net: \la_data_out_mprj[4]
mgmt_core_wrapper/la_output[6] = 1 | mgmt_protect/la_data_out_mprj[4] = 1
mgmt_protect/la_data_out_mprj[6] = 1 | mgmt_core_wrapper/la_output[4] = 1
|
Net: soc/la_output[70] |Net: \la_data_out_mprj[3]
mgmt_core_wrapper/la_output[70] = 1 | mgmt_protect/la_data_out_mprj[3] = 1
mgmt_protect/la_data_out_mprj[70] = 1 | mgmt_core_wrapper/la_output[3] = 1
|
Net: soc/la_output[71] |Net: \la_data_out_mprj[2]
mgmt_core_wrapper/la_output[71] = 1 | mgmt_protect/la_data_out_mprj[2] = 1
mgmt_protect/la_data_out_mprj[71] = 1 | mgmt_core_wrapper/la_output[2] = 1
|
Net: soc/la_output[72] |Net: \la_data_out_mprj[1]
mgmt_core_wrapper/la_output[72] = 1 | mgmt_protect/la_data_out_mprj[1] = 1
mgmt_protect/la_data_out_mprj[72] = 1 | mgmt_core_wrapper/la_output[1] = 1
|
Net: soc/la_output[73] |Net: \la_data_out_mprj[0]
mgmt_core_wrapper/la_output[73] = 1 | mgmt_protect/la_data_out_mprj[0] = 1
mgmt_protect/la_data_out_mprj[73] = 1 | mgmt_core_wrapper/la_output[0] = 1
|
Net: soc/la_output[74] |Net: \la_iena_mprj[127]
mgmt_core_wrapper/la_output[74] = 1 | mgmt_protect/la_iena_mprj[127] = 1
mgmt_protect/la_data_out_mprj[74] = 1 | mgmt_core_wrapper/la_iena[127] = 1
|
Net: soc/la_output[75] |Net: \la_iena_mprj[126]
mgmt_core_wrapper/la_output[75] = 1 | mgmt_protect/la_iena_mprj[126] = 1
mgmt_protect/la_data_out_mprj[75] = 1 | mgmt_core_wrapper/la_iena[126] = 1
|
Net: soc/la_output[76] |Net: \la_iena_mprj[125]
mgmt_core_wrapper/la_output[76] = 1 | mgmt_protect/la_iena_mprj[125] = 1
mgmt_protect/la_data_out_mprj[76] = 1 | mgmt_core_wrapper/la_iena[125] = 1
|
Net: soc/la_output[77] |Net: \la_iena_mprj[124]
mgmt_core_wrapper/la_output[77] = 1 | mgmt_protect/la_iena_mprj[124] = 1
mgmt_protect/la_data_out_mprj[77] = 1 | mgmt_core_wrapper/la_iena[124] = 1
|
Net: soc/la_output[78] |Net: \la_iena_mprj[123]
mgmt_core_wrapper/la_output[78] = 1 | mgmt_protect/la_iena_mprj[123] = 1
mgmt_protect/la_data_out_mprj[78] = 1 | mgmt_core_wrapper/la_iena[123] = 1
|
Net: soc/la_output[79] |Net: \la_iena_mprj[122]
mgmt_core_wrapper/la_output[79] = 1 | mgmt_protect/la_iena_mprj[122] = 1
mgmt_protect/la_data_out_mprj[79] = 1 | mgmt_core_wrapper/la_iena[122] = 1
|
Net: soc/la_output[7] |Net: \la_iena_mprj[121]
mgmt_core_wrapper/la_output[7] = 1 | mgmt_protect/la_iena_mprj[121] = 1
mgmt_protect/la_data_out_mprj[7] = 1 | mgmt_core_wrapper/la_iena[121] = 1
|
Net: soc/la_output[80] |Net: \la_iena_mprj[120]
mgmt_core_wrapper/la_output[80] = 1 | mgmt_protect/la_iena_mprj[120] = 1
mgmt_protect/la_data_out_mprj[80] = 1 | mgmt_core_wrapper/la_iena[120] = 1
|
Net: soc/la_output[81] |Net: \la_iena_mprj[119]
mgmt_core_wrapper/la_output[81] = 1 | mgmt_protect/la_iena_mprj[119] = 1
mgmt_protect/la_data_out_mprj[81] = 1 | mgmt_core_wrapper/la_iena[119] = 1
|
Net: soc/la_output[82] |Net: \la_iena_mprj[118]
mgmt_core_wrapper/la_output[82] = 1 | mgmt_protect/la_iena_mprj[118] = 1
mgmt_protect/la_data_out_mprj[82] = 1 | mgmt_core_wrapper/la_iena[118] = 1
|
Net: soc/la_output[83] |Net: \la_iena_mprj[117]
mgmt_core_wrapper/la_output[83] = 1 | mgmt_protect/la_iena_mprj[117] = 1
mgmt_protect/la_data_out_mprj[83] = 1 | mgmt_core_wrapper/la_iena[117] = 1
|
Net: soc/la_output[84] |Net: \la_iena_mprj[116]
mgmt_core_wrapper/la_output[84] = 1 | mgmt_protect/la_iena_mprj[116] = 1
mgmt_protect/la_data_out_mprj[84] = 1 | mgmt_core_wrapper/la_iena[116] = 1
|
Net: soc/la_output[85] |Net: \la_iena_mprj[115]
mgmt_core_wrapper/la_output[85] = 1 | mgmt_protect/la_iena_mprj[115] = 1
mgmt_protect/la_data_out_mprj[85] = 1 | mgmt_core_wrapper/la_iena[115] = 1
|
Net: soc/la_output[86] |Net: \la_iena_mprj[114]
mgmt_core_wrapper/la_output[86] = 1 | mgmt_protect/la_iena_mprj[114] = 1
mgmt_protect/la_data_out_mprj[86] = 1 | mgmt_core_wrapper/la_iena[114] = 1
|
Net: soc/la_output[87] |Net: \la_iena_mprj[113]
mgmt_core_wrapper/la_output[87] = 1 | mgmt_protect/la_iena_mprj[113] = 1
mgmt_protect/la_data_out_mprj[87] = 1 | mgmt_core_wrapper/la_iena[113] = 1
|
Net: soc/la_output[88] |Net: \la_iena_mprj[112]
mgmt_core_wrapper/la_output[88] = 1 | mgmt_protect/la_iena_mprj[112] = 1
mgmt_protect/la_data_out_mprj[88] = 1 | mgmt_core_wrapper/la_iena[112] = 1
|
Net: soc/la_output[89] |Net: \la_iena_mprj[111]
mgmt_core_wrapper/la_output[89] = 1 | mgmt_protect/la_iena_mprj[111] = 1
mgmt_protect/la_data_out_mprj[89] = 1 | mgmt_core_wrapper/la_iena[111] = 1
|
Net: soc/la_output[8] |Net: \la_iena_mprj[110]
mgmt_core_wrapper/la_output[8] = 1 | mgmt_protect/la_iena_mprj[110] = 1
mgmt_protect/la_data_out_mprj[8] = 1 | mgmt_core_wrapper/la_iena[110] = 1
|
Net: soc/la_output[90] |Net: \la_iena_mprj[109]
mgmt_core_wrapper/la_output[90] = 1 | mgmt_protect/la_iena_mprj[109] = 1
mgmt_protect/la_data_out_mprj[90] = 1 | mgmt_core_wrapper/la_iena[109] = 1
|
Net: soc/la_output[91] |Net: \la_iena_mprj[108]
mgmt_core_wrapper/la_output[91] = 1 | mgmt_protect/la_iena_mprj[108] = 1
mgmt_protect/la_data_out_mprj[91] = 1 | mgmt_core_wrapper/la_iena[108] = 1
|
Net: soc/la_output[92] |Net: \la_iena_mprj[107]
mgmt_core_wrapper/la_output[92] = 1 | mgmt_protect/la_iena_mprj[107] = 1
mgmt_protect/la_data_out_mprj[92] = 1 | mgmt_core_wrapper/la_iena[107] = 1
|
Net: soc/la_output[93] |Net: \la_iena_mprj[106]
mgmt_core_wrapper/la_output[93] = 1 | mgmt_protect/la_iena_mprj[106] = 1
mgmt_protect/la_data_out_mprj[93] = 1 | mgmt_core_wrapper/la_iena[106] = 1
|
Net: soc/la_output[94] |Net: \la_iena_mprj[105]
mgmt_core_wrapper/la_output[94] = 1 | mgmt_protect/la_iena_mprj[105] = 1
mgmt_protect/la_data_out_mprj[94] = 1 | mgmt_core_wrapper/la_iena[105] = 1
|
Net: soc/la_output[95] |Net: \la_iena_mprj[104]
mgmt_core_wrapper/la_output[95] = 1 | mgmt_protect/la_iena_mprj[104] = 1
mgmt_protect/la_data_out_mprj[95] = 1 | mgmt_core_wrapper/la_iena[104] = 1
|
Net: soc/la_output[96] |Net: \la_iena_mprj[103]
mgmt_core_wrapper/la_output[96] = 1 | mgmt_protect/la_iena_mprj[103] = 1
mgmt_protect/la_data_out_mprj[96] = 1 | mgmt_core_wrapper/la_iena[103] = 1
|
Net: soc/la_output[97] |Net: \la_iena_mprj[102]
mgmt_core_wrapper/la_output[97] = 1 | mgmt_protect/la_iena_mprj[102] = 1
mgmt_protect/la_data_out_mprj[97] = 1 | mgmt_core_wrapper/la_iena[102] = 1
|
Net: soc/la_output[98] |Net: \la_iena_mprj[101]
mgmt_core_wrapper/la_output[98] = 1 | mgmt_protect/la_iena_mprj[101] = 1
mgmt_protect/la_data_out_mprj[98] = 1 | mgmt_core_wrapper/la_iena[101] = 1
|
Net: soc/la_output[99] |Net: \la_iena_mprj[100]
mgmt_core_wrapper/la_output[99] = 1 | mgmt_protect/la_iena_mprj[100] = 1
mgmt_protect/la_data_out_mprj[99] = 1 | mgmt_core_wrapper/la_iena[100] = 1
|
Net: soc/la_output[9] |Net: \la_iena_mprj[99]
mgmt_core_wrapper/la_output[9] = 1 | mgmt_protect/la_iena_mprj[99] = 1
mgmt_protect/la_data_out_mprj[9] = 1 | mgmt_core_wrapper/la_iena[99] = 1
|
Net: soc/mprj_ack_i |Net: \la_iena_mprj[98]
mgmt_core_wrapper/mprj_ack_i = 1 | mgmt_protect/la_iena_mprj[98] = 1
mgmt_protect/mprj_ack_i_core = 1 | mgmt_core_wrapper/la_iena[98] = 1
|
Net: soc/mprj_cyc_o |Net: \la_iena_mprj[97]
mgmt_core_wrapper/mprj_cyc_o = 1 | mgmt_protect/la_iena_mprj[97] = 1
mgmt_protect/mprj_cyc_o_core = 1 | mgmt_core_wrapper/la_iena[97] = 1
|
Net: soc/mprj_dat_i[0] |Net: \la_iena_mprj[96]
mgmt_core_wrapper/mprj_dat_i[0] = 1 | mgmt_protect/la_iena_mprj[96] = 1
mgmt_protect/mprj_dat_i_core[0] = 1 | mgmt_core_wrapper/la_iena[96] = 1
|
Net: soc/mprj_dat_i[10] |Net: \la_iena_mprj[95]
mgmt_core_wrapper/mprj_dat_i[10] = 1 | mgmt_protect/la_iena_mprj[95] = 1
mgmt_protect/mprj_dat_i_core[10] = 1 | mgmt_core_wrapper/la_iena[95] = 1
|
Net: soc/mprj_dat_i[11] |Net: \la_iena_mprj[94]
mgmt_core_wrapper/mprj_dat_i[11] = 1 | mgmt_protect/la_iena_mprj[94] = 1
mgmt_protect/mprj_dat_i_core[11] = 1 | mgmt_core_wrapper/la_iena[94] = 1
|
Net: soc/mprj_dat_i[12] |Net: \la_iena_mprj[93]
mgmt_core_wrapper/mprj_dat_i[12] = 1 | mgmt_protect/la_iena_mprj[93] = 1
mgmt_protect/mprj_dat_i_core[12] = 1 | mgmt_core_wrapper/la_iena[93] = 1
|
Net: soc/mprj_dat_i[13] |Net: \la_iena_mprj[92]
mgmt_core_wrapper/mprj_dat_i[13] = 1 | mgmt_protect/la_iena_mprj[92] = 1
mgmt_protect/mprj_dat_i_core[13] = 1 | mgmt_core_wrapper/la_iena[92] = 1
|
Net: soc/mprj_dat_i[14] |Net: \la_iena_mprj[91]
mgmt_core_wrapper/mprj_dat_i[14] = 1 | mgmt_protect/la_iena_mprj[91] = 1
mgmt_protect/mprj_dat_i_core[14] = 1 | mgmt_core_wrapper/la_iena[91] = 1
|
Net: soc/mprj_dat_i[15] |Net: \la_iena_mprj[90]
mgmt_core_wrapper/mprj_dat_i[15] = 1 | mgmt_protect/la_iena_mprj[90] = 1
mgmt_protect/mprj_dat_i_core[15] = 1 | mgmt_core_wrapper/la_iena[90] = 1
|
Net: soc/mprj_dat_i[16] |Net: \la_iena_mprj[89]
mgmt_core_wrapper/mprj_dat_i[16] = 1 | mgmt_protect/la_iena_mprj[89] = 1
mgmt_protect/mprj_dat_i_core[16] = 1 | mgmt_core_wrapper/la_iena[89] = 1
|
Net: soc/mprj_dat_i[17] |Net: \la_iena_mprj[88]
mgmt_core_wrapper/mprj_dat_i[17] = 1 | mgmt_protect/la_iena_mprj[88] = 1
mgmt_protect/mprj_dat_i_core[17] = 1 | mgmt_core_wrapper/la_iena[88] = 1
|
Net: soc/mprj_dat_i[18] |Net: \la_iena_mprj[87]
mgmt_core_wrapper/mprj_dat_i[18] = 1 | mgmt_protect/la_iena_mprj[87] = 1
mgmt_protect/mprj_dat_i_core[18] = 1 | mgmt_core_wrapper/la_iena[87] = 1
|
Net: soc/mprj_dat_i[19] |Net: \la_iena_mprj[86]
mgmt_core_wrapper/mprj_dat_i[19] = 1 | mgmt_protect/la_iena_mprj[86] = 1
mgmt_protect/mprj_dat_i_core[19] = 1 | mgmt_core_wrapper/la_iena[86] = 1
|
Net: soc/mprj_dat_i[1] |Net: \la_iena_mprj[85]
mgmt_core_wrapper/mprj_dat_i[1] = 1 | mgmt_protect/la_iena_mprj[85] = 1
mgmt_protect/mprj_dat_i_core[1] = 1 | mgmt_core_wrapper/la_iena[85] = 1
|
Net: soc/mprj_dat_i[20] |Net: \la_iena_mprj[84]
mgmt_core_wrapper/mprj_dat_i[20] = 1 | mgmt_protect/la_iena_mprj[84] = 1
mgmt_protect/mprj_dat_i_core[20] = 1 | mgmt_core_wrapper/la_iena[84] = 1
|
Net: soc/mprj_dat_i[21] |Net: \la_iena_mprj[83]
mgmt_core_wrapper/mprj_dat_i[21] = 1 | mgmt_protect/la_iena_mprj[83] = 1
mgmt_protect/mprj_dat_i_core[21] = 1 | mgmt_core_wrapper/la_iena[83] = 1
|
Net: soc/mprj_dat_i[22] |Net: \la_iena_mprj[82]
mgmt_core_wrapper/mprj_dat_i[22] = 1 | mgmt_protect/la_iena_mprj[82] = 1
mgmt_protect/mprj_dat_i_core[22] = 1 | mgmt_core_wrapper/la_iena[82] = 1
|
Net: soc/mprj_dat_i[23] |Net: \la_iena_mprj[81]
mgmt_core_wrapper/mprj_dat_i[23] = 1 | mgmt_protect/la_iena_mprj[81] = 1
mgmt_protect/mprj_dat_i_core[23] = 1 | mgmt_core_wrapper/la_iena[81] = 1
|
Net: soc/mprj_dat_i[24] |Net: \la_iena_mprj[80]
mgmt_core_wrapper/mprj_dat_i[24] = 1 | mgmt_protect/la_iena_mprj[80] = 1
mgmt_protect/mprj_dat_i_core[24] = 1 | mgmt_core_wrapper/la_iena[80] = 1
|
Net: soc/mprj_dat_i[25] |Net: \la_iena_mprj[79]
mgmt_core_wrapper/mprj_dat_i[25] = 1 | mgmt_protect/la_iena_mprj[79] = 1
mgmt_protect/mprj_dat_i_core[25] = 1 | mgmt_core_wrapper/la_iena[79] = 1
|
Net: soc/mprj_dat_i[26] |Net: \la_iena_mprj[78]
mgmt_core_wrapper/mprj_dat_i[26] = 1 | mgmt_protect/la_iena_mprj[78] = 1
mgmt_protect/mprj_dat_i_core[26] = 1 | mgmt_core_wrapper/la_iena[78] = 1
|
Net: soc/mprj_dat_i[27] |Net: \la_iena_mprj[77]
mgmt_core_wrapper/mprj_dat_i[27] = 1 | mgmt_protect/la_iena_mprj[77] = 1
mgmt_protect/mprj_dat_i_core[27] = 1 | mgmt_core_wrapper/la_iena[77] = 1
|
Net: soc/mprj_dat_i[28] |Net: \la_iena_mprj[76]
mgmt_core_wrapper/mprj_dat_i[28] = 1 | mgmt_protect/la_iena_mprj[76] = 1
mgmt_protect/mprj_dat_i_core[28] = 1 | mgmt_core_wrapper/la_iena[76] = 1
|
Net: soc/mprj_dat_i[29] |Net: \la_iena_mprj[75]
mgmt_core_wrapper/mprj_dat_i[29] = 1 | mgmt_protect/la_iena_mprj[75] = 1
mgmt_protect/mprj_dat_i_core[29] = 1 | mgmt_core_wrapper/la_iena[75] = 1
|
Net: soc/mprj_dat_i[2] |Net: \la_iena_mprj[74]
mgmt_core_wrapper/mprj_dat_i[2] = 1 | mgmt_protect/la_iena_mprj[74] = 1
mgmt_protect/mprj_dat_i_core[2] = 1 | mgmt_core_wrapper/la_iena[74] = 1
|
Net: soc/mprj_dat_i[30] |Net: \la_iena_mprj[73]
mgmt_core_wrapper/mprj_dat_i[30] = 1 | mgmt_protect/la_iena_mprj[73] = 1
mgmt_protect/mprj_dat_i_core[30] = 1 | mgmt_core_wrapper/la_iena[73] = 1
|
Net: soc/mprj_dat_i[31] |Net: \la_iena_mprj[72]
mgmt_core_wrapper/mprj_dat_i[31] = 1 | mgmt_protect/la_iena_mprj[72] = 1
mgmt_protect/mprj_dat_i_core[31] = 1 | mgmt_core_wrapper/la_iena[72] = 1
|
Net: soc/mprj_dat_i[3] |Net: \la_iena_mprj[71]
mgmt_core_wrapper/mprj_dat_i[3] = 1 | mgmt_protect/la_iena_mprj[71] = 1
mgmt_protect/mprj_dat_i_core[3] = 1 | mgmt_core_wrapper/la_iena[71] = 1
|
Net: soc/mprj_dat_i[4] |Net: \la_iena_mprj[70]
mgmt_core_wrapper/mprj_dat_i[4] = 1 | mgmt_protect/la_iena_mprj[70] = 1
mgmt_protect/mprj_dat_i_core[4] = 1 | mgmt_core_wrapper/la_iena[70] = 1
|
Net: soc/mprj_dat_i[5] |Net: \la_iena_mprj[69]
mgmt_core_wrapper/mprj_dat_i[5] = 1 | mgmt_protect/la_iena_mprj[69] = 1
mgmt_protect/mprj_dat_i_core[5] = 1 | mgmt_core_wrapper/la_iena[69] = 1
|
Net: soc/mprj_dat_i[6] |Net: \la_iena_mprj[68]
mgmt_core_wrapper/mprj_dat_i[6] = 1 | mgmt_protect/la_iena_mprj[68] = 1
mgmt_protect/mprj_dat_i_core[6] = 1 | mgmt_core_wrapper/la_iena[68] = 1
|
Net: soc/mprj_dat_i[7] |Net: \la_iena_mprj[67]
mgmt_core_wrapper/mprj_dat_i[7] = 1 | mgmt_protect/la_iena_mprj[67] = 1
mgmt_protect/mprj_dat_i_core[7] = 1 | mgmt_core_wrapper/la_iena[67] = 1
|
Net: soc/mprj_dat_i[8] |Net: \la_iena_mprj[66]
mgmt_core_wrapper/mprj_dat_i[8] = 1 | mgmt_protect/la_iena_mprj[66] = 1
mgmt_protect/mprj_dat_i_core[8] = 1 | mgmt_core_wrapper/la_iena[66] = 1
|
Net: soc/mprj_dat_i[9] |Net: \la_iena_mprj[65]
mgmt_core_wrapper/mprj_dat_i[9] = 1 | mgmt_protect/la_iena_mprj[65] = 1
mgmt_protect/mprj_dat_i_core[9] = 1 | mgmt_core_wrapper/la_iena[65] = 1
|
Net: soc/mprj_stb_o |Net: \la_iena_mprj[64]
mgmt_core_wrapper/mprj_stb_o = 1 | mgmt_protect/la_iena_mprj[64] = 1
mgmt_protect/mprj_stb_o_core = 1 | mgmt_core_wrapper/la_iena[64] = 1
|
Net: soc/mprj_wb_iena |Net: \la_iena_mprj[63]
mgmt_core_wrapper/mprj_wb_iena = 1 | mgmt_protect/la_iena_mprj[63] = 1
mgmt_protect/mprj_iena_wb = 1 | mgmt_core_wrapper/la_iena[63] = 1
|
Net: soc/resetn_out |Net: \la_iena_mprj[62]
mgmt_core_wrapper/resetn_out = 1 | mgmt_protect/la_iena_mprj[62] = 1
mgmt_protect/caravel_rstn = 1 | mgmt_core_wrapper/la_iena[62] = 1
|
Net: soc/user_irq_ena[0] |Net: \la_iena_mprj[61]
mgmt_core_wrapper/user_irq_ena[0] = 1 | mgmt_protect/la_iena_mprj[61] = 1
mgmt_protect/user_irq_ena[0] = 1 | mgmt_core_wrapper/la_iena[61] = 1
|
Net: soc/user_irq_ena[1] |Net: \la_iena_mprj[60]
mgmt_core_wrapper/user_irq_ena[1] = 1 | mgmt_protect/la_iena_mprj[60] = 1
mgmt_protect/user_irq_ena[1] = 1 | mgmt_core_wrapper/la_iena[60] = 1
|
Net: soc/user_irq_ena[2] |Net: \la_iena_mprj[59]
mgmt_core_wrapper/user_irq_ena[2] = 1 | mgmt_protect/la_iena_mprj[59] = 1
mgmt_protect/user_irq_ena[2] = 1 | mgmt_core_wrapper/la_iena[59] = 1
|
Net: housekeeping/usr1_vcc_pwrgood |Net: \la_iena_mprj[58]
mgmt_protect/user1_vcc_powergood = 1 | mgmt_protect/la_iena_mprj[58] = 1
housekeeping/usr1_vcc_pwrgood = 1 | mgmt_core_wrapper/la_iena[58] = 1
|
Net: housekeeping/usr1_vdd_pwrgood |Net: \la_iena_mprj[57]
mgmt_protect/user1_vdd_powergood = 1 | mgmt_protect/la_iena_mprj[57] = 1
housekeeping/usr1_vdd_pwrgood = 1 | mgmt_core_wrapper/la_iena[57] = 1
|
Net: housekeeping/usr2_vcc_pwrgood |Net: \la_iena_mprj[56]
mgmt_protect/user2_vcc_powergood = 1 | mgmt_protect/la_iena_mprj[56] = 1
housekeeping/usr2_vcc_pwrgood = 1 | mgmt_core_wrapper/la_iena[56] = 1
|
Net: housekeeping/usr2_vdd_pwrgood |Net: \la_iena_mprj[55]
mgmt_protect/user2_vdd_powergood = 1 | mgmt_protect/la_iena_mprj[55] = 1
housekeeping/usr2_vdd_pwrgood = 1 | mgmt_core_wrapper/la_iena[55] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[54]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[54] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[54] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[53]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[53] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[53] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[52]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[52] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[52] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[51]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[51] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[51] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[50]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[50] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[50] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[49]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[49] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[49] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[48]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[48] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[48] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[47]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[47] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[47] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[46]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[46] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[46] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[45]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[45] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[45] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[44]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[44] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[44] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[43]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[43] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[43] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[42]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[42] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[42] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[41]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[41] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[41] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[40]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[40] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[40] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[39]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[39] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[39] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[38]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[38] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[38] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[37]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[37] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[37] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[36]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[36] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[36] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[35]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[35] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[35] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[34]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[34] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[34] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[33]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[33] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[33] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[32]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[32] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[32] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[31]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[31] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[31] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[30]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[30] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[30] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[29]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[29] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[29] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[28]
gpio_logic_high/gpio_logic1 = 1 | mgmt_protect/la_iena_mprj[28] = 1
sky130_fd_sc_hd__and2_2/A = 1 | mgmt_core_wrapper/la_iena[28] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[27]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[27] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[27] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[26]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[26] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[26] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[25]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[25] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[25] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[24]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[24] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[24] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[23]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[23] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[23] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[22]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[22] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[22] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[21]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[21] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[21] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[20]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[20] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[20] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[19]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[19] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[19] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[18]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[18] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[18] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[17]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[17] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[17] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[16]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[16] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[16] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[15]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[15] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[15] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[14]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[14] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[14] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[13]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[13] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[13] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[12]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[12] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[12] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[11]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[11] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[11] = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_iena_mprj[10]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[10] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[10] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[9]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[9] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[9] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[8]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[8] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[8] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[7]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[7] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[7] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[6]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[6] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[6] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[5]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[5] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[5] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_iena_mprj[4]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[4] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[4] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[3]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[3] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[3] = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_iena_mprj[2]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[2] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[2] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[1]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[1] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[1] = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_iena_mprj[0]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_iena_mprj[0] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | mgmt_core_wrapper/la_iena[0] = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_user[127]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[127] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[127]
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_user[126]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[126] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[126]
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_user[125]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[125] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[125]
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_user[124]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[124] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[124]
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_user[123]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[123] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[123]
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_user[122]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[122] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[122]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[121]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[121] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[121]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[120]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[120] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[120]
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_user[119]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[119] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[119]
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_user[118]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[118] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[118]
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_user[117]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[117] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[117]
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_user[116]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[116] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[116]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[115]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[115] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[115]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[114]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[114] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[114]
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_user[113]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[113] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[113]
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_user[112]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[112] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[112]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[111]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[111] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[111]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[110]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[110] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[110]
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_user[109]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[109] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[109]
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_user[108]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[108] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[108]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[107]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[107] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[107]
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[106]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[106] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[106]
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_user[105]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[105] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[105]
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_user[104]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[104] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[104]
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_user[103]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[103] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[103]
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_user[102]
sky130_fd_sc_hd__inv_2/A = 1 | mgmt_protect/la_oenb_core[102] = 1
sky130_fd_sc_hd__nor2_2/Y = 1 | user_analog_project_wrapper/la_oenb[102]
|
Net: padframe/mprj_io_in[14] |Net: \la_oenb_user[101]
sky130_fd_sc_hd__buf_2/A = 1 | mgmt_protect/la_oenb_core[101] = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | user_analog_project_wrapper/la_oenb[101]
chip_io_alt/mprj_io_in[14] = 1 |
|
Net: padframe/mprj_io_in[0] |Net: \la_oenb_user[100]
chip_io_alt/mprj_io_in[0] = 1 | mgmt_protect/la_oenb_core[100] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[100]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[10] |Net: \la_oenb_user[99]
chip_io_alt/mprj_io_in[10] = 1 | mgmt_protect/la_oenb_core[99] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[99]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[11] |Net: \la_oenb_user[98]
chip_io_alt/mprj_io_in[11] = 1 | mgmt_protect/la_oenb_core[98] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[98]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[12] |Net: \la_oenb_user[97]
chip_io_alt/mprj_io_in[12] = 1 | mgmt_protect/la_oenb_core[97] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[97]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[13] |Net: \la_oenb_user[96]
chip_io_alt/mprj_io_in[13] = 1 | mgmt_protect/la_oenb_core[96] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[96]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[1] |Net: \la_oenb_user[95]
chip_io_alt/mprj_io_in[1] = 1 | mgmt_protect/la_oenb_core[95] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[95]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[2] |Net: \la_oenb_user[94]
chip_io_alt/mprj_io_in[2] = 1 | mgmt_protect/la_oenb_core[94] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[94]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[3] |Net: \la_oenb_user[93]
chip_io_alt/mprj_io_in[3] = 1 | mgmt_protect/la_oenb_core[93] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[93]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[4] |Net: \la_oenb_user[92]
chip_io_alt/mprj_io_in[4] = 1 | mgmt_protect/la_oenb_core[92] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[92]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[5] |Net: \la_oenb_user[91]
chip_io_alt/mprj_io_in[5] = 1 | mgmt_protect/la_oenb_core[91] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[91]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[6] |Net: \la_oenb_user[90]
chip_io_alt/mprj_io_in[6] = 1 | mgmt_protect/la_oenb_core[90] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[90]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[7] |Net: \la_oenb_user[89]
chip_io_alt/mprj_io_in[7] = 1 | mgmt_protect/la_oenb_core[89] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[89]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[8] |Net: \la_oenb_user[88]
chip_io_alt/mprj_io_in[8] = 1 | mgmt_protect/la_oenb_core[88] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[88]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[9] |Net: \la_oenb_user[87]
chip_io_alt/mprj_io_in[9] = 1 | mgmt_protect/la_oenb_core[87] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[87]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[24] |Net: \la_oenb_user[86]
chip_io_alt/mprj_io_in[24] = 1 | mgmt_protect/la_oenb_core[86] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[86]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[25] |Net: \la_oenb_user[85]
chip_io_alt/mprj_io_in[25] = 1 | mgmt_protect/la_oenb_core[85] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[85]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[26] |Net: \la_oenb_user[84]
chip_io_alt/mprj_io_in[26] = 1 | mgmt_protect/la_oenb_core[84] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[84]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[15] |Net: \la_oenb_user[83]
chip_io_alt/mprj_io_in[15] = 1 | mgmt_protect/la_oenb_core[83] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[83]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[16] |Net: \la_oenb_user[82]
chip_io_alt/mprj_io_in[16] = 1 | mgmt_protect/la_oenb_core[82] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[82]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[17] |Net: \la_oenb_user[81]
chip_io_alt/mprj_io_in[17] = 1 | mgmt_protect/la_oenb_core[81] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[81]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[18] |Net: \la_oenb_user[80]
chip_io_alt/mprj_io_in[18] = 1 | mgmt_protect/la_oenb_core[80] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[80]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[19] |Net: \la_oenb_user[79]
chip_io_alt/mprj_io_in[19] = 1 | mgmt_protect/la_oenb_core[79] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[79]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[20] |Net: \la_oenb_user[78]
chip_io_alt/mprj_io_in[20] = 1 | mgmt_protect/la_oenb_core[78] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[78]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[21] |Net: \la_oenb_user[77]
chip_io_alt/mprj_io_in[21] = 1 | mgmt_protect/la_oenb_core[77] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[77]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[22] |Net: \la_oenb_user[76]
chip_io_alt/mprj_io_in[22] = 1 | mgmt_protect/la_oenb_core[76] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[76]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: padframe/mprj_io_in[23] |Net: \la_oenb_user[75]
chip_io_alt/mprj_io_in[23] = 1 | mgmt_protect/la_oenb_core[75] = 1
sky130_fd_sc_hd__buf_2/A = 1 | user_analog_project_wrapper/la_oenb[75]
sky130_fd_sc_hd__diode_2/DIODE = 1 |
|
Net: por/vss3v3 |Net: \la_oenb_user[74]
chip_io_alt/vssio = 1 | mgmt_protect/la_oenb_core[74] = 1
simple_por/vss3v3 = 1 | user_analog_project_wrapper/la_oenb[74]
xres_buf/VGND = 1 |
|
Net: por/vdd3v3 |Net: \la_oenb_user[73]
chip_io_alt/vddio = 1 | mgmt_protect/la_oenb_core[73] = 1
simple_por/vdd3v3 = 1 | user_analog_project_wrapper/la_oenb[73]
xres_buf/VPWR = 1 |
|
Net: soc/mprj_adr_o[0] |Net: \la_oenb_user[72]
mgmt_core_wrapper/mprj_adr_o[0] = 1 | mgmt_protect/la_oenb_core[72] = 1
mgmt_protect/mprj_adr_o_core[0] = 1 | user_analog_project_wrapper/la_oenb[72]
housekeeping/wb_adr_i[0] = 1 |
|
Net: soc/mprj_adr_o[10] |Net: \la_oenb_user[71]
mgmt_core_wrapper/mprj_adr_o[10] = 1 | mgmt_protect/la_oenb_core[71] = 1
mgmt_protect/mprj_adr_o_core[10] = 1 | user_analog_project_wrapper/la_oenb[71]
housekeeping/wb_adr_i[10] = 1 |
|
Net: soc/mprj_adr_o[11] |Net: \la_oenb_user[70]
mgmt_core_wrapper/mprj_adr_o[11] = 1 | mgmt_protect/la_oenb_core[70] = 1
mgmt_protect/mprj_adr_o_core[11] = 1 | user_analog_project_wrapper/la_oenb[70]
housekeeping/wb_adr_i[11] = 1 |
|
Net: soc/mprj_adr_o[12] |Net: \la_oenb_user[69]
mgmt_core_wrapper/mprj_adr_o[12] = 1 | mgmt_protect/la_oenb_core[69] = 1
mgmt_protect/mprj_adr_o_core[12] = 1 | user_analog_project_wrapper/la_oenb[69]
housekeeping/wb_adr_i[12] = 1 |
|
Net: soc/mprj_adr_o[13] |Net: \la_oenb_user[68]
mgmt_core_wrapper/mprj_adr_o[13] = 1 | mgmt_protect/la_oenb_core[68] = 1
mgmt_protect/mprj_adr_o_core[13] = 1 | user_analog_project_wrapper/la_oenb[68]
housekeeping/wb_adr_i[13] = 1 |
|
Net: soc/mprj_adr_o[14] |Net: \la_oenb_user[67]
mgmt_core_wrapper/mprj_adr_o[14] = 1 | mgmt_protect/la_oenb_core[67] = 1
mgmt_protect/mprj_adr_o_core[14] = 1 | user_analog_project_wrapper/la_oenb[67]
housekeeping/wb_adr_i[14] = 1 |
|
Net: soc/mprj_adr_o[15] |Net: \la_oenb_user[66]
mgmt_core_wrapper/mprj_adr_o[15] = 1 | mgmt_protect/la_oenb_core[66] = 1
mgmt_protect/mprj_adr_o_core[15] = 1 | user_analog_project_wrapper/la_oenb[66]
housekeeping/wb_adr_i[15] = 1 |
|
Net: soc/mprj_adr_o[16] |Net: \la_oenb_user[65]
mgmt_core_wrapper/mprj_adr_o[16] = 1 | mgmt_protect/la_oenb_core[65] = 1
mgmt_protect/mprj_adr_o_core[16] = 1 | user_analog_project_wrapper/la_oenb[65]
housekeeping/wb_adr_i[16] = 1 |
|
Net: soc/mprj_adr_o[17] |Net: \la_oenb_user[64]
mgmt_core_wrapper/mprj_adr_o[17] = 1 | mgmt_protect/la_oenb_core[64] = 1
mgmt_protect/mprj_adr_o_core[17] = 1 | user_analog_project_wrapper/la_oenb[64]
housekeeping/wb_adr_i[17] = 1 |
|
Net: soc/mprj_adr_o[18] |Net: \la_oenb_user[63]
mgmt_core_wrapper/mprj_adr_o[18] = 1 | mgmt_protect/la_oenb_core[63] = 1
mgmt_protect/mprj_adr_o_core[18] = 1 | user_analog_project_wrapper/la_oenb[63]
housekeeping/wb_adr_i[18] = 1 |
|
Net: soc/mprj_adr_o[19] |Net: \la_oenb_user[62]
mgmt_core_wrapper/mprj_adr_o[19] = 1 | mgmt_protect/la_oenb_core[62] = 1
mgmt_protect/mprj_adr_o_core[19] = 1 | user_analog_project_wrapper/la_oenb[62]
housekeeping/wb_adr_i[19] = 1 |
|
Net: soc/mprj_adr_o[1] |Net: \la_oenb_user[61]
mgmt_core_wrapper/mprj_adr_o[1] = 1 | mgmt_protect/la_oenb_core[61] = 1
mgmt_protect/mprj_adr_o_core[1] = 1 | user_analog_project_wrapper/la_oenb[61]
housekeeping/wb_adr_i[1] = 1 |
|
Net: soc/mprj_adr_o[20] |Net: \la_oenb_user[60]
mgmt_core_wrapper/mprj_adr_o[20] = 1 | mgmt_protect/la_oenb_core[60] = 1
mgmt_protect/mprj_adr_o_core[20] = 1 | user_analog_project_wrapper/la_oenb[60]
housekeeping/wb_adr_i[20] = 1 |
|
Net: soc/mprj_adr_o[21] |Net: \la_oenb_user[59]
mgmt_core_wrapper/mprj_adr_o[21] = 1 | mgmt_protect/la_oenb_core[59] = 1
mgmt_protect/mprj_adr_o_core[21] = 1 | user_analog_project_wrapper/la_oenb[59]
housekeeping/wb_adr_i[21] = 1 |
|
Net: soc/mprj_adr_o[22] |Net: \la_oenb_user[58]
mgmt_core_wrapper/mprj_adr_o[22] = 1 | mgmt_protect/la_oenb_core[58] = 1
mgmt_protect/mprj_adr_o_core[22] = 1 | user_analog_project_wrapper/la_oenb[58]
housekeeping/wb_adr_i[22] = 1 |
|
Net: soc/mprj_adr_o[23] |Net: \la_oenb_user[57]
mgmt_core_wrapper/mprj_adr_o[23] = 1 | mgmt_protect/la_oenb_core[57] = 1
mgmt_protect/mprj_adr_o_core[23] = 1 | user_analog_project_wrapper/la_oenb[57]
housekeeping/wb_adr_i[23] = 1 |
|
Net: soc/mprj_adr_o[24] |Net: \la_oenb_user[56]
mgmt_core_wrapper/mprj_adr_o[24] = 1 | mgmt_protect/la_oenb_core[56] = 1
mgmt_protect/mprj_adr_o_core[24] = 1 | user_analog_project_wrapper/la_oenb[56]
housekeeping/wb_adr_i[24] = 1 |
|
Net: soc/mprj_adr_o[25] |Net: \la_oenb_user[55]
mgmt_core_wrapper/mprj_adr_o[25] = 1 | mgmt_protect/la_oenb_core[55] = 1
mgmt_protect/mprj_adr_o_core[25] = 1 | user_analog_project_wrapper/la_oenb[55]
housekeeping/wb_adr_i[25] = 1 |
|
Net: soc/mprj_adr_o[26] |Net: \la_oenb_user[54]
mgmt_core_wrapper/mprj_adr_o[26] = 1 | mgmt_protect/la_oenb_core[54] = 1
mgmt_protect/mprj_adr_o_core[26] = 1 | user_analog_project_wrapper/la_oenb[54]
housekeeping/wb_adr_i[26] = 1 |
|
Net: soc/mprj_adr_o[27] |Net: \la_oenb_user[53]
mgmt_core_wrapper/mprj_adr_o[27] = 1 | mgmt_protect/la_oenb_core[53] = 1
mgmt_protect/mprj_adr_o_core[27] = 1 | user_analog_project_wrapper/la_oenb[53]
housekeeping/wb_adr_i[27] = 1 |
|
Net: soc/mprj_adr_o[28] |Net: \la_oenb_user[52]
mgmt_core_wrapper/mprj_adr_o[28] = 1 | mgmt_protect/la_oenb_core[52] = 1
mgmt_protect/mprj_adr_o_core[28] = 1 | user_analog_project_wrapper/la_oenb[52]
housekeeping/wb_adr_i[28] = 1 |
|
Net: soc/mprj_adr_o[29] |Net: \la_oenb_user[51]
mgmt_core_wrapper/mprj_adr_o[29] = 1 | mgmt_protect/la_oenb_core[51] = 1
mgmt_protect/mprj_adr_o_core[29] = 1 | user_analog_project_wrapper/la_oenb[51]
housekeeping/wb_adr_i[29] = 1 |
|
Net: soc/mprj_adr_o[2] |Net: \la_oenb_user[50]
mgmt_core_wrapper/mprj_adr_o[2] = 1 | mgmt_protect/la_oenb_core[50] = 1
mgmt_protect/mprj_adr_o_core[2] = 1 | user_analog_project_wrapper/la_oenb[50]
housekeeping/wb_adr_i[2] = 1 |
|
Net: soc/mprj_adr_o[30] |Net: \la_oenb_user[49]
mgmt_core_wrapper/mprj_adr_o[30] = 1 | mgmt_protect/la_oenb_core[49] = 1
mgmt_protect/mprj_adr_o_core[30] = 1 | user_analog_project_wrapper/la_oenb[49]
housekeeping/wb_adr_i[30] = 1 |
|
Net: soc/mprj_adr_o[31] |Net: \la_oenb_user[48]
mgmt_core_wrapper/mprj_adr_o[31] = 1 | mgmt_protect/la_oenb_core[48] = 1
mgmt_protect/mprj_adr_o_core[31] = 1 | user_analog_project_wrapper/la_oenb[48]
housekeeping/wb_adr_i[31] = 1 |
|
Net: soc/mprj_adr_o[3] |Net: \la_oenb_user[47]
mgmt_core_wrapper/mprj_adr_o[3] = 1 | mgmt_protect/la_oenb_core[47] = 1
mgmt_protect/mprj_adr_o_core[3] = 1 | user_analog_project_wrapper/la_oenb[47]
housekeeping/wb_adr_i[3] = 1 |
|
Net: soc/mprj_adr_o[4] |Net: \la_oenb_user[46]
mgmt_core_wrapper/mprj_adr_o[4] = 1 | mgmt_protect/la_oenb_core[46] = 1
mgmt_protect/mprj_adr_o_core[4] = 1 | user_analog_project_wrapper/la_oenb[46]
housekeeping/wb_adr_i[4] = 1 |
|
Net: soc/mprj_adr_o[5] |Net: \la_oenb_user[45]
mgmt_core_wrapper/mprj_adr_o[5] = 1 | mgmt_protect/la_oenb_core[45] = 1
mgmt_protect/mprj_adr_o_core[5] = 1 | user_analog_project_wrapper/la_oenb[45]
housekeeping/wb_adr_i[5] = 1 |
|
Net: soc/mprj_adr_o[6] |Net: \la_oenb_user[44]
mgmt_core_wrapper/mprj_adr_o[6] = 1 | mgmt_protect/la_oenb_core[44] = 1
mgmt_protect/mprj_adr_o_core[6] = 1 | user_analog_project_wrapper/la_oenb[44]
housekeeping/wb_adr_i[6] = 1 |
|
Net: soc/mprj_adr_o[7] |Net: \la_oenb_user[43]
mgmt_core_wrapper/mprj_adr_o[7] = 1 | mgmt_protect/la_oenb_core[43] = 1
mgmt_protect/mprj_adr_o_core[7] = 1 | user_analog_project_wrapper/la_oenb[43]
housekeeping/wb_adr_i[7] = 1 |
|
Net: soc/mprj_adr_o[8] |Net: \la_oenb_user[42]
mgmt_core_wrapper/mprj_adr_o[8] = 1 | mgmt_protect/la_oenb_core[42] = 1
mgmt_protect/mprj_adr_o_core[8] = 1 | user_analog_project_wrapper/la_oenb[42]
housekeeping/wb_adr_i[8] = 1 |
|
Net: soc/mprj_adr_o[9] |Net: \la_oenb_user[41]
mgmt_core_wrapper/mprj_adr_o[9] = 1 | mgmt_protect/la_oenb_core[41] = 1
mgmt_protect/mprj_adr_o_core[9] = 1 | user_analog_project_wrapper/la_oenb[41]
housekeeping/wb_adr_i[9] = 1 |
|
Net: soc/mprj_dat_o[0] |Net: \la_oenb_user[40]
mgmt_core_wrapper/mprj_dat_o[0] = 1 | mgmt_protect/la_oenb_core[40] = 1
mgmt_protect/mprj_dat_o_core[0] = 1 | user_analog_project_wrapper/la_oenb[40]
housekeeping/wb_dat_i[0] = 1 |
|
Net: soc/mprj_dat_o[10] |Net: \la_oenb_user[39]
mgmt_core_wrapper/mprj_dat_o[10] = 1 | mgmt_protect/la_oenb_core[39] = 1
mgmt_protect/mprj_dat_o_core[10] = 1 | user_analog_project_wrapper/la_oenb[39]
housekeeping/wb_dat_i[10] = 1 |
|
Net: soc/mprj_dat_o[11] |Net: \la_oenb_user[38]
mgmt_core_wrapper/mprj_dat_o[11] = 1 | mgmt_protect/la_oenb_core[38] = 1
mgmt_protect/mprj_dat_o_core[11] = 1 | user_analog_project_wrapper/la_oenb[38]
housekeeping/wb_dat_i[11] = 1 |
|
Net: soc/mprj_dat_o[12] |Net: \la_oenb_user[37]
mgmt_core_wrapper/mprj_dat_o[12] = 1 | mgmt_protect/la_oenb_core[37] = 1
mgmt_protect/mprj_dat_o_core[12] = 1 | user_analog_project_wrapper/la_oenb[37]
housekeeping/wb_dat_i[12] = 1 |
|
Net: soc/mprj_dat_o[13] |Net: \la_oenb_user[36]
mgmt_core_wrapper/mprj_dat_o[13] = 1 | mgmt_protect/la_oenb_core[36] = 1
mgmt_protect/mprj_dat_o_core[13] = 1 | user_analog_project_wrapper/la_oenb[36]
housekeeping/wb_dat_i[13] = 1 |
|
Net: soc/mprj_dat_o[14] |Net: \la_oenb_user[35]
mgmt_core_wrapper/mprj_dat_o[14] = 1 | mgmt_protect/la_oenb_core[35] = 1
mgmt_protect/mprj_dat_o_core[14] = 1 | user_analog_project_wrapper/la_oenb[35]
housekeeping/wb_dat_i[14] = 1 |
|
Net: soc/mprj_dat_o[15] |Net: \la_oenb_user[34]
mgmt_core_wrapper/mprj_dat_o[15] = 1 | mgmt_protect/la_oenb_core[34] = 1
mgmt_protect/mprj_dat_o_core[15] = 1 | user_analog_project_wrapper/la_oenb[34]
housekeeping/wb_dat_i[15] = 1 |
|
Net: soc/mprj_dat_o[16] |Net: \la_oenb_user[33]
mgmt_core_wrapper/mprj_dat_o[16] = 1 | mgmt_protect/la_oenb_core[33] = 1
mgmt_protect/mprj_dat_o_core[16] = 1 | user_analog_project_wrapper/la_oenb[33]
housekeeping/wb_dat_i[16] = 1 |
|
Net: soc/mprj_dat_o[17] |Net: \la_oenb_user[32]
mgmt_core_wrapper/mprj_dat_o[17] = 1 | mgmt_protect/la_oenb_core[32] = 1
mgmt_protect/mprj_dat_o_core[17] = 1 | user_analog_project_wrapper/la_oenb[32]
housekeeping/wb_dat_i[17] = 1 |
|
Net: soc/mprj_dat_o[18] |Net: \la_oenb_user[31]
mgmt_core_wrapper/mprj_dat_o[18] = 1 | mgmt_protect/la_oenb_core[31] = 1
mgmt_protect/mprj_dat_o_core[18] = 1 | user_analog_project_wrapper/la_oenb[31]
housekeeping/wb_dat_i[18] = 1 |
|
Net: soc/mprj_dat_o[19] |Net: \la_oenb_user[30]
mgmt_core_wrapper/mprj_dat_o[19] = 1 | mgmt_protect/la_oenb_core[30] = 1
mgmt_protect/mprj_dat_o_core[19] = 1 | user_analog_project_wrapper/la_oenb[30]
housekeeping/wb_dat_i[19] = 1 |
|
Net: soc/mprj_dat_o[1] |Net: \la_oenb_user[29]
mgmt_core_wrapper/mprj_dat_o[1] = 1 | mgmt_protect/la_oenb_core[29] = 1
mgmt_protect/mprj_dat_o_core[1] = 1 | user_analog_project_wrapper/la_oenb[29]
housekeeping/wb_dat_i[1] = 1 |
|
Net: soc/mprj_dat_o[20] |Net: \la_oenb_user[28]
mgmt_core_wrapper/mprj_dat_o[20] = 1 | mgmt_protect/la_oenb_core[28] = 1
mgmt_protect/mprj_dat_o_core[20] = 1 | user_analog_project_wrapper/la_oenb[28]
housekeeping/wb_dat_i[20] = 1 |
|
Net: soc/mprj_dat_o[21] |Net: \la_oenb_user[27]
mgmt_core_wrapper/mprj_dat_o[21] = 1 | mgmt_protect/la_oenb_core[27] = 1
mgmt_protect/mprj_dat_o_core[21] = 1 | user_analog_project_wrapper/la_oenb[27]
housekeeping/wb_dat_i[21] = 1 |
|
Net: soc/mprj_dat_o[22] |Net: \la_oenb_user[26]
mgmt_core_wrapper/mprj_dat_o[22] = 1 | mgmt_protect/la_oenb_core[26] = 1
mgmt_protect/mprj_dat_o_core[22] = 1 | user_analog_project_wrapper/la_oenb[26]
housekeeping/wb_dat_i[22] = 1 |
|
Net: soc/mprj_dat_o[23] |Net: \la_oenb_user[25]
mgmt_core_wrapper/mprj_dat_o[23] = 1 | mgmt_protect/la_oenb_core[25] = 1
mgmt_protect/mprj_dat_o_core[23] = 1 | user_analog_project_wrapper/la_oenb[25]
housekeeping/wb_dat_i[23] = 1 |
|
Net: soc/mprj_dat_o[24] |Net: \la_oenb_user[24]
mgmt_core_wrapper/mprj_dat_o[24] = 1 | mgmt_protect/la_oenb_core[24] = 1
mgmt_protect/mprj_dat_o_core[24] = 1 | user_analog_project_wrapper/la_oenb[24]
housekeeping/wb_dat_i[24] = 1 |
|
Net: soc/mprj_dat_o[25] |Net: \la_oenb_user[23]
mgmt_core_wrapper/mprj_dat_o[25] = 1 | mgmt_protect/la_oenb_core[23] = 1
mgmt_protect/mprj_dat_o_core[25] = 1 | user_analog_project_wrapper/la_oenb[23]
housekeeping/wb_dat_i[25] = 1 |
|
Net: soc/mprj_dat_o[26] |Net: \la_oenb_user[22]
mgmt_core_wrapper/mprj_dat_o[26] = 1 | mgmt_protect/la_oenb_core[22] = 1
mgmt_protect/mprj_dat_o_core[26] = 1 | user_analog_project_wrapper/la_oenb[22]
housekeeping/wb_dat_i[26] = 1 |
|
Net: soc/mprj_dat_o[27] |Net: \la_oenb_user[21]
mgmt_core_wrapper/mprj_dat_o[27] = 1 | mgmt_protect/la_oenb_core[21] = 1
mgmt_protect/mprj_dat_o_core[27] = 1 | user_analog_project_wrapper/la_oenb[21]
housekeeping/wb_dat_i[27] = 1 |
|
Net: soc/mprj_dat_o[28] |Net: \la_oenb_user[20]
mgmt_core_wrapper/mprj_dat_o[28] = 1 | mgmt_protect/la_oenb_core[20] = 1
mgmt_protect/mprj_dat_o_core[28] = 1 | user_analog_project_wrapper/la_oenb[20]
housekeeping/wb_dat_i[28] = 1 |
|
Net: soc/mprj_dat_o[29] |Net: \la_oenb_user[19]
mgmt_core_wrapper/mprj_dat_o[29] = 1 | mgmt_protect/la_oenb_core[19] = 1
mgmt_protect/mprj_dat_o_core[29] = 1 | user_analog_project_wrapper/la_oenb[19]
housekeeping/wb_dat_i[29] = 1 |
|
Net: soc/mprj_dat_o[2] |Net: \la_oenb_user[18]
mgmt_core_wrapper/mprj_dat_o[2] = 1 | mgmt_protect/la_oenb_core[18] = 1
mgmt_protect/mprj_dat_o_core[2] = 1 | user_analog_project_wrapper/la_oenb[18]
housekeeping/wb_dat_i[2] = 1 |
|
Net: soc/mprj_dat_o[30] |Net: \la_oenb_user[17]
mgmt_core_wrapper/mprj_dat_o[30] = 1 | mgmt_protect/la_oenb_core[17] = 1
mgmt_protect/mprj_dat_o_core[30] = 1 | user_analog_project_wrapper/la_oenb[17]
housekeeping/wb_dat_i[30] = 1 |
|
Net: soc/mprj_dat_o[31] |Net: \la_oenb_user[16]
mgmt_core_wrapper/mprj_dat_o[31] = 1 | mgmt_protect/la_oenb_core[16] = 1
mgmt_protect/mprj_dat_o_core[31] = 1 | user_analog_project_wrapper/la_oenb[16]
housekeeping/wb_dat_i[31] = 1 |
|
Net: soc/mprj_dat_o[3] |Net: \la_oenb_user[15]
mgmt_core_wrapper/mprj_dat_o[3] = 1 | mgmt_protect/la_oenb_core[15] = 1
mgmt_protect/mprj_dat_o_core[3] = 1 | user_analog_project_wrapper/la_oenb[15]
housekeeping/wb_dat_i[3] = 1 |
|
Net: soc/mprj_dat_o[4] |Net: \la_oenb_user[14]
mgmt_core_wrapper/mprj_dat_o[4] = 1 | mgmt_protect/la_oenb_core[14] = 1
mgmt_protect/mprj_dat_o_core[4] = 1 | user_analog_project_wrapper/la_oenb[14]
housekeeping/wb_dat_i[4] = 1 |
|
Net: soc/mprj_dat_o[5] |Net: \la_oenb_user[13]
mgmt_core_wrapper/mprj_dat_o[5] = 1 | mgmt_protect/la_oenb_core[13] = 1
mgmt_protect/mprj_dat_o_core[5] = 1 | user_analog_project_wrapper/la_oenb[13]
housekeeping/wb_dat_i[5] = 1 |
|
Net: soc/mprj_dat_o[6] |Net: \la_oenb_user[12]
mgmt_core_wrapper/mprj_dat_o[6] = 1 | mgmt_protect/la_oenb_core[12] = 1
mgmt_protect/mprj_dat_o_core[6] = 1 | user_analog_project_wrapper/la_oenb[12]
housekeeping/wb_dat_i[6] = 1 |
|
Net: soc/mprj_dat_o[7] |Net: \la_oenb_user[11]
mgmt_core_wrapper/mprj_dat_o[7] = 1 | mgmt_protect/la_oenb_core[11] = 1
mgmt_protect/mprj_dat_o_core[7] = 1 | user_analog_project_wrapper/la_oenb[11]
housekeeping/wb_dat_i[7] = 1 |
|
Net: soc/mprj_dat_o[8] |Net: \la_oenb_user[10]
mgmt_core_wrapper/mprj_dat_o[8] = 1 | mgmt_protect/la_oenb_core[10] = 1
mgmt_protect/mprj_dat_o_core[8] = 1 | user_analog_project_wrapper/la_oenb[10]
housekeeping/wb_dat_i[8] = 1 |
|
Net: soc/mprj_dat_o[9] |Net: \la_oenb_user[9]
mgmt_core_wrapper/mprj_dat_o[9] = 1 | mgmt_protect/la_oenb_core[9] = 1
mgmt_protect/mprj_dat_o_core[9] = 1 | user_analog_project_wrapper/la_oenb[9] =
housekeeping/wb_dat_i[9] = 1 |
|
Net: soc/mprj_sel_o[0] |Net: \la_oenb_user[8]
mgmt_core_wrapper/mprj_sel_o[0] = 1 | mgmt_protect/la_oenb_core[8] = 1
mgmt_protect/mprj_sel_o_core[0] = 1 | user_analog_project_wrapper/la_oenb[8] =
housekeeping/wb_sel_i[0] = 1 |
|
Net: soc/mprj_sel_o[1] |Net: \la_oenb_user[7]
mgmt_core_wrapper/mprj_sel_o[1] = 1 | mgmt_protect/la_oenb_core[7] = 1
mgmt_protect/mprj_sel_o_core[1] = 1 | user_analog_project_wrapper/la_oenb[7] =
housekeeping/wb_sel_i[1] = 1 |
|
Net: soc/mprj_sel_o[2] |Net: \la_oenb_user[6]
mgmt_core_wrapper/mprj_sel_o[2] = 1 | mgmt_protect/la_oenb_core[6] = 1
mgmt_protect/mprj_sel_o_core[2] = 1 | user_analog_project_wrapper/la_oenb[6] =
housekeeping/wb_sel_i[2] = 1 |
|
Net: soc/mprj_sel_o[3] |Net: \la_oenb_user[5]
mgmt_core_wrapper/mprj_sel_o[3] = 1 | mgmt_protect/la_oenb_core[5] = 1
mgmt_protect/mprj_sel_o_core[3] = 1 | user_analog_project_wrapper/la_oenb[5] =
housekeeping/wb_sel_i[3] = 1 |
|
Net: soc/mprj_we_o |Net: \la_oenb_user[4]
mgmt_core_wrapper/mprj_we_o = 1 | mgmt_protect/la_oenb_core[4] = 1
mgmt_protect/mprj_we_o_core = 1 | user_analog_project_wrapper/la_oenb[4] =
housekeeping/wb_we_i = 1 |
|
Net: clock_ctrl/user_clk |Net: \la_oenb_user[3]
caravel_clocking/user_clk = 1 | mgmt_protect/la_oenb_core[3] = 1
mgmt_protect/caravel_clk2 = 1 | user_analog_project_wrapper/la_oenb[3] =
housekeeping/user_clock = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[2]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_core[2] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | user_analog_project_wrapper/la_oenb[2] =
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_user[1]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_core[1] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | user_analog_project_wrapper/la_oenb[1] =
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_user[0]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_core[0] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | user_analog_project_wrapper/la_oenb[0] =
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[127]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[127] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[127] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[126]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[126] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[126] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[125]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[125] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[125] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[124]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[124] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[124] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[123]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[123] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[123] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[122]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[122] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[122] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[121]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[121] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[121] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[120]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[120] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[120] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[119]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[119] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[119] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[118]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[118] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[118] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[117]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[117] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[117] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[116]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[116] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[116] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[115]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[115] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[115] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[114]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[114] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[114] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[113]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[113] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[113] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[112]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[112] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[112] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[111]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[111] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[111] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[110]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[110] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[110] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[109]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[109] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[109] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[108]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[108] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[108] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[107]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[107] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[107] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[106]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[106] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[106] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[105]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[105] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[105] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[104]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[104] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[104] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[103]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[103] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[103] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[102]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[102] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[102] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[101]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[101] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[101] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[100]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[100] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[100] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[99]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[99] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[99] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[98]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[98] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[98] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[97]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[97] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[97] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[96]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[96] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[96] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[95]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[95] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[95] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[94]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[94] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[94] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[93]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[93] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[93] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[92]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[92] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[92] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[91]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[91] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[91] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[90]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[90] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[90] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[89]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[89] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[89] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[88]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[88] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[88] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \la_oenb_mprj[87]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[87] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[87] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[86]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[86] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[86] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[85]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[85] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[85] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[84]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[84] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[84] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[83]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[83] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[83] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[82]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[82] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[82] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \la_oenb_mprj[81]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[81] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[81] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[80]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[80] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[80] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_in_1a |Net: \la_oenb_mprj[79]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[79] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[79] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[78]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[78] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[78] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: gpio_control_block:gpio_control_bidir |Net: \la_oenb_mprj[77]
sky130_fd_sc_hd__nand2_2/Y = 1 | mgmt_protect/la_oenb_mprj[77] = 1
sky130_fd_sc_hd__nor2_2/B = 1 | mgmt_core_wrapper/la_oenb[77] = 1
sky130_fd_sc_hd__nor2_2/A = 1 |
|
Net: mprj/io_in[14] |Net: \la_oenb_mprj[76]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[76] = 1
| mgmt_core_wrapper/la_oenb[76] = 1
|
Net: mprj/io_in[5] |Net: \la_oenb_mprj[75]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[75] = 1
| mgmt_core_wrapper/la_oenb[75] = 1
|
Net: mprj/io_in[24] |Net: \la_oenb_mprj[74]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[74] = 1
| mgmt_core_wrapper/la_oenb[74] = 1
|
Net: mprj/io_in[23] |Net: \la_oenb_mprj[73]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[73] = 1
| mgmt_core_wrapper/la_oenb[73] = 1
|
Net: mprj/io_in[12] |Net: \la_oenb_mprj[72]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[72] = 1
| mgmt_core_wrapper/la_oenb[72] = 1
|
Net: mprj/io_in[3] |Net: \la_oenb_mprj[71]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[71] = 1
| mgmt_core_wrapper/la_oenb[71] = 1
|
Net: mprj/io_in[21] |Net: \la_oenb_mprj[70]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[70] = 1
| mgmt_core_wrapper/la_oenb[70] = 1
|
Net: mprj/io_in[10] |Net: \la_oenb_mprj[69]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[69] = 1
| mgmt_core_wrapper/la_oenb[69] = 1
|
Net: mprj/io_in[8] |Net: \la_oenb_mprj[68]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[68] = 1
| mgmt_core_wrapper/la_oenb[68] = 1
|
Net: mprj/io_in[19] |Net: \la_oenb_mprj[67]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[67] = 1
| mgmt_core_wrapper/la_oenb[67] = 1
|
Net: mprj/io_in[17] |Net: \la_oenb_mprj[66]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[66] = 1
| mgmt_core_wrapper/la_oenb[66] = 1
|
Net: mprj/io_in[0] |Net: \la_oenb_mprj[65]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[65] = 1
| mgmt_core_wrapper/la_oenb[65] = 1
|
Net: mprj/io_in[15] |Net: \la_oenb_mprj[64]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[64] = 1
| mgmt_core_wrapper/la_oenb[64] = 1
|
Net: mprj/io_in[6] |Net: \la_oenb_mprj[63]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[63] = 1
| mgmt_core_wrapper/la_oenb[63] = 1
|
Net: mprj/io_in[25] |Net: \la_oenb_mprj[62]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[62] = 1
| mgmt_core_wrapper/la_oenb[62] = 1
|
Net: mprj/io_in[13] |Net: \la_oenb_mprj[61]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[61] = 1
| mgmt_core_wrapper/la_oenb[61] = 1
|
Net: mprj/io_in[4] |Net: \la_oenb_mprj[60]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[60] = 1
| mgmt_core_wrapper/la_oenb[60] = 1
|
Net: mprj/io_in[22] |Net: \la_oenb_mprj[59]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[59] = 1
| mgmt_core_wrapper/la_oenb[59] = 1
|
Net: mprj/io_in[11] |Net: \la_oenb_mprj[58]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[58] = 1
| mgmt_core_wrapper/la_oenb[58] = 1
|
Net: mprj/io_in[2] |Net: \la_oenb_mprj[57]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[57] = 1
| mgmt_core_wrapper/la_oenb[57] = 1
|
Net: mprj/io_in[20] |Net: \la_oenb_mprj[56]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[56] = 1
| mgmt_core_wrapper/la_oenb[56] = 1
|
Net: mprj/io_in[9] |Net: \la_oenb_mprj[55]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[55] = 1
| mgmt_core_wrapper/la_oenb[55] = 1
|
Net: mprj/io_in[18] |Net: \la_oenb_mprj[54]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[54] = 1
| mgmt_core_wrapper/la_oenb[54] = 1
|
Net: mprj/io_in[1] |Net: \la_oenb_mprj[53]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[53] = 1
| mgmt_core_wrapper/la_oenb[53] = 1
|
Net: mprj/io_in[16] |Net: \la_oenb_mprj[52]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[52] = 1
| mgmt_core_wrapper/la_oenb[52] = 1
|
Net: mprj/io_in[7] |Net: \la_oenb_mprj[51]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[51] = 1
| mgmt_core_wrapper/la_oenb[51] = 1
|
Net: mprj/io_in[26] |Net: \la_oenb_mprj[50]
sky130_fd_sc_hd__buf_16/X = 1 | mgmt_protect/la_oenb_mprj[50] = 1
| mgmt_core_wrapper/la_oenb[50] = 1
|
Net: padframe/xresloop |Net: \la_oenb_mprj[49]
chip_io_alt/xresloop = 1 | mgmt_protect/la_oenb_mprj[49] = 1
| mgmt_core_wrapper/la_oenb[49] = 1
|
Net: padframe/xres_vss_loop |Net: \la_oenb_mprj[48]
chip_io_alt/xres_vss_loop = 1 | mgmt_protect/la_oenb_mprj[48] = 1
| mgmt_core_wrapper/la_oenb[48] = 1
|
Net: clock |Net: clock
chip_io_alt/clock = 1 | chip_io_alt/clock = 1
|
Net: flash_clk |Net: flash_clk
chip_io_alt/flash_clk = 1 | chip_io_alt/flash_clk = 1
|
Net: flash_csb |Net: flash_csb
chip_io_alt/flash_csb = 1 | chip_io_alt/flash_csb = 1
|
Net: flash_io0 |Net: flash_io0
chip_io_alt/flash_io0 = 1 | chip_io_alt/flash_io0 = 1
|
Net: flash_io1 |Net: flash_io1
chip_io_alt/flash_io1 = 1 | chip_io_alt/flash_io1 = 1
|
Net: gpio |Net: gpio
chip_io_alt/gpio = 1 | chip_io_alt/gpio = 1
|
Net: vccd |Net: vccd
chip_io_alt/vccd_pad = 1 | chip_io_alt/vccd_pad = 1
|
Net: vdda |Net: vdda
chip_io_alt/vdda_pad = 1 | chip_io_alt/vdda_pad = 1
|
Net: vddio |Net: vddio
chip_io_alt/vddio_pad = 1 | chip_io_alt/vddio_pad = 1
|
Net: vssa |Net: vssa
chip_io_alt/vssa_pad = 1 | chip_io_alt/vssa_pad = 1
|
Net: vssio |Net: vssio
chip_io_alt/vssio_pad = 1 | chip_io_alt/vssio_pad = 1
|
Net: vssio_2 |Net: vssio_2
chip_io_alt/vssio_pad2 = 1 | chip_io_alt/vssio_pad2 = 1
|
Net: mprj_io[0] |Net: mprj_io[0]
chip_io_alt/mprj_io[0] = 1 | chip_io_alt/mprj_io[0] = 1
|
Net: mprj/io_in_3v3[0] |Net: \la_oenb_mprj[34]
chip_io_alt/mprj_io_in_3v3[0] = 1 | mgmt_protect/la_oenb_mprj[34] = 1
| mgmt_core_wrapper/la_oenb[34] = 1
|
Net: mprj/gpio_analog[3] |Net: \la_oenb_mprj[33]
chip_io_alt/mprj_gpio_analog[3] = 1 | mgmt_protect/la_oenb_mprj[33] = 1
| mgmt_core_wrapper/la_oenb[33] = 1
|
Net: mprj/gpio_noesd[3] |Net: \la_oenb_mprj[32]
chip_io_alt/mprj_gpio_noesd[3] = 1 | mgmt_protect/la_oenb_mprj[32] = 1
| mgmt_core_wrapper/la_oenb[32] = 1
|
Net: mprj_io[10] |Net: mprj_io[10]
chip_io_alt/mprj_io[10] = 1 | chip_io_alt/mprj_io[10] = 1
|
Net: mprj/io_in_3v3[10] |Net: \la_oenb_mprj[30]
chip_io_alt/mprj_io_in_3v3[10] = 1 | mgmt_protect/la_oenb_mprj[30] = 1
| mgmt_core_wrapper/la_oenb[30] = 1
|
Net: mprj/gpio_analog[4] |Net: \la_oenb_mprj[29]
chip_io_alt/mprj_gpio_analog[4] = 1 | mgmt_protect/la_oenb_mprj[29] = 1
| mgmt_core_wrapper/la_oenb[29] = 1
|
Net: mprj/gpio_noesd[4] |Net: \la_oenb_mprj[28]
chip_io_alt/mprj_gpio_noesd[4] = 1 | mgmt_protect/la_oenb_mprj[28] = 1
| mgmt_core_wrapper/la_oenb[28] = 1
|
Net: mprj_io[11] |Net: mprj_io[11]
chip_io_alt/mprj_io[11] = 1 | chip_io_alt/mprj_io[11] = 1
|
Net: mprj/io_in_3v3[11] |Net: \la_oenb_mprj[26]
chip_io_alt/mprj_io_in_3v3[11] = 1 | mgmt_protect/la_oenb_mprj[26] = 1
| mgmt_core_wrapper/la_oenb[26] = 1
|
Net: mprj/gpio_analog[5] |Net: \la_oenb_mprj[25]
chip_io_alt/mprj_gpio_analog[5] = 1 | mgmt_protect/la_oenb_mprj[25] = 1
| mgmt_core_wrapper/la_oenb[25] = 1
|
Net: mprj/gpio_noesd[5] |Net: \la_oenb_mprj[24]
chip_io_alt/mprj_gpio_noesd[5] = 1 | mgmt_protect/la_oenb_mprj[24] = 1
| mgmt_core_wrapper/la_oenb[24] = 1
|
Net: mprj_io[12] |Net: mprj_io[12]
chip_io_alt/mprj_io[12] = 1 | chip_io_alt/mprj_io[12] = 1
|
Net: mprj/io_in_3v3[12] |Net: \la_oenb_mprj[22]
chip_io_alt/mprj_io_in_3v3[12] = 1 | mgmt_protect/la_oenb_mprj[22] = 1
| mgmt_core_wrapper/la_oenb[22] = 1
|
Net: mprj/gpio_analog[6] |Net: \la_oenb_mprj[21]
chip_io_alt/mprj_gpio_analog[6] = 1 | mgmt_protect/la_oenb_mprj[21] = 1
| mgmt_core_wrapper/la_oenb[21] = 1
|
Net: mprj/gpio_noesd[6] |Net: \la_oenb_mprj[20]
chip_io_alt/mprj_gpio_noesd[6] = 1 | mgmt_protect/la_oenb_mprj[20] = 1
| mgmt_core_wrapper/la_oenb[20] = 1
|
Net: mprj_io[13] |Net: mprj_io[13]
chip_io_alt/mprj_io[13] = 1 | chip_io_alt/mprj_io[13] = 1
|
Net: mprj/io_in_3v3[13] |Net: \la_oenb_mprj[18]
chip_io_alt/mprj_io_in_3v3[13] = 1 | mgmt_protect/la_oenb_mprj[18] = 1
| mgmt_core_wrapper/la_oenb[18] = 1
|
Net: mprj_io[1] |Net: mprj_io[1]
chip_io_alt/mprj_io[1] = 1 | chip_io_alt/mprj_io[1] = 1
|
Net: mprj/io_in_3v3[1] |Net: \la_oenb_mprj[16]
chip_io_alt/mprj_io_in_3v3[1] = 1 | mgmt_protect/la_oenb_mprj[16] = 1
| mgmt_core_wrapper/la_oenb[16] = 1
|
Net: mprj_io[2] |Net: mprj_io[2]
chip_io_alt/mprj_io[2] = 1 | chip_io_alt/mprj_io[2] = 1
|
Net: mprj/io_in_3v3[2] |Net: \la_oenb_mprj[14]
chip_io_alt/mprj_io_in_3v3[2] = 1 | mgmt_protect/la_oenb_mprj[14] = 1
| mgmt_core_wrapper/la_oenb[14] = 1
|
Net: mprj_io[3] |Net: mprj_io[3]
chip_io_alt/mprj_io[3] = 1 | chip_io_alt/mprj_io[3] = 1
|
Net: mprj/io_in_3v3[3] |Net: \la_oenb_mprj[12]
chip_io_alt/mprj_io_in_3v3[3] = 1 | mgmt_protect/la_oenb_mprj[12] = 1
| mgmt_core_wrapper/la_oenb[12] = 1
|
Net: mprj_io[4] |Net: mprj_io[4]
chip_io_alt/mprj_io[4] = 1 | chip_io_alt/mprj_io[4] = 1
|
Net: mprj/io_in_3v3[4] |Net: \la_oenb_mprj[10]
chip_io_alt/mprj_io_in_3v3[4] = 1 | mgmt_protect/la_oenb_mprj[10] = 1
| mgmt_core_wrapper/la_oenb[10] = 1
|
Net: mprj_io[5] |Net: mprj_io[5]
chip_io_alt/mprj_io[5] = 1 | chip_io_alt/mprj_io[5] = 1
|
Net: mprj/io_in_3v3[5] |Net: \la_oenb_mprj[8]
chip_io_alt/mprj_io_in_3v3[5] = 1 | mgmt_protect/la_oenb_mprj[8] = 1
| mgmt_core_wrapper/la_oenb[8] = 1
|
Net: mprj_io[6] |Net: mprj_io[6]
chip_io_alt/mprj_io[6] = 1 | chip_io_alt/mprj_io[6] = 1
|
Net: mprj/io_in_3v3[6] |Net: \la_oenb_mprj[6]
chip_io_alt/mprj_io_in_3v3[6] = 1 | mgmt_protect/la_oenb_mprj[6] = 1
| mgmt_core_wrapper/la_oenb[6] = 1
|
Net: mprj/gpio_analog[0] |Net: \la_oenb_mprj[5]
chip_io_alt/mprj_gpio_analog[0] = 1 | mgmt_protect/la_oenb_mprj[5] = 1
| mgmt_core_wrapper/la_oenb[5] = 1
|
Net: mprj/gpio_noesd[0] |Net: \la_oenb_mprj[4]
chip_io_alt/mprj_gpio_noesd[0] = 1 | mgmt_protect/la_oenb_mprj[4] = 1
| mgmt_core_wrapper/la_oenb[4] = 1
|
Net: mprj_io[7] |Net: mprj_io[7]
chip_io_alt/mprj_io[7] = 1 | chip_io_alt/mprj_io[7] = 1
|
Net: mprj/io_in_3v3[7] |Net: \la_oenb_mprj[2]
chip_io_alt/mprj_io_in_3v3[7] = 1 | mgmt_protect/la_oenb_mprj[2] = 1
| mgmt_core_wrapper/la_oenb[2] = 1
|
Net: mprj/gpio_analog[1] |Net: \la_oenb_mprj[1]
chip_io_alt/mprj_gpio_analog[1] = 1 | mgmt_protect/la_oenb_mprj[1] = 1
| mgmt_core_wrapper/la_oenb[1] = 1
|
Net: mprj/gpio_noesd[1] |Net: \la_oenb_mprj[0]
chip_io_alt/mprj_gpio_noesd[1] = 1 | mgmt_protect/la_oenb_mprj[0] = 1
| mgmt_core_wrapper/la_oenb[0] = 1
|
Net: mprj_io[8] |Net: mprj_io[8]
chip_io_alt/mprj_io[8] = 1 | chip_io_alt/mprj_io[8] = 1
|
Net: mprj/io_in_3v3[8] |Net: \mprj_adr_o_user[30]
chip_io_alt/mprj_io_in_3v3[8] = 1 | mgmt_protect/mprj_adr_o_user[30] = 1
| user_analog_project_wrapper/wbs_adr_i[30
|
Net: mprj/gpio_analog[2] |Net: \mprj_adr_o_user[29]
chip_io_alt/mprj_gpio_analog[2] = 1 | mgmt_protect/mprj_adr_o_user[29] = 1
| user_analog_project_wrapper/wbs_adr_i[29
|
Net: mprj/gpio_noesd[2] |Net: \mprj_adr_o_user[28]
chip_io_alt/mprj_gpio_noesd[2] = 1 | mgmt_protect/mprj_adr_o_user[28] = 1
| user_analog_project_wrapper/wbs_adr_i[28
|
Net: mprj_io[9] |Net: mprj_io[9]
chip_io_alt/mprj_io[9] = 1 | chip_io_alt/mprj_io[9] = 1
|
Net: mprj/io_in_3v3[9] |Net: \mprj_adr_o_user[26]
chip_io_alt/mprj_io_in_3v3[9] = 1 | mgmt_protect/mprj_adr_o_user[26] = 1
| user_analog_project_wrapper/wbs_adr_i[26
|
Net: mprj/gpio_analog[7] |Net: \mprj_adr_o_user[25]
chip_io_alt/mprj_gpio_analog[7] = 1 | mgmt_protect/mprj_adr_o_user[25] = 1
| user_analog_project_wrapper/wbs_adr_i[25
|
Net: mprj/gpio_noesd[7] |Net: \mprj_adr_o_user[24]
chip_io_alt/mprj_gpio_noesd[7] = 1 | mgmt_protect/mprj_adr_o_user[24] = 1
| user_analog_project_wrapper/wbs_adr_i[24
|
Net: mprj_io[25] |Net: mprj_io[25]
chip_io_alt/mprj_io[25] = 1 | chip_io_alt/mprj_io[25] = 1
|
Net: mprj/io_in_3v3[14] |Net: \mprj_adr_o_user[22]
chip_io_alt/mprj_io_in_3v3[14] = 1 | mgmt_protect/mprj_adr_o_user[22] = 1
| user_analog_project_wrapper/wbs_adr_i[22
|
Net: mprj/gpio_analog[17] |Net: \mprj_adr_o_user[21]
chip_io_alt/mprj_gpio_analog[17] = 1 | mgmt_protect/mprj_adr_o_user[21] = 1
| user_analog_project_wrapper/wbs_adr_i[21
|
Net: mprj/gpio_noesd[17] |Net: \mprj_adr_o_user[20]
chip_io_alt/mprj_gpio_noesd[17] = 1 | mgmt_protect/mprj_adr_o_user[20] = 1
| user_analog_project_wrapper/wbs_adr_i[20
|
Net: mprj_io[35] |Net: mprj_io[35]
chip_io_alt/mprj_io[35] = 1 | chip_io_alt/mprj_io[35] = 1
|
Net: mprj/io_in_3v3[24] |Net: \mprj_adr_o_user[18]
chip_io_alt/mprj_io_in_3v3[24] = 1 | mgmt_protect/mprj_adr_o_user[18] = 1
| user_analog_project_wrapper/wbs_adr_i[18
|
Net: mprj_io[36] |Net: mprj_io[36]
chip_io_alt/mprj_io[36] = 1 | chip_io_alt/mprj_io[36] = 1
|
Net: mprj/io_in_3v3[25] |Net: \mprj_adr_o_user[16]
chip_io_alt/mprj_io_in_3v3[25] = 1 | mgmt_protect/mprj_adr_o_user[16] = 1
| user_analog_project_wrapper/wbs_adr_i[16
|
Net: mprj_io[37] |Net: mprj_io[37]
chip_io_alt/mprj_io[37] = 1 | chip_io_alt/mprj_io[37] = 1
|
Net: mprj/io_in_3v3[26] |Net: \mprj_adr_o_user[14]
chip_io_alt/mprj_io_in_3v3[26] = 1 | mgmt_protect/mprj_adr_o_user[14] = 1
| user_analog_project_wrapper/wbs_adr_i[14
|
Net: mprj/gpio_analog[8] |Net: \mprj_adr_o_user[13]
chip_io_alt/mprj_gpio_analog[8] = 1 | mgmt_protect/mprj_adr_o_user[13] = 1
| user_analog_project_wrapper/wbs_adr_i[13
|
Net: mprj/gpio_noesd[8] |Net: \mprj_adr_o_user[12]
chip_io_alt/mprj_gpio_noesd[8] = 1 | mgmt_protect/mprj_adr_o_user[12] = 1
| user_analog_project_wrapper/wbs_adr_i[12
|
Net: mprj_io[26] |Net: mprj_io[26]
chip_io_alt/mprj_io[26] = 1 | chip_io_alt/mprj_io[26] = 1
|
Net: mprj/io_in_3v3[15] |Net: \mprj_adr_o_user[10]
chip_io_alt/mprj_io_in_3v3[15] = 1 | mgmt_protect/mprj_adr_o_user[10] = 1
| user_analog_project_wrapper/wbs_adr_i[10
|
Net: mprj/gpio_analog[9] |Net: \mprj_adr_o_user[9]
chip_io_alt/mprj_gpio_analog[9] = 1 | mgmt_protect/mprj_adr_o_user[9] = 1
| user_analog_project_wrapper/wbs_adr_i[9]
|
Net: mprj/gpio_noesd[9] |Net: \mprj_adr_o_user[8]
chip_io_alt/mprj_gpio_noesd[9] = 1 | mgmt_protect/mprj_adr_o_user[8] = 1
| user_analog_project_wrapper/wbs_adr_i[8]
|
Net: mprj_io[27] |Net: mprj_io[27]
chip_io_alt/mprj_io[27] = 1 | chip_io_alt/mprj_io[27] = 1
|
Net: mprj/io_in_3v3[16] |Net: \mprj_adr_o_user[6]
chip_io_alt/mprj_io_in_3v3[16] = 1 | mgmt_protect/mprj_adr_o_user[6] = 1
| user_analog_project_wrapper/wbs_adr_i[6]
|
Net: mprj/gpio_analog[10] |Net: \mprj_adr_o_user[5]
chip_io_alt/mprj_gpio_analog[10] = 1 | mgmt_protect/mprj_adr_o_user[5] = 1
| user_analog_project_wrapper/wbs_adr_i[5]
|
Net: mprj/gpio_noesd[10] |Net: \mprj_adr_o_user[4]
chip_io_alt/mprj_gpio_noesd[10] = 1 | mgmt_protect/mprj_adr_o_user[4] = 1
| user_analog_project_wrapper/wbs_adr_i[4]
|
Net: mprj_io[28] |Net: mprj_io[28]
chip_io_alt/mprj_io[28] = 1 | chip_io_alt/mprj_io[28] = 1
|
Net: mprj/io_in_3v3[17] |Net: \mprj_adr_o_user[2]
chip_io_alt/mprj_io_in_3v3[17] = 1 | mgmt_protect/mprj_adr_o_user[2] = 1
| user_analog_project_wrapper/wbs_adr_i[2]
|
Net: mprj/gpio_analog[11] |Net: \mprj_adr_o_user[1]
chip_io_alt/mprj_gpio_analog[11] = 1 | mgmt_protect/mprj_adr_o_user[1] = 1
| user_analog_project_wrapper/wbs_adr_i[1]
|
Net: mprj/gpio_noesd[11] |Net: \mprj_adr_o_user[0]
chip_io_alt/mprj_gpio_noesd[11] = 1 | mgmt_protect/mprj_adr_o_user[0] = 1
| user_analog_project_wrapper/wbs_adr_i[0]
|
Net: mprj_io[29] |Net: mprj_io[29]
chip_io_alt/mprj_io[29] = 1 | chip_io_alt/mprj_io[29] = 1
|
Net: mprj/io_in_3v3[18] |Net: \mprj_dat_i_core[30]
chip_io_alt/mprj_io_in_3v3[18] = 1 | mgmt_protect/mprj_dat_i_core[30] = 1
| mgmt_core_wrapper/mprj_dat_i[30] = 1
|
Net: mprj/gpio_analog[12] |Net: \mprj_dat_i_core[29]
chip_io_alt/mprj_gpio_analog[12] = 1 | mgmt_protect/mprj_dat_i_core[29] = 1
| mgmt_core_wrapper/mprj_dat_i[29] = 1
|
Net: mprj/gpio_noesd[12] |Net: \mprj_dat_i_core[28]
chip_io_alt/mprj_gpio_noesd[12] = 1 | mgmt_protect/mprj_dat_i_core[28] = 1
| mgmt_core_wrapper/mprj_dat_i[28] = 1
|
Net: mprj_io[30] |Net: mprj_io[30]
chip_io_alt/mprj_io[30] = 1 | chip_io_alt/mprj_io[30] = 1
|
Net: mprj/io_in_3v3[19] |Net: \mprj_dat_i_core[26]
chip_io_alt/mprj_io_in_3v3[19] = 1 | mgmt_protect/mprj_dat_i_core[26] = 1
| mgmt_core_wrapper/mprj_dat_i[26] = 1
|
Net: mprj/gpio_analog[13] |Net: \mprj_dat_i_core[25]
chip_io_alt/mprj_gpio_analog[13] = 1 | mgmt_protect/mprj_dat_i_core[25] = 1
| mgmt_core_wrapper/mprj_dat_i[25] = 1
|
Net: mprj/gpio_noesd[13] |Net: \mprj_dat_i_core[24]
chip_io_alt/mprj_gpio_noesd[13] = 1 | mgmt_protect/mprj_dat_i_core[24] = 1
| mgmt_core_wrapper/mprj_dat_i[24] = 1
|
Net: mprj_io[31] |Net: mprj_io[31]
chip_io_alt/mprj_io[31] = 1 | chip_io_alt/mprj_io[31] = 1
|
Net: mprj/io_in_3v3[20] |Net: \mprj_dat_i_core[22]
chip_io_alt/mprj_io_in_3v3[20] = 1 | mgmt_protect/mprj_dat_i_core[22] = 1
| mgmt_core_wrapper/mprj_dat_i[22] = 1
|
Net: mprj/gpio_analog[14] |Net: \mprj_dat_i_core[21]
chip_io_alt/mprj_gpio_analog[14] = 1 | mgmt_protect/mprj_dat_i_core[21] = 1
| mgmt_core_wrapper/mprj_dat_i[21] = 1
|
Net: mprj/gpio_noesd[14] |Net: \mprj_dat_i_core[20]
chip_io_alt/mprj_gpio_noesd[14] = 1 | mgmt_protect/mprj_dat_i_core[20] = 1
| mgmt_core_wrapper/mprj_dat_i[20] = 1
|
Net: mprj_io[32] |Net: mprj_io[32]
chip_io_alt/mprj_io[32] = 1 | chip_io_alt/mprj_io[32] = 1
|
Net: mprj/io_in_3v3[21] |Net: \mprj_dat_i_core[18]
chip_io_alt/mprj_io_in_3v3[21] = 1 | mgmt_protect/mprj_dat_i_core[18] = 1
| mgmt_core_wrapper/mprj_dat_i[18] = 1
|
Net: mprj/gpio_analog[15] |Net: \mprj_dat_i_core[17]
chip_io_alt/mprj_gpio_analog[15] = 1 | mgmt_protect/mprj_dat_i_core[17] = 1
| mgmt_core_wrapper/mprj_dat_i[17] = 1
|
Net: mprj/gpio_noesd[15] |Net: \mprj_dat_i_core[16]
chip_io_alt/mprj_gpio_noesd[15] = 1 | mgmt_protect/mprj_dat_i_core[16] = 1
| mgmt_core_wrapper/mprj_dat_i[16] = 1
|
Net: mprj_io[33] |Net: mprj_io[33]
chip_io_alt/mprj_io[33] = 1 | chip_io_alt/mprj_io[33] = 1
|
Net: mprj/io_in_3v3[22] |Net: \mprj_dat_i_core[14]
chip_io_alt/mprj_io_in_3v3[22] = 1 | mgmt_protect/mprj_dat_i_core[14] = 1
| mgmt_core_wrapper/mprj_dat_i[14] = 1
|
Net: mprj/gpio_analog[16] |Net: \mprj_dat_i_core[13]
chip_io_alt/mprj_gpio_analog[16] = 1 | mgmt_protect/mprj_dat_i_core[13] = 1
| mgmt_core_wrapper/mprj_dat_i[13] = 1
|
Net: mprj/gpio_noesd[16] |Net: \mprj_dat_i_core[12]
chip_io_alt/mprj_gpio_noesd[16] = 1 | mgmt_protect/mprj_dat_i_core[12] = 1
| mgmt_core_wrapper/mprj_dat_i[12] = 1
|
Net: mprj_io[34] |Net: mprj_io[34]
chip_io_alt/mprj_io[34] = 1 | chip_io_alt/mprj_io[34] = 1
|
Net: mprj/io_in_3v3[23] |Net: \mprj_dat_i_core[10]
chip_io_alt/mprj_io_in_3v3[23] = 1 | mgmt_protect/mprj_dat_i_core[10] = 1
| mgmt_core_wrapper/mprj_dat_i[10] = 1
|
Net: resetb |Net: resetb
chip_io_alt/resetb = 1 | chip_io_alt/resetb = 1
|
Net: mprj_io[15] |Net: mprj_io[15]
chip_io_alt/mprj_io[15] = 1 | chip_io_alt/mprj_io[15] = 1
|
Net: mprj/io_analog[2] |Net: \mprj_dat_i_core[7]
chip_io_alt/mprj_analog[2] = 1 | mgmt_protect/mprj_dat_i_core[7] = 1
| mgmt_core_wrapper/mprj_dat_i[7] = 1
|
Net: mprj_io[16] |Net: mprj_io[16]
chip_io_alt/mprj_io[16] = 1 | chip_io_alt/mprj_io[16] = 1
|
Net: mprj_io[17] |Net: mprj_io[17]
chip_io_alt/mprj_io[17] = 1 | chip_io_alt/mprj_io[17] = 1
|
Net: mprj/io_clamp_high[0] |Net: \mprj_dat_i_core[4]
chip_io_alt/mprj_clamp_high[0] = 1 | mgmt_protect/mprj_dat_i_core[4] = 1
| mgmt_core_wrapper/mprj_dat_i[4] = 1
|
Net: mprj_io[18] |Net: mprj_io[18]
chip_io_alt/mprj_io[18] = 1 | chip_io_alt/mprj_io[18] = 1
|
Net: vccd1 |Net: vccd1
chip_io_alt/vccd1_pad = 1 | chip_io_alt/vccd1_pad = 1
|
Net: vdda1 |Net: vdda1
chip_io_alt/vdda1_pad = 1 | chip_io_alt/vdda1_pad = 1
|
Net: vdda1_2 |Net: vdda1_2
chip_io_alt/vdda1_pad2 = 1 | chip_io_alt/vdda1_pad2 = 1
|
Net: vssd1 |Net: vssd1
chip_io_alt/vssd1_pad = 1 | chip_io_alt/vssd1_pad = 1
|
Net: mprj/io_analog[9] |Net: \mprj_dat_i_user[30]
chip_io_alt/mprj_analog[9] = 1 | mgmt_protect/mprj_dat_i_user[30] = 1
| user_analog_project_wrapper/wbs_dat_o[30
|
Net: mprj/io_analog[10] |Net: \mprj_dat_i_user[29]
chip_io_alt/mprj_analog[10] = 1 | mgmt_protect/mprj_dat_i_user[29] = 1
| user_analog_project_wrapper/wbs_dat_o[29
|
Net: mprj_io[24] |Net: mprj_io[24]
chip_io_alt/mprj_io[24] = 1 | chip_io_alt/mprj_io[24] = 1
|
Net: mprj/io_analog[5] |Net: \mprj_dat_i_user[27]
chip_io_alt/mprj_analog[5] = 1 | mgmt_protect/mprj_dat_i_user[27] = 1
| user_analog_project_wrapper/wbs_dat_o[27
|
Net: mprj/io_clamp_high[1] |Net: \mprj_dat_i_user[26]
chip_io_alt/mprj_clamp_high[1] = 1 | mgmt_protect/mprj_dat_i_user[26] = 1
| user_analog_project_wrapper/wbs_dat_o[26
|
Net: mprj/io_clamp_low[1] |Net: \mprj_dat_i_user[25]
chip_io_alt/mprj_clamp_low[1] = 1 | mgmt_protect/mprj_dat_i_user[25] = 1
| user_analog_project_wrapper/wbs_dat_o[25
|
Net: mprj_io[19] |Net: mprj_io[19]
chip_io_alt/mprj_io[19] = 1 | chip_io_alt/mprj_io[19] = 1
|
Net: vccd2 |Net: vccd2
chip_io_alt/vccd2_pad = 1 | chip_io_alt/vccd2_pad = 1
|
Net: vdda2 |Net: vdda2
chip_io_alt/vdda2_pad = 1 | chip_io_alt/vdda2_pad = 1
|
Net: vssa2 |Net: vssa2
chip_io_alt/vssa2_pad = 1 | chip_io_alt/vssa2_pad = 1
|
Net: vssd2 |Net: vssd2
chip_io_alt/vssd2_pad = 1 | chip_io_alt/vssd2_pad = 1
|
Net: w_694469_865869# |Net: \mprj_dat_i_user[19]
chip_io_alt/w_694469_865869# = 1 | mgmt_protect/mprj_dat_i_user[19] = 1
| user_analog_project_wrapper/wbs_dat_o[19
|
Net: w_23367_407274# |Net: \mprj_dat_i_user[18]
chip_io_alt/w_23367_407274# = 1 | mgmt_protect/mprj_dat_i_user[18] = 1
| user_analog_project_wrapper/wbs_dat_o[18
|
Net: w_694469_100152# |Net: \mprj_dat_i_user[17]
chip_io_alt/w_694469_100152# = 1 | mgmt_protect/mprj_dat_i_user[17] = 1
| user_analog_project_wrapper/wbs_dat_o[17
|
Net: w_23367_534874# |Net: \mprj_dat_i_user[16]
chip_io_alt/w_23367_534874# = 1 | mgmt_protect/mprj_dat_i_user[16] = 1
| user_analog_project_wrapper/wbs_dat_o[16
|
Net: w_404752_21253# |Net: \mprj_dat_i_user[15]
chip_io_alt/w_404752_21253# = 1 | mgmt_protect/mprj_dat_i_user[15] = 1
| user_analog_project_wrapper/wbs_dat_o[15
|
Net: w_459552_23367# |Net: \mprj_dat_i_user[14]
chip_io_alt/w_459552_23367# = 1 | mgmt_protect/mprj_dat_i_user[14] = 1
| user_analog_project_wrapper/wbs_dat_o[14
|
Net: w_23367_280765# |Net: \mprj_dat_i_user[13]
chip_io_alt/w_23367_280765# = 1 | mgmt_protect/mprj_dat_i_user[13] = 1
| user_analog_project_wrapper/wbs_dat_o[13
|
Net: w_692253_776670# |Net: \mprj_dat_i_user[12]
chip_io_alt/w_692253_776670# = 1 | mgmt_protect/mprj_dat_i_user[12] = 1
| user_analog_project_wrapper/wbs_dat_o[12
|
Net: w_23367_710765# |Net: \mprj_dat_i_user[11]
chip_io_alt/w_23367_710765# = 1 | mgmt_protect/mprj_dat_i_user[11] = 1
| user_analog_project_wrapper/wbs_dat_o[11
|
Net: w_78010_1007543# |Net: \mprj_dat_i_user[10]
chip_io_alt/w_78010_1007543# = 1 | mgmt_protect/mprj_dat_i_user[10] = 1
| user_analog_project_wrapper/wbs_dat_o[10
|
Net: w_692355_547952# |Net: \mprj_dat_i_user[9]
chip_io_alt/w_692355_547952# = 1 | mgmt_protect/mprj_dat_i_user[9] = 1
| user_analog_project_wrapper/wbs_dat_o[9]
|
Net: w_23367_537965# |Net: \mprj_dat_i_user[8]
chip_io_alt/w_23367_537965# = 1 | mgmt_protect/mprj_dat_i_user[8] = 1
| user_analog_project_wrapper/wbs_dat_o[8]
|
Net: w_21151_364074# |Net: \mprj_dat_i_user[7]
chip_io_alt/w_21151_364074# = 1 | mgmt_protect/mprj_dat_i_user[7] = 1
| user_analog_project_wrapper/wbs_dat_o[7]
|
Net: w_459552_21253# |Net: \mprj_dat_i_user[6]
chip_io_alt/w_459552_21253# = 1 | mgmt_protect/mprj_dat_i_user[6] = 1
| user_analog_project_wrapper/wbs_dat_o[6]
|
Net: w_694469_145352# |Net: \mprj_dat_i_user[5]
chip_io_alt/w_694469_145352# = 1 | mgmt_protect/mprj_dat_i_user[5] = 1
| user_analog_project_wrapper/wbs_dat_o[5]
|
Net: w_692355_593152# |Net: \mprj_dat_i_user[4]
chip_io_alt/w_692355_593152# = 1 | mgmt_protect/mprj_dat_i_user[4] = 1
| user_analog_project_wrapper/wbs_dat_o[4]
|
Net: w_694469_190352# |Net: \mprj_dat_i_user[3]
chip_io_alt/w_694469_190352# = 1 | mgmt_protect/mprj_dat_i_user[3] = 1
| user_analog_project_wrapper/wbs_dat_o[3]
|
Net: w_349952_23367# |Net: \mprj_dat_i_user[2]
chip_io_alt/w_349952_23367# = 1 | mgmt_protect/mprj_dat_i_user[2] = 1
| user_analog_project_wrapper/wbs_dat_o[2]
|
Net: w_692355_325552# |Net: \mprj_dat_i_user[1]
chip_io_alt/w_692355_325552# = 1 | mgmt_protect/mprj_dat_i_user[1] = 1
| user_analog_project_wrapper/wbs_dat_o[1]
|
Net: w_189869_23367# |Net: \mprj_dat_i_user[0]
chip_io_alt/w_189869_23367# = 1 | mgmt_protect/mprj_dat_i_user[0] = 1
| user_analog_project_wrapper/wbs_dat_o[0]
|
Net: w_694469_235552# |Net: \mprj_dat_o_user[31]
chip_io_alt/w_694469_235552# = 1 | mgmt_protect/mprj_dat_o_user[31] = 1
| user_analog_project_wrapper/wbs_dat_i[31
|
Net: w_21151_794074# |Net: \mprj_dat_o_user[30]
chip_io_alt/w_21151_794074# = 1 | mgmt_protect/mprj_dat_o_user[30] = 1
| user_analog_project_wrapper/wbs_dat_i[30
|
Net: w_692355_683352# |Net: \mprj_dat_o_user[29]
chip_io_alt/w_692355_683352# = 1 | mgmt_protect/mprj_dat_o_user[29] = 1
| user_analog_project_wrapper/wbs_dat_i[29
|
Net: w_21253_194365# |Net: \mprj_dat_o_user[28]
chip_io_alt/w_21253_194365# = 1 | mgmt_protect/mprj_dat_o_user[28] = 1
| user_analog_project_wrapper/wbs_dat_i[28
|
Net: w_694469_280552# |Net: \mprj_dat_o_user[27]
chip_io_alt/w_694469_280552# = 1 | mgmt_protect/mprj_dat_o_user[27] = 1
| user_analog_project_wrapper/wbs_dat_i[27
|
Net: w_21253_624365# |Net: \mprj_dat_o_user[26]
chip_io_alt/w_21253_624365# = 1 | mgmt_protect/mprj_dat_o_user[26] = 1
| user_analog_project_wrapper/wbs_dat_i[26
|
Net: w_295152_23367# |Net: \mprj_dat_o_user[25]
chip_io_alt/w_295152_23367# = 1 | mgmt_protect/mprj_dat_o_user[25] = 1
| user_analog_project_wrapper/wbs_dat_i[25
|
Net: w_349952_21253# |Net: \mprj_dat_o_user[24]
chip_io_alt/w_349952_21253# = 1 | mgmt_protect/mprj_dat_o_user[24] = 1
| user_analog_project_wrapper/wbs_dat_i[24
|
Net: w_23367_578074# |Net: \mprj_dat_o_user[23]
chip_io_alt/w_23367_578074# = 1 | mgmt_protect/mprj_dat_o_user[23] = 1
| user_analog_project_wrapper/wbs_dat_i[23
|
Net: w_692253_551270# |Net: \mprj_dat_o_user[22]
chip_io_alt/w_692253_551270# = 1 | mgmt_protect/mprj_dat_o_user[22] = 1
| user_analog_project_wrapper/wbs_dat_i[22
|
Net: w_694469_370752# |Net: \mprj_dat_o_user[21]
chip_io_alt/w_694469_370752# = 1 | mgmt_protect/mprj_dat_o_user[21] = 1
| user_analog_project_wrapper/wbs_dat_i[21
|
Net: w_189869_21253# |Net: \mprj_dat_o_user[20]
chip_io_alt/w_189869_21253# = 1 | mgmt_protect/mprj_dat_o_user[20] = 1
| user_analog_project_wrapper/wbs_dat_i[20
|
Net: w_21151_277674# |Net: \mprj_dat_o_user[19]
chip_io_alt/w_21151_277674# = 1 | mgmt_protect/mprj_dat_o_user[19] = 1
| user_analog_project_wrapper/wbs_dat_i[19
|
Net: mprj_io[21] |Net: mprj_io[21]
chip_io_alt/mprj_io[21] = 1 | chip_io_alt/mprj_io[21] = 1
|
Net: w_692253_641470# |Net: \mprj_dat_o_user[17]
chip_io_alt/w_692253_641470# = 1 | mgmt_protect/mprj_dat_o_user[17] = 1
| user_analog_project_wrapper/wbs_dat_i[17
|
Net: w_295152_21253# |Net: \mprj_dat_o_user[16]
chip_io_alt/w_295152_21253# = 1 | mgmt_protect/mprj_dat_o_user[16] = 1
| user_analog_project_wrapper/wbs_dat_i[16
|
Net: w_21151_707674# |Net: \mprj_dat_o_user[15]
chip_io_alt/w_21151_707674# = 1 | mgmt_protect/mprj_dat_o_user[15] = 1
| user_analog_project_wrapper/wbs_dat_i[15
|
Net: w_23367_234474# |Net: \mprj_dat_o_user[14]
chip_io_alt/w_23367_234474# = 1 | mgmt_protect/mprj_dat_o_user[14] = 1
| user_analog_project_wrapper/wbs_dat_i[14
|
Net: w_692355_100152# |Net: \mprj_dat_o_user[13]
chip_io_alt/w_692355_100152# = 1 | mgmt_protect/mprj_dat_o_user[13] = 1
| user_analog_project_wrapper/wbs_dat_i[13
|
Net: w_694469_776669# |Net: \mprj_dat_o_user[12]
chip_io_alt/w_694469_776669# = 1 | mgmt_protect/mprj_dat_o_user[12] = 1
| user_analog_project_wrapper/wbs_dat_i[12
|
Net: w_692253_596470# |Net: \mprj_dat_o_user[11]
chip_io_alt/w_692253_596470# = 1 | mgmt_protect/mprj_dat_o_user[11] = 1
| user_analog_project_wrapper/wbs_dat_i[11
|
Net: w_692253_731670# |Net: \mprj_dat_o_user[10]
chip_io_alt/w_692253_731670# = 1 | mgmt_protect/mprj_dat_o_user[10] = 1
| user_analog_project_wrapper/wbs_dat_i[10
|
Net: w_21253_280765# |Net: \mprj_dat_o_user[9]
chip_io_alt/w_21253_280765# = 1 | mgmt_protect/mprj_dat_o_user[9] = 1
| user_analog_project_wrapper/wbs_dat_i[9]
|
Net: w_692253_328870# |Net: \mprj_dat_o_user[8]
chip_io_alt/w_692253_328870# = 1 | mgmt_protect/mprj_dat_o_user[8] = 1
| user_analog_project_wrapper/wbs_dat_i[8]
|
Net: w_23367_410365# |Net: \mprj_dat_o_user[7]
chip_io_alt/w_23367_410365# = 1 | mgmt_protect/mprj_dat_o_user[7] = 1
| user_analog_project_wrapper/wbs_dat_i[7]
|
Net: w_21253_710765# |Net: \mprj_dat_o_user[6]
chip_io_alt/w_21253_710765# = 1 | mgmt_protect/mprj_dat_o_user[6] = 1
| user_analog_project_wrapper/wbs_dat_i[6]
|
Net: w_462869_23367# |Net: \mprj_dat_o_user[5]
chip_io_alt/w_462869_23367# = 1 | mgmt_protect/mprj_dat_o_user[5] = 1
| user_analog_project_wrapper/wbs_dat_i[5]
|
Net: w_23367_237565# |Net: \mprj_dat_o_user[4]
chip_io_alt/w_23367_237565# = 1 | mgmt_protect/mprj_dat_o_user[4] = 1
| user_analog_project_wrapper/wbs_dat_i[4]
|
Net: w_21253_537965# |Net: \mprj_dat_o_user[3]
chip_io_alt/w_21253_537965# = 1 | mgmt_protect/mprj_dat_o_user[3] = 1
| user_analog_project_wrapper/wbs_dat_i[3]
|
Net: w_23367_664474# |Net: \mprj_dat_o_user[2]
chip_io_alt/w_23367_664474# = 1 | mgmt_protect/mprj_dat_o_user[2] = 1
| user_analog_project_wrapper/wbs_dat_i[2]
|
Net: w_692253_686670# |Net: \mprj_dat_o_user[1]
chip_io_alt/w_692253_686670# = 1 | mgmt_protect/mprj_dat_o_user[1] = 1
| user_analog_project_wrapper/wbs_dat_i[1]
|
Net: w_21151_191274# |Net: \mprj_dat_o_user[0]
chip_io_alt/w_21151_191274# = 1 | mgmt_protect/mprj_dat_o_user[0] = 1
| user_analog_project_wrapper/wbs_dat_i[0]
|
Net: w_692253_374070# |Net: \mprj_sel_o_user[3]
chip_io_alt/w_692253_374070# = 1 | mgmt_protect/mprj_sel_o_user[3] = 1
| user_analog_project_wrapper/wbs_sel_i[3]
|
Net: mprj/io_analog[6] |Net: \mprj_sel_o_user[2]
chip_io_alt/mprj_analog[6] = 1 | mgmt_protect/mprj_sel_o_user[2] = 1
| user_analog_project_wrapper/wbs_sel_i[2]
|
Net: w_692355_145352# |Net: \mprj_sel_o_user[1]
chip_io_alt/w_692355_145352# = 1 | mgmt_protect/mprj_sel_o_user[1] = 1
| user_analog_project_wrapper/wbs_sel_i[1]
|
Net: w_21151_621274# |Net: \mprj_sel_o_user[0]
chip_io_alt/w_21151_621274# = 1 | mgmt_protect/mprj_sel_o_user[0] = 1
| user_analog_project_wrapper/wbs_sel_i[0]
|
Net: w_692355_190352# |Net: \user_irq[2]
chip_io_alt/w_692355_190352# = 1 | mgmt_protect/user_irq[2] = 1
| mgmt_core_wrapper/irq[2] = 1
|
Net: w_694469_862552# |Net: \user_irq[1]
chip_io_alt/w_694469_862552# = 1 | mgmt_protect/user_irq[1] = 1
| mgmt_core_wrapper/irq[1] = 1
|
Net: w_687543_952480# |Net: \user_irq[0]
chip_io_alt/w_687543_952480# = 1 | mgmt_protect/user_irq[0] = 1
| mgmt_core_wrapper/irq[0] = 1
|
Net: w_180810_1007543# |Net: \user_irq_core[2]
chip_io_alt/w_180810_1007543# = 1 | mgmt_protect/user_irq_core[2] = 1
| user_analog_project_wrapper/user_irq[2]
|
Net: w_462869_21253# |Net: \user_irq_core[1]
chip_io_alt/w_462869_21253# = 1 | mgmt_protect/user_irq_core[1] = 1
| user_analog_project_wrapper/user_irq[1]
|
Net: w_23367_667565# |Net: \user_irq_core[0]
chip_io_alt/w_23367_667565# = 1 | mgmt_protect/user_irq_core[0] = 1
| user_analog_project_wrapper/user_irq[0]
|
Net: w_692355_235552# |Net: \user_irq_ena[2]
chip_io_alt/w_692355_235552# = 1 | mgmt_protect/user_irq_ena[2] = 1
| mgmt_core_wrapper/user_irq_ena[2] = 1
|
Net: w_694469_551269# |Net: \user_irq_ena[1]
chip_io_alt/w_694469_551269# = 1 | mgmt_protect/user_irq_ena[1] = 1
| mgmt_core_wrapper/user_irq_ena[1] = 1
|
Net: w_23367_320874# |Net: \user_irq_ena[0]
chip_io_alt/w_23367_320874# = 1 | mgmt_protect/user_irq_ena[0] = 1
| mgmt_core_wrapper/user_irq_ena[0] = 1
|
Net: w_692355_280552# |Net: \user_gpio_analog[17]
chip_io_alt/w_692355_280552# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[17] = 1
|
Net: mprj/io_analog[7] |Net: \user_gpio_analog[16]
chip_io_alt/mprj_analog[7] = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[16] = 1
|
Net: w_692253_103470# |Net: \user_gpio_analog[15]
chip_io_alt/w_692253_103470# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[15] = 1
|
Net: w_694469_641469# |Net: \user_gpio_analog[14]
chip_io_alt/w_694469_641469# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[14] = 1
|
Net: w_129410_1007543# |Net: \user_gpio_analog[13]
chip_io_alt/w_129410_1007543# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[13] = 1
|
Net: w_692355_370752# |Net: \user_gpio_analog[12]
chip_io_alt/w_692355_370752# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[12] = 1
|
Net: w_23367_323965# |Net: \user_gpio_analog[11]
chip_io_alt/w_23367_323965# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[11] = 1
|
Net: w_23367_750874# |Net: \user_gpio_analog[10]
chip_io_alt/w_23367_750874# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[10] = 1
|
Net: w_694469_596469# |Net: \user_gpio_analog[9]
chip_io_alt/w_694469_596469# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[9] = 1
|
Net: mprj_io[20] |Net: mprj_io[20]
chip_io_alt/mprj_io[20] = 1 | chip_io_alt/mprj_io[20] = 1
|
Net: mprj_io[22] |Net: mprj_io[22]
chip_io_alt/mprj_io[22] = 1 | chip_io_alt/mprj_io[22] = 1
|
Net: w_23367_581165# |Net: \user_gpio_analog[6]
chip_io_alt/w_23367_581165# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[6] = 1
|
Net: w_694469_731669# |Net: \user_gpio_analog[5]
chip_io_alt/w_694469_731669# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[5] = 1
|
Net: w_526010_1007543# |Net: \user_gpio_analog[4]
chip_io_alt/w_526010_1007543# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[4] = 1
|
Net: w_21151_407274# |Net: \user_gpio_analog[3]
chip_io_alt/w_21151_407274# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[3] = 1
|
Net: w_186552_23367# |Net: \user_gpio_analog[2]
chip_io_alt/w_186552_23367# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[2] = 1
|
Net: w_517669_23367# |Net: \user_gpio_analog[1]
chip_io_alt/w_517669_23367# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[1] = 1
|
Net: w_21151_534874# |Net: \user_gpio_analog[0]
chip_io_alt/w_21151_534874# = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[0] = 1
|
Net: w_694469_328869# |Net: \user_gpio_noesd[17]
chip_io_alt/w_694469_328869# = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[17] = 1
|
Net: mprj/io_analog[3] |Net: \user_gpio_noesd[16]
chip_io_alt/mprj_analog[3] = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[16] = 1
|
Net: mprj/io_clamp_low[0] |Net: \user_gpio_noesd[15]
chip_io_alt/mprj_clamp_low[0] = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[15] = 1
|
Net: w_692253_148670# |Net: \user_gpio_noesd[14]
chip_io_alt/w_692253_148670# = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[14] = 1
|
Net: w_23367_753965# |Net: \user_gpio_noesd[13]
chip_io_alt/w_23367_753965# = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[13] = 1
|
Net: w_694469_686669# |Net: \user_gpio_noesd[12]
chip_io_alt/w_694469_686669# = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[12] = 1
|
Net: w_692253_193670# |Net: \user_gpio_noesd[11]
chip_io_alt/w_692253_193670# = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[11] = 1
|
Net: w_694469_374069# |Net: \user_gpio_noesd[10]
chip_io_alt/w_694469_374069# = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[10] = 1
|
Net: w_21253_410365# |Net: \user_gpio_noesd[9]
chip_io_alt/w_21253_410365# = 1 | user_analog_project_wrapper/gpio_noesd[9
| chip_io_alt/mprj_gpio_noesd[9] = 1
|
Net: w_694469_638152# |Net: \user_gpio_noesd[8]
chip_io_alt/w_694469_638152# = 1 | user_analog_project_wrapper/gpio_noesd[8
| chip_io_alt/mprj_gpio_noesd[8] = 1
|
Net: w_186552_21253# |Net: \user_gpio_noesd[7]
chip_io_alt/w_186552_21253# = 1 | user_analog_project_wrapper/gpio_noesd[7
| chip_io_alt/mprj_gpio_noesd[7] = 1
|
Net: w_517669_21253# |Net: \user_gpio_noesd[6]
chip_io_alt/w_517669_21253# = 1 | user_analog_project_wrapper/gpio_noesd[6
| chip_io_alt/mprj_gpio_noesd[6] = 1
|
Net: mprj/io_clamp_high[2] |Net: \user_gpio_noesd[5]
chip_io_alt/mprj_clamp_high[2] = 1 | user_analog_project_wrapper/gpio_noesd[5
| chip_io_alt/mprj_gpio_noesd[5] = 1
|
Net: w_21253_237565# |Net: \user_gpio_noesd[4]
chip_io_alt/w_21253_237565# = 1 | user_analog_project_wrapper/gpio_noesd[4
| chip_io_alt/mprj_gpio_noesd[4] = 1
|
Net: w_692253_238870# |Net: \user_gpio_noesd[3]
chip_io_alt/w_692253_238870# = 1 | user_analog_project_wrapper/gpio_noesd[3
| chip_io_alt/mprj_gpio_noesd[3] = 1
|
Net: w_23367_364074# |Net: \user_gpio_noesd[2]
chip_io_alt/w_23367_364074# = 1 | user_analog_project_wrapper/gpio_noesd[2
| chip_io_alt/mprj_gpio_noesd[2] = 1
|
Net: w_692253_283870# |Net: \user_gpio_noesd[1]
chip_io_alt/w_692253_283870# = 1 | user_analog_project_wrapper/gpio_noesd[1
| chip_io_alt/mprj_gpio_noesd[1] = 1
|
Net: w_474610_1007543# |Net: \user_gpio_noesd[0]
chip_io_alt/w_474610_1007543# = 1 | user_analog_project_wrapper/gpio_noesd[0
| chip_io_alt/mprj_gpio_noesd[0] = 1
|
Net: w_694469_728352# |Net: \user_analog[10]
chip_io_alt/w_694469_728352# = 1 | user_analog_project_wrapper/io_analog[10
| chip_io_alt/mprj_analog[10] = 1
|
Net: w_627810_1007543# |Net: \user_analog[9]
chip_io_alt/w_627810_1007543# = 1 | user_analog_project_wrapper/io_analog[9]
| chip_io_alt/mprj_analog[9] = 1
|
Net: w_692355_862552# |Net: \user_analog[8]
chip_io_alt/w_692355_862552# = 1 | user_analog_project_wrapper/io_analog[8]
| chip_io_alt/mprj_analog[8] = 1
|
Net: mprj/io_clamp_low[2] |Net: \user_analog[7]
chip_io_alt/mprj_clamp_low[2] = 1 | user_analog_project_wrapper/io_analog[7]
| chip_io_alt/mprj_analog[7] = 1
|
Net: w_694469_773352# |Net: \user_analog[6]
chip_io_alt/w_694469_773352# = 1 | user_analog_project_wrapper/io_analog[6]
| chip_io_alt/mprj_analog[6] = 1
|
Net: w_23367_367165# |Net: \user_analog[5]
chip_io_alt/w_23367_367165# = 1 | user_analog_project_wrapper/io_analog[5]
| chip_io_alt/mprj_analog[5] = 1
|
Net: w_21253_667565# |Net: \user_analog[4]
chip_io_alt/w_21253_667565# = 1 | user_analog_project_wrapper/io_analog[4]
| chip_io_alt/mprj_analog[4] = 1
|
Net: w_23367_794074# |Net: \user_analog[3]
chip_io_alt/w_23367_794074# = 1 | user_analog_project_wrapper/io_analog[3]
| chip_io_alt/mprj_analog[3] = 1
|
Net: w_694469_103469# |Net: \user_analog[2]
chip_io_alt/w_694469_103469# = 1 | user_analog_project_wrapper/io_analog[2]
| chip_io_alt/mprj_analog[2] = 1
|
Net: w_353269_23367# |Net: \user_analog[1]
chip_io_alt/w_353269_23367# = 1 | user_analog_project_wrapper/io_analog[1]
| chip_io_alt/mprj_analog[1] = 1
|
Net: w_21151_578074# |Net: \user_analog[0]
chip_io_alt/w_21151_578074# = 1 | user_analog_project_wrapper/io_analog[0]
| chip_io_alt/mprj_analog[0] = 1
|
Net: w_23367_797165# |Net: \user_clamp_high[2]
chip_io_alt/w_23367_797165# = 1 | user_analog_project_wrapper/io_clamp_hig
| chip_io_alt/mprj_clamp_high[2] = 1
|
Net: w_21253_323965# |Net: \user_clamp_high[1]
chip_io_alt/w_21253_323965# = 1 | user_analog_project_wrapper/io_clamp_hig
| chip_io_alt/mprj_clamp_high[1] = 1
|
Net: w_353269_21253# |Net: \user_clamp_high[0]
chip_io_alt/w_353269_21253# = 1 | user_analog_project_wrapper/io_clamp_hig
| chip_io_alt/mprj_clamp_high[0] = 1
|
Net: mprj/io_analog[8] |Net: \user_clamp_low[2]
chip_io_alt/mprj_analog[8] = 1 | user_analog_project_wrapper/io_clamp_low
| chip_io_alt/mprj_clamp_low[2] = 1
|
Net: w_23367_277674# |Net: \user_clamp_low[1]
chip_io_alt/w_23367_277674# = 1 | user_analog_project_wrapper/io_clamp_low
| chip_io_alt/mprj_clamp_low[1] = 1
|
Net: w_694469_148669# |Net: \user_clamp_low[0]
chip_io_alt/w_694469_148669# = 1 | user_analog_project_wrapper/io_clamp_low
| chip_io_alt/mprj_clamp_low[0] = 1
|
Net: w_21253_581165# |Net: \mprj_io_in_3v3[26]
chip_io_alt/w_21253_581165# = 1 | user_analog_project_wrapper/io_in_3v3[26
| chip_io_alt/mprj_io_in_3v3[26] = 1
|
Net: mprj_io[23] |Net: mprj_io[23]
chip_io_alt/mprj_io[23] = 1 | chip_io_alt/mprj_io[23] = 1
|
Net: w_694469_193669# |Net: \mprj_io_in_3v3[24]
chip_io_alt/w_694469_193669# = 1 | user_analog_project_wrapper/io_in_3v3[24
| chip_io_alt/mprj_io_in_3v3[24] = 1
|
Net: w_4069_956010# |Net: \mprj_io_in_3v3[23]
chip_io_alt/w_4069_956010# = 1 | user_analog_project_wrapper/io_in_3v3[23
| chip_io_alt/mprj_io_in_3v3[23] = 1
|
Net: w_23367_707674# |Net: \mprj_io_in_3v3[22]
chip_io_alt/w_23367_707674# = 1 | user_analog_project_wrapper/io_in_3v3[22
| chip_io_alt/mprj_io_in_3v3[22] = 1
|
Net: w_21151_234474# |Net: \mprj_io_in_3v3[21]
chip_io_alt/w_21151_234474# = 1 | user_analog_project_wrapper/io_in_3v3[21
| chip_io_alt/mprj_io_in_3v3[21] = 1
|
Net: padframe/vdda |Net: \mprj_io_in_3v3[20]
chip_io_alt/vdda = 1 | user_analog_project_wrapper/io_in_3v3[20
| chip_io_alt/mprj_io_in_3v3[20] = 1
|
Net: vddio_2 |Net: vddio_2
chip_io_alt/vddio_pad2 = 1 | chip_io_alt/vddio_pad2 = 1
|
Net: w_694469_238869# |Net: \mprj_io_in_3v3[18]
chip_io_alt/w_694469_238869# = 1 | user_analog_project_wrapper/io_in_3v3[18
| chip_io_alt/mprj_io_in_3v3[18] = 1
|
Net: w_21253_753965# |Net: \mprj_io_in_3v3[17]
chip_io_alt/w_21253_753965# = 1 | user_analog_project_wrapper/io_in_3v3[17
| chip_io_alt/mprj_io_in_3v3[17] = 1
|
Net: w_694469_283869# |Net: \mprj_io_in_3v3[16]
chip_io_alt/w_694469_283869# = 1 | user_analog_project_wrapper/io_in_3v3[16
| chip_io_alt/mprj_io_in_3v3[16] = 1
|
Net: w_692253_865870# |Net: \mprj_io_in_3v3[15]
chip_io_alt/w_692253_865870# = 1 | user_analog_project_wrapper/io_in_3v3[15
| chip_io_alt/mprj_io_in_3v3[15] = 1
|
Net: mprj_io[14] |Net: mprj_io[14]
chip_io_alt/mprj_io[14] = 1 | chip_io_alt/mprj_io[14] = 1
|
Net: w_298469_23367# |Net: \mprj_io_in_3v3[13]
chip_io_alt/w_298469_23367# = 1 | user_analog_project_wrapper/io_in_3v3[13
| chip_io_alt/mprj_io_in_3v3[13] = 1
|
Net: mprj/io_analog[0] |Net: \mprj_io_in_3v3[12]
chip_io_alt/mprj_analog[0] = 1 | user_analog_project_wrapper/io_in_3v3[12
| chip_io_alt/mprj_io_in_3v3[12] = 1
|
Net: w_694469_547952# |Net: \mprj_io_in_3v3[11]
chip_io_alt/w_694469_547952# = 1 | user_analog_project_wrapper/io_in_3v3[11
| chip_io_alt/mprj_io_in_3v3[11] = 1
|
Net: w_692355_638152# |Net: \mprj_io_in_3v3[10]
chip_io_alt/w_692355_638152# = 1 | user_analog_project_wrapper/io_in_3v3[10
| chip_io_alt/mprj_io_in_3v3[10] = 1
|
Net: w_21151_664474# |Net: \mprj_io_in_3v3[9]
chip_io_alt/w_21151_664474# = 1 | user_analog_project_wrapper/io_in_3v3[9]
| chip_io_alt/mprj_io_in_3v3[9] = 1
|
Net: w_23367_191274# |Net: \mprj_io_in_3v3[8]
chip_io_alt/w_23367_191274# = 1 | user_analog_project_wrapper/io_in_3v3[8]
| chip_io_alt/mprj_io_in_3v3[8] = 1
|
Net: vssd |Net: vssd
chip_io_alt/vssd_pad = 1 | chip_io_alt/vssd_pad = 1
|
Net: w_408069_23367# |Net: \mprj_io_in_3v3[6]
chip_io_alt/w_408069_23367# = 1 | user_analog_project_wrapper/io_in_3v3[6]
| chip_io_alt/mprj_io_in_3v3[6] = 1
|
Net: w_694469_593152# |Net: \mprj_io_in_3v3[5]
chip_io_alt/w_694469_593152# = 1 | user_analog_project_wrapper/io_in_3v3[5]
| chip_io_alt/mprj_io_in_3v3[5] = 1
|
Net: w_23367_621274# |Net: \mprj_io_in_3v3[4]
chip_io_alt/w_23367_621274# = 1 | user_analog_project_wrapper/io_in_3v3[4]
| chip_io_alt/mprj_io_in_3v3[4] = 1
|
Net: vssa1 |Net: vssa1
chip_io_alt/vssa1_pad = 1 | chip_io_alt/vssa1_pad = 1
|
Net: w_692355_728352# |Net: \mprj_io_in_3v3[2]
chip_io_alt/w_692355_728352# = 1 | user_analog_project_wrapper/io_in_3v3[2]
| chip_io_alt/mprj_io_in_3v3[2] = 1
|
Net: w_514352_23367# |Net: \mprj_io_in_3v3[1]
chip_io_alt/w_514352_23367# = 1 | user_analog_project_wrapper/io_in_3v3[1]
| chip_io_alt/mprj_io_in_3v3[1] = 1
|
Net: w_694469_325552# |Net: \mprj_io_in_3v3[0]
chip_io_alt/w_694469_325552# = 1 | user_analog_project_wrapper/io_in_3v3[0]
| chip_io_alt/mprj_io_in_3v3[0] = 1
|
Net: w_692355_773352# |Net: gpio_in_core
chip_io_alt/w_692355_773352# = 1 | chip_io_alt/gpio_in_core = 1
| mgmt_core_wrapper/gpio_in_pad = 1
|
Net: w_298469_21253# |Net: gpio_inenb_core
chip_io_alt/w_298469_21253# = 1 | chip_io_alt/gpio_inenb_core = 1
| mgmt_core_wrapper/gpio_inenb_pad = 1
|
Net: w_694469_683352# |Net: gpio_mode0_core
chip_io_alt/w_694469_683352# = 1 | chip_io_alt/gpio_mode0_core = 1
| mgmt_core_wrapper/gpio_mode0_pad = 1
|
Net: w_21253_367165# |Net: gpio_mode1_core
chip_io_alt/w_21253_367165# = 1 | chip_io_alt/gpio_mode1_core = 1
| mgmt_core_wrapper/gpio_mode1_pad = 1
|
Net: w_23367_194365# |Net: gpio_out_core
chip_io_alt/w_23367_194365# = 1 | chip_io_alt/gpio_out_core = 1
| mgmt_core_wrapper/gpio_out_pad = 1
|
Net: w_21151_320874# |Net: gpio_outenb_core
chip_io_alt/w_21151_320874# = 1 | chip_io_alt/gpio_outenb_core = 1
| mgmt_core_wrapper/gpio_outenb_pad = 1
|
Net: w_408069_21253# |Net: por_l_buf
chip_io_alt/w_408069_21253# = 1 | chip_io_alt/por = 1
| mgmt_core_wrapper/por_l_out = 1
|
Net: mprj/io_analog[1] |Net: porb_h
chip_io_alt/mprj_analog[1] = 1 | chip_io_alt/porb_h = 1
| simple_por/porb_h = 1
|
Net: w_23367_624365# |Net: rstb_h
chip_io_alt/w_23367_624365# = 1 | chip_io_alt/resetb_core_h = 1
| xres_buf/A = 1
|
Net: w_514352_21253# |Net: \gpio_control_bidir_1[0] /gpio_logic1
chip_io_alt/w_514352_21253# = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: padframe/vssa |Net: \gpio_control_bidir_1[1] /gpio_logic1
chip_io_alt/vssa = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: w_404752_23367# |Net: \gpio_control_bidir_2[0] /gpio_logic1
chip_io_alt/w_404752_23367# = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: vssa1_2 |Net: vssa1_2
chip_io_alt/vssa1_pad2 = 1 | chip_io_alt/vssa1_pad2 = 1
|
Net: mprj/io_analog[4] |Net: \gpio_control_bidir_2[2] /gpio_logic1
chip_io_alt/mprj_analog[4] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: w_21253_797165# |Net: \gpio_control_in_1[0] /gpio_logic1
chip_io_alt/w_21253_797165# = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: w_21151_750874# |Net: \gpio_control_in_1[1] /gpio_logic1
chip_io_alt/w_21151_750874# = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/user_irq[0] |Net: \gpio_control_in_1[2] /gpio_logic1
mgmt_protect/user_irq_core[0] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/user_irq[1] |Net: \gpio_control_in_1[3] /gpio_logic1
mgmt_protect/user_irq_core[1] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/user_irq[2] |Net: \gpio_control_in_1[4] /gpio_logic1
mgmt_protect/user_irq_core[2] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[108] |Net: \gpio_control_in_1[5] /gpio_logic1
mgmt_protect/la_data_in_core[108] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[109] |Net: \gpio_control_in_1a[0] /gpio_logic1
mgmt_protect/la_data_in_core[109] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[110] |Net: \gpio_control_in_1a[1] /gpio_logic1
mgmt_protect/la_data_in_core[110] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[111] |Net: \gpio_control_in_1a[2] /gpio_logic1
mgmt_protect/la_data_in_core[111] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[112] |Net: \gpio_control_in_1a[3] /gpio_logic1
mgmt_protect/la_data_in_core[112] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[113] |Net: \gpio_control_in_1a[4] /gpio_logic1
mgmt_protect/la_data_in_core[113] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[114] |Net: \gpio_control_in_1a[5] /gpio_logic1
mgmt_protect/la_data_in_core[114] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[115] |Net: \gpio_control_in_2[0] /gpio_logic1
mgmt_protect/la_data_in_core[115] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[116] |Net: \gpio_control_in_2[1] /gpio_logic1
mgmt_protect/la_data_in_core[116] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[117] |Net: \gpio_control_in_2[2] /gpio_logic1
mgmt_protect/la_data_in_core[117] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[118] |Net: \gpio_control_in_2[3] /gpio_logic1
mgmt_protect/la_data_in_core[118] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[119] |Net: \gpio_control_in_2[4] /gpio_logic1
mgmt_protect/la_data_in_core[119] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[120] |Net: \gpio_control_in_2[5] /gpio_logic1
mgmt_protect/la_data_in_core[120] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[121] |Net: \gpio_control_in_2[6] /gpio_logic1
mgmt_protect/la_data_in_core[121] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[122] |Net: \gpio_control_in_2[7] /gpio_logic1
mgmt_protect/la_data_in_core[122] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[123] |Net: \gpio_control_in_2[8] /gpio_logic1
mgmt_protect/la_data_in_core[123] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[124] |Net: \gpio_control_in_2[9] /gpio_logic1
mgmt_protect/la_data_in_core[124] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[125] |Net: \gpio_control_bidir_1[0] /spare_cell/
mgmt_protect/la_data_in_core[125] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[126] |Net: \gpio_control_bidir_1[0] /spare_cell/
mgmt_protect/la_data_in_core[126] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[127] |Net: \gpio_control_bidir_1[1] /spare_cell/
mgmt_protect/la_data_in_core[127] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[108] |Net: \gpio_control_bidir_1[1] /spare_cell/
mgmt_protect/la_data_out_core[108] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[109] |Net: \gpio_control_bidir_2[0] /spare_cell/
mgmt_protect/la_data_out_core[109] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[110] |Net: \gpio_control_bidir_2[0] /spare_cell/
mgmt_protect/la_data_out_core[110] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[111] |Net: \gpio_control_bidir_2[1] /spare_cell/
mgmt_protect/la_data_out_core[111] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[112] |Net: \gpio_control_bidir_2[1] /spare_cell/
mgmt_protect/la_data_out_core[112] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[113] |Net: \gpio_control_bidir_2[2] /spare_cell/
mgmt_protect/la_data_out_core[113] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[114] |Net: \gpio_control_bidir_2[2] /spare_cell/
mgmt_protect/la_data_out_core[114] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[115] |Net: \gpio_control_in_1[0] /spare_cell/sky
mgmt_protect/la_data_out_core[115] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[116] |Net: \gpio_control_in_1[0] /spare_cell/sky
mgmt_protect/la_data_out_core[116] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[117] |Net: \gpio_control_in_1[1] /spare_cell/sky
mgmt_protect/la_data_out_core[117] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[118] |Net: \gpio_control_in_1[1] /spare_cell/sky
mgmt_protect/la_data_out_core[118] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[119] |Net: \gpio_control_in_1[2] /spare_cell/sky
mgmt_protect/la_data_out_core[119] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[120] |Net: \gpio_control_in_1[2] /spare_cell/sky
mgmt_protect/la_data_out_core[120] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[121] |Net: \gpio_control_in_1[3] /spare_cell/sky
mgmt_protect/la_data_out_core[121] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[122] |Net: \gpio_control_in_1[3] /spare_cell/sky
mgmt_protect/la_data_out_core[122] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[123] |Net: \gpio_control_in_1[4] /spare_cell/sky
mgmt_protect/la_data_out_core[123] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[124] |Net: \gpio_control_in_1[4] /spare_cell/sky
mgmt_protect/la_data_out_core[124] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[125] |Net: \gpio_control_in_1[5] /spare_cell/sky
mgmt_protect/la_data_out_core[125] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[126] |Net: \gpio_control_in_1[5] /spare_cell/sky
mgmt_protect/la_data_out_core[126] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[127] |Net: \gpio_control_in_1a[0] /spare_cell/sk
mgmt_protect/la_data_out_core[127] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[107] |Net: \gpio_control_in_1a[0] /spare_cell/sk
mgmt_protect/la_oenb_core[107] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[108] |Net: \gpio_control_in_1a[1] /spare_cell/sk
mgmt_protect/la_oenb_core[108] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[109] |Net: \gpio_control_in_1a[1] /spare_cell/sk
mgmt_protect/la_oenb_core[109] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[110] |Net: \gpio_control_in_1a[2] /spare_cell/sk
mgmt_protect/la_oenb_core[110] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[111] |Net: \gpio_control_in_1a[2] /spare_cell/sk
mgmt_protect/la_oenb_core[111] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[112] |Net: \gpio_control_in_1a[3] /spare_cell/sk
mgmt_protect/la_oenb_core[112] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[113] |Net: \gpio_control_in_1a[3] /spare_cell/sk
mgmt_protect/la_oenb_core[113] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[114] |Net: \gpio_control_in_1a[4] /spare_cell/sk
mgmt_protect/la_oenb_core[114] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[115] |Net: \gpio_control_in_1a[4] /spare_cell/sk
mgmt_protect/la_oenb_core[115] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[116] |Net: \gpio_control_in_1a[5] /spare_cell/sk
mgmt_protect/la_oenb_core[116] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[117] |Net: \gpio_control_in_1a[5] /spare_cell/sk
mgmt_protect/la_oenb_core[117] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[118] |Net: \gpio_control_in_2[0] /spare_cell/sky
mgmt_protect/la_oenb_core[118] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[119] |Net: \gpio_control_in_2[0] /spare_cell/sky
mgmt_protect/la_oenb_core[119] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[120] |Net: \gpio_control_in_2[1] /spare_cell/sky
mgmt_protect/la_oenb_core[120] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[121] |Net: \gpio_control_in_2[1] /spare_cell/sky
mgmt_protect/la_oenb_core[121] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[122] |Net: \gpio_control_in_2[2] /spare_cell/sky
mgmt_protect/la_oenb_core[122] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[123] |Net: \gpio_control_in_2[2] /spare_cell/sky
mgmt_protect/la_oenb_core[123] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[124] |Net: \gpio_control_in_2[3] /spare_cell/sky
mgmt_protect/la_oenb_core[124] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[125] |Net: \gpio_control_in_2[3] /spare_cell/sky
mgmt_protect/la_oenb_core[125] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[126] |Net: \gpio_control_in_2[4] /spare_cell/sky
mgmt_protect/la_oenb_core[126] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_oenb[127] |Net: \gpio_control_in_2[4] /spare_cell/sky
mgmt_protect/la_oenb_core[127] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/user_clock2 |Net: \gpio_control_in_2[5] /spare_cell/sky
mgmt_protect/user_clock2 = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[94] |Net: \gpio_control_in_2[5] /spare_cell/sky
mgmt_protect/la_data_in_core[94] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[95] |Net: \gpio_control_in_2[6] /spare_cell/sky
mgmt_protect/la_data_in_core[95] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[96] |Net: \gpio_control_in_2[6] /spare_cell/sky
mgmt_protect/la_data_in_core[96] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[97] |Net: \gpio_control_in_2[7] /spare_cell/sky
mgmt_protect/la_data_in_core[97] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[98] |Net: \gpio_control_in_2[7] /spare_cell/sky
mgmt_protect/la_data_in_core[98] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_in[99] |Net: \gpio_control_in_2[8] /spare_cell/sky
mgmt_protect/la_data_in_core[99] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[87] |Net: \gpio_control_in_2[8] /spare_cell/sky
mgmt_protect/la_data_out_core[87] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[88] |Net: \gpio_control_in_2[9] /spare_cell/sky
mgmt_protect/la_data_out_core[88] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[89] |Net: \gpio_control_in_2[9] /spare_cell/sky
mgmt_protect/la_data_out_core[89] = 1 | sky130_fd_sc_hd__inv_2/A = 1
| sky130_fd_sc_hd__nor2_2/B = 1
|
Net: mprj/la_data_out[90] |Net: caravel_clk2
mgmt_protect/la_data_out_core[90] = 1 | caravel_clocking/user_clk = 1
| housekeeping/user_clock = 1
| mgmt_protect/caravel_clk2 = 1
|
Net: mprj/la_data_out[91] |Net: \mprj_io_in[0]
mgmt_protect/la_data_out_core[91] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[0] = 1
|
Net: mprj/la_data_out[92] |Net: \user_io_oeb[0]
mgmt_protect/la_data_out_core[92] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[0] =
|
Net: mprj/la_data_out[93] |Net: \user_io_out[0]
mgmt_protect/la_data_out_core[93] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[0] =
|
Net: mprj/la_data_out[94] |Net: \mprj_io_in[1]
mgmt_protect/la_data_out_core[94] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[1] = 1
|
Net: mprj/la_data_out[95] |Net: \user_io_oeb[1]
mgmt_protect/la_data_out_core[95] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[1] =
|
Net: mprj/la_data_out[96] |Net: \user_io_out[1]
mgmt_protect/la_data_out_core[96] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[1] =
|
Net: mprj/la_data_out[97] |Net: \mprj_io_in[24]
mgmt_protect/la_data_out_core[97] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[24] = 1
|
Net: mprj/la_data_out[98] |Net: \user_io_oeb[24]
mgmt_protect/la_data_out_core[98] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[24] =
|
Net: mprj/la_data_out[99] |Net: \user_io_out[24]
mgmt_protect/la_data_out_core[99] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[24] =
|
Net: mprj/la_oenb[100] |Net: \mprj_io_in[25]
mgmt_protect/la_oenb_core[100] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[25] = 1
|
Net: mprj/la_oenb[101] |Net: \user_io_oeb[25]
mgmt_protect/la_oenb_core[101] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[25] =
|
Net: mprj/la_oenb[102] |Net: \user_io_out[25]
mgmt_protect/la_oenb_core[102] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[25] =
|
Net: mprj/la_oenb[103] |Net: \mprj_io_in[26]
mgmt_protect/la_oenb_core[103] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[26] = 1
|
Net: mprj/la_oenb[104] |Net: \user_io_oeb[26]
mgmt_protect/la_oenb_core[104] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[26] =
|
Net: mprj/la_oenb[105] |Net: \user_io_out[26]
mgmt_protect/la_oenb_core[105] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[26] =
|
Net: mprj/la_oenb[106] |Net: \mprj_io_in[8]
mgmt_protect/la_oenb_core[106] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[8] = 1
|
Net: mprj/la_data_out[100] |Net: \user_io_oeb[8]
mgmt_protect/la_data_out_core[100] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[8] =
|
Net: mprj/la_data_out[101] |Net: \user_io_out[8]
mgmt_protect/la_data_out_core[101] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[8] =
|
Net: mprj/la_data_out[102] |Net: \mprj_io_in[9]
mgmt_protect/la_data_out_core[102] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[9] = 1
|
Net: mprj/la_data_out[103] |Net: \user_io_oeb[9]
mgmt_protect/la_data_out_core[103] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[9] =
|
Net: mprj/la_data_out[104] |Net: \user_io_out[9]
mgmt_protect/la_data_out_core[104] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[9] =
|
Net: mprj/la_data_out[105] |Net: \mprj_io_in[10]
mgmt_protect/la_data_out_core[105] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[10] = 1
|
Net: mprj/la_data_out[106] |Net: \user_io_oeb[10]
mgmt_protect/la_data_out_core[106] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[10] =
|
Net: mprj/la_data_out[107] |Net: \user_io_out[10]
mgmt_protect/la_data_out_core[107] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[10] =
|
Net: mprj/la_data_in[104] |Net: \mprj_io_in[11]
mgmt_protect/la_data_in_core[104] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[11] = 1
|
Net: mprj/la_data_in[105] |Net: \user_io_oeb[11]
mgmt_protect/la_data_in_core[105] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[11] =
|
Net: mprj/la_data_in[106] |Net: \user_io_out[11]
mgmt_protect/la_data_in_core[106] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[11] =
|
Net: mprj/la_data_in[107] |Net: \mprj_io_in[12]
mgmt_protect/la_data_in_core[107] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[12] = 1
|
Net: mprj/la_data_in[100] |Net: \user_io_oeb[12]
mgmt_protect/la_data_in_core[100] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[12] =
|
Net: mprj/la_data_in[101] |Net: \user_io_out[12]
mgmt_protect/la_data_in_core[101] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[12] =
|
Net: mprj/la_data_in[102] |Net: \mprj_io_in[13]
mgmt_protect/la_data_in_core[102] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[13] = 1
|
Net: mprj/la_data_in[103] |Net: \user_io_oeb[13]
mgmt_protect/la_data_in_core[103] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[13] =
|
Net: mprj/la_data_in[88] |Net: \user_io_out[13]
mgmt_protect/la_data_in_core[88] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[13] =
|
Net: mprj/la_data_in[89] |Net: \mprj_io_in[2]
mgmt_protect/la_data_in_core[89] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[2] = 1
|
Net: mprj/la_data_in[90] |Net: \user_io_oeb[2]
mgmt_protect/la_data_in_core[90] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[2] =
|
Net: mprj/la_data_in[91] |Net: \user_io_out[2]
mgmt_protect/la_data_in_core[91] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[2] =
|
Net: mprj/la_data_in[92] |Net: \mprj_io_in[3]
mgmt_protect/la_data_in_core[92] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[3] = 1
|
Net: mprj/la_oenb[87] |Net: \user_io_oeb[3]
mgmt_protect/la_oenb_core[87] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[3] =
|
Net: mprj/la_oenb[88] |Net: \user_io_out[3]
mgmt_protect/la_oenb_core[88] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[3] =
|
Net: mprj/la_oenb[89] |Net: \mprj_io_in[4]
mgmt_protect/la_oenb_core[89] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[4] = 1
|
Net: mprj/la_oenb[90] |Net: \user_io_oeb[4]
mgmt_protect/la_oenb_core[90] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[4] =
|
Net: mprj/la_oenb[91] |Net: \user_io_out[4]
mgmt_protect/la_oenb_core[91] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[4] =
|
Net: mprj/la_oenb[92] |Net: \mprj_io_in[5]
mgmt_protect/la_oenb_core[92] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[5] = 1
|
Net: mprj/la_oenb[93] |Net: \user_io_oeb[5]
mgmt_protect/la_oenb_core[93] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[5] =
|
Net: mprj/la_oenb[94] |Net: \user_io_out[5]
mgmt_protect/la_oenb_core[94] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[5] =
|
Net: mprj/la_oenb[95] |Net: \mprj_io_in[6]
mgmt_protect/la_oenb_core[95] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[6] = 1
|
Net: mprj/la_oenb[96] |Net: \user_io_oeb[6]
mgmt_protect/la_oenb_core[96] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[6] =
|
Net: mprj/la_oenb[97] |Net: \user_io_out[6]
mgmt_protect/la_oenb_core[97] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[6] =
|
Net: mprj/la_oenb[98] |Net: \mprj_io_in[7]
mgmt_protect/la_oenb_core[98] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[7] = 1
|
Net: mprj/la_oenb[99] |Net: \user_io_oeb[7]
mgmt_protect/la_oenb_core[99] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[7] =
|
Net: mprj/la_data_in[93] |Net: \user_io_out[7]
mgmt_protect/la_data_in_core[93] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[7] =
|
Net: mprj/la_data_out[67] |Net: \mprj_io_in[14]
mgmt_protect/la_data_out_core[67] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[14] = 1
|
Net: mprj/la_data_out[68] |Net: \user_io_oeb[14]
mgmt_protect/la_data_out_core[68] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[14] =
|
Net: mprj/la_data_out[69] |Net: \user_io_out[14]
mgmt_protect/la_data_out_core[69] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[14] =
|
Net: mprj/la_data_out[70] |Net: \mprj_io_in[15]
mgmt_protect/la_data_out_core[70] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[15] = 1
|
Net: mprj/la_data_out[71] |Net: \user_io_oeb[15]
mgmt_protect/la_data_out_core[71] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[15] =
|
Net: mprj/la_data_out[72] |Net: \user_io_out[15]
mgmt_protect/la_data_out_core[72] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[15] =
|
Net: mprj/la_data_out[73] |Net: \mprj_io_in[16]
mgmt_protect/la_data_out_core[73] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[16] = 1
|
Net: mprj/la_data_out[74] |Net: \user_io_oeb[16]
mgmt_protect/la_data_out_core[74] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[16] =
|
Net: mprj/la_data_out[75] |Net: \user_io_out[16]
mgmt_protect/la_data_out_core[75] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[16] =
|
Net: mprj/la_data_out[76] |Net: \mprj_io_in[17]
mgmt_protect/la_data_out_core[76] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[17] = 1
|
Net: mprj/la_data_out[77] |Net: \user_io_oeb[17]
mgmt_protect/la_data_out_core[77] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[17] =
|
Net: mprj/la_data_out[78] |Net: \user_io_out[17]
mgmt_protect/la_data_out_core[78] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[17] =
|
Net: mprj/la_data_out[79] |Net: \mprj_io_in[18]
mgmt_protect/la_data_out_core[79] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[18] = 1
|
Net: mprj/la_data_out[80] |Net: \user_io_oeb[18]
mgmt_protect/la_data_out_core[80] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[18] =
|
Net: mprj/la_data_out[81] |Net: \user_io_out[18]
mgmt_protect/la_data_out_core[81] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[18] =
|
Net: mprj/la_data_out[82] |Net: \mprj_io_in[19]
mgmt_protect/la_data_out_core[82] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[19] = 1
|
Net: mprj/la_data_out[83] |Net: \user_io_oeb[19]
mgmt_protect/la_data_out_core[83] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[19] =
|
Net: mprj/la_data_out[84] |Net: \user_io_out[19]
mgmt_protect/la_data_out_core[84] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[19] =
|
Net: mprj/la_data_out[85] |Net: \mprj_io_in[20]
mgmt_protect/la_data_out_core[85] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[20] = 1
|
Net: mprj/la_data_out[86] |Net: \user_io_oeb[20]
mgmt_protect/la_data_out_core[86] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[20] =
|
Net: mprj/la_data_in[87] |Net: \user_io_out[20]
mgmt_protect/la_data_in_core[87] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[20] =
|
Net: mprj/la_data_in[67] |Net: \mprj_io_in[21]
mgmt_protect/la_data_in_core[67] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[21] = 1
|
Net: mprj/la_data_in[68] |Net: \user_io_oeb[21]
mgmt_protect/la_data_in_core[68] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[21] =
|
Net: mprj/la_data_in[69] |Net: \user_io_out[21]
mgmt_protect/la_data_in_core[69] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[21] =
|
Net: mprj/la_data_in[70] |Net: \mprj_io_in[22]
mgmt_protect/la_data_in_core[70] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[22] = 1
|
Net: mprj/la_data_in[71] |Net: \user_io_oeb[22]
mgmt_protect/la_data_in_core[71] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[22] =
|
Net: mprj/la_data_in[72] |Net: \user_io_out[22]
mgmt_protect/la_data_in_core[72] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[22] =
|
Net: mprj/la_data_in[73] |Net: \mprj_io_in[23]
mgmt_protect/la_data_in_core[73] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__buf_2/A = 1
| chip_io_alt/mprj_io_in[23] = 1
|
Net: mprj/la_data_in[74] |Net: \user_io_oeb[23]
mgmt_protect/la_data_in_core[74] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__mux2_4/A0 = 1
| user_analog_project_wrapper/io_oeb[23] =
|
Net: mprj/la_data_in[75] |Net: \user_io_out[23]
mgmt_protect/la_data_in_core[75] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
| sky130_fd_sc_hd__nand2b_2/B = 1
| user_analog_project_wrapper/io_out[23] =
|
Net: mprj/la_data_in[76] |Net: mprj_we_o_core
mgmt_protect/la_data_in_core[76] = 1 | housekeeping/wb_we_i = 1
| mgmt_protect/mprj_we_o_core = 1
| mgmt_core_wrapper/mprj_we_o = 1
|
Net: mprj/la_data_in[77] |Net: \mprj_adr_o_core[31]
mgmt_protect/la_data_in_core[77] = 1 | housekeeping/wb_adr_i[31] = 1
| mgmt_protect/mprj_adr_o_core[31] = 1
| mgmt_core_wrapper/mprj_adr_o[31] = 1
|
Net: mprj/la_data_in[78] |Net: \mprj_adr_o_core[30]
mgmt_protect/la_data_in_core[78] = 1 | housekeeping/wb_adr_i[30] = 1
| mgmt_protect/mprj_adr_o_core[30] = 1
| mgmt_core_wrapper/mprj_adr_o[30] = 1
|
Net: mprj/la_data_in[79] |Net: \mprj_adr_o_core[29]
mgmt_protect/la_data_in_core[79] = 1 | housekeeping/wb_adr_i[29] = 1
| mgmt_protect/mprj_adr_o_core[29] = 1
| mgmt_core_wrapper/mprj_adr_o[29] = 1
|
Net: mprj/la_data_in[80] |Net: \mprj_adr_o_core[28]
mgmt_protect/la_data_in_core[80] = 1 | housekeeping/wb_adr_i[28] = 1
| mgmt_protect/mprj_adr_o_core[28] = 1
| mgmt_core_wrapper/mprj_adr_o[28] = 1
|
Net: mprj/la_data_in[81] |Net: \mprj_adr_o_core[27]
mgmt_protect/la_data_in_core[81] = 1 | housekeeping/wb_adr_i[27] = 1
| mgmt_protect/mprj_adr_o_core[27] = 1
| mgmt_core_wrapper/mprj_adr_o[27] = 1
|
Net: mprj/la_data_in[82] |Net: \mprj_adr_o_core[26]
mgmt_protect/la_data_in_core[82] = 1 | housekeeping/wb_adr_i[26] = 1
| mgmt_protect/mprj_adr_o_core[26] = 1
| mgmt_core_wrapper/mprj_adr_o[26] = 1
|
Net: mprj/la_data_in[83] |Net: \mprj_adr_o_core[25]
mgmt_protect/la_data_in_core[83] = 1 | housekeeping/wb_adr_i[25] = 1
| mgmt_protect/mprj_adr_o_core[25] = 1
| mgmt_core_wrapper/mprj_adr_o[25] = 1
|
Net: mprj/la_data_in[84] |Net: \mprj_adr_o_core[24]
mgmt_protect/la_data_in_core[84] = 1 | housekeeping/wb_adr_i[24] = 1
| mgmt_protect/mprj_adr_o_core[24] = 1
| mgmt_core_wrapper/mprj_adr_o[24] = 1
|
Net: mprj/la_data_in[85] |Net: \mprj_adr_o_core[23]
mgmt_protect/la_data_in_core[85] = 1 | housekeeping/wb_adr_i[23] = 1
| mgmt_protect/mprj_adr_o_core[23] = 1
| mgmt_core_wrapper/mprj_adr_o[23] = 1
|
Net: mprj/la_data_in[86] |Net: \mprj_adr_o_core[22]
mgmt_protect/la_data_in_core[86] = 1 | housekeeping/wb_adr_i[22] = 1
| mgmt_protect/mprj_adr_o_core[22] = 1
| mgmt_core_wrapper/mprj_adr_o[22] = 1
|
Net: mprj/la_oenb[67] |Net: \mprj_adr_o_core[21]
mgmt_protect/la_oenb_core[67] = 1 | housekeeping/wb_adr_i[21] = 1
| mgmt_protect/mprj_adr_o_core[21] = 1
| mgmt_core_wrapper/mprj_adr_o[21] = 1
|
Net: mprj/la_oenb[68] |Net: \mprj_adr_o_core[20]
mgmt_protect/la_oenb_core[68] = 1 | housekeeping/wb_adr_i[20] = 1
| mgmt_protect/mprj_adr_o_core[20] = 1
| mgmt_core_wrapper/mprj_adr_o[20] = 1
|
Net: mprj/la_oenb[69] |Net: \mprj_adr_o_core[19]
mgmt_protect/la_oenb_core[69] = 1 | housekeeping/wb_adr_i[19] = 1
| mgmt_protect/mprj_adr_o_core[19] = 1
| mgmt_core_wrapper/mprj_adr_o[19] = 1
|
Net: mprj/la_oenb[70] |Net: \mprj_adr_o_core[18]
mgmt_protect/la_oenb_core[70] = 1 | housekeeping/wb_adr_i[18] = 1
| mgmt_protect/mprj_adr_o_core[18] = 1
| mgmt_core_wrapper/mprj_adr_o[18] = 1
|
Net: mprj/la_oenb[71] |Net: \mprj_adr_o_core[17]
mgmt_protect/la_oenb_core[71] = 1 | housekeeping/wb_adr_i[17] = 1
| mgmt_protect/mprj_adr_o_core[17] = 1
| mgmt_core_wrapper/mprj_adr_o[17] = 1
|
Net: mprj/la_oenb[72] |Net: \mprj_adr_o_core[16]
mgmt_protect/la_oenb_core[72] = 1 | housekeeping/wb_adr_i[16] = 1
| mgmt_protect/mprj_adr_o_core[16] = 1
| mgmt_core_wrapper/mprj_adr_o[16] = 1
|
Net: mprj/la_oenb[73] |Net: \mprj_adr_o_core[15]
mgmt_protect/la_oenb_core[73] = 1 | housekeeping/wb_adr_i[15] = 1
| mgmt_protect/mprj_adr_o_core[15] = 1
| mgmt_core_wrapper/mprj_adr_o[15] = 1
|
Net: mprj/la_oenb[74] |Net: \mprj_adr_o_core[14]
mgmt_protect/la_oenb_core[74] = 1 | housekeeping/wb_adr_i[14] = 1
| mgmt_protect/mprj_adr_o_core[14] = 1
| mgmt_core_wrapper/mprj_adr_o[14] = 1
|
Net: mprj/la_oenb[75] |Net: \mprj_adr_o_core[13]
mgmt_protect/la_oenb_core[75] = 1 | housekeeping/wb_adr_i[13] = 1
| mgmt_protect/mprj_adr_o_core[13] = 1
| mgmt_core_wrapper/mprj_adr_o[13] = 1
|
Net: mprj/la_oenb[76] |Net: \mprj_adr_o_core[12]
mgmt_protect/la_oenb_core[76] = 1 | housekeeping/wb_adr_i[12] = 1
| mgmt_protect/mprj_adr_o_core[12] = 1
| mgmt_core_wrapper/mprj_adr_o[12] = 1
|
Net: mprj/la_oenb[77] |Net: \mprj_adr_o_core[11]
mgmt_protect/la_oenb_core[77] = 1 | housekeeping/wb_adr_i[11] = 1
| mgmt_protect/mprj_adr_o_core[11] = 1
| mgmt_core_wrapper/mprj_adr_o[11] = 1
|
Net: mprj/la_oenb[78] |Net: \mprj_adr_o_core[10]
mgmt_protect/la_oenb_core[78] = 1 | housekeeping/wb_adr_i[10] = 1
| mgmt_protect/mprj_adr_o_core[10] = 1
| mgmt_core_wrapper/mprj_adr_o[10] = 1
|
Net: mprj/la_oenb[79] |Net: \mprj_adr_o_core[9]
mgmt_protect/la_oenb_core[79] = 1 | housekeeping/wb_adr_i[9] = 1
| mgmt_protect/mprj_adr_o_core[9] = 1
| mgmt_core_wrapper/mprj_adr_o[9] = 1
|
Net: mprj/la_oenb[80] |Net: \mprj_adr_o_core[8]
mgmt_protect/la_oenb_core[80] = 1 | housekeeping/wb_adr_i[8] = 1
| mgmt_protect/mprj_adr_o_core[8] = 1
| mgmt_core_wrapper/mprj_adr_o[8] = 1
|
Net: mprj/la_oenb[81] |Net: \mprj_adr_o_core[7]
mgmt_protect/la_oenb_core[81] = 1 | housekeeping/wb_adr_i[7] = 1
| mgmt_protect/mprj_adr_o_core[7] = 1
| mgmt_core_wrapper/mprj_adr_o[7] = 1
|
Net: mprj/la_oenb[82] |Net: \mprj_adr_o_core[6]
mgmt_protect/la_oenb_core[82] = 1 | housekeeping/wb_adr_i[6] = 1
| mgmt_protect/mprj_adr_o_core[6] = 1
| mgmt_core_wrapper/mprj_adr_o[6] = 1
|
Net: mprj/la_oenb[83] |Net: \mprj_adr_o_core[5]
mgmt_protect/la_oenb_core[83] = 1 | housekeeping/wb_adr_i[5] = 1
| mgmt_protect/mprj_adr_o_core[5] = 1
| mgmt_core_wrapper/mprj_adr_o[5] = 1
|
Net: mprj/la_oenb[84] |Net: \mprj_adr_o_core[4]
mgmt_protect/la_oenb_core[84] = 1 | housekeeping/wb_adr_i[4] = 1
| mgmt_protect/mprj_adr_o_core[4] = 1
| mgmt_core_wrapper/mprj_adr_o[4] = 1
|
Net: mprj/la_oenb[85] |Net: \mprj_adr_o_core[3]
mgmt_protect/la_oenb_core[85] = 1 | housekeeping/wb_adr_i[3] = 1
| mgmt_protect/mprj_adr_o_core[3] = 1
| mgmt_core_wrapper/mprj_adr_o[3] = 1
|
Net: mprj/la_oenb[86] |Net: \mprj_adr_o_core[2]
mgmt_protect/la_oenb_core[86] = 1 | housekeeping/wb_adr_i[2] = 1
| mgmt_protect/mprj_adr_o_core[2] = 1
| mgmt_core_wrapper/mprj_adr_o[2] = 1
|
Net: mprj/la_data_in[55] |Net: \mprj_adr_o_core[1]
mgmt_protect/la_data_in_core[55] = 1 | housekeeping/wb_adr_i[1] = 1
| mgmt_protect/mprj_adr_o_core[1] = 1
| mgmt_core_wrapper/mprj_adr_o[1] = 1
|
Net: mprj/la_data_in[56] |Net: \mprj_adr_o_core[0]
mgmt_protect/la_data_in_core[56] = 1 | housekeeping/wb_adr_i[0] = 1
| mgmt_protect/mprj_adr_o_core[0] = 1
| mgmt_core_wrapper/mprj_adr_o[0] = 1
|
Net: mprj/la_data_in[57] |Net: \mprj_dat_o_core[31]
mgmt_protect/la_data_in_core[57] = 1 | housekeeping/wb_dat_i[31] = 1
| mgmt_protect/mprj_dat_o_core[31] = 1
| mgmt_core_wrapper/mprj_dat_o[31] = 1
|
Net: mprj/la_data_in[58] |Net: \mprj_dat_o_core[30]
mgmt_protect/la_data_in_core[58] = 1 | housekeeping/wb_dat_i[30] = 1
| mgmt_protect/mprj_dat_o_core[30] = 1
| mgmt_core_wrapper/mprj_dat_o[30] = 1
|
Net: mprj/la_data_in[59] |Net: \mprj_dat_o_core[29]
mgmt_protect/la_data_in_core[59] = 1 | housekeeping/wb_dat_i[29] = 1
| mgmt_protect/mprj_dat_o_core[29] = 1
| mgmt_core_wrapper/mprj_dat_o[29] = 1
|
Net: mprj/la_data_in[60] |Net: \mprj_dat_o_core[28]
mgmt_protect/la_data_in_core[60] = 1 | housekeeping/wb_dat_i[28] = 1
| mgmt_protect/mprj_dat_o_core[28] = 1
| mgmt_core_wrapper/mprj_dat_o[28] = 1
|
Net: mprj/la_oenb[46] |Net: \mprj_dat_o_core[27]
mgmt_protect/la_oenb_core[46] = 1 | housekeeping/wb_dat_i[27] = 1
| mgmt_protect/mprj_dat_o_core[27] = 1
| mgmt_core_wrapper/mprj_dat_o[27] = 1
|
Net: mprj/la_oenb[47] |Net: \mprj_dat_o_core[26]
mgmt_protect/la_oenb_core[47] = 1 | housekeeping/wb_dat_i[26] = 1
| mgmt_protect/mprj_dat_o_core[26] = 1
| mgmt_core_wrapper/mprj_dat_o[26] = 1
|
Net: mprj/la_oenb[48] |Net: \mprj_dat_o_core[25]
mgmt_protect/la_oenb_core[48] = 1 | housekeeping/wb_dat_i[25] = 1
| mgmt_protect/mprj_dat_o_core[25] = 1
| mgmt_core_wrapper/mprj_dat_o[25] = 1
|
Net: mprj/la_oenb[49] |Net: \mprj_dat_o_core[24]
mgmt_protect/la_oenb_core[49] = 1 | housekeeping/wb_dat_i[24] = 1
| mgmt_protect/mprj_dat_o_core[24] = 1
| mgmt_core_wrapper/mprj_dat_o[24] = 1
|
Net: mprj/la_oenb[50] |Net: \mprj_dat_o_core[23]
mgmt_protect/la_oenb_core[50] = 1 | housekeeping/wb_dat_i[23] = 1
| mgmt_protect/mprj_dat_o_core[23] = 1
| mgmt_core_wrapper/mprj_dat_o[23] = 1
|
Net: mprj/la_oenb[51] |Net: \mprj_dat_o_core[22]
mgmt_protect/la_oenb_core[51] = 1 | housekeeping/wb_dat_i[22] = 1
| mgmt_protect/mprj_dat_o_core[22] = 1
| mgmt_core_wrapper/mprj_dat_o[22] = 1
|
Net: mprj/la_oenb[52] |Net: \mprj_dat_o_core[21]
mgmt_protect/la_oenb_core[52] = 1 | housekeeping/wb_dat_i[21] = 1
| mgmt_protect/mprj_dat_o_core[21] = 1
| mgmt_core_wrapper/mprj_dat_o[21] = 1
|
Net: mprj/la_oenb[53] |Net: \mprj_dat_o_core[20]
mgmt_protect/la_oenb_core[53] = 1 | housekeeping/wb_dat_i[20] = 1
| mgmt_protect/mprj_dat_o_core[20] = 1
| mgmt_core_wrapper/mprj_dat_o[20] = 1
|
Net: mprj/la_oenb[54] |Net: \mprj_dat_o_core[19]
mgmt_protect/la_oenb_core[54] = 1 | housekeeping/wb_dat_i[19] = 1
| mgmt_protect/mprj_dat_o_core[19] = 1
| mgmt_core_wrapper/mprj_dat_o[19] = 1
|
Net: mprj/la_oenb[55] |Net: \mprj_dat_o_core[18]
mgmt_protect/la_oenb_core[55] = 1 | housekeeping/wb_dat_i[18] = 1
| mgmt_protect/mprj_dat_o_core[18] = 1
| mgmt_core_wrapper/mprj_dat_o[18] = 1
|
Net: mprj/la_oenb[56] |Net: \mprj_dat_o_core[17]
mgmt_protect/la_oenb_core[56] = 1 | housekeeping/wb_dat_i[17] = 1
| mgmt_protect/mprj_dat_o_core[17] = 1
| mgmt_core_wrapper/mprj_dat_o[17] = 1
|
Net: mprj/la_oenb[57] |Net: \mprj_dat_o_core[16]
mgmt_protect/la_oenb_core[57] = 1 | housekeeping/wb_dat_i[16] = 1
| mgmt_protect/mprj_dat_o_core[16] = 1
| mgmt_core_wrapper/mprj_dat_o[16] = 1
|
Net: mprj/la_oenb[58] |Net: \mprj_dat_o_core[15]
mgmt_protect/la_oenb_core[58] = 1 | housekeeping/wb_dat_i[15] = 1
| mgmt_protect/mprj_dat_o_core[15] = 1
| mgmt_core_wrapper/mprj_dat_o[15] = 1
|
Net: mprj/la_oenb[59] |Net: \mprj_dat_o_core[14]
mgmt_protect/la_oenb_core[59] = 1 | housekeeping/wb_dat_i[14] = 1
| mgmt_protect/mprj_dat_o_core[14] = 1
| mgmt_core_wrapper/mprj_dat_o[14] = 1
|
Net: mprj/la_oenb[60] |Net: \mprj_dat_o_core[13]
mgmt_protect/la_oenb_core[60] = 1 | housekeeping/wb_dat_i[13] = 1
| mgmt_protect/mprj_dat_o_core[13] = 1
| mgmt_core_wrapper/mprj_dat_o[13] = 1
|
Net: mprj/la_oenb[61] |Net: \mprj_dat_o_core[12]
mgmt_protect/la_oenb_core[61] = 1 | housekeeping/wb_dat_i[12] = 1
| mgmt_protect/mprj_dat_o_core[12] = 1
| mgmt_core_wrapper/mprj_dat_o[12] = 1
|
Net: mprj/la_oenb[62] |Net: \mprj_dat_o_core[11]
mgmt_protect/la_oenb_core[62] = 1 | housekeeping/wb_dat_i[11] = 1
| mgmt_protect/mprj_dat_o_core[11] = 1
| mgmt_core_wrapper/mprj_dat_o[11] = 1
|
Net: mprj/la_oenb[63] |Net: \mprj_dat_o_core[10]
mgmt_protect/la_oenb_core[63] = 1 | housekeeping/wb_dat_i[10] = 1
| mgmt_protect/mprj_dat_o_core[10] = 1
| mgmt_core_wrapper/mprj_dat_o[10] = 1
|
Net: mprj/la_oenb[64] |Net: \mprj_dat_o_core[9]
mgmt_protect/la_oenb_core[64] = 1 | housekeeping/wb_dat_i[9] = 1
| mgmt_protect/mprj_dat_o_core[9] = 1
| mgmt_core_wrapper/mprj_dat_o[9] = 1
|
Net: mprj/la_oenb[65] |Net: \mprj_dat_o_core[8]
mgmt_protect/la_oenb_core[65] = 1 | housekeeping/wb_dat_i[8] = 1
| mgmt_protect/mprj_dat_o_core[8] = 1
| mgmt_core_wrapper/mprj_dat_o[8] = 1
|
Net: mprj/la_oenb[66] |Net: \mprj_dat_o_core[7]
mgmt_protect/la_oenb_core[66] = 1 | housekeeping/wb_dat_i[7] = 1
| mgmt_protect/mprj_dat_o_core[7] = 1
| mgmt_core_wrapper/mprj_dat_o[7] = 1
|
Net: mprj/la_data_in[61] |Net: \mprj_dat_o_core[6]
mgmt_protect/la_data_in_core[61] = 1 | housekeeping/wb_dat_i[6] = 1
| mgmt_protect/mprj_dat_o_core[6] = 1
| mgmt_core_wrapper/mprj_dat_o[6] = 1
|
Net: mprj/la_data_in[62] |Net: \mprj_dat_o_core[5]
mgmt_protect/la_data_in_core[62] = 1 | housekeeping/wb_dat_i[5] = 1
| mgmt_protect/mprj_dat_o_core[5] = 1
| mgmt_core_wrapper/mprj_dat_o[5] = 1
|
Net: mprj/la_data_in[63] |Net: \mprj_dat_o_core[4]
mgmt_protect/la_data_in_core[63] = 1 | housekeeping/wb_dat_i[4] = 1
| mgmt_protect/mprj_dat_o_core[4] = 1
| mgmt_core_wrapper/mprj_dat_o[4] = 1
|
Net: mprj/la_data_in[64] |Net: \mprj_dat_o_core[3]
mgmt_protect/la_data_in_core[64] = 1 | housekeeping/wb_dat_i[3] = 1
| mgmt_protect/mprj_dat_o_core[3] = 1
| mgmt_core_wrapper/mprj_dat_o[3] = 1
|
Net: mprj/la_data_in[65] |Net: \mprj_dat_o_core[2]
mgmt_protect/la_data_in_core[65] = 1 | housekeeping/wb_dat_i[2] = 1
| mgmt_protect/mprj_dat_o_core[2] = 1
| mgmt_core_wrapper/mprj_dat_o[2] = 1
|
Net: mprj/la_data_in[66] |Net: \mprj_dat_o_core[1]
mgmt_protect/la_data_in_core[66] = 1 | housekeeping/wb_dat_i[1] = 1
| mgmt_protect/mprj_dat_o_core[1] = 1
| mgmt_core_wrapper/mprj_dat_o[1] = 1
|
Net: mprj/la_data_out[64] |Net: \mprj_dat_o_core[0]
mgmt_protect/la_data_out_core[64] = 1 | housekeeping/wb_dat_i[0] = 1
| mgmt_protect/mprj_dat_o_core[0] = 1
| mgmt_core_wrapper/mprj_dat_o[0] = 1
|
Net: mprj/la_data_out[65] |Net: \mprj_sel_o_core[3]
mgmt_protect/la_data_out_core[65] = 1 | housekeeping/wb_sel_i[3] = 1
| mgmt_protect/mprj_sel_o_core[3] = 1
| mgmt_core_wrapper/mprj_sel_o[3] = 1
|
Net: mprj/la_data_out[66] |Net: \mprj_sel_o_core[2]
mgmt_protect/la_data_out_core[66] = 1 | housekeeping/wb_sel_i[2] = 1
| mgmt_protect/mprj_sel_o_core[2] = 1
| mgmt_core_wrapper/mprj_sel_o[2] = 1
|
Net: mprj/la_data_out[61] |Net: \mprj_sel_o_core[1]
mgmt_protect/la_data_out_core[61] = 1 | housekeeping/wb_sel_i[1] = 1
| mgmt_protect/mprj_sel_o_core[1] = 1
| mgmt_core_wrapper/mprj_sel_o[1] = 1
|
Net: mprj/la_data_out[62] |Net: \mprj_sel_o_core[0]
mgmt_protect/la_data_out_core[62] = 1 | housekeeping/wb_sel_i[0] = 1
| mgmt_protect/mprj_sel_o_core[0] = 1
| mgmt_core_wrapper/mprj_sel_o[0] = 1
|
Net: mprj/la_data_out[63] |Net: vccd2_core
mgmt_protect/la_data_out_core[63] = 1 | mgmt_protect/vccd2 = 1
| user_analog_project_wrapper/vccd2 = 1
| chip_io_alt/vccd2 = 1
|
Net: mprj/la_data_in[47] |Net: vssd2_core
mgmt_protect/la_data_in_core[47] = 1 | mgmt_protect/vssd2 = 1
| user_analog_project_wrapper/vssd2 = 1
| chip_io_alt/vssd2 = 1
|
Net: mprj/la_data_in[48] |Net: vdda1_core
mgmt_protect/la_data_in_core[48] = 1 | mgmt_protect/vdda1 = 1
| user_analog_project_wrapper/vdda1 = 1
| chip_io_alt/vdda1 = 1
|
Net: mprj/la_data_in[49] |Net: vssa1_core
mgmt_protect/la_data_in_core[49] = 1 | mgmt_protect/vssa1 = 1
| user_analog_project_wrapper/vssa1 = 1
| chip_io_alt/vssa1 = 1
|
Net: mprj/la_data_in[50] |Net: vdda2_core
mgmt_protect/la_data_in_core[50] = 1 | mgmt_protect/vdda2 = 1
| user_analog_project_wrapper/vdda2 = 1
| chip_io_alt/vdda2 = 1
|
Net: mprj/la_data_in[51] |Net: vssa2_core
mgmt_protect/la_data_in_core[51] = 1 | mgmt_protect/vssa2 = 1
| user_analog_project_wrapper/vssa2 = 1
| chip_io_alt/vssa2 = 1
|
Net: mprj/la_data_in[52] |Net: vddio_core
mgmt_protect/la_data_in_core[52] = 1 | chip_io_alt/vddio = 1
| simple_por/vdd3v3 = 1
| xres_buf/VPWR = 1
|
Net: mprj/la_data_in[53] |Net: vssio_core
mgmt_protect/la_data_in_core[53] = 1 | chip_io_alt/vssio = 1
| simple_por/vss3v3 = 1
| xres_buf/VGND = 1
|
Net: mprj/la_data_in[54] |Net: \gpio_control_bidir_1[0] /spare_cell/
mgmt_protect/la_data_in_core[54] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[47] |Net: \gpio_control_bidir_1[0] /spare_cell/
mgmt_protect/la_data_out_core[47] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[48] |Net: \gpio_control_bidir_1[1] /spare_cell/
mgmt_protect/la_data_out_core[48] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[49] |Net: \gpio_control_bidir_1[1] /spare_cell/
mgmt_protect/la_data_out_core[49] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[50] |Net: \gpio_control_bidir_2[0] /spare_cell/
mgmt_protect/la_data_out_core[50] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[51] |Net: \gpio_control_bidir_2[0] /spare_cell/
mgmt_protect/la_data_out_core[51] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[52] |Net: \gpio_control_bidir_2[1] /spare_cell/
mgmt_protect/la_data_out_core[52] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[53] |Net: \gpio_control_bidir_2[1] /spare_cell/
mgmt_protect/la_data_out_core[53] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[54] |Net: \gpio_control_bidir_2[2] /spare_cell/
mgmt_protect/la_data_out_core[54] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[55] |Net: \gpio_control_bidir_2[2] /spare_cell/
mgmt_protect/la_data_out_core[55] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[56] |Net: \gpio_control_in_1[0] /spare_cell/sky
mgmt_protect/la_data_out_core[56] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[57] |Net: \gpio_control_in_1[0] /spare_cell/sky
mgmt_protect/la_data_out_core[57] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[58] |Net: \gpio_control_in_1[1] /spare_cell/sky
mgmt_protect/la_data_out_core[58] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[59] |Net: \gpio_control_in_1[1] /spare_cell/sky
mgmt_protect/la_data_out_core[59] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[60] |Net: \gpio_control_in_1[2] /spare_cell/sky
mgmt_protect/la_data_out_core[60] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_in[37] |Net: \gpio_control_in_1[2] /spare_cell/sky
mgmt_protect/la_data_in_core[37] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_in[38] |Net: \gpio_control_in_1[3] /spare_cell/sky
mgmt_protect/la_data_in_core[38] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_in[39] |Net: \gpio_control_in_1[3] /spare_cell/sky
mgmt_protect/la_data_in_core[39] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_in[40] |Net: \gpio_control_in_1[4] /spare_cell/sky
mgmt_protect/la_data_in_core[40] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_in[41] |Net: \gpio_control_in_1[4] /spare_cell/sky
mgmt_protect/la_data_in_core[41] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[26] |Net: \gpio_control_in_1[5] /spare_cell/sky
mgmt_protect/la_data_out_core[26] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[27] |Net: \gpio_control_in_1[5] /spare_cell/sky
mgmt_protect/la_data_out_core[27] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[28] |Net: \gpio_control_in_1a[0] /spare_cell/sk
mgmt_protect/la_data_out_core[28] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[29] |Net: \gpio_control_in_1a[0] /spare_cell/sk
mgmt_protect/la_data_out_core[29] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[30] |Net: \gpio_control_in_1a[1] /spare_cell/sk
mgmt_protect/la_data_out_core[30] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[31] |Net: \gpio_control_in_1a[1] /spare_cell/sk
mgmt_protect/la_data_out_core[31] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[32] |Net: \gpio_control_in_1a[2] /spare_cell/sk
mgmt_protect/la_data_out_core[32] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[33] |Net: \gpio_control_in_1a[2] /spare_cell/sk
mgmt_protect/la_data_out_core[33] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[34] |Net: \gpio_control_in_1a[3] /spare_cell/sk
mgmt_protect/la_data_out_core[34] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[35] |Net: \gpio_control_in_1a[3] /spare_cell/sk
mgmt_protect/la_data_out_core[35] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[36] |Net: \gpio_control_in_1a[4] /spare_cell/sk
mgmt_protect/la_data_out_core[36] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[37] |Net: \gpio_control_in_1a[4] /spare_cell/sk
mgmt_protect/la_data_out_core[37] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[38] |Net: \gpio_control_in_1a[5] /spare_cell/sk
mgmt_protect/la_data_out_core[38] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[39] |Net: \gpio_control_in_1a[5] /spare_cell/sk
mgmt_protect/la_data_out_core[39] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[26] |Net: \gpio_control_in_2[0] /spare_cell/sky
mgmt_protect/la_oenb_core[26] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[27] |Net: \gpio_control_in_2[0] /spare_cell/sky
mgmt_protect/la_oenb_core[27] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[28] |Net: \gpio_control_in_2[1] /spare_cell/sky
mgmt_protect/la_oenb_core[28] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[29] |Net: \gpio_control_in_2[1] /spare_cell/sky
mgmt_protect/la_oenb_core[29] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[30] |Net: \gpio_control_in_2[2] /spare_cell/sky
mgmt_protect/la_oenb_core[30] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[31] |Net: \gpio_control_in_2[2] /spare_cell/sky
mgmt_protect/la_oenb_core[31] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[32] |Net: \gpio_control_in_2[3] /spare_cell/sky
mgmt_protect/la_oenb_core[32] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[33] |Net: \gpio_control_in_2[3] /spare_cell/sky
mgmt_protect/la_oenb_core[33] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[34] |Net: \gpio_control_in_2[4] /spare_cell/sky
mgmt_protect/la_oenb_core[34] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[35] |Net: \gpio_control_in_2[4] /spare_cell/sky
mgmt_protect/la_oenb_core[35] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[36] |Net: \gpio_control_in_2[5] /spare_cell/sky
mgmt_protect/la_oenb_core[36] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[37] |Net: \gpio_control_in_2[5] /spare_cell/sky
mgmt_protect/la_oenb_core[37] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[38] |Net: \gpio_control_in_2[6] /spare_cell/sky
mgmt_protect/la_oenb_core[38] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[39] |Net: \gpio_control_in_2[6] /spare_cell/sky
mgmt_protect/la_oenb_core[39] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[40] |Net: \gpio_control_in_2[7] /spare_cell/sky
mgmt_protect/la_oenb_core[40] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[41] |Net: \gpio_control_in_2[7] /spare_cell/sky
mgmt_protect/la_oenb_core[41] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[42] |Net: \gpio_control_in_2[8] /spare_cell/sky
mgmt_protect/la_oenb_core[42] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[43] |Net: \gpio_control_in_2[8] /spare_cell/sky
mgmt_protect/la_oenb_core[43] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[44] |Net: \gpio_control_in_2[9] /spare_cell/sky
mgmt_protect/la_oenb_core[44] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_oenb[45] |Net: \gpio_control_in_2[9] /spare_cell/sky
mgmt_protect/la_oenb_core[45] = 1 | sky130_fd_sc_hd__nand2_2/A = 1
| sky130_fd_sc_hd__nor2_2/A = 1
| sky130_fd_sc_hd__nor2_2/VGND = 1
|
Net: mprj/la_data_out[40] |Net: \la_oenb_mprj[47]
mgmt_protect/la_data_out_core[40] = 1 | mgmt_protect/la_oenb_mprj[47] = 1
| mgmt_core_wrapper/la_oenb[47] = 1
|
Net: mprj/la_data_out[41] |Net: \la_oenb_mprj[46]
mgmt_protect/la_data_out_core[41] = 1 | mgmt_protect/la_oenb_mprj[46] = 1
| mgmt_core_wrapper/la_oenb[46] = 1
|
Net: mprj/la_data_out[42] |Net: \la_oenb_mprj[45]
mgmt_protect/la_data_out_core[42] = 1 | mgmt_protect/la_oenb_mprj[45] = 1
| mgmt_core_wrapper/la_oenb[45] = 1
|
Net: mprj/la_data_out[43] |Net: \la_oenb_mprj[44]
mgmt_protect/la_data_out_core[43] = 1 | mgmt_protect/la_oenb_mprj[44] = 1
| mgmt_core_wrapper/la_oenb[44] = 1
|
Net: mprj/la_data_out[44] |Net: \la_oenb_mprj[43]
mgmt_protect/la_data_out_core[44] = 1 | mgmt_protect/la_oenb_mprj[43] = 1
| mgmt_core_wrapper/la_oenb[43] = 1
|
Net: mprj/la_data_out[45] |Net: \la_oenb_mprj[42]
mgmt_protect/la_data_out_core[45] = 1 | mgmt_protect/la_oenb_mprj[42] = 1
| mgmt_core_wrapper/la_oenb[42] = 1
|
Net: mprj/la_data_out[46] |Net: \mprj_adr_o_user[15]
mgmt_protect/la_data_out_core[46] = 1 | mgmt_protect/mprj_adr_o_user[15] = 1
| user_analog_project_wrapper/wbs_adr_i[15
|
Net: mprj/la_data_in[42] |Net: \mprj_adr_o_user[17]
mgmt_protect/la_data_in_core[42] = 1 | mgmt_protect/mprj_adr_o_user[17] = 1
| user_analog_project_wrapper/wbs_adr_i[17
|
Net: mprj/la_data_in[43] |Net: \mprj_adr_o_user[19]
mgmt_protect/la_data_in_core[43] = 1 | mgmt_protect/mprj_adr_o_user[19] = 1
| user_analog_project_wrapper/wbs_adr_i[19
|
Net: mprj/la_data_in[44] |Net: \mprj_dat_i_core[11]
mgmt_protect/la_data_in_core[44] = 1 | mgmt_protect/mprj_dat_i_core[11] = 1
| mgmt_core_wrapper/mprj_dat_i[11] = 1
|
Net: mprj/la_data_in[45] |Net: \mprj_dat_i_core[15]
mgmt_protect/la_data_in_core[45] = 1 | mgmt_protect/mprj_dat_i_core[15] = 1
| mgmt_core_wrapper/mprj_dat_i[15] = 1
|
Net: mprj/la_data_in[46] |Net: \mprj_dat_i_core[19]
mgmt_protect/la_data_in_core[46] = 1 | mgmt_protect/mprj_dat_i_core[19] = 1
| mgmt_core_wrapper/mprj_dat_i[19] = 1
|
Net: mprj/la_data_in[26] |Net: \mprj_dat_i_core[23]
mgmt_protect/la_data_in_core[26] = 1 | mgmt_protect/mprj_dat_i_core[23] = 1
| mgmt_core_wrapper/mprj_dat_i[23] = 1
|
Net: mprj/la_data_in[27] |Net: \mprj_dat_i_core[27]
mgmt_protect/la_data_in_core[27] = 1 | mgmt_protect/mprj_dat_i_core[27] = 1
| mgmt_core_wrapper/mprj_dat_i[27] = 1
|
Net: mprj/la_data_in[28] |Net: \mprj_dat_i_core[31]
mgmt_protect/la_data_in_core[28] = 1 | mgmt_protect/mprj_dat_i_core[31] = 1
| mgmt_core_wrapper/mprj_dat_i[31] = 1
|
Net: mprj/la_data_in[29] |Net: \mprj_adr_o_user[3]
mgmt_protect/la_data_in_core[29] = 1 | mgmt_protect/mprj_adr_o_user[3] = 1
| user_analog_project_wrapper/wbs_adr_i[3]
|
Net: mprj/la_data_in[30] |Net: \mprj_adr_o_user[7]
mgmt_protect/la_data_in_core[30] = 1 | mgmt_protect/mprj_adr_o_user[7] = 1
| user_analog_project_wrapper/wbs_adr_i[7]
|
Net: mprj/la_data_in[31] |Net: \mprj_adr_o_user[11]
mgmt_protect/la_data_in_core[31] = 1 | mgmt_protect/mprj_adr_o_user[11] = 1
| user_analog_project_wrapper/wbs_adr_i[11
|
Net: mprj/la_data_in[32] |Net: \mprj_adr_o_user[23]
mgmt_protect/la_data_in_core[32] = 1 | mgmt_protect/mprj_adr_o_user[23] = 1
| user_analog_project_wrapper/wbs_adr_i[23
|
Net: mprj/la_data_in[33] |Net: \mprj_dat_i_user[28]
mgmt_protect/la_data_in_core[33] = 1 | mgmt_protect/mprj_dat_i_user[28] = 1
| user_analog_project_wrapper/wbs_dat_o[28
|
Net: mprj/la_data_in[34] |Net: \mprj_io_in_3v3[25]
mgmt_protect/la_data_in_core[34] = 1 | user_analog_project_wrapper/io_in_3v3[25
| chip_io_alt/mprj_io_in_3v3[25] = 1
|
Net: mprj/la_data_in[35] |Net: \user_gpio_analog[7]
mgmt_protect/la_data_in_core[35] = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[7] = 1
|
Net: mprj/la_data_in[36] |Net: \mprj_dat_o_user[18]
mgmt_protect/la_data_in_core[36] = 1 | mgmt_protect/mprj_dat_o_user[18] = 1
| user_analog_project_wrapper/wbs_dat_i[18
|
Net: mprj/la_data_out[17] |Net: \user_gpio_analog[8]
mgmt_protect/la_data_out_core[17] = 1 | user_analog_project_wrapper/gpio_analog[
| chip_io_alt/mprj_gpio_analog[8] = 1
|
Net: mprj/la_data_out[18] |Net: \mprj_dat_i_user[24]
mgmt_protect/la_data_out_core[18] = 1 | mgmt_protect/mprj_dat_i_user[24] = 1
| user_analog_project_wrapper/wbs_dat_o[24
|
Net: mprj/la_data_out[19] |Net: \mprj_dat_i_core[3]
mgmt_protect/la_data_out_core[19] = 1 | mgmt_protect/mprj_dat_i_core[3] = 1
| mgmt_core_wrapper/mprj_dat_i[3] = 1
|
Net: mprj/la_data_out[20] |Net: \mprj_dat_i_core[5]
mgmt_protect/la_data_out_core[20] = 1 | mgmt_protect/mprj_dat_i_core[5] = 1
| mgmt_core_wrapper/mprj_dat_i[5] = 1
|
Net: mprj/la_data_out[21] |Net: \mprj_dat_i_core[6]
mgmt_protect/la_data_out_core[21] = 1 | mgmt_protect/mprj_dat_i_core[6] = 1
| mgmt_core_wrapper/mprj_dat_i[6] = 1
|
Net: mprj/la_data_out[22] |Net: \mprj_dat_i_core[8]
mgmt_protect/la_data_out_core[22] = 1 | mgmt_protect/mprj_dat_i_core[8] = 1
| mgmt_core_wrapper/mprj_dat_i[8] = 1
|
Net: mprj/la_data_out[23] |Net: \mprj_io_in_3v3[14]
mgmt_protect/la_data_out_core[23] = 1 | user_analog_project_wrapper/io_in_3v3[14
| chip_io_alt/mprj_io_in_3v3[14] = 1
|
Net: mprj/la_oenb[12] |Net: \la_oenb_mprj[19]
mgmt_protect/la_oenb_core[12] = 1 | mgmt_protect/la_oenb_mprj[19] = 1
| mgmt_core_wrapper/la_oenb[19] = 1
|
Net: mprj/la_oenb[13] |Net: \la_oenb_mprj[23]
mgmt_protect/la_oenb_core[13] = 1 | mgmt_protect/la_oenb_mprj[23] = 1
| mgmt_core_wrapper/la_oenb[23] = 1
|
Net: mprj/la_oenb[14] |Net: \la_oenb_mprj[27]
mgmt_protect/la_oenb_core[14] = 1 | mgmt_protect/la_oenb_mprj[27] = 1
| mgmt_core_wrapper/la_oenb[27] = 1
|
Net: mprj/la_oenb[15] |Net: \la_oenb_mprj[31]
mgmt_protect/la_oenb_core[15] = 1 | mgmt_protect/la_oenb_mprj[31] = 1
| mgmt_core_wrapper/la_oenb[31] = 1
|
Net: mprj/la_oenb[16] |Net: \mprj_adr_o_user[27]
mgmt_protect/la_oenb_core[16] = 1 | mgmt_protect/mprj_adr_o_user[27] = 1
| user_analog_project_wrapper/wbs_adr_i[27
|
Net: mprj/la_oenb[17] |Net: \mprj_adr_o_user[31]
mgmt_protect/la_oenb_core[17] = 1 | mgmt_protect/mprj_adr_o_user[31] = 1
| user_analog_project_wrapper/wbs_adr_i[31
|
Net: mprj/la_oenb[18] |Net: \la_oenb_mprj[3]
mgmt_protect/la_oenb_core[18] = 1 | mgmt_protect/la_oenb_mprj[3] = 1
| mgmt_core_wrapper/la_oenb[3] = 1
|
Net: mprj/la_oenb[19] |Net: \la_oenb_mprj[7]
mgmt_protect/la_oenb_core[19] = 1 | mgmt_protect/la_oenb_mprj[7] = 1
| mgmt_core_wrapper/la_oenb[7] = 1
|
Net: mprj/la_oenb[20] |Net: \la_oenb_mprj[9]
mgmt_protect/la_oenb_core[20] = 1 | mgmt_protect/la_oenb_mprj[9] = 1
| mgmt_core_wrapper/la_oenb[9] = 1
|
Net: mprj/la_oenb[21] |Net: \la_oenb_mprj[11]
mgmt_protect/la_oenb_core[21] = 1 | mgmt_protect/la_oenb_mprj[11] = 1
| mgmt_core_wrapper/la_oenb[11] = 1
|
Net: mprj/la_oenb[22] |Net: \la_oenb_mprj[13]
mgmt_protect/la_oenb_core[22] = 1 | mgmt_protect/la_oenb_mprj[13] = 1
| mgmt_core_wrapper/la_oenb[13] = 1
|
Net: mprj/la_oenb[23] |Net: \la_oenb_mprj[15]
mgmt_protect/la_oenb_core[23] = 1 | mgmt_protect/la_oenb_mprj[15] = 1
| mgmt_core_wrapper/la_oenb[15] = 1
|
Net: mprj/la_oenb[24] |Net: \la_oenb_mprj[17]
mgmt_protect/la_oenb_core[24] = 1 | mgmt_protect/la_oenb_mprj[17] = 1
| mgmt_core_wrapper/la_oenb[17] = 1
|
Net: mprj/la_oenb[25] |Net: \la_oenb_mprj[35]
mgmt_protect/la_oenb_core[25] = 1 | mgmt_protect/la_oenb_mprj[35] = 1
| mgmt_core_wrapper/la_oenb[35] = 1
|
Net: mprj/la_data_in[11] |Net: \mprj_dat_i_core[9]
mgmt_protect/la_data_in_core[11] = 1 | mgmt_protect/mprj_dat_i_core[9] = 1
| mgmt_core_wrapper/mprj_dat_i[9] = 1
|
Net: mprj/la_oenb[5] |Net: \mprj_dat_i_core[2]
mgmt_protect/la_oenb_core[5] = 1 | mgmt_protect/mprj_dat_i_core[2] = 1
| mgmt_core_wrapper/mprj_dat_i[2] = 1
|
Net: mprj/la_data_in[8] |Net: \mprj_dat_i_user[23]
mgmt_protect/la_data_in_core[8] = 1 | mgmt_protect/mprj_dat_i_user[23] = 1
| user_analog_project_wrapper/wbs_dat_o[23
|
Net: mprj/la_data_in[10] |Net: \la_oenb_mprj[41]
mgmt_protect/la_data_in_core[10] = 1 | mgmt_protect/la_oenb_mprj[41] = 1
| mgmt_core_wrapper/la_oenb[41] = 1
|
Net: mprj/la_data_in[12] |Net: vdda_core
mgmt_protect/la_data_in_core[12] = 1 | chip_io_alt/vdda = 1
|
Net: mprj/la_data_in[13] |Net: \mprj_dat_i_core[1]
mgmt_protect/la_data_in_core[13] = 1 | mgmt_protect/mprj_dat_i_core[1] = 1
| mgmt_core_wrapper/mprj_dat_i[1] = 1
|
Net: mprj/la_data_in[14] |Net: \mprj_dat_i_core[0]
mgmt_protect/la_data_in_core[14] = 1 | mgmt_protect/mprj_dat_i_core[0] = 1
| mgmt_core_wrapper/mprj_dat_i[0] = 1
|
Net: mprj/la_data_in[15] |Net: \mprj_dat_i_user[22]
mgmt_protect/la_data_in_core[15] = 1 | mgmt_protect/mprj_dat_i_user[22] = 1
| user_analog_project_wrapper/wbs_dat_o[22
|
Net: mprj/la_data_in[16] |Net: \la_oenb_mprj[40]
mgmt_protect/la_data_in_core[16] = 1 | mgmt_protect/la_oenb_mprj[40] = 1
| mgmt_core_wrapper/la_oenb[40] = 1
|
Net: mprj/la_oenb[6] |Net: \la_oenb_mprj[39]
mgmt_protect/la_oenb_core[6] = 1 | mgmt_protect/la_oenb_mprj[39] = 1
| mgmt_core_wrapper/la_oenb[39] = 1
|
Net: mprj/la_data_in[17] |Net: \mprj_io_in_3v3[19]
mgmt_protect/la_data_in_core[17] = 1 | user_analog_project_wrapper/io_in_3v3[19
| chip_io_alt/mprj_io_in_3v3[19] = 1
|
Net: mprj/la_data_in[18] |Net: vssa_core
mgmt_protect/la_data_in_core[18] = 1 | chip_io_alt/vssa = 1
|
Net: mprj/la_data_in[19] |Net: \mprj_io_in_3v3[3]
mgmt_protect/la_data_in_core[19] = 1 | user_analog_project_wrapper/io_in_3v3[3]
| chip_io_alt/mprj_io_in_3v3[3] = 1
|
Net: mprj/la_data_in[9] |Net: \gpio_control_bidir_2[1] /gpio_logic1
mgmt_protect/la_data_in_core[9] = 1 | sky130_fd_sc_hd__and2_2/A = 1
| gpio_logic_high/gpio_logic1 = 1
|
Net: mprj/la_data_in[20] |Net: \mprj_dat_i_user[21]
mgmt_protect/la_data_in_core[20] = 1 | mgmt_protect/mprj_dat_i_user[21] = 1
| user_analog_project_wrapper/wbs_dat_o[21
|
Net: mprj/la_data_out[6] |Net: \la_oenb_mprj[38]
mgmt_protect/la_data_out_core[6] = 1 | mgmt_protect/la_oenb_mprj[38] = 1
| mgmt_core_wrapper/la_oenb[38] = 1
|
Net: mprj/la_data_in[21] |Net: \mprj_dat_i_user[31]
mgmt_protect/la_data_in_core[21] = 1 | mgmt_protect/mprj_dat_i_user[31] = 1
| user_analog_project_wrapper/wbs_dat_o[31
|
Net: mprj/la_oenb[7] |Net: \mprj_dat_i_user[20]
mgmt_protect/la_oenb_core[7] = 1 | mgmt_protect/mprj_dat_i_user[20] = 1
| user_analog_project_wrapper/wbs_dat_o[20
|
Net: mprj/la_data_in[22] |Net: \mprj_io_in_3v3[7]
mgmt_protect/la_data_in_core[22] = 1 | user_analog_project_wrapper/io_in_3v3[7]
| chip_io_alt/mprj_io_in_3v3[7] = 1
|
Net: mprj/la_data_in[23] |Net: \la_oenb_mprj[37]
mgmt_protect/la_data_in_core[23] = 1 | mgmt_protect/la_oenb_mprj[37] = 1
| mgmt_core_wrapper/la_oenb[37] = 1
|
Net: mprj/la_data_in[24] |Net: \la_oenb_mprj[36]
mgmt_protect/la_data_in_core[24] = 1 | mgmt_protect/la_oenb_mprj[36] = 1
| mgmt_core_wrapper/la_oenb[36] = 1
|
Net: mprj/la_data_in[25] |Net: \gpio_control_bidir_1[0] /spare_cell/
mgmt_protect/la_data_in_core[25] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[10] |Net: \gpio_control_bidir_1[0] /spare_cell/
mgmt_protect/la_oenb_core[10] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[24] |Net: \gpio_control_bidir_1[1] /spare_cell/
mgmt_protect/la_data_out_core[24] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[10] |Net: \gpio_control_bidir_1[1] /spare_cell/
mgmt_protect/la_data_out_core[10] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[25] |Net: \gpio_control_bidir_2[0] /spare_cell/
mgmt_protect/la_data_out_core[25] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[7] |Net: \gpio_control_bidir_2[0] /spare_cell/
mgmt_protect/la_data_in_core[7] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[7] |Net: \gpio_control_bidir_2[1] /spare_cell/
mgmt_protect/la_data_out_core[7] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[8] |Net: \gpio_control_bidir_2[1] /spare_cell/
mgmt_protect/la_oenb_core[8] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[6] |Net: \gpio_control_bidir_2[2] /spare_cell/
mgmt_protect/la_data_in_core[6] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[12] |Net: \gpio_control_bidir_2[2] /spare_cell/
mgmt_protect/la_data_out_core[12] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[13] |Net: \gpio_control_in_1[0] /spare_cell/sky
mgmt_protect/la_data_out_core[13] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[14] |Net: \gpio_control_in_1[0] /spare_cell/sky
mgmt_protect/la_data_out_core[14] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[9] |Net: \gpio_control_in_1[1] /spare_cell/sky
mgmt_protect/la_data_out_core[9] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[15] |Net: \gpio_control_in_1[1] /spare_cell/sky
mgmt_protect/la_data_out_core[15] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[16] |Net: \gpio_control_in_1[2] /spare_cell/sky
mgmt_protect/la_data_out_core[16] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[11] |Net: \gpio_control_in_1[2] /spare_cell/sky
mgmt_protect/la_data_out_core[11] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[11] |Net: \gpio_control_in_1[3] /spare_cell/sky
mgmt_protect/la_oenb_core[11] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[9] |Net: \gpio_control_in_1[3] /spare_cell/sky
mgmt_protect/la_oenb_core[9] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[8] |Net: \gpio_control_in_1[4] /spare_cell/sky
mgmt_protect/la_data_out_core[8] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[1] |Net: \gpio_control_in_1[4] /spare_cell/sky
mgmt_protect/la_data_out_core[1] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[0] |Net: \gpio_control_in_1[5] /spare_cell/sky
mgmt_protect/la_data_in_core[0] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[2] |Net: \gpio_control_in_1[5] /spare_cell/sky
mgmt_protect/la_oenb_core[2] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[0] |Net: \gpio_control_in_1a[0] /spare_cell/sk
mgmt_protect/la_data_out_core[0] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[1] |Net: \gpio_control_in_1a[0] /spare_cell/sk
mgmt_protect/la_data_in_core[1] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[2] |Net: \gpio_control_in_1a[1] /spare_cell/sk
mgmt_protect/la_data_in_core[2] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[0] |Net: \gpio_control_in_1a[1] /spare_cell/sk
mgmt_protect/la_oenb_core[0] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[5] |Net: \gpio_control_in_1a[2] /spare_cell/sk
mgmt_protect/la_data_in_core[5] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[4] |Net: \gpio_control_in_1a[2] /spare_cell/sk
mgmt_protect/la_data_in_core[4] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[1] |Net: \gpio_control_in_1a[3] /spare_cell/sk
mgmt_protect/la_oenb_core[1] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_in[3] |Net: \gpio_control_in_1a[3] /spare_cell/sk
mgmt_protect/la_data_in_core[3] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_oenb[3] |Net: \gpio_control_in_1a[4] /spare_cell/sk
mgmt_protect/la_oenb_core[3] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[5] |Net: \gpio_control_in_1a[4] /spare_cell/sk
mgmt_protect/la_data_out_core[5] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[4] |Net: \gpio_control_in_1a[5] /spare_cell/sk
mgmt_protect/la_data_out_core[4] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[3] |Net: \gpio_control_in_1a[5] /spare_cell/sk
mgmt_protect/la_data_out_core[3] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/la_data_out[2] |Net: \gpio_control_in_2[0] /spare_cell/sky
mgmt_protect/la_data_out_core[2] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[18] |Net: \gpio_control_in_2[0] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[18] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[19] |Net: \gpio_control_in_2[1] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[19] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[20] |Net: \gpio_control_in_2[1] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[20] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[21] |Net: \gpio_control_in_2[2] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[21] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[22] |Net: \gpio_control_in_2[2] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[22] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[23] |Net: \gpio_control_in_2[3] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[23] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[24] |Net: \gpio_control_in_2[3] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[24] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[25] |Net: \gpio_control_in_2[4] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[25] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[26] |Net: \gpio_control_in_2[4] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[26] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[27] |Net: \gpio_control_in_2[5] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[27] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[28] |Net: \gpio_control_in_2[5] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[28] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[29] |Net: \gpio_control_in_2[6] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[29] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[30] |Net: \gpio_control_in_2[6] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[30] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_adr_i[31] |Net: \gpio_control_in_2[7] /spare_cell/sky
mgmt_protect/mprj_adr_o_user[31] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_dat_o[17] |Net: \gpio_control_in_2[7] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[17] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_dat_o[18] |Net: \gpio_control_in_2[8] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[18] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_dat_o[19] |Net: \gpio_control_in_2[8] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[19] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_dat_o[20] |Net: \gpio_control_in_2[9] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[20] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_dat_o[21] |Net: \gpio_control_in_2[9] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[21] = 1 | sky130_fd_sc_hd__inv_2/VGND = 1
|
Net: mprj/wbs_dat_o[22] |Net: \gpio_control_bidir_1[0] /spare_cell/
mgmt_protect/mprj_dat_i_user[22] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[23] |Net: \gpio_control_bidir_1[1] /spare_cell/
mgmt_protect/mprj_dat_i_user[23] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[24] |Net: \gpio_control_bidir_2[0] /spare_cell/
mgmt_protect/mprj_dat_i_user[24] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[25] |Net: \gpio_control_bidir_2[1] /spare_cell/
mgmt_protect/mprj_dat_i_user[25] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[26] |Net: \gpio_control_bidir_2[2] /spare_cell/
mgmt_protect/mprj_dat_i_user[26] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[27] |Net: \gpio_control_in_1[0] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[27] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[28] |Net: \gpio_control_in_1[1] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[28] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[29] |Net: \gpio_control_in_1[2] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[29] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[30] |Net: \gpio_control_in_1[3] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[30] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[31] |Net: \gpio_control_in_1[4] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[31] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[17] |Net: \gpio_control_in_1[5] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[17] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[18] |Net: \gpio_control_in_1a[0] /spare_cell/sk
mgmt_protect/mprj_dat_o_user[18] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[19] |Net: \gpio_control_in_1a[1] /spare_cell/sk
mgmt_protect/mprj_dat_o_user[19] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[20] |Net: \gpio_control_in_1a[2] /spare_cell/sk
mgmt_protect/mprj_dat_o_user[20] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[21] |Net: \gpio_control_in_1a[3] /spare_cell/sk
mgmt_protect/mprj_dat_o_user[21] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[22] |Net: \gpio_control_in_1a[4] /spare_cell/sk
mgmt_protect/mprj_dat_o_user[22] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[23] |Net: \gpio_control_in_1a[5] /spare_cell/sk
mgmt_protect/mprj_dat_o_user[23] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[24] |Net: \gpio_control_in_2[0] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[24] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[25] |Net: \gpio_control_in_2[1] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[25] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[26] |Net: \gpio_control_in_2[2] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[26] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[27] |Net: \gpio_control_in_2[3] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[27] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[28] |Net: \gpio_control_in_2[4] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[28] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[29] |Net: \gpio_control_in_2[5] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[29] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[30] |Net: \gpio_control_in_2[6] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[30] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_i[31] |Net: \gpio_control_in_2[7] /spare_cell/sky
mgmt_protect/mprj_dat_o_user[31] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/la_oenb[4] |Net: \gpio_control_in_2[8] /spare_cell/sky
mgmt_protect/la_oenb_core[4] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_dat_o[1] |Net: \gpio_control_in_2[9] /spare_cell/sky
mgmt_protect/mprj_dat_i_user[1] = 1 | sky130_fd_sc_hd__conb_1/VNB = 1
|
Net: mprj/wbs_adr_i[14] |Net: dummy_7789
mgmt_protect/mprj_adr_o_user[14] = 1 | chip_io_alt/proxyxresloop = 1
|
Net: mprj/wbs_adr_i[15] |Net: dummy_7790
mgmt_protect/mprj_adr_o_user[15] = 1 | chip_io_alt/proxyxres_vss_loop = 1
|
Net: mprj/wbs_adr_i[16] |Net: dummy_7791
mgmt_protect/mprj_adr_o_user[16] = 1 | chip_io_alt/proxyw_694469_865869# = 1
|
Net: mprj/wbs_adr_i[17] |Net: dummy_7792
mgmt_protect/mprj_adr_o_user[17] = 1 | chip_io_alt/proxyw_23367_407274# = 1
|
Net: mprj/wbs_ack_o |Net: dummy_7793
mgmt_protect/mprj_ack_i_user = 1 | chip_io_alt/proxyw_694469_100152# = 1
|
Net: mprj/wbs_adr_i[0] |Net: dummy_7794
mgmt_protect/mprj_adr_o_user[0] = 1 | chip_io_alt/proxyw_23367_534874# = 1
|
Net: mprj/wbs_adr_i[2] |Net: dummy_7795
mgmt_protect/mprj_adr_o_user[2] = 1 | chip_io_alt/proxyw_404752_21253# = 1
|
Net: mprj/wbs_adr_i[1] |Net: dummy_7796
mgmt_protect/mprj_adr_o_user[1] = 1 | chip_io_alt/proxyw_459552_23367# = 1
|
Net: mprj/wbs_adr_i[10] |Net: dummy_7797
mgmt_protect/mprj_adr_o_user[10] = 1 | chip_io_alt/proxyw_23367_280765# = 1
|
Net: mprj/wbs_adr_i[3] |Net: dummy_7798
mgmt_protect/mprj_adr_o_user[3] = 1 | chip_io_alt/proxyw_692253_776670# = 1
|
Net: mprj/wbs_dat_o[2] |Net: dummy_7799
mgmt_protect/mprj_dat_i_user[2] = 1 | chip_io_alt/proxyw_23367_710765# = 1
|
Net: mprj/wbs_adr_i[4] |Net: dummy_7800
mgmt_protect/mprj_adr_o_user[4] = 1 | chip_io_alt/proxyw_78010_1007543# = 1
|
Net: mprj/wbs_adr_i[5] |Net: dummy_7801
mgmt_protect/mprj_adr_o_user[5] = 1 | chip_io_alt/proxyw_692355_547952# = 1
|
Net: mprj/wbs_dat_o[3] |Net: dummy_7802
mgmt_protect/mprj_dat_i_user[3] = 1 | chip_io_alt/proxyw_23367_537965# = 1
|
Net: mprj/wbs_dat_o[4] |Net: dummy_7803
mgmt_protect/mprj_dat_i_user[4] = 1 | chip_io_alt/proxyw_21151_364074# = 1
|
Net: mprj/wbs_dat_o[5] |Net: dummy_7804
mgmt_protect/mprj_dat_i_user[5] = 1 | chip_io_alt/proxyw_459552_21253# = 1
|
Net: mprj/wbs_dat_o[6] |Net: dummy_7805
mgmt_protect/mprj_dat_i_user[6] = 1 | chip_io_alt/proxyw_694469_145352# = 1
|
Net: mprj/wbs_dat_o[7] |Net: dummy_7806
mgmt_protect/mprj_dat_i_user[7] = 1 | chip_io_alt/proxyw_692355_593152# = 1
|
Net: mprj/wbs_dat_o[8] |Net: dummy_7807
mgmt_protect/mprj_dat_i_user[8] = 1 | chip_io_alt/proxyw_694469_190352# = 1
|
Net: mprj/wbs_dat_o[9] |Net: dummy_7808
mgmt_protect/mprj_dat_i_user[9] = 1 | chip_io_alt/proxyw_349952_23367# = 1
|
Net: mprj/wbs_dat_i[0] |Net: dummy_7809
mgmt_protect/mprj_dat_o_user[0] = 1 | chip_io_alt/proxyw_692355_325552# = 1
|
Net: mprj/wbs_dat_i[10] |Net: dummy_7810
mgmt_protect/mprj_dat_o_user[10] = 1 | chip_io_alt/proxyw_189869_23367# = 1
|
Net: mprj/wbs_dat_i[11] |Net: dummy_7811
mgmt_protect/mprj_dat_o_user[11] = 1 | chip_io_alt/proxyw_694469_235552# = 1
|
Net: mprj/wbs_dat_i[12] |Net: dummy_7812
mgmt_protect/mprj_dat_o_user[12] = 1 | chip_io_alt/proxyw_21151_794074# = 1
|
Net: mprj/wbs_dat_i[13] |Net: dummy_7813
mgmt_protect/mprj_dat_o_user[13] = 1 | chip_io_alt/proxyw_692355_683352# = 1
|
Net: mprj/wbs_dat_i[14] |Net: dummy_7814
mgmt_protect/mprj_dat_o_user[14] = 1 | chip_io_alt/proxyw_21253_194365# = 1
|
Net: mprj/wbs_dat_i[15] |Net: dummy_7815
mgmt_protect/mprj_dat_o_user[15] = 1 | chip_io_alt/proxyw_694469_280552# = 1
|
Net: mprj/wbs_dat_i[16] |Net: dummy_7816
mgmt_protect/mprj_dat_o_user[16] = 1 | chip_io_alt/proxyw_21253_624365# = 1
|
Net: mprj/wbs_adr_i[6] |Net: dummy_7817
mgmt_protect/mprj_adr_o_user[6] = 1 | chip_io_alt/proxyw_295152_23367# = 1
|
Net: mprj/wbs_adr_i[7] |Net: dummy_7818
mgmt_protect/mprj_adr_o_user[7] = 1 | chip_io_alt/proxyw_349952_21253# = 1
|
Net: mprj/wbs_adr_i[8] |Net: dummy_7819
mgmt_protect/mprj_adr_o_user[8] = 1 | chip_io_alt/proxyw_23367_578074# = 1
|
Net: mprj/wbs_dat_i[1] |Net: dummy_7820
mgmt_protect/mprj_dat_o_user[1] = 1 | chip_io_alt/proxyw_692253_551270# = 1
|
Net: mprj/wbs_adr_i[9] |Net: dummy_7821
mgmt_protect/mprj_adr_o_user[9] = 1 | chip_io_alt/proxyw_694469_370752# = 1
|
Net: mprj/wbs_cyc_i |Net: dummy_7822
mgmt_protect/mprj_cyc_o_user = 1 | chip_io_alt/proxyw_189869_21253# = 1
|
Net: mprj/wbs_dat_o[0] |Net: dummy_7823
mgmt_protect/mprj_dat_i_user[0] = 1 | chip_io_alt/proxyw_21151_277674# = 1
|
Net: mprj/wbs_dat_o[10] |Net: dummy_7824
mgmt_protect/mprj_dat_i_user[10] = 1 | chip_io_alt/proxyw_692253_641470# = 1
|
Net: mprj/wbs_dat_o[11] |Net: dummy_7825
mgmt_protect/mprj_dat_i_user[11] = 1 | chip_io_alt/proxyw_295152_21253# = 1
|
Net: mprj/wbs_dat_o[12] |Net: dummy_7826
mgmt_protect/mprj_dat_i_user[12] = 1 | chip_io_alt/proxyw_21151_707674# = 1
|
Net: mprj/wbs_dat_o[13] |Net: dummy_7827
mgmt_protect/mprj_dat_i_user[13] = 1 | chip_io_alt/proxyw_23367_234474# = 1
|
Net: mprj/wbs_dat_o[14] |Net: dummy_7828
mgmt_protect/mprj_dat_i_user[14] = 1 | chip_io_alt/proxyw_692355_100152# = 1
|
Net: mprj/wbs_dat_o[15] |Net: dummy_7829
mgmt_protect/mprj_dat_i_user[15] = 1 | chip_io_alt/proxyw_694469_776669# = 1
|
Net: mprj/wbs_dat_o[16] |Net: dummy_7830
mgmt_protect/mprj_dat_i_user[16] = 1 | chip_io_alt/proxyw_692253_596470# = 1
|
Net: mprj/wbs_dat_i[2] |Net: dummy_7831
mgmt_protect/mprj_dat_o_user[2] = 1 | chip_io_alt/proxyw_692253_731670# = 1
|
Net: mprj/wbs_adr_i[11] |Net: dummy_7832
mgmt_protect/mprj_adr_o_user[11] = 1 | chip_io_alt/proxyw_21253_280765# = 1
|
Net: mprj/wbs_adr_i[12] |Net: dummy_7833
mgmt_protect/mprj_adr_o_user[12] = 1 | chip_io_alt/proxyw_692253_328870# = 1
|
Net: mprj/wbs_dat_i[3] |Net: dummy_7834
mgmt_protect/mprj_dat_o_user[3] = 1 | chip_io_alt/proxyw_23367_410365# = 1
|
Net: mprj/wbs_dat_i[4] |Net: dummy_7835
mgmt_protect/mprj_dat_o_user[4] = 1 | chip_io_alt/proxyw_21253_710765# = 1
|
Net: mprj/wbs_dat_i[5] |Net: dummy_7836
mgmt_protect/mprj_dat_o_user[5] = 1 | chip_io_alt/proxyw_462869_23367# = 1
|
Net: mprj/wbs_dat_i[6] |Net: dummy_7837
mgmt_protect/mprj_dat_o_user[6] = 1 | chip_io_alt/proxyw_23367_237565# = 1
|
Net: mprj/wbs_dat_i[7] |Net: dummy_7838
mgmt_protect/mprj_dat_o_user[7] = 1 | chip_io_alt/proxyw_21253_537965# = 1
|
Net: mprj/wbs_dat_i[8] |Net: dummy_7839
mgmt_protect/mprj_dat_o_user[8] = 1 | chip_io_alt/proxyw_23367_664474# = 1
|
Net: mprj/wbs_dat_i[9] |Net: dummy_7840
mgmt_protect/mprj_dat_o_user[9] = 1 | chip_io_alt/proxyw_692253_686670# = 1
|
Net: mprj/wbs_sel_i[0] |Net: dummy_7841
mgmt_protect/mprj_sel_o_user[0] = 1 | chip_io_alt/proxyw_21151_191274# = 1
|
Net: mprj/wbs_sel_i[1] |Net: dummy_7842
mgmt_protect/mprj_sel_o_user[1] = 1 | chip_io_alt/proxyw_692253_374070# = 1
|
Net: mprj/wbs_sel_i[2] |Net: dummy_7843
mgmt_protect/mprj_sel_o_user[2] = 1 | chip_io_alt/proxyw_692355_145352# = 1
|
Net: mprj/wbs_sel_i[3] |Net: dummy_7844
mgmt_protect/mprj_sel_o_user[3] = 1 | chip_io_alt/proxyw_21151_621274# = 1
|
Net: mprj/wbs_stb_i |Net: dummy_7845
mgmt_protect/mprj_stb_o_user = 1 | chip_io_alt/proxyw_692355_190352# = 1
|
Net: mprj/wbs_we_i |Net: dummy_7846
mgmt_protect/mprj_we_o_user = 1 | chip_io_alt/proxyw_694469_862552# = 1
|
Net: mprj/wb_clk_i |Net: dummy_7847
mgmt_protect/user_clock = 1 | chip_io_alt/proxyw_687543_952480# = 1
|
Net: mprj/wbs_adr_i[13] |Net: dummy_7848
mgmt_protect/mprj_adr_o_user[13] = 1 | chip_io_alt/proxyw_180810_1007543# = 1
|
Net: mprj/wb_rst_i |Net: dummy_7849
mgmt_protect/user_reset = 1 | chip_io_alt/proxyw_462869_21253# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7850
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_667565# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7851
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692355_235552# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7852
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_551269# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7853
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_320874# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7854
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692355_280552# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7855
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692253_103470# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7856
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_641469# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7857
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_129410_1007543# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7858
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692355_370752# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7859
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_323965# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7860
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_750874# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7861
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_596469# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7862
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_581165# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7863
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_731669# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7864
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_526010_1007543# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7865
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21151_407274# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7866
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_186552_23367# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7867
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_517669_23367# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7868
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21151_534874# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7869
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_328869# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7870
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692253_148670# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7871
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_753965# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7872
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_686669# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7873
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692253_193670# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7874
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_374069# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7875
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21253_410365# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7876
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_638152# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7877
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_186552_21253# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7878
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_517669_21253# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7879
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21253_237565# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7880
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692253_238870# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7881
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_364074# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7882
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692253_283870# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7883
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_474610_1007543# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7884
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_728352# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7885
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_627810_1007543# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7886
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_692355_862552# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7887
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_773352# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7888
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_367165# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7889
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21253_667565# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7890
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_794074# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7891
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_103469# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7892
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_353269_23367# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7893
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21151_578074# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7894
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_797165# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7895
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21253_323965# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7896
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_353269_21253# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7897
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_277674# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7898
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_148669# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7899
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21253_581165# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7900
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_694469_193669# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7901
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_4069_956010# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7902
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_23367_707674# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7903
sky130_fd_sc_hd__inv_2/Y = 1 | chip_io_alt/proxyw_21151_234474# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7904
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_694469_238869# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7905
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_21253_753965# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7906
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_694469_283869# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7907
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_692253_865870# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7908
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_298469_23367# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7909
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_694469_547952# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7910
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_692355_638152# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7911
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_21151_664474# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7912
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_23367_191274# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7913
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_408069_23367# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7914
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_694469_593152# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7915
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_23367_621274# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7916
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_692355_728352# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7917
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_514352_23367# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7918
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_694469_325552# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7919
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_692355_773352# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7920
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_298469_21253# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7921
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_694469_683352# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7922
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_21253_367165# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7923
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_23367_194365# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7924
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_21151_320874# = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: dummy_7925
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_408069_21253# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7926
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_23367_624365# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7927
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_514352_21253# = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: dummy_7928
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_404752_23367# = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: dummy_7929
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_21253_797165# = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: dummy_7930
sky130_fd_sc_hd__conb_1/HI = 1 | chip_io_alt/proxyw_21151_750874# = 1
|
Net: soc/VPWR |Net: dummy_7931
sky130_fd_sc_hd__dfrtp_4/VPWR = 351 | gpio_signal_buffering_alt/proxyvccd_uq0
sky130_fd_sc_hd__dfrtp_4/VPB = 351 |
sky130_fd_sc_hd__nand2b_2/VPWR = 378 |
sky130_fd_sc_hd__nand2b_2/VPB = 378 |
sky130_fd_sc_hd__dfbbn_2/VPWR = 351 |
sky130_fd_sc_hd__dfbbn_2/VPB = 351 |
sky130_fd_sc_hd__inv_2/VPWR = 432 |
sky130_fd_sc_hd__inv_2/VPB = 432 |
sky130_fd_sc_hd__buf_16/VPWR = 513 |
sky130_fd_sc_hd__buf_16/VPB = 513 |
sky130_fd_sc_hd__mux2_4/VPWR = 27 |
sky130_fd_sc_hd__mux2_4/VPB = 27 |
sky130_fd_sc_hd__clkbuf_16/VPWR = 216 |
sky130_fd_sc_hd__clkbuf_16/VPB = 216 |
sky130_fd_sc_hd__and2_0/VPWR = 27 |
sky130_fd_sc_hd__and2_0/VPB = 27 |
sky130_fd_sc_hd__dlygate4sd3_1/VPWR = 35 |
sky130_fd_sc_hd__dlygate4sd3_1/VPB = 351 |
sky130_fd_sc_hd__diode_2/VPWR = 621 |
sky130_fd_sc_hd__diode_2/VPB = 621 |
sky130_fd_sc_hd__decap_3/VPWR = 1 |
sky130_fd_sc_hd__decap_3/VPB = 1 |
sky130_fd_sc_hd__conb_1/VPB = 54 |
sky130_fd_sc_hd__conb_1/VPWR = 54 |
sky130_fd_sc_hd__buf_2/VPWR = 432 |
sky130_fd_sc_hd__buf_2/VPB = 432 |
sky130_fd_sc_hd__or2_0/VPWR = 351 |
sky130_fd_sc_hd__or2_0/VPB = 351 |
sky130_fd_sc_hd__nand2_2/VPWR = 54 |
sky130_fd_sc_hd__nand2_2/VPB = 54 |
sky130_fd_sc_hd__nor2_2/VPWR = 54 |
sky130_fd_sc_hd__nor2_2/VPB = 54 |
sky130_fd_sc_hd__and2_2/VPWR = 27 |
sky130_fd_sc_hd__and2_2/VPB = 27 |
sky130_fd_sc_hd__o21ai_4/VPWR = 27 |
sky130_fd_sc_hd__o21ai_4/VPB = 27 |
sky130_fd_sc_hd__o21ai_2/VPWR = 27 |
sky130_fd_sc_hd__o21ai_2/VPB = 27 |
sky130_fd_sc_hd__and2b_2/VPWR = 27 |
sky130_fd_sc_hd__and2b_2/VPB = 27 |
sky130_fd_sc_hd__dfrtp_2/VPWR = 27 |
sky130_fd_sc_hd__dfrtp_2/VPB = 27 |
sky130_fd_sc_hd__and3b_2/VPWR = 27 |
sky130_fd_sc_hd__and3b_2/VPB = 27 |
gpio_defaults_block_0403/VPWR = 24 |
digital_pll/VPWR = 1 |
chip_io_alt/vccd = 1 |
mgmt_core_wrapper/VPWR = 1 |
simple_por/vdd1v8 = 1 |
caravel_clocking/VPWR = 1 |
gpio_defaults_block_1803/VPWR = 2 |
spare_logic_block/vccd = 4 |
user_id_programming/VPWR = 1 |
gpio_defaults_block_0801/VPWR = 1 |
gpio_signal_buffering_alt/vccd = 1 |
gpio_signal_buffering_alt/vccd_uq0 = 1 |
gpio_signal_buffering_alt/vccd_uq1 = 1 |
gpio_signal_buffering_alt/vccd_uq3 = 1 |
gpio_signal_buffering_alt/vccd_uq4 = 1 |
gpio_signal_buffering_alt/vccd_uq2 = 1 |
mgmt_protect/vccd = 1 |
xres_buf/LVPWR = 1 |
housekeeping/VPWR = 1 |
buff_flash_clkrst/VPWR = 1 |
|
Net: VSUBS |Net: dummy_7932
sky130_fd_sc_hd__dfrtp_4/VGND = 351 | gpio_signal_buffering_alt/proxyvccd_uq1
sky130_fd_sc_hd__dfrtp_4/VNB = 351 |
sky130_fd_sc_hd__nand2b_2/VGND = 378 |
sky130_fd_sc_hd__nand2b_2/VNB = 378 |
sky130_fd_sc_hd__dfbbn_2/VGND = 351 |
sky130_fd_sc_hd__dfbbn_2/VNB = 351 |
sky130_fd_sc_hd__inv_2/VGND = 432 |
sky130_fd_sc_hd__inv_2/VNB = 432 |
sky130_fd_sc_hd__buf_16/VGND = 513 |
sky130_fd_sc_hd__buf_16/VNB = 513 |
sky130_fd_sc_hd__mux2_4/VGND = 27 |
sky130_fd_sc_hd__mux2_4/VNB = 27 |
sky130_fd_sc_hd__clkbuf_16/VGND = 216 |
sky130_fd_sc_hd__clkbuf_16/VNB = 216 |
sky130_fd_sc_hd__and2_0/VGND = 27 |
sky130_fd_sc_hd__and2_0/VNB = 27 |
sky130_fd_sc_hd__dlygate4sd3_1/VGND = 35 |
sky130_fd_sc_hd__dlygate4sd3_1/VNB = 351 |
sky130_fd_sc_hd__diode_2/VGND = 621 |
sky130_fd_sc_hd__diode_2/VNB = 621 |
sky130_fd_sc_hd__decap_3/VGND = 1 |
sky130_fd_sc_hd__decap_3/VNB = 1 |
sky130_fd_sc_hd__conb_1/VNB = 54 |
sky130_fd_sc_hd__conb_1/VGND = 54 |
sky130_fd_sc_hd__buf_2/VGND = 432 |
sky130_fd_sc_hd__buf_2/VNB = 432 |
sky130_fd_sc_hd__or2_0/VGND = 351 |
sky130_fd_sc_hd__or2_0/VNB = 351 |
sky130_fd_sc_hd__nand2_2/VGND = 54 |
sky130_fd_sc_hd__nand2_2/VNB = 54 |
sky130_fd_sc_hd__nor2_2/VGND = 54 |
sky130_fd_sc_hd__nor2_2/VNB = 54 |
sky130_fd_sc_hd__and2_2/VGND = 27 |
sky130_fd_sc_hd__and2_2/VNB = 27 |
sky130_fd_sc_hd__o21ai_4/VGND = 27 |
sky130_fd_sc_hd__o21ai_4/VNB = 27 |
sky130_fd_sc_hd__o21ai_2/VGND = 27 |
sky130_fd_sc_hd__o21ai_2/VNB = 27 |
sky130_fd_sc_hd__and2b_2/VGND = 27 |
sky130_fd_sc_hd__and2b_2/VNB = 27 |
sky130_fd_sc_hd__dfrtp_2/VGND = 27 |
sky130_fd_sc_hd__dfrtp_2/VNB = 27 |
sky130_fd_sc_hd__and3b_2/VGND = 27 |
sky130_fd_sc_hd__and3b_2/VNB = 27 |
gpio_defaults_block_0403/VGND = 24 |
digital_pll/VGND = 1 |
chip_io_alt/vssd = 1 |
mgmt_core_wrapper/VGND = 1 |
simple_por/vss1v8 = 1 |
caravel_clocking/VGND = 1 |
gpio_defaults_block_1803/VGND = 2 |
spare_logic_block/vssd = 4 |
user_id_programming/VGND = 1 |
gpio_defaults_block_0801/VGND = 1 |
gpio_signal_buffering_alt/vssd = 1 |
mgmt_protect/vssd = 1 |
xres_buf/LVGND = 1 |
housekeeping/VGND = 1 |
buff_flash_clkrst/VGND = 1 |
|
(no matching net) |Net: dummy_7933
| gpio_signal_buffering_alt/proxyvccd_uq3
|
(no matching net) |Net: dummy_7934
| gpio_signal_buffering_alt/proxyvccd_uq4
|
(no matching net) |Net: dummy_7935
| gpio_signal_buffering_alt/proxyvccd_uq2
|
(no matching net) |Net: vccd_core
| caravel_clocking/VPWR = 1
| buff_flash_clkrst/VPWR = 1
| sky130_fd_sc_hd__diode_2/VPWR = 621
| sky130_fd_sc_hd__diode_2/VPB = 621
| sky130_fd_sc_hd__decap_3/VPWR = 1
| sky130_fd_sc_hd__decap_3/VPB = 1
| sky130_fd_sc_hd__inv_2/VPWR = 432
| sky130_fd_sc_hd__inv_2/VPB = 378
| sky130_fd_sc_hd__and2_0/VPWR = 27
| sky130_fd_sc_hd__and2_0/VPB = 27
| sky130_fd_sc_hd__mux2_4/VPWR = 27
| sky130_fd_sc_hd__mux2_4/VPB = 27
| sky130_fd_sc_hd__nand2b_2/VPWR = 378
| sky130_fd_sc_hd__nand2b_2/VPB = 378
| sky130_fd_sc_hd__and3b_2/VPWR = 27
| sky130_fd_sc_hd__and3b_2/VPB = 27
| sky130_fd_sc_hd__and2b_2/VPWR = 27
| sky130_fd_sc_hd__and2b_2/VPB = 27
| sky130_fd_sc_hd__o21ai_2/VPWR = 27
| sky130_fd_sc_hd__o21ai_2/VPB = 27
| sky130_fd_sc_hd__o21ai_4/VPWR = 27
| sky130_fd_sc_hd__o21ai_4/VPB = 27
| sky130_fd_sc_hd__and2_2/VPWR = 27
| sky130_fd_sc_hd__and2_2/VPB = 27
| sky130_fd_sc_hd__or2_0/VPWR = 351
| sky130_fd_sc_hd__or2_0/VPB = 351
| sky130_fd_sc_hd__dfbbn_2/VPWR = 351
| sky130_fd_sc_hd__dfbbn_2/VPB = 351
| sky130_fd_sc_hd__dfrtp_4/VPWR = 351
| sky130_fd_sc_hd__dfrtp_4/VPB = 351
| sky130_fd_sc_hd__dfrtp_2/VPWR = 27
| sky130_fd_sc_hd__dfrtp_2/VPB = 27
| sky130_fd_sc_hd__buf_2/VPWR = 432
| sky130_fd_sc_hd__buf_2/VPB = 432
| sky130_fd_sc_hd__clkbuf_16/VPWR = 216
| sky130_fd_sc_hd__clkbuf_16/VPB = 216
| sky130_fd_sc_hd__conb_1/VPB = 54
| sky130_fd_sc_hd__conb_1/VPWR = 27
| sky130_fd_sc_hd__dlygate4sd3_1/VPWR = 35
| sky130_fd_sc_hd__dlygate4sd3_1/VPB = 351
| sky130_fd_sc_hd__buf_16/VPWR = 513
| sky130_fd_sc_hd__buf_16/VPB = 513
| sky130_fd_sc_hd__nand2_2/Y = 54
| sky130_fd_sc_hd__nand2_2/VNB = 54
| sky130_fd_sc_hd__inv_2/VNB = 54
| sky130_fd_sc_hd__nor2_2/Y = 54
| sky130_fd_sc_hd__nor2_2/VNB = 54
| sky130_fd_sc_hd__conb_1/LO = 27
| gpio_defaults_block_1803/VPWR = 2
| gpio_defaults_block_0403/VPWR = 24
| gpio_defaults_block_0801/VPWR = 1
| housekeeping/VPWR = 1
| mgmt_protect/vccd = 1
| chip_io_alt/vccd = 1
| digital_pll/VPWR = 1
| simple_por/vdd1v8 = 1
| xres_buf/LVPWR = 1
| gpio_signal_buffering_alt/vccd = 1
| mgmt_core_wrapper/VPWR = 1
| spare_logic_block/vccd = 4
| user_id_programming/VPWR = 1
|
(no matching net) |Net: vssd_core
| caravel_clocking/VGND = 1
| buff_flash_clkrst/VGND = 1
| sky130_fd_sc_hd__diode_2/VGND = 621
| sky130_fd_sc_hd__diode_2/VNB = 621
| sky130_fd_sc_hd__decap_3/VGND = 1
| sky130_fd_sc_hd__decap_3/VNB = 1
| sky130_fd_sc_hd__inv_2/VGND = 378
| sky130_fd_sc_hd__inv_2/VNB = 378
| sky130_fd_sc_hd__and2_0/VGND = 27
| sky130_fd_sc_hd__and2_0/VNB = 27
| sky130_fd_sc_hd__mux2_4/VGND = 27
| sky130_fd_sc_hd__mux2_4/VNB = 27
| sky130_fd_sc_hd__nand2b_2/VGND = 378
| sky130_fd_sc_hd__nand2b_2/VNB = 378
| sky130_fd_sc_hd__and3b_2/VGND = 27
| sky130_fd_sc_hd__and3b_2/VNB = 27
| sky130_fd_sc_hd__and2b_2/VGND = 27
| sky130_fd_sc_hd__and2b_2/VNB = 27
| sky130_fd_sc_hd__o21ai_2/VGND = 27
| sky130_fd_sc_hd__o21ai_2/VNB = 27
| sky130_fd_sc_hd__o21ai_4/VGND = 27
| sky130_fd_sc_hd__o21ai_4/VNB = 27
| sky130_fd_sc_hd__and2_2/VGND = 27
| sky130_fd_sc_hd__and2_2/VNB = 27
| sky130_fd_sc_hd__or2_0/VGND = 351
| sky130_fd_sc_hd__or2_0/VNB = 351
| sky130_fd_sc_hd__dfbbn_2/VGND = 351
| sky130_fd_sc_hd__dfbbn_2/VNB = 351
| sky130_fd_sc_hd__dfrtp_4/VGND = 351
| sky130_fd_sc_hd__dfrtp_4/VNB = 351
| sky130_fd_sc_hd__dfrtp_2/VGND = 27
| sky130_fd_sc_hd__dfrtp_2/VNB = 27
| sky130_fd_sc_hd__buf_2/VGND = 432
| sky130_fd_sc_hd__buf_2/VNB = 432
| sky130_fd_sc_hd__clkbuf_16/VGND = 216
| sky130_fd_sc_hd__clkbuf_16/VNB = 216
| sky130_fd_sc_hd__conb_1/VNB = 27
| sky130_fd_sc_hd__conb_1/VGND = 27
| sky130_fd_sc_hd__dlygate4sd3_1/VGND = 35
| sky130_fd_sc_hd__dlygate4sd3_1/VNB = 351
| sky130_fd_sc_hd__buf_16/VGND = 513
| sky130_fd_sc_hd__buf_16/VNB = 513
| sky130_fd_sc_hd__nand2_2/VPWR = 54
| sky130_fd_sc_hd__nand2_2/VPB = 54
| sky130_fd_sc_hd__inv_2/Y = 54
| sky130_fd_sc_hd__inv_2/VPB = 54
| sky130_fd_sc_hd__nor2_2/VPWR = 54
| sky130_fd_sc_hd__nor2_2/VPB = 54
| sky130_fd_sc_hd__conb_1/HI = 27
| sky130_fd_sc_hd__conb_1/VPWR = 27
| gpio_defaults_block_1803/VGND = 2
| gpio_defaults_block_0403/VGND = 24
| gpio_defaults_block_0801/VGND = 1
| housekeeping/VGND = 1
| mgmt_protect/vssd = 1
| chip_io_alt/vssd = 1
| digital_pll/VGND = 1
| simple_por/vss1v8 = 1
| xres_buf/LVGND = 1
| gpio_signal_buffering_alt/vssd = 1
| mgmt_core_wrapper/VGND = 1
| spare_logic_block/vssd = 4
| user_id_programming/VGND = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
(no matching net) |Net: vssd1_core
| gpio_logic_high/vssd1 = 27
| mgmt_protect/vssd1 = 1
| user_analog_project_wrapper/vssd1 = 1
| chip_io_alt/vssd1 = 1
|
(no matching net) |Net: vccd1_core
| gpio_logic_high/vccd1 = 27
| mgmt_protect/vccd1 = 1
| user_analog_project_wrapper/vccd1 = 1
| chip_io_alt/vccd1 = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: gpio_control_block:gpio_control_bidir |Net: \gpio_control_in_2[9] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \gpio_control_in_2[8] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_2[7] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \gpio_control_in_2[6] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_2[5] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \gpio_control_in_2[4] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_2[3] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \gpio_control_in_2[2] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \gpio_control_in_2[1] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_2[0] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \gpio_control_in_1a[5] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \gpio_control_in_1a[4] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \gpio_control_in_1a[3] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \gpio_control_in_1a[2] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_1a[1] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \gpio_control_in_1a[0] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_1[5] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_1[4] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \gpio_control_in_1[3] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \gpio_control_in_1[2] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_in_1[1] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \gpio_control_in_1[0] /_noconnect_1_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1\ |Net: \gpio_control_bidir_2[2] /_noconnect_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_bidir_2[1] /_noconnect_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_bidir |Net: \gpio_control_bidir_2[0] /_noconnect_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_1a |Net: \gpio_control_bidir_1[1] /_noconnect_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
|
Net: gpio_control_block:gpio_control_in_2\ |Net: \gpio_control_bidir_1[0] /_noconnect_
sky130_fd_sc_hd__nand2_2/A = 2 | sky130_fd_sc_hd__nand2_2/B = 2
sky130_fd_sc_hd__nand2_2/B = 2 | sky130_fd_sc_hd__nand2_2/VGND = 2
sky130_fd_sc_hd__conb_1/LO = 1 | sky130_fd_sc_hd__conb_1/VGND = 1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: mprj/vssd1 |(no matching net)
gpio_logic_high/vssd1 = 27 |
chip_io_alt/vssd1 = 1 |
mgmt_protect/vssd1 = 1 |
|
Net: mprj/vccd1 |(no matching net)
gpio_logic_high/vccd1 = 27 |
chip_io_alt/vccd1 = 1 |
mgmt_protect/vccd1 = 1 |
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Net: padframe/mprj_io_one[23] |Net: \mprj_io_one[23]
chip_io_alt/mprj_io_one[23] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[23] = 1
|
Net: padframe/mprj_io_one[22] |Net: \mprj_io_one[22]
chip_io_alt/mprj_io_one[22] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[22] = 1
|
Net: padframe/mprj_io_one[21] |Net: \mprj_io_one[21]
chip_io_alt/mprj_io_one[21] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[21] = 1
|
Net: padframe/mprj_io_one[20] |Net: \mprj_io_one[20]
chip_io_alt/mprj_io_one[20] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[20] = 1
|
Net: padframe/mprj_io_one[19] |Net: \mprj_io_one[19]
chip_io_alt/mprj_io_one[19] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[19] = 1
|
Net: padframe/mprj_io_one[18] |Net: \mprj_io_one[18]
chip_io_alt/mprj_io_one[18] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[18] = 1
|
Net: padframe/mprj_io_one[17] |Net: \mprj_io_one[17]
chip_io_alt/mprj_io_one[17] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[17] = 1
|
Net: padframe/mprj_io_one[16] |Net: \mprj_io_one[16]
chip_io_alt/mprj_io_one[16] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[16] = 1
|
Net: padframe/mprj_io_one[15] |Net: \mprj_io_one[15]
chip_io_alt/mprj_io_one[15] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[15] = 1
|
Net: padframe/mprj_io_one[13] |Net: \mprj_io_one[14]
chip_io_alt/mprj_io_one[13] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[14] = 1
|
Net: padframe/mprj_io_one[12] |Net: \mprj_io_one[7]
chip_io_alt/mprj_io_one[12] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[7] = 1
|
Net: padframe/mprj_io_one[11] |Net: \mprj_io_one[6]
chip_io_alt/mprj_io_one[11] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[6] = 1
|
Net: padframe/mprj_io_one[10] |Net: \mprj_io_one[5]
chip_io_alt/mprj_io_one[10] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[5] = 1
|
Net: padframe/mprj_io_one[9] |Net: \mprj_io_one[4]
chip_io_alt/mprj_io_one[9] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[4] = 1
|
Net: padframe/mprj_io_one[8] |Net: \mprj_io_one[3]
chip_io_alt/mprj_io_one[8] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[3] = 1
|
Net: padframe/mprj_io_one[7] |Net: \mprj_io_one[2]
chip_io_alt/mprj_io_one[7] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[2] = 1
|
Net: padframe/mprj_io_one[6] |Net: \mprj_io_one[13]
chip_io_alt/mprj_io_one[6] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[13] = 1
|
Net: padframe/mprj_io_one[5] |Net: \mprj_io_one[12]
chip_io_alt/mprj_io_one[5] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[12] = 1
|
Net: padframe/mprj_io_one[4] |Net: \mprj_io_one[11]
chip_io_alt/mprj_io_one[4] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[11] = 1
|
Net: padframe/mprj_io_one[3] |Net: \mprj_io_one[10]
chip_io_alt/mprj_io_one[3] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[10] = 1
|
Net: padframe/mprj_io_one[2] |Net: \mprj_io_one[9]
chip_io_alt/mprj_io_one[2] = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_16/X = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | chip_io_alt/mprj_io_one[9] = 1
|
Net: padframe/mprj_io_one[14] |Net: \mprj_io_one[8]
sky130_fd_sc_hd__buf_2/A = 1 | sky130_fd_sc_hd__diode_2/DIODE = 1
sky130_fd_sc_hd__buf_16/X = 1 | sky130_fd_sc_hd__buf_2/A = 1
sky130_fd_sc_hd__diode_2/DIODE = 1 | sky130_fd_sc_hd__buf_16/X = 1
chip_io_alt/mprj_io_one[14] = 1 | chip_io_alt/mprj_io_one[8] = 1
---------------------------------------------------------------------------------------
DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: caravan |Circuit 2: caravan
---------------------------------------------------------------------------------------
(no matching instance) |Instance: mprj
| gpio_analog[17] = 2
| gpio_analog[16] = 2
| gpio_analog[15] = 2
| gpio_analog[14] = 2
| gpio_analog[13] = 2
| gpio_analog[12] = 2
| gpio_analog[11] = 2
| gpio_analog[10] = 2
| gpio_analog[9] = 2
| gpio_analog[8] = 2
| gpio_analog[7] = 2
| gpio_analog[6] = 2
| gpio_analog[5] = 2
| gpio_analog[4] = 2
| gpio_analog[3] = 2
| gpio_analog[2] = 2
| gpio_analog[1] = 2
| gpio_analog[0] = 2
| gpio_noesd[17] = 2
| gpio_noesd[16] = 2
| gpio_noesd[15] = 2
| gpio_noesd[14] = 2
| gpio_noesd[13] = 2
| gpio_noesd[12] = 2
| gpio_noesd[11] = 2
| gpio_noesd[10] = 2
| gpio_noesd[9] = 2
| gpio_noesd[8] = 2
| gpio_noesd[7] = 2
| gpio_noesd[6] = 2
| gpio_noesd[5] = 2
| gpio_noesd[4] = 2
| gpio_noesd[3] = 2
| gpio_noesd[2] = 2
| gpio_noesd[1] = 2
| gpio_noesd[0] = 2
| io_analog[10] = 2
| io_analog[9] = 2
| io_analog[8] = 2
| io_analog[7] = 2
| io_analog[6] = 2
| io_analog[5] = 2
| io_analog[4] = 2
| io_analog[3] = 2
| io_analog[2] = 2
| io_analog[1] = 2
| io_analog[0] = 2
| io_clamp_high[2] = 2
| io_clamp_high[1] = 2
| io_clamp_high[0] = 2
| io_clamp_low[2] = 2
| io_clamp_low[1] = 2
| io_clamp_low[0] = 2
| io_in[26] = 2
| io_in[25] = 2
| io_in[24] = 2
| io_in[23] = 2
| io_in[22] = 2
| io_in[21] = 2
| io_in[20] = 2
| io_in[19] = 2
| io_in[18] = 2
| io_in[17] = 2
| io_in[16] = 2
| io_in[15] = 2
| io_in[14] = 2
| io_in[13] = 2
| io_in[12] = 2
| io_in[11] = 2
| io_in[10] = 2
| io_in[9] = 2
| io_in[8] = 2
| io_in[7] = 2
| io_in[6] = 2
| io_in[5] = 2
| io_in[4] = 2
| io_in[3] = 2
| io_in[2] = 2
| io_in[1] = 2
| io_in[0] = 2
| io_in_3v3[26] = 2
| io_in_3v3[25] = 2
| io_in_3v3[24] = 2
| io_in_3v3[23] = 2
| io_in_3v3[22] = 2
| io_in_3v3[21] = 2
| io_in_3v3[20] = 2
| io_in_3v3[19] = 2
| io_in_3v3[18] = 2
| io_in_3v3[17] = 2
| io_in_3v3[16] = 2
| io_in_3v3[15] = 2
| io_in_3v3[14] = 2
| io_in_3v3[13] = 2
| io_in_3v3[12] = 2
| io_in_3v3[11] = 2
| io_in_3v3[10] = 2
| io_in_3v3[9] = 2
| io_in_3v3[8] = 2
| io_in_3v3[7] = 2
| io_in_3v3[6] = 2
| io_in_3v3[5] = 2
| io_in_3v3[4] = 2
| io_in_3v3[3] = 2
| io_in_3v3[2] = 2
| io_in_3v3[1] = 2
| io_in_3v3[0] = 2
| io_oeb[26] = 3
| io_oeb[25] = 3
| io_oeb[24] = 3
| io_oeb[23] = 3
| io_oeb[22] = 3
| io_oeb[21] = 3
| io_oeb[20] = 3
| io_oeb[19] = 3
| io_oeb[18] = 3
| io_oeb[17] = 3
| io_oeb[16] = 3
| io_oeb[15] = 3
| io_oeb[14] = 3
| io_oeb[13] = 3
| io_oeb[12] = 3
| io_oeb[11] = 3
| io_oeb[10] = 3
| io_oeb[9] = 3
| io_oeb[8] = 3
| io_oeb[7] = 3
| io_oeb[6] = 3
| io_oeb[5] = 3
| io_oeb[4] = 3
| io_oeb[3] = 3
| io_oeb[2] = 3
| io_oeb[1] = 3
| io_oeb[0] = 3
| io_out[26] = 3
| io_out[25] = 3
| io_out[24] = 3
| io_out[23] = 3
| io_out[22] = 3
| io_out[21] = 3
| io_out[20] = 3
| io_out[19] = 3
| io_out[18] = 3
| io_out[17] = 3
| io_out[16] = 3
| io_out[15] = 3
| io_out[14] = 3
| io_out[13] = 3
| io_out[12] = 3
| io_out[11] = 3
| io_out[10] = 3
| io_out[9] = 3
| io_out[8] = 3
| io_out[7] = 3
| io_out[6] = 3
| io_out[5] = 3
| io_out[4] = 3
| io_out[3] = 3
| io_out[2] = 3
| io_out[1] = 3
| io_out[0] = 3
| la_data_in[127] = 2
| la_data_in[126] = 2
| la_data_in[125] = 2
| la_data_in[124] = 2
| la_data_in[123] = 2
| la_data_in[122] = 2
| la_data_in[121] = 2
| la_data_in[120] = 2
| la_data_in[119] = 2
| la_data_in[118] = 2
| la_data_in[117] = 2
| la_data_in[116] = 2
| la_data_in[115] = 2
| la_data_in[114] = 2
| la_data_in[113] = 2
| la_data_in[112] = 2
| la_data_in[111] = 2
| la_data_in[110] = 2
| la_data_in[109] = 2
| la_data_in[108] = 2
| la_data_in[107] = 2
| la_data_in[106] = 2
| la_data_in[105] = 2
| la_data_in[104] = 2
| la_data_in[103] = 2
| la_data_in[102] = 2
| la_data_in[101] = 2
| la_data_in[100] = 2
| la_data_in[99] = 2
| la_data_in[98] = 2
| la_data_in[97] = 2
| la_data_in[96] = 2
| la_data_in[95] = 2
| la_data_in[94] = 2
| la_data_in[93] = 2
| la_data_in[92] = 2
| la_data_in[91] = 2
| la_data_in[90] = 2
| la_data_in[89] = 2
| la_data_in[88] = 2
| la_data_in[87] = 2
| la_data_in[86] = 2
| la_data_in[85] = 2
| la_data_in[84] = 2
| la_data_in[83] = 2
| la_data_in[82] = 2
| la_data_in[81] = 2
| la_data_in[80] = 2
| la_data_in[79] = 2
| la_data_in[78] = 2
| la_data_in[77] = 2
| la_data_in[76] = 2
| la_data_in[75] = 2
| la_data_in[74] = 2
| la_data_in[73] = 2
| la_data_in[72] = 2
| la_data_in[71] = 2
| la_data_in[70] = 2
| la_data_in[69] = 2
| la_data_in[68] = 2
| la_data_in[67] = 2
| la_data_in[66] = 2
| la_data_in[65] = 2
| la_data_in[64] = 2
| la_data_in[63] = 2
| la_data_in[62] = 2
| la_data_in[61] = 2
| la_data_in[60] = 2
| la_data_in[59] = 2
| la_data_in[58] = 2
| la_data_in[57] = 2
| la_data_in[56] = 2
| la_data_in[55] = 2
| la_data_in[54] = 2
| la_data_in[53] = 2
| la_data_in[52] = 2
| la_data_in[51] = 2
| la_data_in[50] = 2
| la_data_in[49] = 2
| la_data_in[48] = 2
| la_data_in[47] = 2
| la_data_in[46] = 2
| la_data_in[45] = 2
| la_data_in[44] = 2
| la_data_in[43] = 2
| la_data_in[42] = 2
| la_data_in[41] = 2
| la_data_in[40] = 2
| la_data_in[39] = 2
| la_data_in[38] = 2
| la_data_in[37] = 2
| la_data_in[36] = 2
| la_data_in[35] = 2
| la_data_in[34] = 2
| la_data_in[33] = 2
| la_data_in[32] = 2
| la_data_in[31] = 2
| la_data_in[30] = 2
| la_data_in[29] = 2
| la_data_in[28] = 2
| la_data_in[27] = 2
| la_data_in[26] = 2
| la_data_in[25] = 2
| la_data_in[24] = 2
| la_data_in[23] = 2
| la_data_in[22] = 2
| la_data_in[21] = 2
| la_data_in[20] = 2
| la_data_in[19] = 2
| la_data_in[18] = 2
| la_data_in[17] = 2
| la_data_in[16] = 2
| la_data_in[15] = 2
| la_data_in[14] = 2
| la_data_in[13] = 2
| la_data_in[12] = 2
| la_data_in[11] = 2
| la_data_in[10] = 2
| la_data_in[9] = 2
| la_data_in[8] = 2
| la_data_in[7] = 2
| la_data_in[6] = 2
| la_data_in[5] = 2
| la_data_in[4] = 2
| la_data_in[3] = 2
| la_data_in[2] = 2
| la_data_in[1] = 2
| la_data_in[0] = 2
| la_data_out[127] = 2
| la_data_out[126] = 2
| la_data_out[125] = 2
| la_data_out[124] = 2
| la_data_out[123] = 2
| la_data_out[122] = 2
| la_data_out[121] = 2
| la_data_out[120] = 2
| la_data_out[119] = 2
| la_data_out[118] = 2
| la_data_out[117] = 2
| la_data_out[116] = 2
| la_data_out[115] = 2
| la_data_out[114] = 2
| la_data_out[113] = 2
| la_data_out[112] = 2
| la_data_out[111] = 2
| la_data_out[110] = 2
| la_data_out[109] = 2
| la_data_out[108] = 2
| la_data_out[107] = 2
| la_data_out[106] = 2
| la_data_out[105] = 2
| la_data_out[104] = 2
| la_data_out[103] = 2
| la_data_out[102] = 2
| la_data_out[101] = 2
| la_data_out[100] = 2
| la_data_out[99] = 2
| la_data_out[98] = 2
| la_data_out[97] = 2
| la_data_out[96] = 2
| la_data_out[95] = 2
| la_data_out[94] = 2
| la_data_out[93] = 2
| la_data_out[92] = 2
| la_data_out[91] = 2
| la_data_out[90] = 2
| la_data_out[89] = 2
| la_data_out[88] = 2
| la_data_out[87] = 2
| la_data_out[86] = 2
| la_data_out[85] = 2
| la_data_out[84] = 2
| la_data_out[83] = 2
| la_data_out[82] = 2
| la_data_out[81] = 2
| la_data_out[80] = 2
| la_data_out[79] = 2
| la_data_out[78] = 2
| la_data_out[77] = 2
| la_data_out[76] = 2
| la_data_out[75] = 2
| la_data_out[74] = 2
| la_data_out[73] = 2
| la_data_out[72] = 2
| la_data_out[71] = 2
| la_data_out[70] = 2
| la_data_out[69] = 2
| la_data_out[68] = 2
| la_data_out[67] = 2
| la_data_out[66] = 2
| la_data_out[65] = 2
| la_data_out[64] = 2
| la_data_out[63] = 2
| la_data_out[62] = 2
| la_data_out[61] = 2
| la_data_out[60] = 2
| la_data_out[59] = 2
| la_data_out[58] = 2
| la_data_out[57] = 2
| la_data_out[56] = 2
| la_data_out[55] = 2
| la_data_out[54] = 2
| la_data_out[53] = 2
| la_data_out[52] = 2
| la_data_out[51] = 2
| la_data_out[50] = 2
| la_data_out[49] = 2
| la_data_out[48] = 2
| la_data_out[47] = 2
| la_data_out[46] = 2
| la_data_out[45] = 2
| la_data_out[44] = 2
| la_data_out[43] = 2
| la_data_out[42] = 2
| la_data_out[41] = 2
| la_data_out[40] = 2
| la_data_out[39] = 2
| la_data_out[38] = 2
| la_data_out[37] = 2
| la_data_out[36] = 2
| la_data_out[35] = 2
| la_data_out[34] = 2
| la_data_out[33] = 2
| la_data_out[32] = 2
| la_data_out[31] = 2
| la_data_out[30] = 2
| la_data_out[29] = 2
| la_data_out[28] = 2
| la_data_out[27] = 2
| la_data_out[26] = 2
| la_data_out[25] = 2
| la_data_out[24] = 2
| la_data_out[23] = 2
| la_data_out[22] = 2
| la_data_out[21] = 2
| la_data_out[20] = 2
| la_data_out[19] = 2
| la_data_out[18] = 2
| la_data_out[17] = 2
| la_data_out[16] = 2
| la_data_out[15] = 2
| la_data_out[14] = 2
| la_data_out[13] = 2
| la_data_out[12] = 2
| la_data_out[11] = 2
| la_data_out[10] = 2
| la_data_out[9] = 2
| la_data_out[8] = 2
| la_data_out[7] = 2
| la_data_out[6] = 2
| la_data_out[5] = 2
| la_data_out[4] = 2
| la_data_out[3] = 2
| la_data_out[2] = 2
| la_data_out[1] = 2
| la_data_out[0] = 2
| la_oenb[127] = 2
| la_oenb[126] = 2
| la_oenb[125] = 2
| la_oenb[124] = 2
| la_oenb[123] = 2
| la_oenb[122] = 2
| la_oenb[121] = 2
| la_oenb[120] = 2
| la_oenb[119] = 2
| la_oenb[118] = 2
| la_oenb[117] = 2
| la_oenb[116] = 2
| la_oenb[115] = 2
| la_oenb[114] = 2
| la_oenb[113] = 2
| la_oenb[112] = 2
| la_oenb[111] = 2
| la_oenb[110] = 2
| la_oenb[109] = 2
| la_oenb[108] = 2
| la_oenb[107] = 2
| la_oenb[106] = 2
| la_oenb[105] = 2
| la_oenb[104] = 2
| la_oenb[103] = 2
| la_oenb[102] = 2
| la_oenb[101] = 2
| la_oenb[100] = 2
| la_oenb[99] = 2
| la_oenb[98] = 2
| la_oenb[97] = 2
| la_oenb[96] = 2
| la_oenb[95] = 2
| la_oenb[94] = 2
| la_oenb[93] = 2
| la_oenb[92] = 2
| la_oenb[91] = 2
| la_oenb[90] = 2
| la_oenb[89] = 2
| la_oenb[88] = 2
| la_oenb[87] = 2
| la_oenb[86] = 2
| la_oenb[85] = 2
| la_oenb[84] = 2
| la_oenb[83] = 2
| la_oenb[82] = 2
| la_oenb[81] = 2
| la_oenb[80] = 2
| la_oenb[79] = 2
| la_oenb[78] = 2
| la_oenb[77] = 2
| la_oenb[76] = 2
| la_oenb[75] = 2
| la_oenb[74] = 2
| la_oenb[73] = 2
| la_oenb[72] = 2
| la_oenb[71] = 2
| la_oenb[70] = 2
| la_oenb[69] = 2
| la_oenb[68] = 2
| la_oenb[67] = 2
| la_oenb[66] = 2
| la_oenb[65] = 2
| la_oenb[64] = 2
| la_oenb[63] = 2
| la_oenb[62] = 2
| la_oenb[61] = 2
| la_oenb[60] = 2
| la_oenb[59] = 2
| la_oenb[58] = 2
| la_oenb[57] = 2
| la_oenb[56] = 2
| la_oenb[55] = 2
| la_oenb[54] = 2
| la_oenb[53] = 2
| la_oenb[52] = 2
| la_oenb[51] = 2
| la_oenb[50] = 2
| la_oenb[49] = 2
| la_oenb[48] = 2
| la_oenb[47] = 2
| la_oenb[46] = 2
| la_oenb[45] = 2
| la_oenb[44] = 2
| la_oenb[43] = 2
| la_oenb[42] = 2
| la_oenb[41] = 2
| la_oenb[40] = 2
| la_oenb[39] = 2
| la_oenb[38] = 2
| la_oenb[37] = 2
| la_oenb[36] = 2
| la_oenb[35] = 2
| la_oenb[34] = 2
| la_oenb[33] = 2
| la_oenb[32] = 2
| la_oenb[31] = 2
| la_oenb[30] = 2
| la_oenb[29] = 2
| la_oenb[28] = 2
| la_oenb[27] = 2
| la_oenb[26] = 2
| la_oenb[25] = 2
| la_oenb[24] = 2
| la_oenb[23] = 2
| la_oenb[22] = 2
| la_oenb[21] = 2
| la_oenb[20] = 2
| la_oenb[19] = 2
| la_oenb[18] = 2
| la_oenb[17] = 2
| la_oenb[16] = 2
| la_oenb[15] = 2
| la_oenb[14] = 2
| la_oenb[13] = 2
| la_oenb[12] = 2
| la_oenb[11] = 2
| la_oenb[10] = 2
| la_oenb[9] = 2
| la_oenb[8] = 2
| la_oenb[7] = 2
| la_oenb[6] = 2
| la_oenb[5] = 2
| la_oenb[4] = 2
| la_oenb[3] = 2
| la_oenb[2] = 2
| la_oenb[1] = 2
| la_oenb[0] = 2
| user_clock2 = 2
| user_irq[2] = 2
| user_irq[1] = 2
| user_irq[0] = 2
| vccd1 = 30
| vccd2 = 3
| vdda1 = 3
| vdda2 = 3
| vssa1 = 3
| vssa2 = 3
| vssd1 = 30
| vssd2 = 3
| wb_clk_i = 2
| wb_rst_i = 2
| wbs_ack_o = 2
| wbs_adr_i[31] = 2
| wbs_adr_i[30] = 2
| wbs_adr_i[29] = 2
| wbs_adr_i[28] = 2
| wbs_adr_i[27] = 2
| wbs_adr_i[26] = 2
| wbs_adr_i[25] = 2
| wbs_adr_i[24] = 2
| wbs_adr_i[23] = 2
| wbs_adr_i[22] = 2
| wbs_adr_i[21] = 2
| wbs_adr_i[20] = 2
| wbs_adr_i[19] = 2
| wbs_adr_i[18] = 2
| wbs_adr_i[17] = 2
| wbs_adr_i[16] = 2
| wbs_adr_i[15] = 2
| wbs_adr_i[14] = 2
| wbs_adr_i[13] = 2
| wbs_adr_i[12] = 2
| wbs_adr_i[11] = 2
| wbs_adr_i[10] = 2
| wbs_adr_i[9] = 2
| wbs_adr_i[8] = 2
| wbs_adr_i[7] = 2
| wbs_adr_i[6] = 2
| wbs_adr_i[5] = 2
| wbs_adr_i[4] = 2
| wbs_adr_i[3] = 2
| wbs_adr_i[2] = 2
| wbs_adr_i[1] = 2
| wbs_adr_i[0] = 2
| wbs_cyc_i = 2
| wbs_dat_i[31] = 2
| wbs_dat_i[30] = 2
| wbs_dat_i[29] = 2
| wbs_dat_i[28] = 2
| wbs_dat_i[27] = 2
| wbs_dat_i[26] = 2
| wbs_dat_i[25] = 2
| wbs_dat_i[24] = 2
| wbs_dat_i[23] = 2
| wbs_dat_i[22] = 2
| wbs_dat_i[21] = 2
| wbs_dat_i[20] = 2
| wbs_dat_i[19] = 2
| wbs_dat_i[18] = 2
| wbs_dat_i[17] = 2
| wbs_dat_i[16] = 2
| wbs_dat_i[15] = 2
| wbs_dat_i[14] = 2
| wbs_dat_i[13] = 2
| wbs_dat_i[12] = 2
| wbs_dat_i[11] = 2
| wbs_dat_i[10] = 2
| wbs_dat_i[9] = 2
| wbs_dat_i[8] = 2
| wbs_dat_i[7] = 2
| wbs_dat_i[6] = 2
| wbs_dat_i[5] = 2
| wbs_dat_i[4] = 2
| wbs_dat_i[3] = 2
| wbs_dat_i[2] = 2
| wbs_dat_i[1] = 2
| wbs_dat_i[0] = 2
| wbs_dat_o[31] = 2
| wbs_dat_o[30] = 2
| wbs_dat_o[29] = 2
| wbs_dat_o[28] = 2
| wbs_dat_o[27] = 2
| wbs_dat_o[26] = 2
| wbs_dat_o[25] = 2
| wbs_dat_o[24] = 2
| wbs_dat_o[23] = 2
| wbs_dat_o[22] = 2
| wbs_dat_o[21] = 2
| wbs_dat_o[20] = 2
| wbs_dat_o[19] = 2
| wbs_dat_o[18] = 2
| wbs_dat_o[17] = 2
| wbs_dat_o[16] = 2
| wbs_dat_o[15] = 2
| wbs_dat_o[14] = 2
| wbs_dat_o[13] = 2
| wbs_dat_o[12] = 2
| wbs_dat_o[11] = 2
| wbs_dat_o[10] = 2
| wbs_dat_o[9] = 2
| wbs_dat_o[8] = 2
| wbs_dat_o[7] = 2
| wbs_dat_o[6] = 2
| wbs_dat_o[5] = 2
| wbs_dat_o[4] = 2
| wbs_dat_o[3] = 2
| wbs_dat_o[2] = 2
| wbs_dat_o[1] = 2
| wbs_dat_o[0] = 2
| wbs_sel_i[3] = 2
| wbs_sel_i[2] = 2
| wbs_sel_i[1] = 2
| wbs_sel_i[0] = 2
| wbs_stb_i = 2
| wbs_we_i = 2
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: mgmt_protect:mgmt_buffers |Instance: mgmt_buffers
caravel_clk2 = 3 | caravel_clk2 = 3
user1_vcc_powergood = 2 | user1_vcc_powergood = 2
user1_vdd_powergood = 2 | user1_vdd_powergood = 2
user2_vcc_powergood = 2 | user2_vcc_powergood = 2
user2_vdd_powergood = 2 | user2_vdd_powergood = 2
user_irq[0] = 2 | user_irq[0] = 2
user_irq[1] = 2 | user_irq[1] = 2
user_irq[2] = 2 | user_irq[2] = 2
user_irq_core[0] = 1 | user_irq_core[0] = 2
user_irq_core[1] = 1 | user_irq_core[1] = 2
user_irq_core[2] = 1 | user_irq_core[2] = 2
user_irq_ena[0] = 2 | user_irq_ena[0] = 2
user_irq_ena[1] = 2 | user_irq_ena[1] = 2
user_irq_ena[2] = 2 | user_irq_ena[2] = 2
la_data_in_core[108] = 1 | la_data_in_core[108] = 2
la_data_in_core[109] = 1 | la_data_in_core[109] = 2
la_data_in_core[110] = 1 | la_data_in_core[110] = 2
la_data_in_core[111] = 1 | la_data_in_core[111] = 2
la_data_in_core[112] = 1 | la_data_in_core[112] = 2
la_data_in_core[113] = 1 | la_data_in_core[113] = 2
la_data_in_core[114] = 1 | la_data_in_core[114] = 2
la_data_in_core[115] = 1 | la_data_in_core[115] = 2
la_data_in_core[116] = 1 | la_data_in_core[116] = 2
la_data_in_core[117] = 1 | la_data_in_core[117] = 2
la_data_in_core[118] = 1 | la_data_in_core[118] = 2
la_data_in_core[119] = 1 | la_data_in_core[119] = 2
la_data_in_core[120] = 1 | la_data_in_core[120] = 2
la_data_in_core[121] = 1 | la_data_in_core[121] = 2
la_data_in_core[122] = 1 | la_data_in_core[122] = 2
la_data_in_core[123] = 1 | la_data_in_core[123] = 2
la_data_in_core[124] = 1 | la_data_in_core[124] = 2
la_data_in_core[125] = 1 | la_data_in_core[125] = 2
la_data_in_core[126] = 1 | la_data_in_core[126] = 2
la_data_in_core[127] = 1 | la_data_in_core[127] = 2
la_data_out_core[108] = 1 | la_data_out_core[108] = 2
la_data_out_core[109] = 1 | la_data_out_core[109] = 2
la_data_out_core[110] = 1 | la_data_out_core[110] = 2
la_data_out_core[111] = 1 | la_data_out_core[111] = 2
la_data_out_core[112] = 1 | la_data_out_core[112] = 2
la_data_out_core[113] = 1 | la_data_out_core[113] = 2
la_data_out_core[114] = 1 | la_data_out_core[114] = 2
la_data_out_core[115] = 1 | la_data_out_core[115] = 2
la_data_out_core[116] = 1 | la_data_out_core[116] = 2
la_data_out_core[117] = 1 | la_data_out_core[117] = 2
la_data_out_core[118] = 1 | la_data_out_core[118] = 2
la_data_out_core[119] = 1 | la_data_out_core[119] = 2
la_data_out_core[120] = 1 | la_data_out_core[120] = 2
la_data_out_core[121] = 1 | la_data_out_core[121] = 2
la_data_out_core[122] = 1 | la_data_out_core[122] = 2
la_data_out_core[123] = 1 | la_data_out_core[123] = 2
la_data_out_core[124] = 1 | la_data_out_core[124] = 2
la_data_out_core[125] = 1 | la_data_out_core[125] = 2
la_data_out_core[126] = 1 | la_data_out_core[126] = 2
la_data_out_core[127] = 1 | la_data_out_core[127] = 2
la_oenb_core[107] = 1 | la_oenb_core[107] = 2
la_oenb_core[108] = 1 | la_oenb_core[108] = 2
la_oenb_core[109] = 1 | la_oenb_core[109] = 2
la_oenb_core[110] = 1 | la_oenb_core[110] = 2
la_oenb_core[111] = 1 | la_oenb_core[111] = 2
la_oenb_core[112] = 1 | la_oenb_core[112] = 2
la_oenb_core[113] = 1 | la_oenb_core[113] = 2
la_oenb_core[114] = 1 | la_oenb_core[114] = 2
la_oenb_core[115] = 1 | la_oenb_core[115] = 2
la_oenb_core[116] = 1 | la_oenb_core[116] = 2
la_oenb_core[117] = 1 | la_oenb_core[117] = 2
la_oenb_core[118] = 1 | la_oenb_core[118] = 2
la_oenb_core[119] = 1 | la_oenb_core[119] = 2
la_oenb_core[120] = 1 | la_oenb_core[120] = 2
la_oenb_core[121] = 1 | la_oenb_core[121] = 2
la_oenb_core[122] = 1 | la_oenb_core[122] = 2
la_oenb_core[123] = 1 | la_oenb_core[123] = 2
la_oenb_core[124] = 1 | la_oenb_core[124] = 2
la_oenb_core[125] = 1 | la_oenb_core[125] = 2
la_oenb_core[126] = 1 | la_oenb_core[126] = 2
la_oenb_core[127] = 1 | la_oenb_core[127] = 2
user_clock2 = 1 | user_clock2 = 2
la_data_in_core[94] = 1 | la_data_in_core[94] = 2
la_data_in_core[95] = 1 | la_data_in_core[95] = 2
la_data_in_core[96] = 1 | la_data_in_core[96] = 2
la_data_in_core[97] = 1 | la_data_in_core[97] = 2
la_data_in_core[98] = 1 | la_data_in_core[98] = 2
la_data_in_core[99] = 1 | la_data_in_core[99] = 2
la_data_out_core[87] = 1 | la_data_out_core[87] = 2
la_data_out_core[88] = 1 | la_data_out_core[88] = 2
la_data_out_core[89] = 1 | la_data_out_core[89] = 2
la_data_out_core[90] = 1 | la_data_out_core[90] = 2
la_data_out_core[91] = 1 | la_data_out_core[91] = 2
la_data_out_core[92] = 1 | la_data_out_core[92] = 2
la_data_out_core[93] = 1 | la_data_out_core[93] = 2
la_data_out_core[94] = 1 | la_data_out_core[94] = 2
la_data_out_core[95] = 1 | la_data_out_core[95] = 2
la_data_out_core[96] = 1 | la_data_out_core[96] = 2
la_data_out_core[97] = 1 | la_data_out_core[97] = 2
la_data_out_core[98] = 1 | la_data_out_core[98] = 2
la_data_out_core[99] = 1 | la_data_out_core[99] = 2
la_oenb_core[100] = 1 | la_oenb_core[100] = 2
la_oenb_core[101] = 1 | la_oenb_core[101] = 2
la_oenb_core[102] = 1 | la_oenb_core[102] = 2
la_oenb_core[103] = 1 | la_oenb_core[103] = 2
la_oenb_core[104] = 1 | la_oenb_core[104] = 2
la_oenb_core[105] = 1 | la_oenb_core[105] = 2
la_oenb_core[106] = 1 | la_oenb_core[106] = 2
la_data_out_core[100] = 1 | la_data_out_core[100] = 2
la_data_out_core[101] = 1 | la_data_out_core[101] = 2
la_data_out_core[102] = 1 | la_data_out_core[102] = 2
la_data_out_core[103] = 1 | la_data_out_core[103] = 2
la_data_out_core[104] = 1 | la_data_out_core[104] = 2
la_data_out_core[105] = 1 | la_data_out_core[105] = 2
la_data_out_core[106] = 1 | la_data_out_core[106] = 2
la_data_out_core[107] = 1 | la_data_out_core[107] = 2
la_data_in_core[104] = 1 | la_data_in_core[104] = 2
la_data_in_core[105] = 1 | la_data_in_core[105] = 2
la_data_in_core[106] = 1 | la_data_in_core[106] = 2
la_data_in_core[107] = 1 | la_data_in_core[107] = 2
la_data_in_core[100] = 1 | la_data_in_core[100] = 2
la_data_in_core[101] = 1 | la_data_in_core[101] = 2
la_data_in_core[102] = 1 | la_data_in_core[102] = 2
la_data_in_core[103] = 1 | la_data_in_core[103] = 2
la_data_in_core[88] = 1 | la_data_in_core[88] = 2
la_data_in_core[89] = 1 | la_data_in_core[89] = 2
la_data_in_core[90] = 1 | la_data_in_core[90] = 2
la_data_in_core[91] = 1 | la_data_in_core[91] = 2
la_data_in_core[92] = 1 | la_data_in_core[92] = 2
la_oenb_core[87] = 1 | la_oenb_core[87] = 2
la_oenb_core[88] = 1 | la_oenb_core[88] = 2
la_oenb_core[89] = 1 | la_oenb_core[89] = 2
la_oenb_core[90] = 1 | la_oenb_core[90] = 2
la_oenb_core[91] = 1 | la_oenb_core[91] = 2
la_oenb_core[92] = 1 | la_oenb_core[92] = 2
la_oenb_core[93] = 1 | la_oenb_core[93] = 2
la_oenb_core[94] = 1 | la_oenb_core[94] = 2
la_oenb_core[95] = 1 | la_oenb_core[95] = 2
la_oenb_core[96] = 1 | la_oenb_core[96] = 2
la_oenb_core[97] = 1 | la_oenb_core[97] = 2
la_oenb_core[98] = 1 | la_oenb_core[98] = 2
la_oenb_core[99] = 1 | la_oenb_core[99] = 2
la_data_in_core[93] = 1 | la_data_in_core[93] = 2
la_data_out_core[67] = 1 | la_data_out_core[67] = 2
la_data_out_core[68] = 1 | la_data_out_core[68] = 2
la_data_out_core[69] = 1 | la_data_out_core[69] = 2
la_data_out_core[70] = 1 | la_data_out_core[70] = 2
la_data_out_core[71] = 1 | la_data_out_core[71] = 2
la_data_out_core[72] = 1 | la_data_out_core[72] = 2
la_data_out_core[73] = 1 | la_data_out_core[73] = 2
la_data_out_core[74] = 1 | la_data_out_core[74] = 2
la_data_out_core[75] = 1 | la_data_out_core[75] = 2
la_data_out_core[76] = 1 | la_data_out_core[76] = 2
la_data_out_core[77] = 1 | la_data_out_core[77] = 2
la_data_out_core[78] = 1 | la_data_out_core[78] = 2
la_data_out_core[79] = 1 | la_data_out_core[79] = 2
la_data_out_core[80] = 1 | la_data_out_core[80] = 2
la_data_out_core[81] = 1 | la_data_out_core[81] = 2
la_data_out_core[82] = 1 | la_data_out_core[82] = 2
la_data_out_core[83] = 1 | la_data_out_core[83] = 2
la_data_out_core[84] = 1 | la_data_out_core[84] = 2
la_data_out_core[85] = 1 | la_data_out_core[85] = 2
la_data_out_core[86] = 1 | la_data_out_core[86] = 2
la_data_in_core[87] = 1 | la_data_in_core[87] = 2
la_data_in_core[67] = 1 | la_data_in_core[67] = 2
la_data_in_core[68] = 1 | la_data_in_core[68] = 2
la_data_in_core[69] = 1 | la_data_in_core[69] = 2
la_data_in_core[70] = 1 | la_data_in_core[70] = 2
la_data_in_core[71] = 1 | la_data_in_core[71] = 2
la_data_in_core[72] = 1 | la_data_in_core[72] = 2
la_data_in_core[73] = 1 | la_data_in_core[73] = 2
la_data_in_core[74] = 1 | la_data_in_core[74] = 2
la_data_in_core[75] = 1 | la_data_in_core[75] = 2
la_data_in_core[76] = 1 | la_data_in_core[76] = 2
la_data_in_core[77] = 1 | la_data_in_core[77] = 2
la_data_in_core[78] = 1 | la_data_in_core[78] = 2
la_data_in_core[79] = 1 | la_data_in_core[79] = 2
la_data_in_core[80] = 1 | la_data_in_core[80] = 2
la_data_in_core[81] = 1 | la_data_in_core[81] = 2
la_data_in_core[82] = 1 | la_data_in_core[82] = 2
la_data_in_core[83] = 1 | la_data_in_core[83] = 2
la_data_in_core[84] = 1 | la_data_in_core[84] = 2
la_data_in_core[85] = 1 | la_data_in_core[85] = 2
la_data_in_core[86] = 1 | la_data_in_core[86] = 2
la_oenb_core[67] = 1 | la_oenb_core[67] = 2
la_oenb_core[68] = 1 | la_oenb_core[68] = 2
la_oenb_core[69] = 1 | la_oenb_core[69] = 2
la_oenb_core[70] = 1 | la_oenb_core[70] = 2
la_oenb_core[71] = 1 | la_oenb_core[71] = 2
la_oenb_core[72] = 1 | la_oenb_core[72] = 2
la_oenb_core[73] = 1 | la_oenb_core[73] = 2
la_oenb_core[74] = 1 | la_oenb_core[74] = 2
la_oenb_core[75] = 1 | la_oenb_core[75] = 2
la_oenb_core[76] = 1 | la_oenb_core[76] = 2
la_oenb_core[77] = 1 | la_oenb_core[77] = 2
la_oenb_core[78] = 1 | la_oenb_core[78] = 2
la_oenb_core[79] = 1 | la_oenb_core[79] = 2
la_oenb_core[80] = 1 | la_oenb_core[80] = 2
la_oenb_core[81] = 1 | la_oenb_core[81] = 2
la_oenb_core[82] = 1 | la_oenb_core[82] = 2
la_oenb_core[83] = 1 | la_oenb_core[83] = 2
la_oenb_core[84] = 1 | la_oenb_core[84] = 2
la_oenb_core[85] = 1 | la_oenb_core[85] = 2
la_oenb_core[86] = 1 | la_oenb_core[86] = 2
la_data_in_core[55] = 1 | la_data_in_core[55] = 2
la_data_in_core[56] = 1 | la_data_in_core[56] = 2
la_data_in_core[57] = 1 | la_data_in_core[57] = 2
la_data_in_core[58] = 1 | la_data_in_core[58] = 2
la_data_in_core[59] = 1 | la_data_in_core[59] = 2
la_data_in_core[60] = 1 | la_data_in_core[60] = 2
la_oenb_core[46] = 1 | la_oenb_core[46] = 2
la_oenb_core[47] = 1 | la_oenb_core[47] = 2
la_oenb_core[48] = 1 | la_oenb_core[48] = 2
la_oenb_core[49] = 1 | la_oenb_core[49] = 2
la_oenb_core[50] = 1 | la_oenb_core[50] = 2
la_oenb_core[51] = 1 | la_oenb_core[51] = 2
la_oenb_core[52] = 1 | la_oenb_core[52] = 2
la_oenb_core[53] = 1 | la_oenb_core[53] = 2
la_oenb_core[54] = 1 | la_oenb_core[54] = 2
la_oenb_core[55] = 1 | la_oenb_core[55] = 2
la_oenb_core[56] = 1 | la_oenb_core[56] = 2
la_oenb_core[57] = 1 | la_oenb_core[57] = 2
la_oenb_core[58] = 1 | la_oenb_core[58] = 2
la_oenb_core[59] = 1 | la_oenb_core[59] = 2
la_oenb_core[60] = 1 | la_oenb_core[60] = 2
la_oenb_core[61] = 1 | la_oenb_core[61] = 2
la_oenb_core[62] = 1 | la_oenb_core[62] = 2
la_oenb_core[63] = 1 | la_oenb_core[63] = 2
la_oenb_core[64] = 1 | la_oenb_core[64] = 2
la_oenb_core[65] = 1 | la_oenb_core[65] = 2
la_oenb_core[66] = 1 | la_oenb_core[66] = 2
la_data_in_core[61] = 1 | la_data_in_core[61] = 2
la_data_in_core[62] = 1 | la_data_in_core[62] = 2
la_data_in_core[63] = 1 | la_data_in_core[63] = 2
la_data_in_core[64] = 1 | la_data_in_core[64] = 2
la_data_in_core[65] = 1 | la_data_in_core[65] = 2
la_data_in_core[66] = 1 | la_data_in_core[66] = 2
la_data_out_core[64] = 1 | la_data_out_core[64] = 2
la_data_out_core[65] = 1 | la_data_out_core[65] = 2
la_data_out_core[66] = 1 | la_data_out_core[66] = 2
la_data_out_core[61] = 1 | la_data_out_core[61] = 2
la_data_out_core[62] = 1 | la_data_out_core[62] = 2
la_data_out_core[63] = 1 | la_data_out_core[63] = 2
la_data_in_core[47] = 1 | la_data_in_core[47] = 2
la_data_in_core[48] = 1 | la_data_in_core[48] = 2
la_data_in_core[49] = 1 | la_data_in_core[49] = 2
la_data_in_core[50] = 1 | la_data_in_core[50] = 2
la_data_in_core[51] = 1 | la_data_in_core[51] = 2
la_data_in_core[52] = 1 | la_data_in_core[52] = 2
la_data_in_core[53] = 1 | la_data_in_core[53] = 2
la_data_in_core[54] = 1 | la_data_in_core[54] = 2
la_data_out_core[47] = 1 | la_data_out_core[47] = 2
la_data_out_core[48] = 1 | la_data_out_core[48] = 2
la_data_out_core[49] = 1 | la_data_out_core[49] = 2
la_data_out_core[50] = 1 | la_data_out_core[50] = 2
la_data_out_core[51] = 1 | la_data_out_core[51] = 2
la_data_out_core[52] = 1 | la_data_out_core[52] = 2
la_data_out_core[53] = 1 | la_data_out_core[53] = 2
la_data_out_core[54] = 1 | la_data_out_core[54] = 2
la_data_out_core[55] = 1 | la_data_out_core[55] = 2
la_data_out_core[56] = 1 | la_data_out_core[56] = 2
la_data_out_core[57] = 1 | la_data_out_core[57] = 2
la_data_out_core[58] = 1 | la_data_out_core[58] = 2
la_data_out_core[59] = 1 | la_data_out_core[59] = 2
la_data_out_core[60] = 1 | la_data_out_core[60] = 2
la_data_in_core[37] = 1 | la_data_in_core[37] = 2
la_data_in_core[38] = 1 | la_data_in_core[38] = 2
la_data_in_core[39] = 1 | la_data_in_core[39] = 2
la_data_in_core[40] = 1 | la_data_in_core[40] = 2
la_data_in_core[41] = 1 | la_data_in_core[41] = 2
la_data_out_core[26] = 1 | la_data_out_core[26] = 2
la_data_out_core[27] = 1 | la_data_out_core[27] = 2
la_data_out_core[28] = 1 | la_data_out_core[28] = 2
la_data_out_core[29] = 1 | la_data_out_core[29] = 2
la_data_out_core[30] = 1 | la_data_out_core[30] = 2
la_data_out_core[31] = 1 | la_data_out_core[31] = 2
la_data_out_core[32] = 1 | la_data_out_core[32] = 2
la_data_out_core[33] = 1 | la_data_out_core[33] = 2
la_data_out_core[34] = 1 | la_data_out_core[34] = 2
la_data_out_core[35] = 1 | la_data_out_core[35] = 2
la_data_out_core[36] = 1 | la_data_out_core[36] = 2
la_data_out_core[37] = 1 | la_data_out_core[37] = 2
la_data_out_core[38] = 1 | la_data_out_core[38] = 2
la_data_out_core[39] = 1 | la_data_out_core[39] = 2
la_oenb_core[26] = 1 | la_oenb_core[26] = 2
la_oenb_core[27] = 1 | la_oenb_core[27] = 2
la_oenb_core[28] = 1 | la_oenb_core[28] = 2
la_oenb_core[29] = 1 | la_oenb_core[29] = 2
la_oenb_core[30] = 1 | la_oenb_core[30] = 2
la_oenb_core[31] = 1 | la_oenb_core[31] = 2
la_oenb_core[32] = 1 | la_oenb_core[32] = 2
la_oenb_core[33] = 1 | la_oenb_core[33] = 2
la_oenb_core[34] = 1 | la_oenb_core[34] = 2
la_oenb_core[35] = 1 | la_oenb_core[35] = 2
la_oenb_core[36] = 1 | la_oenb_core[36] = 2
la_oenb_core[37] = 1 | la_oenb_core[37] = 2
la_oenb_core[38] = 1 | la_oenb_core[38] = 2
la_oenb_core[39] = 1 | la_oenb_core[39] = 2
la_oenb_core[40] = 1 | la_oenb_core[40] = 2
la_oenb_core[41] = 1 | la_oenb_core[41] = 2
la_oenb_core[42] = 1 | la_oenb_core[42] = 2
la_oenb_core[43] = 1 | la_oenb_core[43] = 2
la_oenb_core[44] = 1 | la_oenb_core[44] = 2
la_oenb_core[45] = 1 | la_oenb_core[45] = 2
la_data_out_core[40] = 1 | la_data_out_core[40] = 2
la_data_out_core[41] = 1 | la_data_out_core[41] = 2
la_data_out_core[42] = 1 | la_data_out_core[42] = 2
la_data_out_core[43] = 1 | la_data_out_core[43] = 2
la_data_out_core[44] = 1 | la_data_out_core[44] = 2
la_data_out_core[45] = 1 | la_data_out_core[45] = 2
la_data_out_core[46] = 1 | la_data_out_core[46] = 2
la_data_in_core[42] = 1 | la_data_in_core[42] = 2
la_data_in_core[43] = 1 | la_data_in_core[43] = 2
la_data_in_core[44] = 1 | la_data_in_core[44] = 2
la_data_in_core[45] = 1 | la_data_in_core[45] = 2
la_data_in_core[46] = 1 | la_data_in_core[46] = 2
la_data_in_core[26] = 1 | la_data_in_core[26] = 2
la_data_in_core[27] = 1 | la_data_in_core[27] = 2
la_data_in_core[28] = 1 | la_data_in_core[28] = 2
la_data_in_core[29] = 1 | la_data_in_core[29] = 2
la_data_in_core[30] = 1 | la_data_in_core[30] = 2
la_data_in_core[31] = 1 | la_data_in_core[31] = 2
la_data_in_core[32] = 1 | la_data_in_core[32] = 2
la_data_in_core[33] = 1 | la_data_in_core[33] = 2
la_data_in_core[34] = 1 | la_data_in_core[34] = 2
la_data_in_core[35] = 1 | la_data_in_core[35] = 2
la_data_in_core[36] = 1 | la_data_in_core[36] = 2
la_data_out_core[17] = 1 | la_data_out_core[17] = 2
la_data_out_core[18] = 1 | la_data_out_core[18] = 2
la_data_out_core[19] = 1 | la_data_out_core[19] = 2
la_data_out_core[20] = 1 | la_data_out_core[20] = 2
la_data_out_core[21] = 1 | la_data_out_core[21] = 2
la_data_out_core[22] = 1 | la_data_out_core[22] = 2
la_data_out_core[23] = 1 | la_data_out_core[23] = 2
la_oenb_core[12] = 1 | la_oenb_core[12] = 2
la_oenb_core[13] = 1 | la_oenb_core[13] = 2
la_oenb_core[14] = 1 | la_oenb_core[14] = 2
la_oenb_core[15] = 1 | la_oenb_core[15] = 2
la_oenb_core[16] = 1 | la_oenb_core[16] = 2
la_oenb_core[17] = 1 | la_oenb_core[17] = 2
la_oenb_core[18] = 1 | la_oenb_core[18] = 2
la_oenb_core[19] = 1 | la_oenb_core[19] = 2
la_oenb_core[20] = 1 | la_oenb_core[20] = 2
la_oenb_core[21] = 1 | la_oenb_core[21] = 2
la_oenb_core[22] = 1 | la_oenb_core[22] = 2
la_oenb_core[23] = 1 | la_oenb_core[23] = 2
la_oenb_core[24] = 1 | la_oenb_core[24] = 2
la_oenb_core[25] = 1 | la_oenb_core[25] = 2
la_data_in_core[11] = 1 | la_data_in_core[11] = 2
la_oenb_core[5] = 1 | la_oenb_core[5] = 2
la_data_in_core[8] = 1 | la_data_in_core[8] = 2
la_data_in_core[10] = 1 | la_data_in_core[10] = 2
la_data_in_core[12] = 1 | la_data_in_core[12] = 2
la_data_in_core[13] = 1 | la_data_in_core[13] = 2
la_data_in_core[14] = 1 | la_data_in_core[14] = 2
la_data_in_core[15] = 1 | la_data_in_core[15] = 2
la_data_in_core[16] = 1 | la_data_in_core[16] = 2
la_oenb_core[6] = 1 | la_oenb_core[6] = 2
la_data_in_core[17] = 1 | la_data_in_core[17] = 2
la_data_in_core[18] = 1 | la_data_in_core[18] = 2
la_data_in_core[19] = 1 | la_data_in_core[19] = 2
la_data_in_core[9] = 1 | la_data_in_core[9] = 2
la_data_in_core[20] = 1 | la_data_in_core[20] = 2
la_data_out_core[6] = 1 | la_data_out_core[6] = 2
la_data_in_core[21] = 1 | la_data_in_core[21] = 2
la_oenb_core[7] = 1 | la_oenb_core[7] = 2
la_data_in_core[22] = 1 | la_data_in_core[22] = 2
la_data_in_core[23] = 1 | la_data_in_core[23] = 2
la_data_in_core[24] = 1 | la_data_in_core[24] = 2
la_data_in_core[25] = 1 | la_data_in_core[25] = 2
la_oenb_core[10] = 1 | la_oenb_core[10] = 2
la_data_out_core[24] = 1 | la_data_out_core[24] = 2
la_data_out_core[10] = 1 | la_data_out_core[10] = 2
la_data_out_core[25] = 1 | la_data_out_core[25] = 2
la_data_in_core[7] = 1 | la_data_in_core[7] = 2
la_data_out_core[7] = 1 | la_data_out_core[7] = 2
la_oenb_core[8] = 1 | la_oenb_core[8] = 2
la_data_in_core[6] = 1 | la_data_in_core[6] = 2
la_data_out_core[12] = 1 | la_data_out_core[12] = 2
la_data_out_core[13] = 1 | la_data_out_core[13] = 2
la_data_out_core[14] = 1 | la_data_out_core[14] = 2
la_data_out_core[9] = 1 | la_data_out_core[9] = 2
la_data_out_core[15] = 1 | la_data_out_core[15] = 2
la_data_out_core[16] = 1 | la_data_out_core[16] = 2
la_data_out_core[11] = 1 | la_data_out_core[11] = 2
la_oenb_core[11] = 1 | la_oenb_core[11] = 2
la_oenb_core[9] = 1 | la_oenb_core[9] = 2
la_data_out_core[8] = 1 | la_data_out_core[8] = 2
la_data_out_core[1] = 1 | la_data_out_core[1] = 2
la_data_in_core[0] = 1 | la_data_in_core[0] = 2
la_oenb_core[2] = 1 | la_oenb_core[2] = 2
la_data_out_core[0] = 1 | la_data_out_core[0] = 2
la_data_in_core[1] = 1 | la_data_in_core[1] = 2
la_data_in_core[2] = 1 | la_data_in_core[2] = 2
la_oenb_core[0] = 1 | la_oenb_core[0] = 2
la_data_in_core[5] = 1 | la_data_in_core[5] = 2
la_data_in_core[4] = 1 | la_data_in_core[4] = 2
la_oenb_core[1] = 1 | la_oenb_core[1] = 2
la_data_in_core[3] = 1 | la_data_in_core[3] = 2
la_oenb_core[3] = 1 | la_oenb_core[3] = 2
la_data_out_core[5] = 1 | la_data_out_core[5] = 2
la_data_out_core[4] = 1 | la_data_out_core[4] = 2
la_data_out_core[3] = 1 | la_data_out_core[3] = 2
la_data_out_core[2] = 1 | la_data_out_core[2] = 2
mprj_adr_o_user[18] = 1 | mprj_adr_o_user[18] = 2
mprj_adr_o_user[19] = 1 | mprj_adr_o_user[19] = 2
mprj_adr_o_user[20] = 1 | mprj_adr_o_user[20] = 2
mprj_adr_o_user[21] = 1 | mprj_adr_o_user[21] = 2
mprj_adr_o_user[22] = 1 | mprj_adr_o_user[22] = 2
mprj_adr_o_user[23] = 1 | mprj_adr_o_user[23] = 2
mprj_adr_o_user[24] = 1 | mprj_adr_o_user[24] = 2
mprj_adr_o_user[25] = 1 | mprj_adr_o_user[25] = 2
mprj_adr_o_user[26] = 1 | mprj_adr_o_user[26] = 2
mprj_adr_o_user[27] = 1 | mprj_adr_o_user[27] = 2
mprj_adr_o_user[28] = 1 | mprj_adr_o_user[28] = 2
mprj_adr_o_user[29] = 1 | mprj_adr_o_user[29] = 2
mprj_adr_o_user[30] = 1 | mprj_adr_o_user[30] = 2
mprj_adr_o_user[31] = 1 | mprj_adr_o_user[31] = 2
mprj_dat_i_user[17] = 1 | mprj_dat_i_user[17] = 2
mprj_dat_i_user[18] = 1 | mprj_dat_i_user[18] = 2
mprj_dat_i_user[19] = 1 | mprj_dat_i_user[19] = 2
mprj_dat_i_user[20] = 1 | mprj_dat_i_user[20] = 2
mprj_dat_i_user[21] = 1 | mprj_dat_i_user[21] = 2
mprj_dat_i_user[22] = 1 | mprj_dat_i_user[22] = 2
mprj_dat_i_user[23] = 1 | mprj_dat_i_user[23] = 2
mprj_dat_i_user[24] = 1 | mprj_dat_i_user[24] = 2
mprj_dat_i_user[25] = 1 | mprj_dat_i_user[25] = 2
mprj_dat_i_user[26] = 1 | mprj_dat_i_user[26] = 2
mprj_dat_i_user[27] = 1 | mprj_dat_i_user[27] = 2
mprj_dat_i_user[28] = 1 | mprj_dat_i_user[28] = 2
mprj_dat_i_user[29] = 1 | mprj_dat_i_user[29] = 2
mprj_dat_i_user[30] = 1 | mprj_dat_i_user[30] = 2
mprj_dat_i_user[31] = 1 | mprj_dat_i_user[31] = 2
mprj_dat_o_user[17] = 1 | mprj_dat_o_user[17] = 2
mprj_dat_o_user[18] = 1 | mprj_dat_o_user[18] = 2
mprj_dat_o_user[19] = 1 | mprj_dat_o_user[19] = 2
mprj_dat_o_user[20] = 1 | mprj_dat_o_user[20] = 2
mprj_dat_o_user[21] = 1 | mprj_dat_o_user[21] = 2
mprj_dat_o_user[22] = 1 | mprj_dat_o_user[22] = 2
mprj_dat_o_user[23] = 1 | mprj_dat_o_user[23] = 2
mprj_dat_o_user[24] = 1 | mprj_dat_o_user[24] = 2
mprj_dat_o_user[25] = 1 | mprj_dat_o_user[25] = 2
mprj_dat_o_user[26] = 1 | mprj_dat_o_user[26] = 2
mprj_dat_o_user[27] = 1 | mprj_dat_o_user[27] = 2
mprj_dat_o_user[28] = 1 | mprj_dat_o_user[28] = 2
mprj_dat_o_user[29] = 1 | mprj_dat_o_user[29] = 2
mprj_dat_o_user[30] = 1 | mprj_dat_o_user[30] = 2
mprj_dat_o_user[31] = 1 | mprj_dat_o_user[31] = 2
la_oenb_core[4] = 1 | la_oenb_core[4] = 2
mprj_dat_i_user[1] = 1 | mprj_dat_i_user[1] = 2
mprj_adr_o_user[14] = 1 | mprj_adr_o_user[14] = 2
mprj_adr_o_user[15] = 1 | mprj_adr_o_user[15] = 2
mprj_adr_o_user[16] = 1 | mprj_adr_o_user[16] = 2
mprj_adr_o_user[17] = 1 | mprj_adr_o_user[17] = 2
mprj_ack_i_user = 1 | mprj_ack_i_user = 2
mprj_adr_o_user[0] = 1 | mprj_adr_o_user[0] = 2
mprj_adr_o_user[2] = 1 | mprj_adr_o_user[2] = 2
mprj_adr_o_user[1] = 1 | mprj_adr_o_user[1] = 2
mprj_adr_o_user[10] = 1 | mprj_adr_o_user[10] = 2
mprj_adr_o_user[3] = 1 | mprj_adr_o_user[3] = 2
mprj_dat_i_user[2] = 1 | mprj_dat_i_user[2] = 2
mprj_adr_o_user[4] = 1 | mprj_adr_o_user[4] = 2
mprj_adr_o_user[5] = 1 | mprj_adr_o_user[5] = 2
mprj_dat_i_user[3] = 1 | mprj_dat_i_user[3] = 2
mprj_dat_i_user[4] = 1 | mprj_dat_i_user[4] = 2
mprj_dat_i_user[5] = 1 | mprj_dat_i_user[5] = 2
mprj_dat_i_user[6] = 1 | mprj_dat_i_user[6] = 2
mprj_dat_i_user[7] = 1 | mprj_dat_i_user[7] = 2
mprj_dat_i_user[8] = 1 | mprj_dat_i_user[8] = 2
mprj_dat_i_user[9] = 1 | mprj_dat_i_user[9] = 2
mprj_dat_o_user[0] = 1 | mprj_dat_o_user[0] = 2
mprj_dat_o_user[10] = 1 | mprj_dat_o_user[10] = 2
mprj_dat_o_user[11] = 1 | mprj_dat_o_user[11] = 2
mprj_dat_o_user[12] = 1 | mprj_dat_o_user[12] = 2
mprj_dat_o_user[13] = 1 | mprj_dat_o_user[13] = 2
mprj_dat_o_user[14] = 1 | mprj_dat_o_user[14] = 2
mprj_dat_o_user[15] = 1 | mprj_dat_o_user[15] = 2
mprj_dat_o_user[16] = 1 | mprj_dat_o_user[16] = 2
mprj_adr_o_user[6] = 1 | mprj_adr_o_user[6] = 2
mprj_adr_o_user[7] = 1 | mprj_adr_o_user[7] = 2
mprj_adr_o_user[8] = 1 | mprj_adr_o_user[8] = 2
mprj_dat_o_user[1] = 1 | mprj_dat_o_user[1] = 2
mprj_adr_o_user[9] = 1 | mprj_adr_o_user[9] = 2
mprj_cyc_o_user = 1 | mprj_cyc_o_user = 2
mprj_dat_i_user[0] = 1 | mprj_dat_i_user[0] = 2
mprj_dat_i_user[10] = 1 | mprj_dat_i_user[10] = 2
mprj_dat_i_user[11] = 1 | mprj_dat_i_user[11] = 2
mprj_dat_i_user[12] = 1 | mprj_dat_i_user[12] = 2
mprj_dat_i_user[13] = 1 | mprj_dat_i_user[13] = 2
mprj_dat_i_user[14] = 1 | mprj_dat_i_user[14] = 2
mprj_dat_i_user[15] = 1 | mprj_dat_i_user[15] = 2
mprj_dat_i_user[16] = 1 | mprj_dat_i_user[16] = 2
mprj_dat_o_user[2] = 1 | mprj_dat_o_user[2] = 2
mprj_adr_o_user[11] = 1 | mprj_adr_o_user[11] = 2
mprj_adr_o_user[12] = 1 | mprj_adr_o_user[12] = 2
mprj_dat_o_user[3] = 1 | mprj_dat_o_user[3] = 2
mprj_dat_o_user[4] = 1 | mprj_dat_o_user[4] = 2
mprj_dat_o_user[5] = 1 | mprj_dat_o_user[5] = 2
mprj_dat_o_user[6] = 1 | mprj_dat_o_user[6] = 2
mprj_dat_o_user[7] = 1 | mprj_dat_o_user[7] = 2
mprj_dat_o_user[8] = 1 | mprj_dat_o_user[8] = 2
mprj_dat_o_user[9] = 1 | mprj_dat_o_user[9] = 2
mprj_sel_o_user[0] = 1 | mprj_sel_o_user[0] = 2
mprj_sel_o_user[1] = 1 | mprj_sel_o_user[1] = 2
mprj_sel_o_user[2] = 1 | mprj_sel_o_user[2] = 2
mprj_sel_o_user[3] = 1 | mprj_sel_o_user[3] = 2
mprj_stb_o_user = 1 | mprj_stb_o_user = 2
mprj_we_o_user = 1 | mprj_we_o_user = 2
user_clock = 1 | user_clock = 2
mprj_adr_o_user[13] = 1 | mprj_adr_o_user[13] = 2
user_reset = 1 | user_reset = 2
la_data_in_mprj[5] = 2 | la_data_in_mprj[5] = 2
la_data_in_mprj[6] = 2 | la_data_in_mprj[6] = 2
la_data_in_mprj[7] = 2 | la_data_in_mprj[7] = 2
la_data_in_mprj[8] = 2 | la_data_in_mprj[8] = 2
la_data_in_mprj[9] = 2 | la_data_in_mprj[9] = 2
la_data_in_mprj[0] = 2 | la_data_in_mprj[0] = 2
la_data_in_mprj[10] = 2 | la_data_in_mprj[10] = 2
la_data_in_mprj[11] = 2 | la_data_in_mprj[11] = 2
la_data_in_mprj[12] = 2 | la_data_in_mprj[12] = 2
la_data_in_mprj[13] = 2 | la_data_in_mprj[13] = 2
la_data_in_mprj[14] = 2 | la_data_in_mprj[14] = 2
la_data_in_mprj[15] = 2 | la_data_in_mprj[15] = 2
la_data_in_mprj[16] = 2 | la_data_in_mprj[16] = 2
la_data_in_mprj[17] = 2 | la_data_in_mprj[17] = 2
la_data_in_mprj[18] = 2 | la_data_in_mprj[18] = 2
la_data_in_mprj[1] = 2 | la_data_in_mprj[1] = 2
la_data_in_mprj[2] = 2 | la_data_in_mprj[2] = 2
la_data_in_mprj[3] = 2 | la_data_in_mprj[3] = 2
la_data_in_mprj[4] = 2 | la_data_in_mprj[4] = 2
la_data_out_mprj[0] = 2 | la_data_out_mprj[0] = 2
la_data_out_mprj[10] = 2 | la_data_out_mprj[10] = 2
la_data_out_mprj[11] = 2 | la_data_out_mprj[11] = 2
la_data_out_mprj[12] = 2 | la_data_out_mprj[12] = 2
la_data_out_mprj[13] = 2 | la_data_out_mprj[13] = 2
la_data_out_mprj[14] = 2 | la_data_out_mprj[14] = 2
la_data_out_mprj[15] = 2 | la_data_out_mprj[15] = 2
la_data_out_mprj[16] = 2 | la_data_out_mprj[16] = 2
la_data_out_mprj[17] = 2 | la_data_out_mprj[17] = 2
la_data_out_mprj[1] = 2 | la_data_out_mprj[1] = 2
la_data_out_mprj[2] = 2 | la_data_out_mprj[2] = 2
la_data_out_mprj[3] = 2 | la_data_out_mprj[3] = 2
la_data_out_mprj[4] = 2 | la_data_out_mprj[4] = 2
la_oenb_mprj[0] = 2 | la_oenb_mprj[0] = 2
la_oenb_mprj[10] = 2 | la_oenb_mprj[10] = 2
la_oenb_mprj[11] = 2 | la_oenb_mprj[11] = 2
la_oenb_mprj[12] = 2 | la_oenb_mprj[12] = 2
la_oenb_mprj[13] = 2 | la_oenb_mprj[13] = 2
la_oenb_mprj[14] = 2 | la_oenb_mprj[14] = 2
la_oenb_mprj[15] = 2 | la_oenb_mprj[15] = 2
la_oenb_mprj[16] = 2 | la_oenb_mprj[16] = 2
la_oenb_mprj[17] = 2 | la_oenb_mprj[17] = 2
la_oenb_mprj[1] = 2 | la_oenb_mprj[1] = 2
la_oenb_mprj[2] = 2 | la_oenb_mprj[2] = 2
la_oenb_mprj[3] = 2 | la_oenb_mprj[3] = 2
la_oenb_mprj[4] = 2 | la_oenb_mprj[4] = 2
la_oenb_mprj[5] = 2 | la_oenb_mprj[5] = 2
la_oenb_mprj[6] = 2 | la_oenb_mprj[6] = 2
la_oenb_mprj[7] = 2 | la_oenb_mprj[7] = 2
la_oenb_mprj[8] = 2 | la_oenb_mprj[8] = 2
la_oenb_mprj[9] = 2 | la_oenb_mprj[9] = 2
la_data_out_mprj[5] = 2 | la_data_out_mprj[5] = 2
la_data_out_mprj[6] = 2 | la_data_out_mprj[6] = 2
la_data_out_mprj[7] = 2 | la_data_out_mprj[7] = 2
la_data_out_mprj[8] = 2 | la_data_out_mprj[8] = 2
la_data_out_mprj[9] = 2 | la_data_out_mprj[9] = 2
la_iena_mprj[0] = 2 | la_iena_mprj[0] = 2
la_iena_mprj[10] = 2 | la_iena_mprj[10] = 2
la_iena_mprj[11] = 2 | la_iena_mprj[11] = 2
la_iena_mprj[12] = 2 | la_iena_mprj[12] = 2
la_iena_mprj[13] = 2 | la_iena_mprj[13] = 2
la_iena_mprj[14] = 2 | la_iena_mprj[14] = 2
la_iena_mprj[15] = 2 | la_iena_mprj[15] = 2
la_iena_mprj[16] = 2 | la_iena_mprj[16] = 2
la_iena_mprj[17] = 2 | la_iena_mprj[17] = 2
la_iena_mprj[1] = 2 | la_iena_mprj[1] = 2
la_iena_mprj[2] = 2 | la_iena_mprj[2] = 2
la_iena_mprj[3] = 2 | la_iena_mprj[3] = 2
la_iena_mprj[4] = 2 | la_iena_mprj[4] = 2
la_iena_mprj[5] = 2 | la_iena_mprj[5] = 2
la_iena_mprj[6] = 2 | la_iena_mprj[6] = 2
la_iena_mprj[7] = 2 | la_iena_mprj[7] = 2
la_iena_mprj[8] = 2 | la_iena_mprj[8] = 2
la_iena_mprj[9] = 2 | la_iena_mprj[9] = 2
la_data_in_mprj[36] = 2 | la_data_in_mprj[36] = 2
la_data_in_mprj[37] = 2 | la_data_in_mprj[37] = 2
la_data_in_mprj[20] = 2 | la_data_in_mprj[20] = 2
la_data_in_mprj[21] = 2 | la_data_in_mprj[21] = 2
la_data_in_mprj[22] = 2 | la_data_in_mprj[22] = 2
la_data_in_mprj[23] = 2 | la_data_in_mprj[23] = 2
la_data_in_mprj[24] = 2 | la_data_in_mprj[24] = 2
la_oenb_mprj[18] = 2 | la_oenb_mprj[18] = 2
la_oenb_mprj[19] = 2 | la_oenb_mprj[19] = 2
la_data_in_mprj[25] = 2 | la_data_in_mprj[25] = 2
la_oenb_mprj[20] = 2 | la_oenb_mprj[20] = 2
la_oenb_mprj[21] = 2 | la_oenb_mprj[21] = 2
la_oenb_mprj[22] = 2 | la_oenb_mprj[22] = 2
la_oenb_mprj[23] = 2 | la_oenb_mprj[23] = 2
la_oenb_mprj[24] = 2 | la_oenb_mprj[24] = 2
la_oenb_mprj[25] = 2 | la_oenb_mprj[25] = 2
la_oenb_mprj[26] = 2 | la_oenb_mprj[26] = 2
la_oenb_mprj[27] = 2 | la_oenb_mprj[27] = 2
la_oenb_mprj[28] = 2 | la_oenb_mprj[28] = 2
la_oenb_mprj[29] = 2 | la_oenb_mprj[29] = 2
la_data_in_mprj[26] = 2 | la_data_in_mprj[26] = 2
la_oenb_mprj[30] = 2 | la_oenb_mprj[30] = 2
la_oenb_mprj[31] = 2 | la_oenb_mprj[31] = 2
la_oenb_mprj[32] = 2 | la_oenb_mprj[32] = 2
la_oenb_mprj[33] = 2 | la_oenb_mprj[33] = 2
la_oenb_mprj[34] = 2 | la_oenb_mprj[34] = 2
la_oenb_mprj[35] = 2 | la_oenb_mprj[35] = 2
la_oenb_mprj[36] = 2 | la_oenb_mprj[36] = 2
la_oenb_mprj[37] = 2 | la_oenb_mprj[37] = 2
la_data_in_mprj[27] = 2 | la_data_in_mprj[27] = 2
la_data_in_mprj[28] = 2 | la_data_in_mprj[28] = 2
la_data_in_mprj[29] = 2 | la_data_in_mprj[29] = 2
la_data_in_mprj[19] = 2 | la_data_in_mprj[19] = 2
la_data_out_mprj[18] = 2 | la_data_out_mprj[18] = 2
la_data_out_mprj[19] = 2 | la_data_out_mprj[19] = 2
la_data_in_mprj[30] = 2 | la_data_in_mprj[30] = 2
la_data_out_mprj[20] = 2 | la_data_out_mprj[20] = 2
la_data_out_mprj[21] = 2 | la_data_out_mprj[21] = 2
la_data_out_mprj[22] = 2 | la_data_out_mprj[22] = 2
la_data_out_mprj[23] = 2 | la_data_out_mprj[23] = 2
la_data_out_mprj[24] = 2 | la_data_out_mprj[24] = 2
la_data_out_mprj[25] = 2 | la_data_out_mprj[25] = 2
la_data_out_mprj[26] = 2 | la_data_out_mprj[26] = 2
la_data_out_mprj[27] = 2 | la_data_out_mprj[27] = 2
la_data_out_mprj[28] = 2 | la_data_out_mprj[28] = 2
la_data_out_mprj[29] = 2 | la_data_out_mprj[29] = 2
la_data_in_mprj[31] = 2 | la_data_in_mprj[31] = 2
la_data_out_mprj[30] = 2 | la_data_out_mprj[30] = 2
la_data_out_mprj[31] = 2 | la_data_out_mprj[31] = 2
la_data_out_mprj[32] = 2 | la_data_out_mprj[32] = 2
la_iena_mprj[18] = 2 | la_iena_mprj[18] = 2
la_iena_mprj[19] = 2 | la_iena_mprj[19] = 2
la_data_out_mprj[33] = 2 | la_data_out_mprj[33] = 2
la_iena_mprj[20] = 2 | la_iena_mprj[20] = 2
la_iena_mprj[21] = 2 | la_iena_mprj[21] = 2
la_iena_mprj[22] = 2 | la_iena_mprj[22] = 2
la_iena_mprj[23] = 2 | la_iena_mprj[23] = 2
la_iena_mprj[24] = 2 | la_iena_mprj[24] = 2
la_iena_mprj[25] = 2 | la_iena_mprj[25] = 2
la_iena_mprj[26] = 2 | la_iena_mprj[26] = 2
la_iena_mprj[27] = 2 | la_iena_mprj[27] = 2
la_iena_mprj[28] = 2 | la_iena_mprj[28] = 2
la_iena_mprj[29] = 2 | la_iena_mprj[29] = 2
la_data_out_mprj[34] = 2 | la_data_out_mprj[34] = 2
la_iena_mprj[30] = 2 | la_iena_mprj[30] = 2
la_iena_mprj[31] = 2 | la_iena_mprj[31] = 2
la_iena_mprj[32] = 2 | la_iena_mprj[32] = 2
la_iena_mprj[33] = 2 | la_iena_mprj[33] = 2
la_iena_mprj[34] = 2 | la_iena_mprj[34] = 2
la_iena_mprj[35] = 2 | la_iena_mprj[35] = 2
la_iena_mprj[36] = 2 | la_iena_mprj[36] = 2
la_iena_mprj[37] = 2 | la_iena_mprj[37] = 2
la_data_out_mprj[35] = 2 | la_data_out_mprj[35] = 2
la_data_out_mprj[36] = 2 | la_data_out_mprj[36] = 2
la_data_out_mprj[37] = 2 | la_data_out_mprj[37] = 2
la_data_in_mprj[32] = 2 | la_data_in_mprj[32] = 2
la_data_in_mprj[33] = 2 | la_data_in_mprj[33] = 2
la_data_in_mprj[34] = 2 | la_data_in_mprj[34] = 2
la_data_in_mprj[35] = 2 | la_data_in_mprj[35] = 2
la_data_in_mprj[38] = 2 | la_data_in_mprj[38] = 2
la_data_in_mprj[39] = 2 | la_data_in_mprj[39] = 2
la_oenb_mprj[38] = 2 | la_oenb_mprj[38] = 2
la_oenb_mprj[39] = 2 | la_oenb_mprj[39] = 2
la_oenb_mprj[40] = 2 | la_oenb_mprj[40] = 2
la_oenb_mprj[41] = 2 | la_oenb_mprj[41] = 2
la_oenb_mprj[42] = 2 | la_oenb_mprj[42] = 2
la_oenb_mprj[43] = 2 | la_oenb_mprj[43] = 2
la_oenb_mprj[44] = 2 | la_oenb_mprj[44] = 2
la_oenb_mprj[45] = 2 | la_oenb_mprj[45] = 2
la_oenb_mprj[46] = 2 | la_oenb_mprj[46] = 2
la_oenb_mprj[47] = 2 | la_oenb_mprj[47] = 2
la_oenb_mprj[48] = 2 | la_oenb_mprj[48] = 2
la_oenb_mprj[49] = 2 | la_oenb_mprj[49] = 2
la_data_in_mprj[40] = 2 | la_data_in_mprj[40] = 2
la_oenb_mprj[50] = 2 | la_oenb_mprj[50] = 2
la_oenb_mprj[51] = 2 | la_oenb_mprj[51] = 2
la_oenb_mprj[52] = 2 | la_oenb_mprj[52] = 2
la_oenb_mprj[53] = 2 | la_oenb_mprj[53] = 2
la_oenb_mprj[54] = 2 | la_oenb_mprj[54] = 2
la_oenb_mprj[55] = 2 | la_oenb_mprj[55] = 2
la_oenb_mprj[56] = 2 | la_oenb_mprj[56] = 2
la_data_in_mprj[41] = 2 | la_data_in_mprj[41] = 2
la_data_in_mprj[42] = 2 | la_data_in_mprj[42] = 2
la_data_in_mprj[43] = 2 | la_data_in_mprj[43] = 2
la_data_in_mprj[44] = 2 | la_data_in_mprj[44] = 2
la_data_out_mprj[38] = 2 | la_data_out_mprj[38] = 2
la_data_out_mprj[54] = 2 | la_data_out_mprj[54] = 2
la_data_out_mprj[55] = 2 | la_data_out_mprj[55] = 2
la_data_out_mprj[56] = 2 | la_data_out_mprj[56] = 2
la_data_out_mprj[57] = 2 | la_data_out_mprj[57] = 2
la_data_out_mprj[39] = 2 | la_data_out_mprj[39] = 2
la_data_in_mprj[45] = 2 | la_data_in_mprj[45] = 2
la_data_out_mprj[40] = 2 | la_data_out_mprj[40] = 2
la_data_out_mprj[41] = 2 | la_data_out_mprj[41] = 2
la_data_out_mprj[42] = 2 | la_data_out_mprj[42] = 2
la_data_out_mprj[43] = 2 | la_data_out_mprj[43] = 2
la_data_out_mprj[44] = 2 | la_data_out_mprj[44] = 2
la_data_out_mprj[45] = 2 | la_data_out_mprj[45] = 2
la_data_out_mprj[46] = 2 | la_data_out_mprj[46] = 2
la_data_out_mprj[47] = 2 | la_data_out_mprj[47] = 2
la_data_out_mprj[48] = 2 | la_data_out_mprj[48] = 2
la_data_out_mprj[49] = 2 | la_data_out_mprj[49] = 2
la_data_in_mprj[46] = 2 | la_data_in_mprj[46] = 2
la_data_out_mprj[50] = 2 | la_data_out_mprj[50] = 2
la_data_out_mprj[51] = 2 | la_data_out_mprj[51] = 2
la_data_out_mprj[52] = 2 | la_data_out_mprj[52] = 2
la_data_out_mprj[53] = 2 | la_data_out_mprj[53] = 2
la_data_in_mprj[47] = 2 | la_data_in_mprj[47] = 2
la_data_in_mprj[48] = 2 | la_data_in_mprj[48] = 2
la_data_in_mprj[49] = 2 | la_data_in_mprj[49] = 2
la_data_in_mprj[50] = 2 | la_data_in_mprj[50] = 2
la_data_in_mprj[51] = 2 | la_data_in_mprj[51] = 2
la_data_in_mprj[55] = 2 | la_data_in_mprj[55] = 2
la_data_in_mprj[56] = 2 | la_data_in_mprj[56] = 2
la_iena_mprj[38] = 2 | la_iena_mprj[38] = 2
la_iena_mprj[39] = 2 | la_iena_mprj[39] = 2
la_data_in_mprj[57] = 2 | la_data_in_mprj[57] = 2
la_iena_mprj[40] = 2 | la_iena_mprj[40] = 2
la_iena_mprj[41] = 2 | la_iena_mprj[41] = 2
la_iena_mprj[42] = 2 | la_iena_mprj[42] = 2
la_iena_mprj[43] = 2 | la_iena_mprj[43] = 2
la_iena_mprj[44] = 2 | la_iena_mprj[44] = 2
la_iena_mprj[45] = 2 | la_iena_mprj[45] = 2
la_iena_mprj[46] = 2 | la_iena_mprj[46] = 2
la_iena_mprj[47] = 2 | la_iena_mprj[47] = 2
la_iena_mprj[48] = 2 | la_iena_mprj[48] = 2
la_iena_mprj[49] = 2 | la_iena_mprj[49] = 2
la_iena_mprj[50] = 2 | la_iena_mprj[50] = 2
la_iena_mprj[51] = 2 | la_iena_mprj[51] = 2
la_iena_mprj[52] = 2 | la_iena_mprj[52] = 2
la_iena_mprj[53] = 2 | la_iena_mprj[53] = 2
la_iena_mprj[54] = 2 | la_iena_mprj[54] = 2
la_iena_mprj[55] = 2 | la_iena_mprj[55] = 2
la_iena_mprj[56] = 2 | la_iena_mprj[56] = 2
la_iena_mprj[57] = 2 | la_iena_mprj[57] = 2
la_data_in_mprj[54] = 2 | la_data_in_mprj[54] = 2
la_data_in_mprj[52] = 2 | la_data_in_mprj[52] = 2
la_data_in_mprj[53] = 2 | la_data_in_mprj[53] = 2
la_oenb_mprj[66] = 2 | la_oenb_mprj[66] = 2
la_oenb_mprj[67] = 2 | la_oenb_mprj[67] = 2
la_oenb_mprj[68] = 2 | la_oenb_mprj[68] = 2
la_oenb_mprj[69] = 2 | la_oenb_mprj[69] = 2
la_data_in_mprj[64] = 2 | la_data_in_mprj[64] = 2
la_oenb_mprj[70] = 2 | la_oenb_mprj[70] = 2
la_oenb_mprj[71] = 2 | la_oenb_mprj[71] = 2
la_oenb_mprj[72] = 2 | la_oenb_mprj[72] = 2
la_oenb_mprj[73] = 2 | la_oenb_mprj[73] = 2
la_oenb_mprj[74] = 2 | la_oenb_mprj[74] = 2
la_oenb_mprj[75] = 2 | la_oenb_mprj[75] = 2
la_oenb_mprj[76] = 2 | la_oenb_mprj[76] = 2
la_data_in_mprj[62] = 2 | la_data_in_mprj[62] = 2
la_data_in_mprj[63] = 2 | la_data_in_mprj[63] = 2
la_oenb_mprj[57] = 2 | la_oenb_mprj[57] = 2
la_data_in_mprj[65] = 2 | la_data_in_mprj[65] = 2
la_oenb_mprj[58] = 2 | la_oenb_mprj[58] = 2
la_oenb_mprj[59] = 2 | la_oenb_mprj[59] = 2
la_data_in_mprj[66] = 2 | la_data_in_mprj[66] = 2
la_data_in_mprj[67] = 2 | la_data_in_mprj[67] = 2
la_data_in_mprj[68] = 2 | la_data_in_mprj[68] = 2
la_data_in_mprj[69] = 2 | la_data_in_mprj[69] = 2
la_data_in_mprj[61] = 2 | la_data_in_mprj[61] = 2
la_data_in_mprj[70] = 2 | la_data_in_mprj[70] = 2
la_data_in_mprj[71] = 2 | la_data_in_mprj[71] = 2
la_data_in_mprj[72] = 2 | la_data_in_mprj[72] = 2
la_data_in_mprj[73] = 2 | la_data_in_mprj[73] = 2
la_data_in_mprj[74] = 2 | la_data_in_mprj[74] = 2
la_data_in_mprj[75] = 2 | la_data_in_mprj[75] = 2
la_data_in_mprj[76] = 2 | la_data_in_mprj[76] = 2
la_oenb_mprj[60] = 2 | la_oenb_mprj[60] = 2
la_data_out_mprj[58] = 2 | la_data_out_mprj[58] = 2
la_data_out_mprj[59] = 2 | la_data_out_mprj[59] = 2
la_oenb_mprj[61] = 2 | la_oenb_mprj[61] = 2
la_data_out_mprj[60] = 2 | la_data_out_mprj[60] = 2
la_data_out_mprj[61] = 2 | la_data_out_mprj[61] = 2
la_data_out_mprj[62] = 2 | la_data_out_mprj[62] = 2
la_data_out_mprj[63] = 2 | la_data_out_mprj[63] = 2
la_data_out_mprj[64] = 2 | la_data_out_mprj[64] = 2
la_data_out_mprj[65] = 2 | la_data_out_mprj[65] = 2
la_data_out_mprj[66] = 2 | la_data_out_mprj[66] = 2
la_data_out_mprj[67] = 2 | la_data_out_mprj[67] = 2
la_data_out_mprj[68] = 2 | la_data_out_mprj[68] = 2
la_data_out_mprj[69] = 2 | la_data_out_mprj[69] = 2
la_data_in_mprj[58] = 2 | la_data_in_mprj[58] = 2
la_oenb_mprj[62] = 2 | la_oenb_mprj[62] = 2
la_data_out_mprj[70] = 2 | la_data_out_mprj[70] = 2
la_data_out_mprj[71] = 2 | la_data_out_mprj[71] = 2
la_data_out_mprj[72] = 2 | la_data_out_mprj[72] = 2
la_data_out_mprj[73] = 2 | la_data_out_mprj[73] = 2
la_data_out_mprj[74] = 2 | la_data_out_mprj[74] = 2
la_data_out_mprj[75] = 2 | la_data_out_mprj[75] = 2
la_data_out_mprj[76] = 2 | la_data_out_mprj[76] = 2
la_iena_mprj[58] = 2 | la_iena_mprj[58] = 2
la_iena_mprj[59] = 2 | la_iena_mprj[59] = 2
caravel_clk = 2 | caravel_clk = 2
la_iena_mprj[60] = 2 | la_iena_mprj[60] = 2
la_iena_mprj[61] = 2 | la_iena_mprj[61] = 2
la_iena_mprj[62] = 2 | la_iena_mprj[62] = 2
la_iena_mprj[63] = 2 | la_iena_mprj[63] = 2
la_iena_mprj[64] = 2 | la_iena_mprj[64] = 2
la_iena_mprj[65] = 2 | la_iena_mprj[65] = 2
la_iena_mprj[66] = 2 | la_iena_mprj[66] = 2
la_iena_mprj[67] = 2 | la_iena_mprj[67] = 2
la_iena_mprj[68] = 2 | la_iena_mprj[68] = 2
la_iena_mprj[69] = 2 | la_iena_mprj[69] = 2
caravel_rstn = 2 | caravel_rstn = 2
la_iena_mprj[70] = 2 | la_iena_mprj[70] = 2
la_iena_mprj[71] = 2 | la_iena_mprj[71] = 2
la_iena_mprj[72] = 2 | la_iena_mprj[72] = 2
la_iena_mprj[73] = 2 | la_iena_mprj[73] = 2
la_iena_mprj[74] = 2 | la_iena_mprj[74] = 2
la_iena_mprj[75] = 2 | la_iena_mprj[75] = 2
la_iena_mprj[76] = 2 | la_iena_mprj[76] = 2
la_data_in_mprj[59] = 2 | la_data_in_mprj[59] = 2
la_oenb_mprj[63] = 2 | la_oenb_mprj[63] = 2
la_data_in_mprj[60] = 2 | la_data_in_mprj[60] = 2
la_oenb_mprj[64] = 2 | la_oenb_mprj[64] = 2
la_oenb_mprj[65] = 2 | la_oenb_mprj[65] = 2
la_iena_mprj[80] = 2 | la_iena_mprj[80] = 2
la_iena_mprj[81] = 2 | la_iena_mprj[81] = 2
la_iena_mprj[82] = 2 | la_iena_mprj[82] = 2
la_iena_mprj[83] = 2 | la_iena_mprj[83] = 2
la_iena_mprj[84] = 2 | la_iena_mprj[84] = 2
la_iena_mprj[85] = 2 | la_iena_mprj[85] = 2
la_iena_mprj[86] = 2 | la_iena_mprj[86] = 2
la_iena_mprj[87] = 2 | la_iena_mprj[87] = 2
la_iena_mprj[88] = 2 | la_iena_mprj[88] = 2
la_iena_mprj[89] = 2 | la_iena_mprj[89] = 2
la_iena_mprj[90] = 2 | la_iena_mprj[90] = 2
la_iena_mprj[91] = 2 | la_iena_mprj[91] = 2
la_iena_mprj[92] = 2 | la_iena_mprj[92] = 2
la_iena_mprj[93] = 2 | la_iena_mprj[93] = 2
la_iena_mprj[94] = 2 | la_iena_mprj[94] = 2
la_iena_mprj[95] = 2 | la_iena_mprj[95] = 2
la_data_out_mprj[77] = 2 | la_data_out_mprj[77] = 2
la_data_out_mprj[78] = 2 | la_data_out_mprj[78] = 2
la_data_out_mprj[79] = 2 | la_data_out_mprj[79] = 2
la_data_out_mprj[80] = 2 | la_data_out_mprj[80] = 2
la_data_out_mprj[81] = 2 | la_data_out_mprj[81] = 2
la_data_out_mprj[82] = 2 | la_data_out_mprj[82] = 2
la_data_out_mprj[83] = 2 | la_data_out_mprj[83] = 2
la_data_out_mprj[84] = 2 | la_data_out_mprj[84] = 2
la_data_out_mprj[85] = 2 | la_data_out_mprj[85] = 2
la_data_out_mprj[86] = 2 | la_data_out_mprj[86] = 2
la_data_out_mprj[87] = 2 | la_data_out_mprj[87] = 2
la_data_out_mprj[88] = 2 | la_data_out_mprj[88] = 2
la_data_out_mprj[89] = 2 | la_data_out_mprj[89] = 2
la_data_out_mprj[90] = 2 | la_data_out_mprj[90] = 2
la_data_out_mprj[91] = 2 | la_data_out_mprj[91] = 2
la_data_out_mprj[92] = 2 | la_data_out_mprj[92] = 2
la_data_out_mprj[93] = 2 | la_data_out_mprj[93] = 2
la_data_out_mprj[94] = 2 | la_data_out_mprj[94] = 2
la_data_out_mprj[95] = 2 | la_data_out_mprj[95] = 2
la_data_out_mprj[96] = 2 | la_data_out_mprj[96] = 2
la_oenb_mprj[77] = 2 | la_oenb_mprj[77] = 2
la_oenb_mprj[78] = 2 | la_oenb_mprj[78] = 2
la_oenb_mprj[79] = 2 | la_oenb_mprj[79] = 2
la_oenb_mprj[80] = 2 | la_oenb_mprj[80] = 2
la_oenb_mprj[81] = 2 | la_oenb_mprj[81] = 2
la_oenb_mprj[82] = 2 | la_oenb_mprj[82] = 2
la_oenb_mprj[83] = 2 | la_oenb_mprj[83] = 2
la_oenb_mprj[84] = 2 | la_oenb_mprj[84] = 2
la_oenb_mprj[85] = 2 | la_oenb_mprj[85] = 2
la_oenb_mprj[86] = 2 | la_oenb_mprj[86] = 2
la_oenb_mprj[87] = 2 | la_oenb_mprj[87] = 2
la_oenb_mprj[88] = 2 | la_oenb_mprj[88] = 2
la_oenb_mprj[89] = 2 | la_oenb_mprj[89] = 2
la_oenb_mprj[90] = 2 | la_oenb_mprj[90] = 2
la_oenb_mprj[91] = 2 | la_oenb_mprj[91] = 2
la_oenb_mprj[92] = 2 | la_oenb_mprj[92] = 2
la_oenb_mprj[93] = 2 | la_oenb_mprj[93] = 2
la_oenb_mprj[94] = 2 | la_oenb_mprj[94] = 2
la_oenb_mprj[95] = 2 | la_oenb_mprj[95] = 2
la_data_in_mprj[80] = 2 | la_data_in_mprj[80] = 2
la_data_in_mprj[81] = 2 | la_data_in_mprj[81] = 2
la_data_in_mprj[82] = 2 | la_data_in_mprj[82] = 2
la_data_in_mprj[83] = 2 | la_data_in_mprj[83] = 2
la_data_in_mprj[84] = 2 | la_data_in_mprj[84] = 2
la_data_in_mprj[85] = 2 | la_data_in_mprj[85] = 2
la_data_in_mprj[86] = 2 | la_data_in_mprj[86] = 2
la_data_in_mprj[87] = 2 | la_data_in_mprj[87] = 2
la_data_in_mprj[88] = 2 | la_data_in_mprj[88] = 2
la_data_in_mprj[89] = 2 | la_data_in_mprj[89] = 2
la_data_in_mprj[90] = 2 | la_data_in_mprj[90] = 2
la_data_in_mprj[91] = 2 | la_data_in_mprj[91] = 2
la_data_in_mprj[92] = 2 | la_data_in_mprj[92] = 2
la_data_in_mprj[93] = 2 | la_data_in_mprj[93] = 2
la_data_in_mprj[94] = 2 | la_data_in_mprj[94] = 2
la_data_in_mprj[95] = 2 | la_data_in_mprj[95] = 2
la_data_in_mprj[96] = 2 | la_data_in_mprj[96] = 2
la_data_in_mprj[77] = 2 | la_data_in_mprj[77] = 2
la_data_in_mprj[78] = 2 | la_data_in_mprj[78] = 2
la_data_in_mprj[79] = 2 | la_data_in_mprj[79] = 2
la_iena_mprj[77] = 2 | la_iena_mprj[77] = 2
la_iena_mprj[78] = 2 | la_iena_mprj[78] = 2
la_iena_mprj[79] = 2 | la_iena_mprj[79] = 2
la_iena_mprj[110] = 2 | la_iena_mprj[110] = 2
la_oenb_mprj[96] = 2 | la_oenb_mprj[96] = 2
la_oenb_mprj[97] = 2 | la_oenb_mprj[97] = 2
la_oenb_mprj[98] = 2 | la_oenb_mprj[98] = 2
la_oenb_mprj[99] = 2 | la_oenb_mprj[99] = 2
la_iena_mprj[111] = 2 | la_iena_mprj[111] = 2
la_iena_mprj[112] = 2 | la_iena_mprj[112] = 2
la_iena_mprj[113] = 2 | la_iena_mprj[113] = 2
la_iena_mprj[114] = 2 | la_iena_mprj[114] = 2
la_iena_mprj[115] = 2 | la_iena_mprj[115] = 2
la_data_in_mprj[116] = 2 | la_data_in_mprj[116] = 2
la_iena_mprj[96] = 2 | la_iena_mprj[96] = 2
la_iena_mprj[97] = 2 | la_iena_mprj[97] = 2
la_iena_mprj[98] = 2 | la_iena_mprj[98] = 2
la_iena_mprj[99] = 2 | la_iena_mprj[99] = 2
la_data_out_mprj[97] = 2 | la_data_out_mprj[97] = 2
la_data_out_mprj[98] = 2 | la_data_out_mprj[98] = 2
la_data_out_mprj[99] = 2 | la_data_out_mprj[99] = 2
la_iena_mprj[100] = 2 | la_iena_mprj[100] = 2
la_iena_mprj[101] = 2 | la_iena_mprj[101] = 2
la_iena_mprj[102] = 2 | la_iena_mprj[102] = 2
la_iena_mprj[103] = 2 | la_iena_mprj[103] = 2
la_data_in_mprj[97] = 2 | la_data_in_mprj[97] = 2
la_data_in_mprj[98] = 2 | la_data_in_mprj[98] = 2
la_data_in_mprj[99] = 2 | la_data_in_mprj[99] = 2
la_data_in_mprj[101] = 2 | la_data_in_mprj[101] = 2
la_data_in_mprj[102] = 2 | la_data_in_mprj[102] = 2
la_data_in_mprj[103] = 2 | la_data_in_mprj[103] = 2
la_data_in_mprj[104] = 2 | la_data_in_mprj[104] = 2
la_data_in_mprj[105] = 2 | la_data_in_mprj[105] = 2
la_data_in_mprj[106] = 2 | la_data_in_mprj[106] = 2
la_data_in_mprj[107] = 2 | la_data_in_mprj[107] = 2
la_data_in_mprj[108] = 2 | la_data_in_mprj[108] = 2
la_data_in_mprj[109] = 2 | la_data_in_mprj[109] = 2
la_data_in_mprj[100] = 2 | la_data_in_mprj[100] = 2
la_data_in_mprj[110] = 2 | la_data_in_mprj[110] = 2
la_data_in_mprj[111] = 2 | la_data_in_mprj[111] = 2
la_data_in_mprj[112] = 2 | la_data_in_mprj[112] = 2
la_data_in_mprj[113] = 2 | la_data_in_mprj[113] = 2
la_data_in_mprj[114] = 2 | la_data_in_mprj[114] = 2
la_data_in_mprj[115] = 2 | la_data_in_mprj[115] = 2
la_iena_mprj[104] = 2 | la_iena_mprj[104] = 2
la_iena_mprj[105] = 2 | la_iena_mprj[105] = 2
la_data_out_mprj[100] = 2 | la_data_out_mprj[100] = 2
la_data_out_mprj[101] = 2 | la_data_out_mprj[101] = 2
la_data_out_mprj[102] = 2 | la_data_out_mprj[102] = 2
la_data_out_mprj[103] = 2 | la_data_out_mprj[103] = 2
la_data_out_mprj[104] = 2 | la_data_out_mprj[104] = 2
la_data_out_mprj[105] = 2 | la_data_out_mprj[105] = 2
la_data_out_mprj[106] = 2 | la_data_out_mprj[106] = 2
la_data_out_mprj[107] = 2 | la_data_out_mprj[107] = 2
la_data_out_mprj[108] = 2 | la_data_out_mprj[108] = 2
la_data_out_mprj[109] = 2 | la_data_out_mprj[109] = 2
la_iena_mprj[106] = 2 | la_iena_mprj[106] = 2
la_data_out_mprj[110] = 2 | la_data_out_mprj[110] = 2
la_data_out_mprj[111] = 2 | la_data_out_mprj[111] = 2
la_data_out_mprj[112] = 2 | la_data_out_mprj[112] = 2
la_data_out_mprj[113] = 2 | la_data_out_mprj[113] = 2
la_data_out_mprj[114] = 2 | la_data_out_mprj[114] = 2
la_data_out_mprj[115] = 2 | la_data_out_mprj[115] = 2
la_iena_mprj[107] = 2 | la_iena_mprj[107] = 2
la_iena_mprj[108] = 2 | la_iena_mprj[108] = 2
la_oenb_mprj[100] = 2 | la_oenb_mprj[100] = 2
la_oenb_mprj[101] = 2 | la_oenb_mprj[101] = 2
la_oenb_mprj[102] = 2 | la_oenb_mprj[102] = 2
la_oenb_mprj[103] = 2 | la_oenb_mprj[103] = 2
la_oenb_mprj[104] = 2 | la_oenb_mprj[104] = 2
la_oenb_mprj[105] = 2 | la_oenb_mprj[105] = 2
la_oenb_mprj[106] = 2 | la_oenb_mprj[106] = 2
la_oenb_mprj[107] = 2 | la_oenb_mprj[107] = 2
la_oenb_mprj[108] = 2 | la_oenb_mprj[108] = 2
la_oenb_mprj[109] = 2 | la_oenb_mprj[109] = 2
la_iena_mprj[109] = 2 | la_iena_mprj[109] = 2
la_oenb_mprj[110] = 2 | la_oenb_mprj[110] = 2
la_oenb_mprj[111] = 2 | la_oenb_mprj[111] = 2
la_oenb_mprj[112] = 2 | la_oenb_mprj[112] = 2
la_oenb_mprj[113] = 2 | la_oenb_mprj[113] = 2
la_oenb_mprj[114] = 2 | la_oenb_mprj[114] = 2
la_oenb_mprj[115] = 2 | la_oenb_mprj[115] = 2
la_data_in_mprj[118] = 2 | la_data_in_mprj[118] = 2
la_data_in_mprj[119] = 2 | la_data_in_mprj[119] = 2
la_data_in_mprj[120] = 2 | la_data_in_mprj[120] = 2
la_data_in_mprj[121] = 2 | la_data_in_mprj[121] = 2
la_data_in_mprj[122] = 2 | la_data_in_mprj[122] = 2
mprj_cyc_o_core = 2 | mprj_cyc_o_core = 2
la_data_in_mprj[123] = 2 | la_data_in_mprj[123] = 2
mprj_dat_i_core[0] = 2 | mprj_dat_i_core[0] = 2
mprj_dat_i_core[1] = 2 | mprj_dat_i_core[1] = 2
mprj_dat_i_core[2] = 2 | mprj_dat_i_core[2] = 2
mprj_dat_i_core[3] = 2 | mprj_dat_i_core[3] = 2
mprj_dat_i_core[4] = 2 | mprj_dat_i_core[4] = 2
mprj_dat_i_core[5] = 2 | mprj_dat_i_core[5] = 2
mprj_dat_i_core[6] = 2 | mprj_dat_i_core[6] = 2
mprj_dat_i_core[7] = 2 | mprj_dat_i_core[7] = 2
la_data_in_mprj[124] = 2 | la_data_in_mprj[124] = 2
la_data_in_mprj[125] = 2 | la_data_in_mprj[125] = 2
la_data_in_mprj[126] = 2 | la_data_in_mprj[126] = 2
la_data_in_mprj[127] = 2 | la_data_in_mprj[127] = 2
mprj_adr_o_core[1] = 3 | mprj_adr_o_core[1] = 3
mprj_adr_o_core[2] = 3 | mprj_adr_o_core[2] = 3
mprj_adr_o_core[3] = 3 | mprj_adr_o_core[3] = 3
mprj_adr_o_core[4] = 3 | mprj_adr_o_core[4] = 3
mprj_adr_o_core[5] = 3 | mprj_adr_o_core[5] = 3
mprj_adr_o_core[6] = 3 | mprj_adr_o_core[6] = 3
mprj_adr_o_core[7] = 3 | mprj_adr_o_core[7] = 3
la_iena_mprj[125] = 2 | la_iena_mprj[125] = 2
mprj_dat_o_core[0] = 3 | mprj_dat_o_core[0] = 3
mprj_dat_o_core[1] = 3 | mprj_dat_o_core[1] = 3
mprj_dat_o_core[2] = 3 | mprj_dat_o_core[2] = 3
mprj_dat_o_core[3] = 3 | mprj_dat_o_core[3] = 3
mprj_dat_o_core[4] = 3 | mprj_dat_o_core[4] = 3
mprj_dat_o_core[5] = 3 | mprj_dat_o_core[5] = 3
mprj_dat_o_core[6] = 3 | mprj_dat_o_core[6] = 3
mprj_dat_o_core[7] = 3 | mprj_dat_o_core[7] = 3
la_iena_mprj[126] = 2 | la_iena_mprj[126] = 2
la_iena_mprj[127] = 2 | la_iena_mprj[127] = 2
la_data_out_mprj[126] = 2 | la_data_out_mprj[126] = 2
la_data_out_mprj[127] = 2 | la_data_out_mprj[127] = 2
la_data_out_mprj[123] = 2 | la_data_out_mprj[123] = 2
la_data_out_mprj[120] = 2 | la_data_out_mprj[120] = 2
la_data_out_mprj[116] = 2 | la_data_out_mprj[116] = 2
la_data_out_mprj[117] = 2 | la_data_out_mprj[117] = 2
la_data_out_mprj[118] = 2 | la_data_out_mprj[118] = 2
la_iena_mprj[122] = 2 | la_iena_mprj[122] = 2
la_data_out_mprj[121] = 2 | la_data_out_mprj[121] = 2
la_iena_mprj[121] = 2 | la_iena_mprj[121] = 2
la_data_out_mprj[124] = 2 | la_data_out_mprj[124] = 2
la_data_out_mprj[122] = 2 | la_data_out_mprj[122] = 2
la_iena_mprj[116] = 2 | la_iena_mprj[116] = 2
la_iena_mprj[117] = 2 | la_iena_mprj[117] = 2
la_iena_mprj[118] = 2 | la_iena_mprj[118] = 2
la_data_in_mprj[117] = 2 | la_data_in_mprj[117] = 2
la_iena_mprj[119] = 2 | la_iena_mprj[119] = 2
la_data_out_mprj[125] = 2 | la_data_out_mprj[125] = 2
la_iena_mprj[120] = 2 | la_iena_mprj[120] = 2
la_iena_mprj[123] = 2 | la_iena_mprj[123] = 2
mprj_ack_i_core = 2 | mprj_ack_i_core = 2
la_iena_mprj[124] = 2 | la_iena_mprj[124] = 2
mprj_adr_o_core[0] = 3 | mprj_adr_o_core[0] = 3
la_oenb_mprj[116] = 2 | la_oenb_mprj[116] = 2
la_oenb_mprj[117] = 2 | la_oenb_mprj[117] = 2
la_oenb_mprj[118] = 2 | la_oenb_mprj[118] = 2
la_oenb_mprj[119] = 2 | la_oenb_mprj[119] = 2
mprj_sel_o_core[0] = 3 | mprj_sel_o_core[0] = 3
mprj_sel_o_core[1] = 3 | mprj_sel_o_core[1] = 3
mprj_sel_o_core[2] = 3 | mprj_sel_o_core[2] = 3
mprj_sel_o_core[3] = 3 | mprj_sel_o_core[3] = 3
la_data_out_mprj[119] = 2 | la_data_out_mprj[119] = 2
la_oenb_mprj[120] = 2 | la_oenb_mprj[120] = 2
la_oenb_mprj[121] = 2 | la_oenb_mprj[121] = 2
la_oenb_mprj[122] = 2 | la_oenb_mprj[122] = 2
mprj_stb_o_core = 2 | mprj_stb_o_core = 2
la_oenb_mprj[123] = 2 | la_oenb_mprj[123] = 2
mprj_we_o_core = 3 | mprj_we_o_core = 3
la_oenb_mprj[124] = 2 | la_oenb_mprj[124] = 2
la_oenb_mprj[125] = 2 | la_oenb_mprj[125] = 2
la_oenb_mprj[126] = 2 | la_oenb_mprj[126] = 2
la_oenb_mprj[127] = 2 | la_oenb_mprj[127] = 2
mprj_dat_o_core[16] = 3 | mprj_dat_o_core[16] = 3
mprj_dat_o_core[17] = 3 | mprj_dat_o_core[17] = 3
mprj_dat_o_core[18] = 3 | mprj_dat_o_core[18] = 3
mprj_dat_o_core[19] = 3 | mprj_dat_o_core[19] = 3
mprj_dat_i_core[28] = 2 | mprj_dat_i_core[28] = 2
mprj_dat_o_core[20] = 3 | mprj_dat_o_core[20] = 3
mprj_dat_o_core[21] = 3 | mprj_dat_o_core[21] = 3
mprj_dat_o_core[22] = 3 | mprj_dat_o_core[22] = 3
mprj_dat_o_core[23] = 3 | mprj_dat_o_core[23] = 3
mprj_dat_o_core[24] = 3 | mprj_dat_o_core[24] = 3
mprj_dat_o_core[25] = 3 | mprj_dat_o_core[25] = 3
mprj_dat_o_core[26] = 3 | mprj_dat_o_core[26] = 3
mprj_dat_o_core[27] = 3 | mprj_dat_o_core[27] = 3
mprj_dat_o_core[28] = 3 | mprj_dat_o_core[28] = 3
mprj_dat_o_core[29] = 3 | mprj_dat_o_core[29] = 3
mprj_dat_i_core[29] = 2 | mprj_dat_i_core[29] = 2
mprj_dat_o_core[30] = 3 | mprj_dat_o_core[30] = 3
mprj_dat_o_core[31] = 3 | mprj_dat_o_core[31] = 3
mprj_dat_i_core[10] = 2 | mprj_dat_i_core[10] = 2
mprj_dat_i_core[30] = 2 | mprj_dat_i_core[30] = 2
mprj_dat_i_core[31] = 2 | mprj_dat_i_core[31] = 2
mprj_dat_i_core[11] = 2 | mprj_dat_i_core[11] = 2
mprj_dat_i_core[12] = 2 | mprj_dat_i_core[12] = 2
mprj_dat_o_core[8] = 3 | mprj_dat_o_core[8] = 3
mprj_dat_o_core[9] = 3 | mprj_dat_o_core[9] = 3
mprj_dat_i_core[13] = 2 | mprj_dat_i_core[13] = 2
mprj_dat_i_core[14] = 2 | mprj_dat_i_core[14] = 2
mprj_dat_i_core[15] = 2 | mprj_dat_i_core[15] = 2
mprj_dat_i_core[8] = 2 | mprj_dat_i_core[8] = 2
mprj_dat_i_core[9] = 2 | mprj_dat_i_core[9] = 2
mprj_dat_i_core[16] = 2 | mprj_dat_i_core[16] = 2
mprj_dat_i_core[17] = 2 | mprj_dat_i_core[17] = 2
mprj_dat_i_core[18] = 2 | mprj_dat_i_core[18] = 2
mprj_dat_i_core[19] = 2 | mprj_dat_i_core[19] = 2
mprj_adr_o_core[14] = 3 | mprj_adr_o_core[14] = 3
mprj_adr_o_core[15] = 3 | mprj_adr_o_core[15] = 3
mprj_adr_o_core[16] = 3 | mprj_adr_o_core[16] = 3
mprj_adr_o_core[17] = 3 | mprj_adr_o_core[17] = 3
mprj_adr_o_core[18] = 3 | mprj_adr_o_core[18] = 3
mprj_adr_o_core[19] = 3 | mprj_adr_o_core[19] = 3
mprj_adr_o_core[13] = 3 | mprj_adr_o_core[13] = 3
mprj_adr_o_core[20] = 3 | mprj_adr_o_core[20] = 3
mprj_adr_o_core[21] = 3 | mprj_adr_o_core[21] = 3
mprj_adr_o_core[22] = 3 | mprj_adr_o_core[22] = 3
mprj_adr_o_core[23] = 3 | mprj_adr_o_core[23] = 3
mprj_adr_o_core[24] = 3 | mprj_adr_o_core[24] = 3
mprj_adr_o_core[25] = 3 | mprj_adr_o_core[25] = 3
mprj_adr_o_core[26] = 3 | mprj_adr_o_core[26] = 3
mprj_adr_o_core[27] = 3 | mprj_adr_o_core[27] = 3
mprj_adr_o_core[28] = 3 | mprj_adr_o_core[28] = 3
mprj_adr_o_core[10] = 3 | mprj_adr_o_core[10] = 3
mprj_adr_o_core[11] = 3 | mprj_adr_o_core[11] = 3
mprj_adr_o_core[12] = 3 | mprj_adr_o_core[12] = 3
mprj_adr_o_core[29] = 3 | mprj_adr_o_core[29] = 3
mprj_dat_i_core[20] = 2 | mprj_dat_i_core[20] = 2
mprj_adr_o_core[30] = 3 | mprj_adr_o_core[30] = 3
mprj_adr_o_core[31] = 3 | mprj_adr_o_core[31] = 3
mprj_iena_wb = 2 | mprj_iena_wb = 2
mprj_dat_i_core[21] = 2 | mprj_dat_i_core[21] = 2
mprj_dat_i_core[22] = 2 | mprj_dat_i_core[22] = 2
mprj_dat_i_core[23] = 2 | mprj_dat_i_core[23] = 2
mprj_dat_i_core[24] = 2 | mprj_dat_i_core[24] = 2
mprj_dat_i_core[25] = 2 | mprj_dat_i_core[25] = 2
mprj_adr_o_core[8] = 3 | mprj_adr_o_core[8] = 3
mprj_adr_o_core[9] = 3 | mprj_adr_o_core[9] = 3
mprj_dat_i_core[26] = 2 | mprj_dat_i_core[26] = 2
mprj_dat_i_core[27] = 2 | mprj_dat_i_core[27] = 2
mprj_dat_o_core[10] = 3 | mprj_dat_o_core[10] = 3
mprj_dat_o_core[11] = 3 | mprj_dat_o_core[11] = 3
mprj_dat_o_core[12] = 3 | mprj_dat_o_core[12] = 3
mprj_dat_o_core[13] = 3 | mprj_dat_o_core[13] = 3
mprj_dat_o_core[14] = 3 | mprj_dat_o_core[14] = 3
mprj_dat_o_core[15] = 3 | mprj_dat_o_core[15] = 3
vccd1 = 29 | vccd1 = 30
vccd2 = 2 | vccd2 = 3
vdda1 = 2 | vdda1 = 3
vdda2 = 2 | vdda2 = 3
vssa1 = 2 | vssa1 = 3
vssa2 = 2 | vssa2 = 3
vssd2 = 2 | vssd2 = 3
vccd = 8797 | vccd = 8792
vssd = 8792 | vssd = 8792
vssd1 = 29 | vssd1 = 30
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: chip_io_alt:padframe |Instance: padframe
xresloop = 1 | proxyxresloop = 1
xres_vss_loop = 1 | proxyxres_vss_loop = 1
clock = 1 | clock = 1
clock_core = 2 | clock_core = 2
por = 2 | por = 2
flash_clk = 1 | flash_clk = 1
flash_csb = 1 | flash_csb = 1
flash_io0 = 1 | flash_io0 = 1
flash_io0_di_core = 2 | flash_io0_di_core = 2
flash_io0_do_core = 2 | flash_io0_do_core = 2
flash_io0_ieb_core = 2 | flash_io0_ieb_core = 2
flash_io0_oeb_core = 2 | flash_io0_oeb_core = 2
flash_io1 = 1 | flash_io1 = 1
flash_io1_di_core = 2 | flash_io1_di_core = 2
flash_io1_do_core = 2 | flash_io1_do_core = 2
flash_io1_ieb_core = 2 | flash_io1_ieb_core = 2
flash_io1_oeb_core = 2 | flash_io1_oeb_core = 2
gpio = 1 | gpio = 1
gpio_in_core = 2 | gpio_in_core = 2
gpio_inenb_core = 2 | gpio_inenb_core = 2
gpio_mode0_core = 2 | gpio_mode0_core = 2
gpio_out_core = 2 | gpio_out_core = 2
gpio_outenb_core = 2 | gpio_outenb_core = 2
vccd_pad = 1 | vccd_pad = 1
vdda_pad = 1 | vdda_pad = 1
vddio_pad = 1 | vddio_pad = 1
vssa_pad = 1 | vssa_pad = 1
vssio_pad = 1 | vssio_pad = 1
vssio_pad2 = 1 | vssio_pad2 = 1
mprj_io[0] = 1 | mprj_io[0] = 1
mprj_io_analog_en[0] = 2 | mprj_io_analog_en[0] = 2
mprj_io_analog_pol[0] = 2 | mprj_io_analog_pol[0] = 2
mprj_io_analog_sel[0] = 2 | mprj_io_analog_sel[0] = 2
mprj_io_dm[0] = 2 | mprj_io_dm[0] = 2
mprj_io_dm[1] = 2 | mprj_io_dm[1] = 2
mprj_io_dm[2] = 2 | mprj_io_dm[2] = 2
mprj_io_holdover[0] = 2 | mprj_io_holdover[0] = 2
mprj_io_ib_mode_sel[0] = 2 | mprj_io_ib_mode_sel[0] = 2
mprj_io_inp_dis[0] = 2 | mprj_io_inp_dis[0] = 2
mprj_io_oeb[0] = 2 | mprj_io_oeb[0] = 2
mprj_io_out[0] = 2 | mprj_io_out[0] = 2
mprj_io_slow_sel[0] = 2 | mprj_io_slow_sel[0] = 2
mprj_io_vtrip_sel[0] = 2 | mprj_io_vtrip_sel[0] = 2
mprj_io_in[0] = 3 | mprj_io_in[0] = 3
mprj_io_in_3v3[0] = 1 | mprj_io_in_3v3[0] = 2
mprj_gpio_analog[3] = 1 | mprj_gpio_analog[3] = 2
mprj_gpio_noesd[3] = 1 | mprj_gpio_noesd[3] = 2
mprj_io[10] = 1 | mprj_io[10] = 1
mprj_io_analog_en[10] = 2 | mprj_io_analog_en[10] = 2
mprj_io_analog_pol[10] = 2 | mprj_io_analog_pol[10] = 2
mprj_io_analog_sel[10] = 2 | mprj_io_analog_sel[10] = 2
mprj_io_dm[30] = 2 | mprj_io_dm[30] = 2
mprj_io_dm[31] = 2 | mprj_io_dm[31] = 2
mprj_io_dm[32] = 2 | mprj_io_dm[32] = 2
mprj_io_holdover[10] = 2 | mprj_io_holdover[10] = 2
mprj_io_ib_mode_sel[10] = 2 | mprj_io_ib_mode_sel[10] = 2
mprj_io_inp_dis[10] = 2 | mprj_io_inp_dis[10] = 2
mprj_io_oeb[10] = 2 | mprj_io_oeb[10] = 2
mprj_io_out[10] = 2 | mprj_io_out[10] = 2
mprj_io_slow_sel[10] = 2 | mprj_io_slow_sel[10] = 2
mprj_io_vtrip_sel[10] = 2 | mprj_io_vtrip_sel[10] = 2
mprj_io_in[10] = 3 | mprj_io_in[10] = 3
mprj_io_in_3v3[10] = 1 | mprj_io_in_3v3[10] = 2
mprj_gpio_analog[4] = 1 | mprj_gpio_analog[4] = 2
mprj_gpio_noesd[4] = 1 | mprj_gpio_noesd[4] = 2
mprj_io[11] = 1 | mprj_io[11] = 1
mprj_io_analog_en[11] = 2 | mprj_io_analog_en[11] = 2
mprj_io_analog_pol[11] = 2 | mprj_io_analog_pol[11] = 2
mprj_io_analog_sel[11] = 2 | mprj_io_analog_sel[11] = 2
mprj_io_dm[33] = 2 | mprj_io_dm[33] = 2
mprj_io_dm[34] = 2 | mprj_io_dm[34] = 2
mprj_io_dm[35] = 2 | mprj_io_dm[35] = 2
mprj_io_holdover[11] = 2 | mprj_io_holdover[11] = 2
mprj_io_ib_mode_sel[11] = 2 | mprj_io_ib_mode_sel[11] = 2
mprj_io_inp_dis[11] = 2 | mprj_io_inp_dis[11] = 2
mprj_io_oeb[11] = 2 | mprj_io_oeb[11] = 2
mprj_io_out[11] = 2 | mprj_io_out[11] = 2
mprj_io_slow_sel[11] = 2 | mprj_io_slow_sel[11] = 2
mprj_io_vtrip_sel[11] = 2 | mprj_io_vtrip_sel[11] = 2
mprj_io_in[11] = 3 | mprj_io_in[11] = 3
mprj_io_in_3v3[11] = 1 | mprj_io_in_3v3[11] = 2
mprj_gpio_analog[5] = 1 | mprj_gpio_analog[5] = 2
mprj_gpio_noesd[5] = 1 | mprj_gpio_noesd[5] = 2
mprj_io[12] = 1 | mprj_io[12] = 1
mprj_io_analog_en[12] = 2 | mprj_io_analog_en[12] = 2
mprj_io_analog_pol[12] = 2 | mprj_io_analog_pol[12] = 2
mprj_io_analog_sel[12] = 2 | mprj_io_analog_sel[12] = 2
mprj_io_dm[36] = 2 | mprj_io_dm[36] = 2
mprj_io_dm[37] = 2 | mprj_io_dm[37] = 2
mprj_io_dm[38] = 2 | mprj_io_dm[38] = 2
mprj_io_holdover[12] = 2 | mprj_io_holdover[12] = 2
mprj_io_ib_mode_sel[12] = 2 | mprj_io_ib_mode_sel[12] = 2
mprj_io_inp_dis[12] = 2 | mprj_io_inp_dis[12] = 2
mprj_io_oeb[12] = 2 | mprj_io_oeb[12] = 2
mprj_io_out[12] = 2 | mprj_io_out[12] = 2
mprj_io_slow_sel[12] = 2 | mprj_io_slow_sel[12] = 2
mprj_io_vtrip_sel[12] = 2 | mprj_io_vtrip_sel[12] = 2
mprj_io_in[12] = 3 | mprj_io_in[12] = 3
mprj_io_in_3v3[12] = 1 | mprj_io_in_3v3[12] = 2
mprj_gpio_analog[6] = 1 | mprj_gpio_analog[6] = 2
mprj_gpio_noesd[6] = 1 | mprj_gpio_noesd[6] = 2
mprj_io[13] = 1 | mprj_io[13] = 1
mprj_io_analog_en[13] = 2 | mprj_io_analog_en[13] = 2
mprj_io_analog_pol[13] = 2 | mprj_io_analog_pol[13] = 2
mprj_io_analog_sel[13] = 2 | mprj_io_analog_sel[13] = 2
mprj_io_dm[39] = 2 | mprj_io_dm[39] = 2
mprj_io_dm[40] = 2 | mprj_io_dm[40] = 2
mprj_io_dm[41] = 2 | mprj_io_dm[41] = 2
mprj_io_holdover[13] = 2 | mprj_io_holdover[13] = 2
mprj_io_ib_mode_sel[13] = 2 | mprj_io_ib_mode_sel[13] = 2
mprj_io_inp_dis[13] = 2 | mprj_io_inp_dis[13] = 2
mprj_io_oeb[13] = 2 | mprj_io_oeb[13] = 2
mprj_io_out[13] = 2 | mprj_io_out[13] = 2
mprj_io_slow_sel[13] = 2 | mprj_io_slow_sel[13] = 2
mprj_io_vtrip_sel[13] = 2 | mprj_io_vtrip_sel[13] = 2
mprj_io_in[13] = 3 | mprj_io_in[13] = 3
mprj_io_in_3v3[13] = 1 | mprj_io_in_3v3[13] = 2
mprj_io[1] = 1 | mprj_io[1] = 1
mprj_io_analog_en[1] = 2 | mprj_io_analog_en[1] = 2
mprj_io_analog_pol[1] = 2 | mprj_io_analog_pol[1] = 2
mprj_io_analog_sel[1] = 2 | mprj_io_analog_sel[1] = 2
mprj_io_dm[3] = 2 | mprj_io_dm[3] = 2
mprj_io_dm[4] = 2 | mprj_io_dm[4] = 2
mprj_io_dm[5] = 2 | mprj_io_dm[5] = 2
mprj_io_holdover[1] = 2 | mprj_io_holdover[1] = 2
mprj_io_ib_mode_sel[1] = 2 | mprj_io_ib_mode_sel[1] = 2
mprj_io_inp_dis[1] = 2 | mprj_io_inp_dis[1] = 2
mprj_io_oeb[1] = 2 | mprj_io_oeb[1] = 2
mprj_io_out[1] = 2 | mprj_io_out[1] = 2
mprj_io_slow_sel[1] = 2 | mprj_io_slow_sel[1] = 2
mprj_io_vtrip_sel[1] = 2 | mprj_io_vtrip_sel[1] = 2
mprj_io_in[1] = 3 | mprj_io_in[1] = 3
mprj_io_in_3v3[1] = 1 | mprj_io_in_3v3[1] = 2
mprj_io[2] = 1 | mprj_io[2] = 1
mprj_io_analog_en[2] = 2 | mprj_io_analog_en[2] = 2
mprj_io_analog_pol[2] = 2 | mprj_io_analog_pol[2] = 2
mprj_io_analog_sel[2] = 2 | mprj_io_analog_sel[2] = 2
mprj_io_dm[6] = 2 | mprj_io_dm[6] = 2
mprj_io_dm[7] = 2 | mprj_io_dm[7] = 2
mprj_io_dm[8] = 2 | mprj_io_dm[8] = 2
mprj_io_holdover[2] = 2 | mprj_io_holdover[2] = 2
mprj_io_ib_mode_sel[2] = 2 | mprj_io_ib_mode_sel[2] = 2
mprj_io_inp_dis[2] = 2 | mprj_io_inp_dis[2] = 2
mprj_io_oeb[2] = 2 | mprj_io_oeb[2] = 2
mprj_io_out[2] = 2 | mprj_io_out[2] = 2
mprj_io_slow_sel[2] = 2 | mprj_io_slow_sel[2] = 2
mprj_io_vtrip_sel[2] = 2 | mprj_io_vtrip_sel[2] = 2
mprj_io_in[2] = 3 | mprj_io_in[2] = 3
mprj_io_in_3v3[2] = 1 | mprj_io_in_3v3[2] = 2
mprj_io[3] = 1 | mprj_io[3] = 1
mprj_io_analog_en[3] = 2 | mprj_io_analog_en[3] = 2
mprj_io_analog_pol[3] = 2 | mprj_io_analog_pol[3] = 2
mprj_io_analog_sel[3] = 2 | mprj_io_analog_sel[3] = 2
mprj_io_dm[10] = 2 | mprj_io_dm[10] = 2
mprj_io_dm[11] = 2 | mprj_io_dm[11] = 2
mprj_io_dm[9] = 2 | mprj_io_dm[9] = 2
mprj_io_holdover[3] = 2 | mprj_io_holdover[3] = 2
mprj_io_ib_mode_sel[3] = 2 | mprj_io_ib_mode_sel[3] = 2
mprj_io_inp_dis[3] = 2 | mprj_io_inp_dis[3] = 2
mprj_io_oeb[3] = 2 | mprj_io_oeb[3] = 2
mprj_io_out[3] = 2 | mprj_io_out[3] = 2
mprj_io_slow_sel[3] = 2 | mprj_io_slow_sel[3] = 2
mprj_io_vtrip_sel[3] = 2 | mprj_io_vtrip_sel[3] = 2
mprj_io_in[3] = 3 | mprj_io_in[3] = 3
mprj_io_in_3v3[3] = 1 | mprj_io_in_3v3[3] = 2
mprj_io[4] = 1 | mprj_io[4] = 1
mprj_io_analog_en[4] = 2 | mprj_io_analog_en[4] = 2
mprj_io_analog_pol[4] = 2 | mprj_io_analog_pol[4] = 2
mprj_io_analog_sel[4] = 2 | mprj_io_analog_sel[4] = 2
mprj_io_dm[12] = 2 | mprj_io_dm[12] = 2
mprj_io_dm[13] = 2 | mprj_io_dm[13] = 2
mprj_io_dm[14] = 2 | mprj_io_dm[14] = 2
mprj_io_holdover[4] = 2 | mprj_io_holdover[4] = 2
mprj_io_ib_mode_sel[4] = 2 | mprj_io_ib_mode_sel[4] = 2
mprj_io_inp_dis[4] = 2 | mprj_io_inp_dis[4] = 2
mprj_io_oeb[4] = 2 | mprj_io_oeb[4] = 2
mprj_io_out[4] = 2 | mprj_io_out[4] = 2
mprj_io_slow_sel[4] = 2 | mprj_io_slow_sel[4] = 2
mprj_io_vtrip_sel[4] = 2 | mprj_io_vtrip_sel[4] = 2
mprj_io_in[4] = 3 | mprj_io_in[4] = 3
mprj_io_in_3v3[4] = 1 | mprj_io_in_3v3[4] = 2
mprj_io[5] = 1 | mprj_io[5] = 1
mprj_io_analog_en[5] = 2 | mprj_io_analog_en[5] = 2
mprj_io_analog_pol[5] = 2 | mprj_io_analog_pol[5] = 2
mprj_io_analog_sel[5] = 2 | mprj_io_analog_sel[5] = 2
mprj_io_dm[15] = 2 | mprj_io_dm[15] = 2
mprj_io_dm[16] = 2 | mprj_io_dm[16] = 2
mprj_io_dm[17] = 2 | mprj_io_dm[17] = 2
mprj_io_holdover[5] = 2 | mprj_io_holdover[5] = 2
mprj_io_ib_mode_sel[5] = 2 | mprj_io_ib_mode_sel[5] = 2
mprj_io_inp_dis[5] = 2 | mprj_io_inp_dis[5] = 2
mprj_io_oeb[5] = 2 | mprj_io_oeb[5] = 2
mprj_io_out[5] = 2 | mprj_io_out[5] = 2
mprj_io_slow_sel[5] = 2 | mprj_io_slow_sel[5] = 2
mprj_io_vtrip_sel[5] = 2 | mprj_io_vtrip_sel[5] = 2
mprj_io_in[5] = 3 | mprj_io_in[5] = 3
mprj_io_in_3v3[5] = 1 | mprj_io_in_3v3[5] = 2
mprj_io[6] = 1 | mprj_io[6] = 1
mprj_io_analog_en[6] = 2 | mprj_io_analog_en[6] = 2
mprj_io_analog_pol[6] = 2 | mprj_io_analog_pol[6] = 2
mprj_io_analog_sel[6] = 2 | mprj_io_analog_sel[6] = 2
mprj_io_dm[18] = 2 | mprj_io_dm[18] = 2
mprj_io_dm[19] = 2 | mprj_io_dm[19] = 2
mprj_io_dm[20] = 2 | mprj_io_dm[20] = 2
mprj_io_holdover[6] = 2 | mprj_io_holdover[6] = 2
mprj_io_ib_mode_sel[6] = 2 | mprj_io_ib_mode_sel[6] = 2
mprj_io_inp_dis[6] = 2 | mprj_io_inp_dis[6] = 2
mprj_io_oeb[6] = 2 | mprj_io_oeb[6] = 2
mprj_io_out[6] = 2 | mprj_io_out[6] = 2
mprj_io_slow_sel[6] = 2 | mprj_io_slow_sel[6] = 2
mprj_io_vtrip_sel[6] = 2 | mprj_io_vtrip_sel[6] = 2
mprj_io_in[6] = 3 | mprj_io_in[6] = 3
mprj_io_in_3v3[6] = 1 | mprj_io_in_3v3[6] = 2
mprj_gpio_analog[0] = 1 | mprj_gpio_analog[0] = 2
mprj_gpio_noesd[0] = 1 | mprj_gpio_noesd[0] = 2
mprj_io[7] = 1 | mprj_io[7] = 1
mprj_io_analog_en[7] = 2 | mprj_io_analog_en[7] = 2
mprj_io_analog_pol[7] = 2 | mprj_io_analog_pol[7] = 2
mprj_io_analog_sel[7] = 2 | mprj_io_analog_sel[7] = 2
mprj_io_dm[21] = 2 | mprj_io_dm[21] = 2
mprj_io_dm[22] = 2 | mprj_io_dm[22] = 2
mprj_io_dm[23] = 2 | mprj_io_dm[23] = 2
mprj_io_holdover[7] = 2 | mprj_io_holdover[7] = 2
mprj_io_ib_mode_sel[7] = 2 | mprj_io_ib_mode_sel[7] = 2
mprj_io_inp_dis[7] = 2 | mprj_io_inp_dis[7] = 2
mprj_io_oeb[7] = 2 | mprj_io_oeb[7] = 2
mprj_io_out[7] = 2 | mprj_io_out[7] = 2
mprj_io_slow_sel[7] = 2 | mprj_io_slow_sel[7] = 2
mprj_io_vtrip_sel[7] = 2 | mprj_io_vtrip_sel[7] = 2
mprj_io_in[7] = 3 | mprj_io_in[7] = 3
mprj_io_in_3v3[7] = 1 | mprj_io_in_3v3[7] = 2
mprj_gpio_analog[1] = 1 | mprj_gpio_analog[1] = 2
mprj_gpio_noesd[1] = 1 | mprj_gpio_noesd[1] = 2
mprj_io[8] = 1 | mprj_io[8] = 1
mprj_io_analog_en[8] = 2 | mprj_io_analog_en[8] = 2
mprj_io_analog_pol[8] = 2 | mprj_io_analog_pol[8] = 2
mprj_io_analog_sel[8] = 2 | mprj_io_analog_sel[8] = 2
mprj_io_dm[24] = 2 | mprj_io_dm[24] = 2
mprj_io_dm[25] = 2 | mprj_io_dm[25] = 2
mprj_io_dm[26] = 2 | mprj_io_dm[26] = 2
mprj_io_holdover[8] = 2 | mprj_io_holdover[8] = 2
mprj_io_ib_mode_sel[8] = 2 | mprj_io_ib_mode_sel[8] = 2
mprj_io_inp_dis[8] = 2 | mprj_io_inp_dis[8] = 2
mprj_io_oeb[8] = 2 | mprj_io_oeb[8] = 2
mprj_io_out[8] = 2 | mprj_io_out[8] = 2
mprj_io_slow_sel[8] = 2 | mprj_io_slow_sel[8] = 2
mprj_io_vtrip_sel[8] = 2 | mprj_io_vtrip_sel[8] = 2
mprj_io_in[8] = 3 | mprj_io_in[8] = 3
mprj_io_in_3v3[8] = 1 | mprj_io_in_3v3[8] = 2
mprj_gpio_analog[2] = 1 | mprj_gpio_analog[2] = 2
mprj_gpio_noesd[2] = 1 | mprj_gpio_noesd[2] = 2
mprj_io[9] = 1 | mprj_io[9] = 1
mprj_io_analog_en[9] = 2 | mprj_io_analog_en[9] = 2
mprj_io_analog_pol[9] = 2 | mprj_io_analog_pol[9] = 2
mprj_io_analog_sel[9] = 2 | mprj_io_analog_sel[9] = 2
mprj_io_dm[27] = 2 | mprj_io_dm[27] = 2
mprj_io_dm[28] = 2 | mprj_io_dm[28] = 2
mprj_io_dm[29] = 2 | mprj_io_dm[29] = 2
mprj_io_holdover[9] = 2 | mprj_io_holdover[9] = 2
mprj_io_ib_mode_sel[9] = 2 | mprj_io_ib_mode_sel[9] = 2
mprj_io_inp_dis[9] = 2 | mprj_io_inp_dis[9] = 2
mprj_io_oeb[9] = 2 | mprj_io_oeb[9] = 2
mprj_io_out[9] = 2 | mprj_io_out[9] = 2
mprj_io_slow_sel[9] = 2 | mprj_io_slow_sel[9] = 2
mprj_io_vtrip_sel[9] = 2 | mprj_io_vtrip_sel[9] = 2
mprj_io_in[9] = 3 | mprj_io_in[9] = 3
mprj_io_in_3v3[9] = 1 | mprj_io_in_3v3[9] = 2
mprj_gpio_analog[7] = 1 | mprj_gpio_analog[7] = 2
mprj_gpio_noesd[7] = 1 | mprj_gpio_noesd[7] = 2
mprj_io[25] = 1 | mprj_io[25] = 1
mprj_io_analog_en[14] = 2 | mprj_io_analog_en[14] = 2
mprj_io_analog_pol[14] = 2 | mprj_io_analog_pol[14] = 2
mprj_io_analog_sel[14] = 2 | mprj_io_analog_sel[14] = 2
mprj_io_dm[42] = 2 | mprj_io_dm[42] = 2
mprj_io_dm[43] = 2 | mprj_io_dm[43] = 2
mprj_io_dm[44] = 2 | mprj_io_dm[44] = 2
mprj_io_holdover[14] = 2 | mprj_io_holdover[14] = 2
mprj_io_ib_mode_sel[14] = 2 | mprj_io_ib_mode_sel[14] = 2
mprj_io_inp_dis[14] = 2 | mprj_io_inp_dis[14] = 2
mprj_io_oeb[14] = 2 | mprj_io_oeb[14] = 2
mprj_io_out[14] = 2 | mprj_io_out[14] = 2
mprj_io_slow_sel[14] = 2 | mprj_io_slow_sel[14] = 2
mprj_io_vtrip_sel[14] = 2 | mprj_io_vtrip_sel[14] = 2
mprj_io_in[14] = 3 | mprj_io_in[14] = 3
mprj_io_in_3v3[14] = 1 | mprj_io_in_3v3[14] = 2
mprj_gpio_analog[17] = 1 | mprj_gpio_analog[17] = 2
mprj_gpio_noesd[17] = 1 | mprj_gpio_noesd[17] = 2
mprj_io[35] = 1 | mprj_io[35] = 1
mprj_io_analog_en[24] = 2 | mprj_io_analog_en[24] = 2
mprj_io_analog_pol[24] = 2 | mprj_io_analog_pol[24] = 2
mprj_io_analog_sel[24] = 2 | mprj_io_analog_sel[24] = 2
mprj_io_dm[72] = 2 | mprj_io_dm[72] = 2
mprj_io_dm[73] = 2 | mprj_io_dm[73] = 2
mprj_io_dm[74] = 2 | mprj_io_dm[74] = 2
mprj_io_holdover[24] = 2 | mprj_io_holdover[24] = 2
mprj_io_ib_mode_sel[24] = 2 | mprj_io_ib_mode_sel[24] = 2
mprj_io_inp_dis[24] = 2 | mprj_io_inp_dis[24] = 2
mprj_io_oeb[24] = 2 | mprj_io_oeb[24] = 2
mprj_io_out[24] = 2 | mprj_io_out[24] = 2
mprj_io_slow_sel[24] = 2 | mprj_io_slow_sel[24] = 2
mprj_io_vtrip_sel[24] = 2 | mprj_io_vtrip_sel[24] = 2
mprj_io_in[24] = 3 | mprj_io_in[24] = 3
mprj_io_in_3v3[24] = 1 | mprj_io_in_3v3[24] = 2
mprj_io[36] = 1 | mprj_io[36] = 1
mprj_io_analog_en[25] = 2 | mprj_io_analog_en[25] = 2
mprj_io_analog_pol[25] = 2 | mprj_io_analog_pol[25] = 2
mprj_io_analog_sel[25] = 2 | mprj_io_analog_sel[25] = 2
mprj_io_dm[75] = 2 | mprj_io_dm[75] = 2
mprj_io_dm[76] = 2 | mprj_io_dm[76] = 2
mprj_io_dm[77] = 2 | mprj_io_dm[77] = 2
mprj_io_holdover[25] = 2 | mprj_io_holdover[25] = 2
mprj_io_ib_mode_sel[25] = 2 | mprj_io_ib_mode_sel[25] = 2
mprj_io_inp_dis[25] = 2 | mprj_io_inp_dis[25] = 2
mprj_io_oeb[25] = 2 | mprj_io_oeb[25] = 2
mprj_io_out[25] = 2 | mprj_io_out[25] = 2
mprj_io_slow_sel[25] = 2 | mprj_io_slow_sel[25] = 2
mprj_io_vtrip_sel[25] = 2 | mprj_io_vtrip_sel[25] = 2
mprj_io_in[25] = 3 | mprj_io_in[25] = 3
mprj_io_in_3v3[25] = 1 | mprj_io_in_3v3[25] = 2
mprj_io[37] = 1 | mprj_io[37] = 1
mprj_io_analog_en[26] = 2 | mprj_io_analog_en[26] = 2
mprj_io_analog_pol[26] = 2 | mprj_io_analog_pol[26] = 2
mprj_io_analog_sel[26] = 2 | mprj_io_analog_sel[26] = 2
mprj_io_dm[78] = 2 | mprj_io_dm[78] = 2
mprj_io_dm[79] = 2 | mprj_io_dm[79] = 2
mprj_io_dm[80] = 2 | mprj_io_dm[80] = 2
mprj_io_holdover[26] = 2 | mprj_io_holdover[26] = 2
mprj_io_ib_mode_sel[26] = 2 | mprj_io_ib_mode_sel[26] = 2
mprj_io_inp_dis[26] = 2 | mprj_io_inp_dis[26] = 2
mprj_io_oeb[26] = 2 | mprj_io_oeb[26] = 2
mprj_io_out[26] = 2 | mprj_io_out[26] = 2
mprj_io_slow_sel[26] = 2 | mprj_io_slow_sel[26] = 2
mprj_io_vtrip_sel[26] = 2 | mprj_io_vtrip_sel[26] = 2
mprj_io_in[26] = 3 | mprj_io_in[26] = 3
mprj_io_in_3v3[26] = 1 | mprj_io_in_3v3[26] = 2
mprj_gpio_analog[8] = 1 | mprj_gpio_analog[8] = 2
mprj_gpio_noesd[8] = 1 | mprj_gpio_noesd[8] = 2
mprj_io[26] = 1 | mprj_io[26] = 1
mprj_io_analog_en[15] = 2 | mprj_io_analog_en[15] = 2
mprj_io_analog_pol[15] = 2 | mprj_io_analog_pol[15] = 2
mprj_io_analog_sel[15] = 2 | mprj_io_analog_sel[15] = 2
mprj_io_dm[45] = 2 | mprj_io_dm[45] = 2
mprj_io_dm[46] = 2 | mprj_io_dm[46] = 2
mprj_io_dm[47] = 2 | mprj_io_dm[47] = 2
mprj_io_holdover[15] = 2 | mprj_io_holdover[15] = 2
mprj_io_ib_mode_sel[15] = 2 | mprj_io_ib_mode_sel[15] = 2
mprj_io_inp_dis[15] = 2 | mprj_io_inp_dis[15] = 2
mprj_io_oeb[15] = 2 | mprj_io_oeb[15] = 2
mprj_io_out[15] = 2 | mprj_io_out[15] = 2
mprj_io_slow_sel[15] = 2 | mprj_io_slow_sel[15] = 2
mprj_io_vtrip_sel[15] = 2 | mprj_io_vtrip_sel[15] = 2
mprj_io_in[15] = 3 | mprj_io_in[15] = 3
mprj_io_in_3v3[15] = 1 | mprj_io_in_3v3[15] = 2
mprj_gpio_analog[9] = 1 | mprj_gpio_analog[9] = 2
mprj_gpio_noesd[9] = 1 | mprj_gpio_noesd[9] = 2
mprj_io[27] = 1 | mprj_io[27] = 1
mprj_io_analog_en[16] = 2 | mprj_io_analog_en[16] = 2
mprj_io_analog_pol[16] = 2 | mprj_io_analog_pol[16] = 2
mprj_io_analog_sel[16] = 2 | mprj_io_analog_sel[16] = 2
mprj_io_dm[48] = 2 | mprj_io_dm[48] = 2
mprj_io_dm[49] = 2 | mprj_io_dm[49] = 2
mprj_io_dm[50] = 2 | mprj_io_dm[50] = 2
mprj_io_holdover[16] = 2 | mprj_io_holdover[16] = 2
mprj_io_ib_mode_sel[16] = 2 | mprj_io_ib_mode_sel[16] = 2
mprj_io_inp_dis[16] = 2 | mprj_io_inp_dis[16] = 2
mprj_io_oeb[16] = 2 | mprj_io_oeb[16] = 2
mprj_io_out[16] = 2 | mprj_io_out[16] = 2
mprj_io_slow_sel[16] = 2 | mprj_io_slow_sel[16] = 2
mprj_io_vtrip_sel[16] = 2 | mprj_io_vtrip_sel[16] = 2
mprj_io_in[16] = 3 | mprj_io_in[16] = 3
mprj_io_in_3v3[16] = 1 | mprj_io_in_3v3[16] = 2
mprj_gpio_analog[10] = 1 | mprj_gpio_analog[10] = 2
mprj_gpio_noesd[10] = 1 | mprj_gpio_noesd[10] = 2
mprj_io[28] = 1 | mprj_io[28] = 1
mprj_io_analog_en[17] = 2 | mprj_io_analog_en[17] = 2
mprj_io_analog_pol[17] = 2 | mprj_io_analog_pol[17] = 2
mprj_io_analog_sel[17] = 2 | mprj_io_analog_sel[17] = 2
mprj_io_dm[51] = 2 | mprj_io_dm[51] = 2
mprj_io_dm[52] = 2 | mprj_io_dm[52] = 2
mprj_io_dm[53] = 2 | mprj_io_dm[53] = 2
mprj_io_holdover[17] = 2 | mprj_io_holdover[17] = 2
mprj_io_ib_mode_sel[17] = 2 | mprj_io_ib_mode_sel[17] = 2
mprj_io_inp_dis[17] = 2 | mprj_io_inp_dis[17] = 2
mprj_io_oeb[17] = 2 | mprj_io_oeb[17] = 2
mprj_io_out[17] = 2 | mprj_io_out[17] = 2
mprj_io_slow_sel[17] = 2 | mprj_io_slow_sel[17] = 2
mprj_io_vtrip_sel[17] = 2 | mprj_io_vtrip_sel[17] = 2
mprj_io_in[17] = 3 | mprj_io_in[17] = 3
mprj_io_in_3v3[17] = 1 | mprj_io_in_3v3[17] = 2
mprj_gpio_analog[11] = 1 | mprj_gpio_analog[11] = 2
mprj_gpio_noesd[11] = 1 | mprj_gpio_noesd[11] = 2
mprj_io[29] = 1 | mprj_io[29] = 1
mprj_io_analog_en[18] = 2 | mprj_io_analog_en[18] = 2
mprj_io_analog_pol[18] = 2 | mprj_io_analog_pol[18] = 2
mprj_io_analog_sel[18] = 2 | mprj_io_analog_sel[18] = 2
mprj_io_dm[54] = 2 | mprj_io_dm[54] = 2
mprj_io_dm[55] = 2 | mprj_io_dm[55] = 2
mprj_io_dm[56] = 2 | mprj_io_dm[56] = 2
mprj_io_holdover[18] = 2 | mprj_io_holdover[18] = 2
mprj_io_ib_mode_sel[18] = 2 | mprj_io_ib_mode_sel[18] = 2
mprj_io_inp_dis[18] = 2 | mprj_io_inp_dis[18] = 2
mprj_io_oeb[18] = 2 | mprj_io_oeb[18] = 2
mprj_io_out[18] = 2 | mprj_io_out[18] = 2
mprj_io_slow_sel[18] = 2 | mprj_io_slow_sel[18] = 2
mprj_io_vtrip_sel[18] = 2 | mprj_io_vtrip_sel[18] = 2
mprj_io_in[18] = 3 | mprj_io_in[18] = 3
mprj_io_in_3v3[18] = 1 | mprj_io_in_3v3[18] = 2
mprj_gpio_analog[12] = 1 | mprj_gpio_analog[12] = 2
mprj_gpio_noesd[12] = 1 | mprj_gpio_noesd[12] = 2
mprj_io[30] = 1 | mprj_io[30] = 1
mprj_io_analog_en[19] = 2 | mprj_io_analog_en[19] = 2
mprj_io_analog_pol[19] = 2 | mprj_io_analog_pol[19] = 2
mprj_io_analog_sel[19] = 2 | mprj_io_analog_sel[19] = 2
mprj_io_dm[57] = 2 | mprj_io_dm[57] = 2
mprj_io_dm[58] = 2 | mprj_io_dm[58] = 2
mprj_io_dm[59] = 2 | mprj_io_dm[59] = 2
mprj_io_holdover[19] = 2 | mprj_io_holdover[19] = 2
mprj_io_ib_mode_sel[19] = 2 | mprj_io_ib_mode_sel[19] = 2
mprj_io_inp_dis[19] = 2 | mprj_io_inp_dis[19] = 2
mprj_io_oeb[19] = 2 | mprj_io_oeb[19] = 2
mprj_io_out[19] = 2 | mprj_io_out[19] = 2
mprj_io_slow_sel[19] = 2 | mprj_io_slow_sel[19] = 2
mprj_io_vtrip_sel[19] = 2 | mprj_io_vtrip_sel[19] = 2
mprj_io_in[19] = 3 | mprj_io_in[19] = 3
mprj_io_in_3v3[19] = 1 | mprj_io_in_3v3[19] = 2
mprj_gpio_analog[13] = 1 | mprj_gpio_analog[13] = 2
mprj_gpio_noesd[13] = 1 | mprj_gpio_noesd[13] = 2
mprj_io[31] = 1 | mprj_io[31] = 1
mprj_io_analog_en[20] = 2 | mprj_io_analog_en[20] = 2
mprj_io_analog_pol[20] = 2 | mprj_io_analog_pol[20] = 2
mprj_io_analog_sel[20] = 2 | mprj_io_analog_sel[20] = 2
mprj_io_dm[60] = 2 | mprj_io_dm[60] = 2
mprj_io_dm[61] = 2 | mprj_io_dm[61] = 2
mprj_io_dm[62] = 2 | mprj_io_dm[62] = 2
mprj_io_holdover[20] = 2 | mprj_io_holdover[20] = 2
mprj_io_ib_mode_sel[20] = 2 | mprj_io_ib_mode_sel[20] = 2
mprj_io_inp_dis[20] = 2 | mprj_io_inp_dis[20] = 2
mprj_io_oeb[20] = 2 | mprj_io_oeb[20] = 2
mprj_io_out[20] = 2 | mprj_io_out[20] = 2
mprj_io_slow_sel[20] = 2 | mprj_io_slow_sel[20] = 2
mprj_io_vtrip_sel[20] = 2 | mprj_io_vtrip_sel[20] = 2
mprj_io_in[20] = 3 | mprj_io_in[20] = 3
mprj_io_in_3v3[20] = 1 | mprj_io_in_3v3[20] = 2
mprj_gpio_analog[14] = 1 | mprj_gpio_analog[14] = 2
mprj_gpio_noesd[14] = 1 | mprj_gpio_noesd[14] = 2
mprj_io[32] = 1 | mprj_io[32] = 1
mprj_io_analog_en[21] = 2 | mprj_io_analog_en[21] = 2
mprj_io_analog_pol[21] = 2 | mprj_io_analog_pol[21] = 2
mprj_io_analog_sel[21] = 2 | mprj_io_analog_sel[21] = 2
mprj_io_dm[63] = 2 | mprj_io_dm[63] = 2
mprj_io_dm[64] = 2 | mprj_io_dm[64] = 2
mprj_io_dm[65] = 2 | mprj_io_dm[65] = 2
mprj_io_holdover[21] = 2 | mprj_io_holdover[21] = 2
mprj_io_ib_mode_sel[21] = 2 | mprj_io_ib_mode_sel[21] = 2
mprj_io_inp_dis[21] = 2 | mprj_io_inp_dis[21] = 2
mprj_io_oeb[21] = 2 | mprj_io_oeb[21] = 2
mprj_io_out[21] = 2 | mprj_io_out[21] = 2
mprj_io_slow_sel[21] = 2 | mprj_io_slow_sel[21] = 2
mprj_io_vtrip_sel[21] = 2 | mprj_io_vtrip_sel[21] = 2
mprj_io_in[21] = 3 | mprj_io_in[21] = 3
mprj_io_in_3v3[21] = 1 | mprj_io_in_3v3[21] = 2
mprj_gpio_analog[15] = 1 | mprj_gpio_analog[15] = 2
mprj_gpio_noesd[15] = 1 | mprj_gpio_noesd[15] = 2
mprj_io[33] = 1 | mprj_io[33] = 1
mprj_io_analog_en[22] = 2 | mprj_io_analog_en[22] = 2
mprj_io_analog_pol[22] = 2 | mprj_io_analog_pol[22] = 2
mprj_io_analog_sel[22] = 2 | mprj_io_analog_sel[22] = 2
mprj_io_dm[66] = 2 | mprj_io_dm[66] = 2
mprj_io_dm[67] = 2 | mprj_io_dm[67] = 2
mprj_io_dm[68] = 2 | mprj_io_dm[68] = 2
mprj_io_holdover[22] = 2 | mprj_io_holdover[22] = 2
mprj_io_ib_mode_sel[22] = 2 | mprj_io_ib_mode_sel[22] = 2
mprj_io_inp_dis[22] = 2 | mprj_io_inp_dis[22] = 2
mprj_io_oeb[22] = 2 | mprj_io_oeb[22] = 2
mprj_io_out[22] = 2 | mprj_io_out[22] = 2
mprj_io_slow_sel[22] = 2 | mprj_io_slow_sel[22] = 2
mprj_io_vtrip_sel[22] = 2 | mprj_io_vtrip_sel[22] = 2
mprj_io_in[22] = 3 | mprj_io_in[22] = 3
mprj_io_in_3v3[22] = 1 | mprj_io_in_3v3[22] = 2
mprj_gpio_analog[16] = 1 | mprj_gpio_analog[16] = 2
mprj_gpio_noesd[16] = 1 | mprj_gpio_noesd[16] = 2
mprj_io[34] = 1 | mprj_io[34] = 1
mprj_io_analog_en[23] = 2 | mprj_io_analog_en[23] = 2
mprj_io_analog_pol[23] = 2 | mprj_io_analog_pol[23] = 2
mprj_io_analog_sel[23] = 2 | mprj_io_analog_sel[23] = 2
mprj_io_dm[69] = 2 | mprj_io_dm[69] = 2
mprj_io_dm[70] = 2 | mprj_io_dm[70] = 2
mprj_io_dm[71] = 2 | mprj_io_dm[71] = 2
mprj_io_holdover[23] = 2 | mprj_io_holdover[23] = 2
mprj_io_ib_mode_sel[23] = 2 | mprj_io_ib_mode_sel[23] = 2
mprj_io_inp_dis[23] = 2 | mprj_io_inp_dis[23] = 2
mprj_io_oeb[23] = 2 | mprj_io_oeb[23] = 2
mprj_io_out[23] = 2 | mprj_io_out[23] = 2
mprj_io_slow_sel[23] = 2 | mprj_io_slow_sel[23] = 2
mprj_io_vtrip_sel[23] = 2 | mprj_io_vtrip_sel[23] = 2
mprj_io_in[23] = 3 | mprj_io_in[23] = 3
mprj_io_in_3v3[23] = 1 | mprj_io_in_3v3[23] = 2
resetb = 1 | resetb = 1
resetb_core_h = 2 | resetb_core_h = 2
mprj_io[15] = 1 | mprj_io[15] = 1
mprj_analog[2] = 1 | mprj_analog[2] = 2
mprj_io[16] = 1 | mprj_io[16] = 1
mprj_io[17] = 1 | mprj_io[17] = 1
mprj_clamp_high[0] = 1 | mprj_clamp_high[0] = 2
mprj_io[18] = 1 | mprj_io[18] = 1
vccd1_pad = 1 | vccd1_pad = 1
vdda1_pad = 1 | vdda1_pad = 1
vdda1_pad2 = 1 | vdda1_pad2 = 1
vccd1 = 29 | vccd1 = 30
vdda1 = 2 | vdda1 = 3
vssd1_pad = 1 | vssd1_pad = 1
mprj_analog[9] = 1 | mprj_analog[9] = 2
mprj_analog[10] = 1 | mprj_analog[10] = 2
mprj_io[24] = 1 | mprj_io[24] = 1
mprj_analog[5] = 1 | mprj_analog[5] = 2
mprj_clamp_high[1] = 1 | mprj_clamp_high[1] = 2
mprj_clamp_low[1] = 1 | mprj_clamp_low[1] = 2
mprj_io[19] = 1 | mprj_io[19] = 1
vccd2_pad = 1 | vccd2_pad = 1
vdda2_pad = 1 | vdda2_pad = 1
vssa2_pad = 1 | vssa2_pad = 1
vccd2 = 2 | vccd2 = 3
vdda2 = 2 | vdda2 = 3
vssd2_pad = 1 | vssd2_pad = 1
flash_csb_core = 2 | flash_csb_core = 2
flash_clk_oeb_core = 2 | flash_clk_oeb_core = 2
flash_clk_core = 2 | flash_clk_core = 2
flash_csb_oeb_core = 2 | flash_csb_oeb_core = 2
mprj_io_one[0] = 2 | mprj_io_one[0] = 2
mprj_io_one[1] = 2 | mprj_io_one[1] = 2
mprj_io_one[2] = 4 | mprj_io_one[2] = 4
mprj_io_one[3] = 4 | mprj_io_one[3] = 4
mprj_io_one[4] = 4 | mprj_io_one[4] = 4
mprj_io_one[5] = 4 | mprj_io_one[5] = 4
mprj_io_one[6] = 4 | mprj_io_one[6] = 4
mprj_io_one[7] = 4 | mprj_io_one[7] = 4
mprj_io_one[8] = 4 | mprj_io_one[8] = 4
mprj_io_one[9] = 4 | mprj_io_one[9] = 4
mprj_io_one[10] = 4 | mprj_io_one[10] = 4
mprj_io_one[11] = 4 | mprj_io_one[11] = 4
mprj_io_one[12] = 4 | mprj_io_one[12] = 4
mprj_io_one[13] = 4 | mprj_io_one[13] = 4
mprj_io_one[14] = 4 | mprj_io_one[14] = 4
mprj_io_one[15] = 4 | mprj_io_one[15] = 4
mprj_io_one[16] = 4 | mprj_io_one[16] = 4
mprj_io_one[17] = 4 | mprj_io_one[17] = 4
mprj_io_one[18] = 4 | mprj_io_one[18] = 4
mprj_io_one[19] = 4 | mprj_io_one[19] = 4
mprj_io_one[20] = 4 | mprj_io_one[20] = 4
mprj_io_one[21] = 4 | mprj_io_one[21] = 4
mprj_io_one[22] = 4 | mprj_io_one[22] = 4
mprj_io_one[23] = 4 | mprj_io_one[23] = 4
mprj_io_one[24] = 2 | mprj_io_one[24] = 2
mprj_io_one[25] = 2 | mprj_io_one[25] = 2
mprj_io_one[26] = 2 | mprj_io_one[26] = 2
porb_h = 2 | porb_h = 2
gpio_mode1_core = 2 | gpio_mode1_core = 2
w_694469_865869# = 1 | proxyw_694469_865869# = 1
w_23367_407274# = 1 | proxyw_23367_407274# = 1
w_694469_100152# = 1 | proxyw_694469_100152# = 1
w_23367_534874# = 1 | proxyw_23367_534874# = 1
w_404752_21253# = 1 | proxyw_404752_21253# = 1
w_459552_23367# = 1 | proxyw_459552_23367# = 1
w_23367_280765# = 1 | proxyw_23367_280765# = 1
w_692253_776670# = 1 | proxyw_692253_776670# = 1
w_23367_710765# = 1 | proxyw_23367_710765# = 1
w_78010_1007543# = 1 | proxyw_78010_1007543# = 1
w_692355_547952# = 1 | proxyw_692355_547952# = 1
w_23367_537965# = 1 | proxyw_23367_537965# = 1
w_21151_364074# = 1 | proxyw_21151_364074# = 1
w_459552_21253# = 1 | proxyw_459552_21253# = 1
w_694469_145352# = 1 | proxyw_694469_145352# = 1
w_692355_593152# = 1 | proxyw_692355_593152# = 1
w_694469_190352# = 1 | proxyw_694469_190352# = 1
w_349952_23367# = 1 | proxyw_349952_23367# = 1
w_692355_325552# = 1 | proxyw_692355_325552# = 1
w_189869_23367# = 1 | proxyw_189869_23367# = 1
w_694469_235552# = 1 | proxyw_694469_235552# = 1
w_21151_794074# = 1 | proxyw_21151_794074# = 1
w_692355_683352# = 1 | proxyw_692355_683352# = 1
w_21253_194365# = 1 | proxyw_21253_194365# = 1
w_694469_280552# = 1 | proxyw_694469_280552# = 1
w_21253_624365# = 1 | proxyw_21253_624365# = 1
w_295152_23367# = 1 | proxyw_295152_23367# = 1
w_349952_21253# = 1 | proxyw_349952_21253# = 1
w_23367_578074# = 1 | proxyw_23367_578074# = 1
w_692253_551270# = 1 | proxyw_692253_551270# = 1
w_694469_370752# = 1 | proxyw_694469_370752# = 1
w_189869_21253# = 1 | proxyw_189869_21253# = 1
w_21151_277674# = 1 | proxyw_21151_277674# = 1
mprj_io[21] = 1 | mprj_io[21] = 1
w_692253_641470# = 1 | proxyw_692253_641470# = 1
w_295152_21253# = 1 | proxyw_295152_21253# = 1
w_21151_707674# = 1 | proxyw_21151_707674# = 1
w_23367_234474# = 1 | proxyw_23367_234474# = 1
w_692355_100152# = 1 | proxyw_692355_100152# = 1
w_694469_776669# = 1 | proxyw_694469_776669# = 1
w_692253_596470# = 1 | proxyw_692253_596470# = 1
w_692253_731670# = 1 | proxyw_692253_731670# = 1
w_21253_280765# = 1 | proxyw_21253_280765# = 1
w_692253_328870# = 1 | proxyw_692253_328870# = 1
w_23367_410365# = 1 | proxyw_23367_410365# = 1
w_21253_710765# = 1 | proxyw_21253_710765# = 1
w_462869_23367# = 1 | proxyw_462869_23367# = 1
w_23367_237565# = 1 | proxyw_23367_237565# = 1
w_21253_537965# = 1 | proxyw_21253_537965# = 1
w_23367_664474# = 1 | proxyw_23367_664474# = 1
w_692253_686670# = 1 | proxyw_692253_686670# = 1
w_21151_191274# = 1 | proxyw_21151_191274# = 1
w_692253_374070# = 1 | proxyw_692253_374070# = 1
mprj_analog[6] = 1 | mprj_analog[6] = 2
w_692355_145352# = 1 | proxyw_692355_145352# = 1
w_21151_621274# = 1 | proxyw_21151_621274# = 1
w_692355_190352# = 1 | proxyw_692355_190352# = 1
w_694469_862552# = 1 | proxyw_694469_862552# = 1
w_687543_952480# = 1 | proxyw_687543_952480# = 1
w_180810_1007543# = 1 | proxyw_180810_1007543# = 1
w_462869_21253# = 1 | proxyw_462869_21253# = 1
w_23367_667565# = 1 | proxyw_23367_667565# = 1
w_692355_235552# = 1 | proxyw_692355_235552# = 1
w_694469_551269# = 1 | proxyw_694469_551269# = 1
w_23367_320874# = 1 | proxyw_23367_320874# = 1
w_692355_280552# = 1 | proxyw_692355_280552# = 1
mprj_analog[7] = 1 | mprj_analog[7] = 2
w_692253_103470# = 1 | proxyw_692253_103470# = 1
w_694469_641469# = 1 | proxyw_694469_641469# = 1
w_129410_1007543# = 1 | proxyw_129410_1007543# = 1
w_692355_370752# = 1 | proxyw_692355_370752# = 1
w_23367_323965# = 1 | proxyw_23367_323965# = 1
w_23367_750874# = 1 | proxyw_23367_750874# = 1
w_694469_596469# = 1 | proxyw_694469_596469# = 1
mprj_io[20] = 1 | mprj_io[20] = 1
mprj_io[22] = 1 | mprj_io[22] = 1
w_23367_581165# = 1 | proxyw_23367_581165# = 1
w_694469_731669# = 1 | proxyw_694469_731669# = 1
w_526010_1007543# = 1 | proxyw_526010_1007543# = 1
w_21151_407274# = 1 | proxyw_21151_407274# = 1
w_186552_23367# = 1 | proxyw_186552_23367# = 1
w_517669_23367# = 1 | proxyw_517669_23367# = 1
w_21151_534874# = 1 | proxyw_21151_534874# = 1
w_694469_328869# = 1 | proxyw_694469_328869# = 1
mprj_analog[3] = 1 | mprj_analog[3] = 2
mprj_clamp_low[0] = 1 | mprj_clamp_low[0] = 2
w_692253_148670# = 1 | proxyw_692253_148670# = 1
w_23367_753965# = 1 | proxyw_23367_753965# = 1
w_694469_686669# = 1 | proxyw_694469_686669# = 1
w_692253_193670# = 1 | proxyw_692253_193670# = 1
w_694469_374069# = 1 | proxyw_694469_374069# = 1
vssd1 = 29 | vssd1 = 30
w_21253_410365# = 1 | proxyw_21253_410365# = 1
w_694469_638152# = 1 | proxyw_694469_638152# = 1
w_186552_21253# = 1 | proxyw_186552_21253# = 1
w_517669_21253# = 1 | proxyw_517669_21253# = 1
mprj_clamp_high[2] = 1 | mprj_clamp_high[2] = 2
w_21253_237565# = 1 | proxyw_21253_237565# = 1
w_692253_238870# = 1 | proxyw_692253_238870# = 1
w_23367_364074# = 1 | proxyw_23367_364074# = 1
w_692253_283870# = 1 | proxyw_692253_283870# = 1
w_474610_1007543# = 1 | proxyw_474610_1007543# = 1
w_694469_728352# = 1 | proxyw_694469_728352# = 1
w_627810_1007543# = 1 | proxyw_627810_1007543# = 1
w_692355_862552# = 1 | proxyw_692355_862552# = 1
mprj_clamp_low[2] = 1 | mprj_clamp_low[2] = 2
w_694469_773352# = 1 | proxyw_694469_773352# = 1
w_23367_367165# = 1 | proxyw_23367_367165# = 1
w_21253_667565# = 1 | proxyw_21253_667565# = 1
w_23367_794074# = 1 | proxyw_23367_794074# = 1
w_694469_103469# = 1 | proxyw_694469_103469# = 1
w_353269_23367# = 1 | proxyw_353269_23367# = 1
vssd2 = 2 | vssd2 = 3
w_21151_578074# = 1 | proxyw_21151_578074# = 1
w_23367_797165# = 1 | proxyw_23367_797165# = 1
w_21253_323965# = 1 | proxyw_21253_323965# = 1
w_353269_21253# = 1 | proxyw_353269_21253# = 1
mprj_analog[8] = 1 | mprj_analog[8] = 2
w_23367_277674# = 1 | proxyw_23367_277674# = 1
w_694469_148669# = 1 | proxyw_694469_148669# = 1
w_21253_581165# = 1 | proxyw_21253_581165# = 1
mprj_io[23] = 1 | mprj_io[23] = 1
w_694469_193669# = 1 | proxyw_694469_193669# = 1
w_4069_956010# = 1 | proxyw_4069_956010# = 1
w_23367_707674# = 1 | proxyw_23367_707674# = 1
w_21151_234474# = 1 | proxyw_21151_234474# = 1
vdda = 1 | vdda = 1
vddio_pad2 = 1 | vddio_pad2 = 1
w_694469_238869# = 1 | proxyw_694469_238869# = 1
w_21253_753965# = 1 | proxyw_21253_753965# = 1
w_694469_283869# = 1 | proxyw_694469_283869# = 1
w_692253_865870# = 1 | proxyw_692253_865870# = 1
mprj_io[14] = 1 | mprj_io[14] = 1
w_298469_23367# = 1 | proxyw_298469_23367# = 1
mprj_analog[0] = 1 | mprj_analog[0] = 2
w_694469_547952# = 1 | proxyw_694469_547952# = 1
w_692355_638152# = 1 | proxyw_692355_638152# = 1
w_21151_664474# = 1 | proxyw_21151_664474# = 1
w_23367_191274# = 1 | proxyw_23367_191274# = 1
vssd_pad = 1 | vssd_pad = 1
w_408069_23367# = 1 | proxyw_408069_23367# = 1
w_694469_593152# = 1 | proxyw_694469_593152# = 1
w_23367_621274# = 1 | proxyw_23367_621274# = 1
vssa1_pad = 1 | vssa1_pad = 1
w_692355_728352# = 1 | proxyw_692355_728352# = 1
w_514352_23367# = 1 | proxyw_514352_23367# = 1
w_694469_325552# = 1 | proxyw_694469_325552# = 1
w_692355_773352# = 1 | proxyw_692355_773352# = 1
w_298469_21253# = 1 | proxyw_298469_21253# = 1
w_694469_683352# = 1 | proxyw_694469_683352# = 1
w_21253_367165# = 1 | proxyw_21253_367165# = 1
w_23367_194365# = 1 | proxyw_23367_194365# = 1
w_21151_320874# = 1 | proxyw_21151_320874# = 1
w_408069_21253# = 1 | proxyw_408069_21253# = 1
mprj_analog[1] = 1 | mprj_analog[1] = 2
w_23367_624365# = 1 | proxyw_23367_624365# = 1
vssa2 = 2 | vssa2 = 3
w_514352_21253# = 1 | proxyw_514352_21253# = 1
vccd = 8797 | vccd = 8792
vssa = 1 | vssa = 1
w_404752_23367# = 1 | proxyw_404752_23367# = 1
vssa1_pad2 = 1 | vssa1_pad2 = 1
vssio = 3 | vssio = 3
mprj_analog[4] = 1 | mprj_analog[4] = 2
vddio = 3 | vddio = 3
w_21253_797165# = 1 | proxyw_21253_797165# = 1
vssa1 = 2 | vssa1 = 3
w_21151_750874# = 1 | proxyw_21151_750874# = 1
vssd = 8792 | vssd = 8792
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[9] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[8] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[7] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[6] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[5] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[4] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[3] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[2] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[1] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[0] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[5] /gpio_log
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[4] /gpio_log
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[3] /gpio_log
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[2] /gpio_log
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[1] /gpio_log
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[0] /gpio_log
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[5] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[4] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[3] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[2] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[1] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[0] /gpio_logi
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[2] /gpio_l
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[1] /gpio_l
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[0] /gpio_l
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[1] /gpio_l
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[0] /gpio_l
gpio_logic1 = 2 | gpio_logic1 = 2
vccd1 = 29 | vccd1 = 30
vssd1 = 29 | vssd1 = 30
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[9] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[9] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[8] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[8] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[7] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[7] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[6] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[6] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[5] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[5] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[4] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[4] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[3] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[3] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[2] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[2] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[1] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[1] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[0] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[0] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[5] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[5] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[4] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[4] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[3] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[3] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[2] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[2] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[1] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[1] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[0] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[0] /spare_ce
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[5] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[5] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[4] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[4] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[3] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[3] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[2] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[2] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[1] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[1] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[0] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[0] /spare_cel
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[2] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[2] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[1] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[1] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[0] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[0] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[1] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[1] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[0] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[0] /spare_
Y = 3 | Y = 8792
A = 5 | A = 3
B = 5 | B = 5
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
VNB = 8792 | VNB = 8792
VPB = 8797 | VPB = 8792
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[9] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[8] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[7] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[6] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[5] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[4] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[3] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[2] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[1] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_2[0] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[5] /spare_ce
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[4] /spare_ce
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[3] /spare_ce
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[2] /spare_ce
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[1] /spare_ce
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1a[0] /spare_ce
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[5] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[4] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[3] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[2] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[1] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_in_1[0] /spare_cel
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[2] /spare_
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[1] /spare_
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_2[0] /spare_
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[1] /spare_
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
|
Instance: gpio_control_block:gpio_control_ |Instance: \gpio_control_bidir_1[0] /spare_
LO = 5 | LO = 8792
HI = 1 | HI = 8792
VPB = 8797 | VPB = 8792
VNB = 8792 | VNB = 1
VGND = 8792 | VGND = 5
VPWR = 8797 | VPWR = 8792
---------------------------------------------------------------------------------------
Netlists do not match.
Subcircuit pins:
Circuit 1: caravan |Circuit 2: caravan
-------------------------------------------|-------------------------------------------
clock |(no matching pin)
flash_clk |(no matching pin)
flash_csb |(no matching pin)
flash_io0 |(no matching pin)
flash_io1 |(no matching pin)
gpio |(no matching pin)
vccd |(no matching pin)
vdda |(no matching pin)
vddio |(no matching pin)
vssa |(no matching pin)
vssio |(no matching pin)
vssio_2 |(no matching pin)
mprj_io[0] |(no matching pin)
mprj_io[10] |(no matching pin)
mprj_io[11] |(no matching pin)
mprj_io[12] |(no matching pin)
mprj_io[13] |(no matching pin)
mprj_io[1] |(no matching pin)
mprj_io[2] |(no matching pin)
mprj_io[3] |(no matching pin)
mprj_io[4] |(no matching pin)
mprj_io[5] |(no matching pin)
mprj_io[6] |(no matching pin)
mprj_io[7] |(no matching pin)
mprj_io[8] |(no matching pin)
mprj_io[9] |(no matching pin)
mprj_io[25] |(no matching pin)
mprj_io[35] |(no matching pin)
mprj_io[36] |(no matching pin)
mprj_io[37] |(no matching pin)
mprj_io[26] |(no matching pin)
mprj_io[27] |(no matching pin)
mprj_io[28] |(no matching pin)
mprj_io[29] |(no matching pin)
mprj_io[30] |(no matching pin)
mprj_io[31] |(no matching pin)
mprj_io[32] |(no matching pin)
mprj_io[33] |(no matching pin)
mprj_io[34] |(no matching pin)
resetb |(no matching pin)
mprj_io[15] |(no matching pin)
mprj_io[16] |(no matching pin)
mprj_io[17] |(no matching pin)
mprj_io[18] |(no matching pin)
vccd1 |(no matching pin)
vdda1 |(no matching pin)
vdda1_2 |(no matching pin)
vssd1 |(no matching pin)
mprj_io[24] |(no matching pin)
mprj_io[19] |(no matching pin)
vccd2 |(no matching pin)
vdda2 |(no matching pin)
vssa2 |(no matching pin)
vssd2 |(no matching pin)
mprj_io[21] |(no matching pin)
mprj_io[20] |(no matching pin)
mprj_io[22] |(no matching pin)
mprj_io[23] |(no matching pin)
vddio_2 |(no matching pin)
mprj_io[14] |(no matching pin)
vssd |(no matching pin)
vssa1 |(no matching pin)
vssa1_2 |(no matching pin)
(no matching pin) |clock
(no matching pin) |flash_clk
(no matching pin) |flash_csb
(no matching pin) |flash_io0
(no matching pin) |flash_io1
(no matching pin) |gpio
(no matching pin) |mprj_io[37]
(no matching pin) |mprj_io[36]
(no matching pin) |mprj_io[35]
(no matching pin) |mprj_io[34]
(no matching pin) |mprj_io[33]
(no matching pin) |mprj_io[32]
(no matching pin) |mprj_io[31]
(no matching pin) |mprj_io[30]
(no matching pin) |mprj_io[29]
(no matching pin) |mprj_io[28]
(no matching pin) |mprj_io[27]
(no matching pin) |mprj_io[26]
(no matching pin) |mprj_io[25]
(no matching pin) |mprj_io[24]
(no matching pin) |mprj_io[23]
(no matching pin) |mprj_io[22]
(no matching pin) |mprj_io[21]
(no matching pin) |mprj_io[20]
(no matching pin) |mprj_io[19]
(no matching pin) |mprj_io[18]
(no matching pin) |mprj_io[17]
(no matching pin) |mprj_io[16]
(no matching pin) |mprj_io[15]
(no matching pin) |mprj_io[14]
(no matching pin) |mprj_io[13]
(no matching pin) |mprj_io[12]
(no matching pin) |mprj_io[11]
(no matching pin) |mprj_io[10]
(no matching pin) |mprj_io[9]
(no matching pin) |mprj_io[8]
(no matching pin) |mprj_io[7]
(no matching pin) |mprj_io[6]
(no matching pin) |mprj_io[5]
(no matching pin) |mprj_io[4]
(no matching pin) |mprj_io[3]
(no matching pin) |mprj_io[2]
(no matching pin) |mprj_io[1]
(no matching pin) |mprj_io[0]
(no matching pin) |resetb
(no matching pin) |vccd
(no matching pin) |vccd1
(no matching pin) |vccd2
(no matching pin) |vdda
(no matching pin) |vdda1
(no matching pin) |vdda1_2
(no matching pin) |vdda2
(no matching pin) |vddio
(no matching pin) |vddio_2
(no matching pin) |vssa
(no matching pin) |vssa1
(no matching pin) |vssa1_2
(no matching pin) |vssa2
(no matching pin) |vssd
(no matching pin) |vssd1
(no matching pin) |vssd2
(no matching pin) |vssio
(no matching pin) |vssio_2
clock |(no matching pin)
flash_clk |(no matching pin)
flash_csb |(no matching pin)
flash_io0 |(no matching pin)
flash_io1 |(no matching pin)
gpio |(no matching pin)
mprj_io[0] |(no matching pin)
mprj_io[10] |(no matching pin)
mprj_io[11] |(no matching pin)
mprj_io[12] |(no matching pin)
mprj_io[13] |(no matching pin)
mprj_io[14] |(no matching pin)
mprj_io[15] |(no matching pin)
mprj_io[16] |(no matching pin)
mprj_io[17] |(no matching pin)
mprj_io[18] |(no matching pin)
mprj_io[19] |(no matching pin)
mprj_io[1] |(no matching pin)
mprj_io[20] |(no matching pin)
mprj_io[21] |(no matching pin)
mprj_io[22] |(no matching pin)
mprj_io[23] |(no matching pin)
mprj_io[24] |(no matching pin)
mprj_io[25] |(no matching pin)
mprj_io[26] |(no matching pin)
mprj_io[27] |(no matching pin)
mprj_io[28] |(no matching pin)
mprj_io[29] |(no matching pin)
mprj_io[2] |(no matching pin)
mprj_io[30] |(no matching pin)
mprj_io[31] |(no matching pin)
mprj_io[32] |(no matching pin)
mprj_io[33] |(no matching pin)
mprj_io[34] |(no matching pin)
mprj_io[35] |(no matching pin)
mprj_io[36] |(no matching pin)
mprj_io[37] |(no matching pin)
mprj_io[3] |(no matching pin)
mprj_io[4] |(no matching pin)
mprj_io[5] |(no matching pin)
mprj_io[6] |(no matching pin)
mprj_io[7] |(no matching pin)
mprj_io[8] |(no matching pin)
mprj_io[9] |(no matching pin)
resetb |(no matching pin)
vccd |(no matching pin)
vccd1 |(no matching pin)
vccd2 |(no matching pin)
vdda |(no matching pin)
vdda1 |(no matching pin)
vdda1_2 |(no matching pin)
vdda2 |(no matching pin)
vddio |(no matching pin)
vddio_2 |(no matching pin)
vssa |(no matching pin)
vssa1 |(no matching pin)
vssa1_2 |(no matching pin)
vssa2 |(no matching pin)
vssd |(no matching pin)
vssd1 |(no matching pin)
vssd2 |(no matching pin)
vssio |(no matching pin)
vssio_2 |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists for caravan and caravan altered to match.
Device classes caravan and caravan are equivalent.
Final result: Top level cell failed pin matching.
The following cells had property errors:
mgmt_protect
Warning: device level LVS may be incomplete due to 5 unflattened cell(s): see /home/passant/caravel/signoff/caravan/standalone_pvr/caravan.unflattened