riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/signoff/digital_pll/openlane-signoff/18-rcx_mcsta.max.log

6497 lines
378 KiB
Plaintext
Raw Normal View History

reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/results/routing/digital_pll.odb
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
min_report
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.68 0.68 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.07 0.00 0.68 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
-----------------------------------------------------------------------------
0.20 data required time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.68 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.22 0.82 0.83 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.03 pll_control.oscbuf[1] (net)
0.22 0.00 0.83 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.10 0.16 library hold time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.16 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.67 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.72 0.72 ^ _445_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.01 pll_control.prep[0] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.72 ^ _337_/A (sky130_fd_sc_hd__or2_2)
0.06 0.19 0.91 ^ _337_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _152_ (net)
0.06 0.00 0.91 ^ _338_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.07 ^ _338_/X (sky130_fd_sc_hd__buf_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.05 0.00 1.07 ^ _445_/D (sky130_fd_sc_hd__dfrtp_2)
1.07 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
-----------------------------------------------------------------------------
0.20 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.07 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.87 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.19 0.80 0.80 ^ _453_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tval[0] (net)
0.19 0.00 0.80 ^ _320_/A1 (sky130_fd_sc_hd__o21a_2)
0.06 0.28 1.08 ^ _320_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.06 0.00 1.08 ^ _453_/D (sky130_fd_sc_hd__dfrtp_2)
1.08 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
-----------------------------------------------------------------------------
0.20 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.08 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.89 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.21 0.82 0.82 ^ _452_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[4] (net)
0.21 0.00 0.82 ^ _323_/A1 (sky130_fd_sc_hd__o21a_2)
0.05 0.28 1.10 ^ _323_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.05 0.00 1.10 ^ _452_/D (sky130_fd_sc_hd__dfrtp_2)
1.10 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.10 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.91 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.69 0.70 ^ _447_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.prep[2] (net)
0.08 0.00 0.70 ^ _333_/A1 (sky130_fd_sc_hd__mux2_2)
0.07 0.26 0.96 ^ _333_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _150_ (net)
0.07 0.00 0.96 ^ _334_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.12 ^ _334_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.05 0.00 1.12 ^ _447_/D (sky130_fd_sc_hd__dfrtp_2)
1.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.12 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.92 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.77 0.78 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tint[1] (net)
0.17 0.00 0.78 ^ _308_/A (sky130_fd_sc_hd__inv_2)
0.11 0.16 0.93 v _308_/Y (sky130_fd_sc_hd__inv_2)
4 0.02 _134_ (net)
0.11 0.00 0.94 v _312_/A (sky130_fd_sc_hd__xnor2_2)
0.06 0.22 1.16 ^ _312_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.06 0.00 1.16 ^ _456_/D (sky130_fd_sc_hd__dfrtp_2)
1.16 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.19 library hold time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.16 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.97 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.73 0.74 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[4] (net)
0.12 0.00 0.74 ^ _211_/A1 (sky130_fd_sc_hd__mux2_2)
0.07 0.27 1.01 ^ _211_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _045_ (net)
0.07 0.00 1.01 ^ _212_/A (sky130_fd_sc_hd__buf_2)
0.04 0.16 1.17 ^ _212_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.04 0.00 1.17 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.97 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _446_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.72 0.72 ^ _445_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.10 0.00 0.72 ^ _335_/A1 (sky130_fd_sc_hd__mux2_2)
0.07 0.28 1.00 ^ _335_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _151_ (net)
0.07 0.00 1.00 ^ _336_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.17 ^ _336_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.05 0.00 1.17 ^ _446_/D (sky130_fd_sc_hd__dfrtp_2)
1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _446_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.97 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.78 0.78 ^ _451_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.count0[3] (net)
0.17 0.00 0.78 ^ _325_/A1 (sky130_fd_sc_hd__o211a_2)
0.07 0.38 1.17 ^ _325_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.07 0.00 1.17 ^ _451_/D (sky130_fd_sc_hd__dfrtp_2)
1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.06 0.19 library hold time
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.19 data required time
-1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.98 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.21 0.82 0.82 ^ _452_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[4] (net)
0.21 0.00 0.82 ^ _326_/A (sky130_fd_sc_hd__nand2_2)
0.16 0.22 1.04 v _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.16 0.00 1.04 v _332_/C (sky130_fd_sc_hd__nand3_2)
0.07 0.14 1.17 ^ _332_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.07 0.00 1.17 ^ _448_/D (sky130_fd_sc_hd__dfrtp_2)
1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.17 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.98 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.74 0.75 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[3] (net)
0.13 0.00 0.75 ^ _213_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.27 1.02 ^ _213_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.06 0.00 1.02 ^ _214_/A (sky130_fd_sc_hd__buf_2)
0.04 0.15 1.18 ^ _214_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.04 0.00 1.18 ^ _466_/D (sky130_fd_sc_hd__dfrtp_2)
1.18 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.06 0.20 library hold time
0.20 data required time
-----------------------------------------------------------------------------
0.20 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.18 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.98 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.76 0.76 ^ _454_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.tval[1] (net)
0.15 0.00 0.76 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.06 0.28 1.04 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _141_ (net)
0.06 0.00 1.04 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.04 0.15 1.19 ^ _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.04 0.00 1.19 ^ _454_/D (sky130_fd_sc_hd__dfrtp_2)
1.19 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.19 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.99 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 0.81 0.81 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[0] (net)
0.20 0.00 0.81 ^ _314_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.08 0.37 1.19 ^ _314_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.08 0.00 1.19 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
1.19 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.07 0.19 library hold time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.19 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.19 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.00 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.14 0.75 0.76 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[2] (net)
0.14 0.00 0.76 ^ _215_/A1 (sky130_fd_sc_hd__mux2_2)
0.07 0.28 1.04 ^ _215_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.07 0.00 1.04 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.04 0.15 1.20 ^ _216_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.04 0.00 1.20 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
-----------------------------------------------------------------------------
0.20 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.20 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.00 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.15 0.76 0.77 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.15 0.00 0.77 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.06 0.28 1.05 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.06 0.00 1.05 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.05 0.16 1.21 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.05 0.00 1.21 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.00 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.14 0.75 0.76 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[0] (net)
0.14 0.00 0.76 ^ _220_/A1 (sky130_fd_sc_hd__mux2_2)
0.08 0.29 1.05 ^ _220_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _050_ (net)
0.08 0.00 1.05 ^ _221_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.22 ^ _221_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _038_ (net)
0.05 0.00 1.22 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
1.22 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.22 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.02 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _450_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.18 0.79 0.80 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.02 pll_control.oscbuf[2] (net)
0.18 0.00 0.80 ^ _276_/B (sky130_fd_sc_hd__xor2_2)
0.13 0.25 1.05 v _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.13 0.00 1.05 v _329_/B1 (sky130_fd_sc_hd__a21oi_2)
0.13 0.18 1.23 ^ _329_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _028_ (net)
0.13 0.00 1.23 ^ _450_/D (sky130_fd_sc_hd__dfrtp_2)
1.23 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _450_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.08 0.18 library hold time
0.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.18 data required time
-1.23 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.05 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.18 0.79 0.80 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
2 0.02 pll_control.oscbuf[2] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.18 0.00 0.80 ^ _276_/B (sky130_fd_sc_hd__xor2_2)
0.13 0.25 1.05 v _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.13 0.00 1.05 v _331_/B1 (sky130_fd_sc_hd__a21oi_2)
0.13 0.19 1.24 ^ _331_/Y (sky130_fd_sc_hd__a21oi_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _027_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.13 0.00 1.24 ^ _449_/D (sky130_fd_sc_hd__dfrtp_2)
1.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.08 0.18 library hold time
0.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.18 data required time
-1.24 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.06 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 0.78 0.78 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[4] (net)
0.17 0.00 0.79 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.31 0.40 1.18 ^ _222_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _051_ (net)
0.31 0.00 1.18 ^ _300_/A1 (sky130_fd_sc_hd__o22a_2)
0.05 0.36 1.54 ^ _300_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.05 0.00 1.54 ^ _459_/D (sky130_fd_sc_hd__dfrtp_2)
1.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.34 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.71 0.72 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[2] (net)
0.10 0.00 0.72 ^ _266_/A (sky130_fd_sc_hd__buf_2)
0.27 0.33 1.05 ^ _266_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _095_ (net)
0.27 0.00 1.05 ^ _306_/A0 (sky130_fd_sc_hd__mux2_2)
0.08 0.35 1.40 ^ _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.08 0.00 1.40 ^ _307_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.57 ^ _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.05 0.00 1.57 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
1.57 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.57 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.71 0.72 ^ _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[3] (net)
0.10 0.00 0.72 ^ _223_/A (sky130_fd_sc_hd__buf_2)
0.29 0.35 1.07 ^ _223_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _052_ (net)
0.29 0.00 1.07 ^ _303_/A0 (sky130_fd_sc_hd__mux2_2)
0.08 0.35 1.42 ^ _303_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _131_ (net)
0.08 0.00 1.42 ^ _304_/A (sky130_fd_sc_hd__buf_2)
0.05 0.17 1.59 ^ _304_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.05 0.00 1.59 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
1.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 0.20 library hold time
0.20 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.20 data required time
-1.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
1.39 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.33 0.34 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.04 0.00 0.34 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.03 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.23 data required time
-0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
0.11 slack (MET)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.42 0.43 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.03 pll_control.oscbuf[1] (net)
0.13 0.00 0.43 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.05 0.21 library hold time
0.21 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.21 data required time
-0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.21 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.40 0.41 ^ _453_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tval[0] (net)
0.11 0.00 0.41 ^ _320_/A1 (sky130_fd_sc_hd__o21a_2)
0.03 0.13 0.54 ^ _320_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.03 0.00 0.54 ^ _453_/D (sky130_fd_sc_hd__dfrtp_2)
0.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
-0.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.31 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.36 0.36 ^ _445_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.06 0.00 0.36 ^ _337_/A (sky130_fd_sc_hd__or2_2)
0.04 0.10 0.47 ^ _337_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _152_ (net)
0.04 0.00 0.47 ^ _338_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.55 ^ _338_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _023_ (net)
0.03 0.00 0.55 ^ _445_/D (sky130_fd_sc_hd__dfrtp_2)
0.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.32 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.41 0.42 ^ _452_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[4] (net)
0.13 0.00 0.42 ^ _323_/A1 (sky130_fd_sc_hd__o21a_2)
0.03 0.13 0.55 ^ _323_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.03 0.00 0.55 ^ _452_/D (sky130_fd_sc_hd__dfrtp_2)
0.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.32 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.34 0.35 ^ _447_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.prep[2] (net)
0.05 0.00 0.35 ^ _333_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.13 0.48 ^ _333_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _150_ (net)
0.04 0.00 0.48 ^ _334_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.56 ^ _334_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.03 0.00 0.56 ^ _447_/D (sky130_fd_sc_hd__dfrtp_2)
0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.33 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.40 ^ _451_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.count0[3] (net)
0.10 0.00 0.40 ^ _325_/A1 (sky130_fd_sc_hd__o211a_2)
0.04 0.17 0.56 ^ _325_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.04 0.00 0.56 ^ _451_/D (sky130_fd_sc_hd__dfrtp_2)
0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.03 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
-0.56 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.34 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.37 0.37 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[4] (net)
0.07 0.00 0.37 ^ _211_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.13 0.51 ^ _211_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _045_ (net)
0.04 0.00 0.51 ^ _212_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.59 ^ _212_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.03 0.00 0.59 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _446_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.36 0.36 ^ _445_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.06 0.00 0.36 ^ _335_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.14 0.50 ^ _335_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _151_ (net)
0.04 0.00 0.50 ^ _336_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.59 ^ _336_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.03 0.00 0.59 ^ _446_/D (sky130_fd_sc_hd__dfrtp_2)
0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _446_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.13 0.41 0.42 ^ _452_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[4] (net)
0.13 0.00 0.42 ^ _326_/A (sky130_fd_sc_hd__nand2_2)
0.08 0.10 0.52 v _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.08 0.00 0.52 v _332_/C (sky130_fd_sc_hd__nand3_2)
0.04 0.07 0.60 ^ _332_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.04 0.00 0.60 ^ _448_/D (sky130_fd_sc_hd__dfrtp_2)
0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.37 0.38 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[3] (net)
0.08 0.00 0.38 ^ _213_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.13 0.51 ^ _213_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.03 0.00 0.51 ^ _214_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.59 ^ _214_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.03 0.00 0.59 ^ _466_/D (sky130_fd_sc_hd__dfrtp_2)
0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.59 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.39 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tint[1] (net)
0.10 0.00 0.39 ^ _308_/A (sky130_fd_sc_hd__inv_2)
0.06 0.08 0.47 v _308_/Y (sky130_fd_sc_hd__inv_2)
4 0.02 _134_ (net)
0.06 0.00 0.47 v _312_/A (sky130_fd_sc_hd__xnor2_2)
0.03 0.12 0.60 v _312_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.03 0.00 0.60 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
-0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.39 ^ _454_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.tval[1] (net)
0.09 0.00 0.39 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.14 0.52 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _141_ (net)
0.03 0.00 0.52 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.61 ^ _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.03 0.00 0.61 ^ _454_/D (sky130_fd_sc_hd__dfrtp_2)
0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.41 0.41 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[0] (net)
0.12 0.00 0.41 ^ _314_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.05 0.18 0.60 ^ _314_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.05 0.00 0.60 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.03 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.60 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.38 0.38 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[2] (net)
0.08 0.00 0.39 ^ _215_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.14 0.52 ^ _215_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.04 0.00 0.52 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.61 ^ _216_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.03 0.00 0.61 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.38 0.39 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.09 0.00 0.39 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.14 0.53 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.03 0.00 0.53 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.03 0.08 0.61 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.03 0.00 0.61 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.61 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.38 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _450_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.44 0.44 v _452_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[4] (net)
0.09 0.00 0.44 v _326_/A (sky130_fd_sc_hd__nand2_2)
0.11 0.12 0.56 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.11 0.00 0.56 ^ _329_/A1 (sky130_fd_sc_hd__a21oi_2)
0.03 0.06 0.62 v _329_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _028_ (net)
0.03 0.00 0.62 v _450_/D (sky130_fd_sc_hd__dfrtp_2)
0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _450_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.23 library hold time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.39 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.44 0.44 v _452_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.02 pll_control.count0[4] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.44 v _326_/A (sky130_fd_sc_hd__nand2_2)
0.11 0.12 0.56 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.11 0.00 0.56 ^ _331_/A1 (sky130_fd_sc_hd__a21oi_2)
0.03 0.06 0.62 v _331_/Y (sky130_fd_sc_hd__a21oi_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _027_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.03 0.00 0.62 v _449_/D (sky130_fd_sc_hd__dfrtp_2)
0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.39 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.38 0.39 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[0] (net)
0.08 0.00 0.39 ^ _220_/A1 (sky130_fd_sc_hd__mux2_2)
0.04 0.15 0.53 ^ _220_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _050_ (net)
0.04 0.00 0.53 ^ _221_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.62 ^ _221_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _038_ (net)
0.03 0.00 0.62 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.23 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.39 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.39 0.40 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[4] (net)
0.10 0.00 0.40 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.20 0.22 0.62 ^ _222_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _051_ (net)
0.20 0.00 0.63 ^ _300_/A1 (sky130_fd_sc_hd__o22a_2)
0.03 0.17 0.79 ^ _300_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.03 0.00 0.79 ^ _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.56 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.35 0.36 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[2] (net)
0.06 0.00 0.36 ^ _266_/A (sky130_fd_sc_hd__buf_2)
0.17 0.19 0.55 ^ _266_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _095_ (net)
0.17 0.00 0.55 ^ _306_/A0 (sky130_fd_sc_hd__mux2_2)
0.05 0.18 0.73 ^ _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.05 0.00 0.73 ^ _307_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.82 ^ _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.03 0.00 0.82 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
0.82 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.82 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.58 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.35 0.36 ^ _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[3] (net)
0.06 0.00 0.36 ^ _223_/A (sky130_fd_sc_hd__buf_2)
0.18 0.20 0.56 ^ _223_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _052_ (net)
0.18 0.00 0.56 ^ _303_/A0 (sky130_fd_sc_hd__mux2_2)
0.04 0.18 0.74 ^ _303_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _131_ (net)
0.04 0.00 0.74 ^ _304_/A (sky130_fd_sc_hd__buf_2)
0.03 0.09 0.83 ^ _304_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.03 0.00 0.83 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.59 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.21 0.22 ^ _460_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.03 0.00 0.22 ^ _461_/D (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.22 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
-0.22 data arrival time
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.27 0.28 ^ _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.03 pll_control.oscbuf[1] (net)
0.10 0.00 0.28 ^ _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.28 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.04 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.26 0.26 ^ _453_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tval[0] (net)
0.08 0.00 0.26 ^ _320_/A1 (sky130_fd_sc_hd__o21a_2)
0.02 0.08 0.34 ^ _320_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.02 0.00 0.34 ^ _453_/D (sky130_fd_sc_hd__dfrtp_2)
0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.22 0.23 ^ _445_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.04 0.00 0.23 ^ _337_/A (sky130_fd_sc_hd__or2_2)
0.03 0.07 0.30 ^ _337_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _152_ (net)
0.03 0.00 0.30 ^ _338_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.35 ^ _338_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _023_ (net)
0.02 0.00 0.36 ^ _445_/D (sky130_fd_sc_hd__dfrtp_2)
0.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.27 0.27 ^ _452_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[4] (net)
0.10 0.00 0.27 ^ _323_/A1 (sky130_fd_sc_hd__o21a_2)
0.02 0.08 0.35 ^ _323_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.02 0.00 0.35 ^ _452_/D (sky130_fd_sc_hd__dfrtp_2)
0.35 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.35 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.12 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.25 ^ _451_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.count0[3] (net)
0.07 0.00 0.26 ^ _325_/A1 (sky130_fd_sc_hd__o211a_2)
0.02 0.10 0.35 ^ _325_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.02 0.00 0.35 ^ _451_/D (sky130_fd_sc_hd__dfrtp_2)
0.35 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.35 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.12 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.21 0.22 ^ _447_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.prep[2] (net)
0.03 0.00 0.22 ^ _333_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.08 0.30 ^ _333_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _150_ (net)
0.03 0.00 0.30 ^ _334_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.36 ^ _334_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 0.36 ^ _447_/D (sky130_fd_sc_hd__dfrtp_2)
0.36 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.36 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.12 slack (MET)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.23 0.24 ^ _467_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[4] (net)
0.05 0.00 0.24 ^ _211_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.08 0.32 ^ _211_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _045_ (net)
0.02 0.00 0.32 ^ _212_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.37 ^ _212_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.02 0.00 0.37 ^ _467_/D (sky130_fd_sc_hd__dfrtp_2)
0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.37 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _446_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.22 0.23 ^ _445_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.04 0.00 0.23 ^ _335_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.09 0.32 ^ _335_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _151_ (net)
0.03 0.00 0.32 ^ _336_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.38 ^ _336_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.02 0.00 0.38 ^ _446_/D (sky130_fd_sc_hd__dfrtp_2)
0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _446_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.27 0.27 ^ _452_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.02 pll_control.count0[4] (net)
0.10 0.00 0.27 ^ _326_/A (sky130_fd_sc_hd__nand2_2)
0.05 0.06 0.33 v _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.05 0.00 0.33 v _332_/C (sky130_fd_sc_hd__nand3_2)
0.03 0.05 0.38 ^ _332_/Y (sky130_fd_sc_hd__nand3_2)
1 0.00 _026_ (net)
0.03 0.00 0.38 ^ _448_/D (sky130_fd_sc_hd__dfrtp_2)
0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.24 ^ _466_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[3] (net)
0.06 0.00 0.24 ^ _213_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.08 0.33 ^ _213_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.02 0.00 0.33 ^ _214_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.38 ^ _214_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.02 0.00 0.38 ^ _466_/D (sky130_fd_sc_hd__dfrtp_2)
0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.26 0.27 ^ _455_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[0] (net)
0.09 0.00 0.27 ^ _314_/B1 (sky130_fd_sc_hd__o2bb2a_2)
0.03 0.11 0.38 ^ _314_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.01 _033_ (net)
0.03 0.00 0.38 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _454_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.tval[1] (net)
0.06 0.00 0.25 ^ _317_/A0 (sky130_fd_sc_hd__mux2_2)
0.02 0.09 0.34 ^ _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _141_ (net)
0.02 0.00 0.34 ^ _318_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.39 ^ _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 0.39 ^ _454_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _465_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[2] (net)
0.06 0.00 0.25 ^ _215_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.09 0.33 ^ _215_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.02 0.00 0.33 ^ _216_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.39 ^ _216_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 0.39 ^ _465_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _464_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.count1[1] (net)
0.06 0.00 0.25 ^ _217_/A1 (sky130_fd_sc_hd__mux2_2)
0.02 0.09 0.34 ^ _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.02 0.00 0.34 ^ _218_/A (sky130_fd_sc_hd__buf_2)
0.02 0.05 0.39 ^ _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.02 0.00 0.39 ^ _464_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _450_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.25 0.26 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
2 0.02 pll_control.oscbuf[2] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.26 ^ _276_/B (sky130_fd_sc_hd__xor2_2)
0.05 0.07 0.33 v _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.05 0.00 0.34 v _329_/B1 (sky130_fd_sc_hd__a21oi_2)
0.04 0.05 0.39 ^ _329_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _028_ (net)
0.04 0.00 0.39 ^ _450_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _450_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.25 0.26 ^ _462_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.02 pll_control.oscbuf[2] (net)
0.08 0.00 0.26 ^ _276_/B (sky130_fd_sc_hd__xor2_2)
0.05 0.07 0.33 v _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.05 0.00 0.34 v _331_/B1 (sky130_fd_sc_hd__a21oi_2)
0.05 0.05 0.39 ^ _331_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _027_ (net)
0.05 0.00 0.39 ^ _449_/D (sky130_fd_sc_hd__dfrtp_2)
0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.25 ^ _456_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.02 pll_control.tint[1] (net)
0.07 0.00 0.25 ^ _308_/A (sky130_fd_sc_hd__inv_2)
0.05 0.05 0.30 v _308_/Y (sky130_fd_sc_hd__inv_2)
4 0.02 _134_ (net)
0.05 0.00 0.30 v _312_/A (sky130_fd_sc_hd__xnor2_2)
0.02 0.08 0.38 v _312_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.02 0.00 0.38 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 0.00 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.23 data required time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.38 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.24 0.25 ^ _463_/Q (sky130_fd_sc_hd__dfrtp_2)
4 0.01 pll_control.count1[0] (net)
0.06 0.00 0.25 ^ _220_/A1 (sky130_fd_sc_hd__mux2_2)
0.03 0.09 0.34 ^ _220_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _050_ (net)
0.03 0.00 0.34 ^ _221_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.40 ^ _221_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _038_ (net)
0.02 0.00 0.40 ^ _463_/D (sky130_fd_sc_hd__dfrtp_2)
0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.16 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.25 0.26 ^ _459_/Q (sky130_fd_sc_hd__dfrtp_2)
5 0.02 pll_control.tint[4] (net)
0.07 0.00 0.26 ^ _222_/A (sky130_fd_sc_hd__buf_2)
0.15 0.15 0.41 ^ _222_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _051_ (net)
0.15 0.00 0.41 ^ _300_/A1 (sky130_fd_sc_hd__o22a_2)
0.02 0.09 0.50 ^ _300_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.02 0.00 0.50 ^ _459_/D (sky130_fd_sc_hd__dfrtp_2)
0.50 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.50 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.26 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.22 0.23 ^ _457_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[2] (net)
0.04 0.00 0.23 ^ _266_/A (sky130_fd_sc_hd__buf_2)
0.13 0.13 0.36 ^ _266_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _095_ (net)
0.13 0.00 0.36 ^ _306_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.11 0.47 ^ _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.01 _133_ (net)
0.03 0.00 0.47 ^ _307_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.53 ^ _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.02 0.00 0.53 ^ _457_/D (sky130_fd_sc_hd__dfrtp_2)
0.53 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.24 data required time
-0.53 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.29 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.22 0.23 ^ _458_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.tint[3] (net)
0.04 0.00 0.23 ^ _223_/A (sky130_fd_sc_hd__buf_2)
0.14 0.14 0.37 ^ _223_/X (sky130_fd_sc_hd__buf_2)
7 0.04 _052_ (net)
0.14 0.00 0.37 ^ _303_/A0 (sky130_fd_sc_hd__mux2_2)
0.03 0.11 0.48 ^ _303_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _131_ (net)
0.03 0.00 0.48 ^ _304_/A (sky130_fd_sc_hd__buf_2)
0.02 0.06 0.54 ^ _304_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 0.54 ^ _458_/D (sky130_fd_sc_hd__dfrtp_2)
0.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.25 0.26 clock uncertainty
0.00 0.26 clock reconvergence pessimism
-0.02 0.24 library hold time
0.24 data required time
-----------------------------------------------------------------------------
0.24 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.30 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
min_report_end
max_report
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _306_/S (sky130_fd_sc_hd__mux2_2)
0.10 0.63 7.85 v _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.10 0.00 7.85 v _307_/A (sky130_fd_sc_hd__buf_2)
0.05 0.26 8.11 v _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.05 0.00 8.11 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
8.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-8.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.93 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _303_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.62 7.85 v _303_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _131_ (net)
0.09 0.00 7.85 v _304_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 8.10 v _304_/X (sky130_fd_sc_hd__buf_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
1 0.00 _036_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.05 0.00 8.10 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
8.10 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-8.10 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.92 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _317_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.59 7.82 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _141_ (net)
0.08 0.00 7.82 v _318_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 8.06 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.04 0.00 8.06 v _454_/D (sky130_fd_sc_hd__dfrtp_2)
8.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
-----------------------------------------------------------------------------
6.18 data required time
-8.06 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.88 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _300_/A2 (sky130_fd_sc_hd__o22a_2)
0.07 0.44 7.67 v _300_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.07 0.00 7.67 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
7.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
-7.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.50 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _314_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.09 0.55 7.77 ^ _314_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.09 0.00 7.78 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
7.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.13 6.29 library setup time
6.29 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.29 data required time
-7.78 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.48 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _319_/B (sky130_fd_sc_hd__nand2_2)
0.07 0.14 7.37 ^ _319_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _142_ (net)
0.07 0.00 7.37 ^ _320_/B1 (sky130_fd_sc_hd__o21a_2)
0.06 0.25 7.62 ^ _320_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _031_ (net)
0.06 0.00 7.62 ^ _453_/D (sky130_fd_sc_hd__dfrtp_2)
7.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.12 6.30 library setup time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.30 data required time
-----------------------------------------------------------------------------
6.30 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-7.62 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.32 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _311_/C1 (sky130_fd_sc_hd__o211a_2)
0.11 0.28 7.14 v _311_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _137_ (net)
0.11 0.00 7.14 v _312_/B (sky130_fd_sc_hd__xnor2_2)
0.08 0.25 7.39 v _312_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.08 0.00 7.39 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
7.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.26 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.16 data required time
-7.39 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.23 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.17 0.00 1.02 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.39 0.47 1.49 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.39 0.00 1.49 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.27 0.50 1.99 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.27 0.00 1.99 ^ _211_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 2.76 v _211_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _045_ (net)
0.09 0.00 2.76 v _212_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 3.00 v _212_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.04 0.00 3.00 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.17 0.00 1.02 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.39 0.47 1.49 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.39 0.00 1.49 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.27 0.50 1.99 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.27 0.00 1.99 ^ _215_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.77 2.76 v _215_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.09 0.00 2.76 v _216_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 3.00 v _216_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.04 0.00 3.00 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.17 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.17 0.00 1.02 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.39 0.47 1.49 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.39 0.00 1.49 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.27 0.50 1.99 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.27 0.00 1.99 ^ _213_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.77 2.76 v _213_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.08 0.00 2.76 v _214_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 3.00 v _214_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.04 0.00 3.00 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.18 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.17 0.00 1.02 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.39 0.47 1.49 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.39 0.00 1.49 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.27 0.50 1.99 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.27 0.00 1.99 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.08 0.77 2.76 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.08 0.00 2.76 v _218_/A (sky130_fd_sc_hd__buf_2)
0.04 0.24 3.00 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.04 0.00 3.00 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-3.00 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.19 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.77 0.78 ^ _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.08 0.00 0.78 ^ _219_/A (sky130_fd_sc_hd__buf_2)
0.27 0.36 1.14 ^ _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.27 0.00 1.14 ^ _321_/C (sky130_fd_sc_hd__and3_2)
0.12 0.50 1.64 ^ _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.12 0.00 1.64 ^ _322_/B (sky130_fd_sc_hd__and2_2)
0.12 0.36 2.00 ^ _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.12 0.00 2.00 ^ _324_/B_N (sky130_fd_sc_hd__or2b_2)
0.11 0.71 2.70 v _324_/X (sky130_fd_sc_hd__or2b_2)
1 0.00 _145_ (net)
0.11 0.00 2.70 v _325_/B1 (sky130_fd_sc_hd__o211a_2)
0.07 0.26 2.96 v _325_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.07 0.00 2.96 v _451_/D (sky130_fd_sc_hd__dfrtp_2)
2.96 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
-2.96 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.20 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _450_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.89 0.90 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.08 0.00 0.90 v _219_/A (sky130_fd_sc_hd__buf_2)
0.16 0.36 1.26 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.16 0.00 1.26 v _321_/C (sky130_fd_sc_hd__and3_2)
0.10 0.54 1.80 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.10 0.00 1.80 v _328_/A (sky130_fd_sc_hd__or2_2)
0.13 0.74 2.53 v _328_/X (sky130_fd_sc_hd__or2_2)
1 0.01 _148_ (net)
0.13 0.00 2.54 v _329_/A2 (sky130_fd_sc_hd__a21oi_2)
0.15 0.25 2.79 ^ _329_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _028_ (net)
0.15 0.00 2.79 ^ _450_/D (sky130_fd_sc_hd__dfrtp_2)
2.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _450_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.14 6.28 library setup time
6.28 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.28 data required time
-2.79 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.89 0.90 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.08 0.00 0.90 v _219_/A (sky130_fd_sc_hd__buf_2)
0.16 0.36 1.26 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.16 0.00 1.26 v _321_/C (sky130_fd_sc_hd__and3_2)
0.10 0.54 1.80 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.10 0.00 1.80 v _322_/B (sky130_fd_sc_hd__and2_2)
0.10 0.47 2.27 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.10 0.00 2.27 v _326_/B (sky130_fd_sc_hd__nand2_2)
0.18 0.21 2.48 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.18 0.00 2.48 ^ _332_/C (sky130_fd_sc_hd__nand3_2)
0.11 0.18 2.66 v _332_/Y (sky130_fd_sc_hd__nand3_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _026_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 2.66 v _448_/D (sky130_fd_sc_hd__dfrtp_2)
2.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.27 6.16 library setup time
6.16 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.16 data required time
-2.66 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _446_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.oscbuf[1] (net)
0.17 0.00 1.02 v _276_/A (sky130_fd_sc_hd__xor2_2)
0.47 0.54 1.56 ^ _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.47 0.00 1.56 ^ _335_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.85 2.41 v _335_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _151_ (net)
0.09 0.00 2.41 v _336_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 2.67 v _336_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.05 0.00 2.67 v _446_/D (sky130_fd_sc_hd__dfrtp_2)
2.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _446_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-2.67 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.51 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.89 0.90 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.08 0.00 0.90 v _219_/A (sky130_fd_sc_hd__buf_2)
0.16 0.36 1.26 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.16 0.00 1.26 v _321_/C (sky130_fd_sc_hd__and3_2)
0.10 0.54 1.80 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.10 0.00 1.80 v _322_/B (sky130_fd_sc_hd__and2_2)
0.10 0.47 2.27 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.10 0.00 2.27 v _323_/A2 (sky130_fd_sc_hd__o21a_2)
0.06 0.38 2.65 v _323_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.06 0.00 2.65 v _452_/D (sky130_fd_sc_hd__dfrtp_2)
2.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.25 6.17 library setup time
6.17 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.17 data required time
-2.65 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.52 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.89 0.90 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.08 0.00 0.90 v _219_/A (sky130_fd_sc_hd__buf_2)
0.16 0.36 1.26 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.16 0.00 1.26 v _321_/C (sky130_fd_sc_hd__and3_2)
0.10 0.54 1.80 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.10 0.00 1.80 v _322_/B (sky130_fd_sc_hd__and2_2)
0.10 0.47 2.27 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.10 0.00 2.27 v _326_/B (sky130_fd_sc_hd__nand2_2)
0.18 0.21 2.48 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.18 0.00 2.48 ^ _331_/A1 (sky130_fd_sc_hd__a21oi_2)
0.11 0.15 2.63 v _331_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _027_ (net)
0.11 0.00 2.63 v _449_/D (sky130_fd_sc_hd__dfrtp_2)
2.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.27 6.15 library setup time
6.15 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.15 data required time
-2.63 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.52 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.oscbuf[1] (net)
0.17 0.00 1.02 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.39 0.47 1.49 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.39 0.00 1.49 ^ _220_/S (sky130_fd_sc_hd__mux2_2)
0.10 0.83 2.32 v _220_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _050_ (net)
0.10 0.00 2.32 v _221_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 2.57 v _221_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _038_ (net)
0.05 0.00 2.57 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
2.57 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.25 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-2.57 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.61 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.17 0.00 1.02 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.39 0.47 1.49 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.39 0.00 1.49 ^ _333_/S (sky130_fd_sc_hd__mux2_2)
0.09 0.82 2.30 v _333_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _150_ (net)
0.09 0.00 2.30 v _334_/A (sky130_fd_sc_hd__buf_2)
0.05 0.25 2.55 v _334_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.05 0.00 2.55 v _447_/D (sky130_fd_sc_hd__dfrtp_2)
2.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-2.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.63 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.17 0.00 1.02 v _276_/A (sky130_fd_sc_hd__xor2_2)
0.22 0.44 1.46 v _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.22 0.00 1.46 v _337_/B (sky130_fd_sc_hd__or2_2)
0.12 0.72 2.18 v _337_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _152_ (net)
0.12 0.00 2.18 v _338_/A (sky130_fd_sc_hd__buf_2)
0.04 0.26 2.44 v _338_/X (sky130_fd_sc_hd__buf_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.04 0.00 2.44 v _445_/D (sky130_fd_sc_hd__dfrtp_2)
2.44 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.67 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-2.44 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.74 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.17 1.00 1.01 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.17 0.00 1.02 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
1.02 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.29 6.13 library setup time
6.13 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.13 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.02 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.07 0.87 0.88 v _460_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.07 0.00 0.88 v _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.26 6.17 library setup time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.17 data required time
-----------------------------------------------------------------------------
6.17 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.29 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _284_/A (sky130_fd_sc_hd__buf_2)
0.08 0.19 3.60 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.08 0.00 3.60 v _306_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.30 3.91 v _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.05 0.00 3.91 v _307_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 4.03 v _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.03 0.00 4.03 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
4.03 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-4.03 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.30 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _284_/A (sky130_fd_sc_hd__buf_2)
0.08 0.19 3.60 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.08 0.00 3.60 v _303_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.30 3.90 v _303_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _131_ (net)
0.05 0.00 3.90 v _304_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 4.03 v _304_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.03 0.00 4.03 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
4.03 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-4.03 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.30 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _284_/A (sky130_fd_sc_hd__buf_2)
0.08 0.19 3.60 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.08 0.00 3.60 v _317_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.29 3.89 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _141_ (net)
0.04 0.00 3.89 v _318_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 4.01 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 4.01 v _454_/D (sky130_fd_sc_hd__dfrtp_2)
4.01 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.67 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-4.01 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.32 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _284_/A (sky130_fd_sc_hd__buf_2)
0.08 0.19 3.60 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.08 0.00 3.60 v _314_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.05 0.28 3.88 ^ _314_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.00 _033_ (net)
0.05 0.00 3.88 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
3.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-3.88 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.48 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _284_/A (sky130_fd_sc_hd__buf_2)
0.08 0.19 3.60 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.08 0.00 3.60 v _300_/A2 (sky130_fd_sc_hd__o22a_2)
0.03 0.24 3.84 v _300_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.03 0.00 3.84 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
3.84 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.10 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-3.84 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.49 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _284_/A (sky130_fd_sc_hd__buf_2)
0.08 0.19 3.60 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.08 0.00 3.60 v _319_/B (sky130_fd_sc_hd__nand2_2)
0.04 0.08 3.68 ^ _319_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _142_ (net)
0.04 0.00 3.68 ^ _320_/B1 (sky130_fd_sc_hd__o21a_2)
0.03 0.12 3.81 ^ _320_/X (sky130_fd_sc_hd__o21a_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.03 0.00 3.81 ^ _453_/D (sky130_fd_sc_hd__dfrtp_2)
3.81 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.67 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.05 6.37 library setup time
6.37 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.37 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-3.81 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.56 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _311_/C1 (sky130_fd_sc_hd__o211a_2)
0.06 0.15 3.56 v _311_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _137_ (net)
0.06 0.00 3.56 v _312_/B (sky130_fd_sc_hd__xnor2_2)
0.04 0.13 3.70 v _312_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.04 0.00 3.70 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.10 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
-3.70 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.62 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.50 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.26 0.28 0.78 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.26 0.00 0.78 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.17 0.27 1.06 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.17 0.00 1.06 ^ _211_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 1.43 v _211_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _045_ (net)
0.05 0.00 1.43 v _212_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.55 v _212_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _042_ (net)
0.02 0.00 1.55 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
1.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 6.67 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.78 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.50 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.26 0.28 0.78 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.26 0.00 0.78 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.17 0.27 1.06 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.17 0.00 1.06 ^ _215_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.37 1.43 v _215_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.05 0.00 1.43 v _216_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.55 v _216_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 1.55 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
1.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 6.67 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.55 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.78 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.50 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.26 0.28 0.78 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.26 0.00 0.78 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.17 0.27 1.06 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.17 0.00 1.06 ^ _213_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.36 1.42 v _213_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.05 0.00 1.42 v _214_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.54 v _214_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.02 0.00 1.54 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
1.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.78 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.50 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.26 0.28 0.78 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.26 0.00 0.78 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.17 0.27 1.06 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.17 0.00 1.06 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.36 1.42 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.04 0.00 1.42 v _218_/A (sky130_fd_sc_hd__buf_2)
0.02 0.12 1.54 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.02 0.00 1.54 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
1.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.54 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.79 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.38 0.39 ^ _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.05 0.00 0.39 ^ _219_/A (sky130_fd_sc_hd__buf_2)
0.17 0.21 0.60 ^ _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.17 0.00 0.60 ^ _321_/C (sky130_fd_sc_hd__and3_2)
0.07 0.24 0.84 ^ _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.07 0.00 0.84 ^ _322_/B (sky130_fd_sc_hd__and2_2)
0.07 0.18 1.02 ^ _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.07 0.00 1.02 ^ _324_/B_N (sky130_fd_sc_hd__or2b_2)
0.05 0.31 1.32 v _324_/X (sky130_fd_sc_hd__or2b_2)
1 0.00 _145_ (net)
0.05 0.00 1.32 v _325_/B1 (sky130_fd_sc_hd__o211a_2)
0.04 0.13 1.46 v _325_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.04 0.00 1.46 v _451_/D (sky130_fd_sc_hd__dfrtp_2)
1.46 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 6.67 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.32 data required time
-----------------------------------------------------------------------------
6.32 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.46 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.86 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _446_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.50 v _276_/A (sky130_fd_sc_hd__xor2_2)
0.31 0.33 0.83 ^ _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.31 0.00 0.83 ^ _335_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.40 1.23 v _335_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _151_ (net)
0.05 0.00 1.23 v _336_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.36 v _336_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.03 0.00 1.36 v _446_/D (sky130_fd_sc_hd__dfrtp_2)
1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.67 ^ _446_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.36 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.97 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.43 0.44 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.04 0.00 0.44 v _219_/A (sky130_fd_sc_hd__buf_2)
0.09 0.18 0.62 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.09 0.00 0.62 v _321_/C (sky130_fd_sc_hd__and3_2)
0.05 0.25 0.88 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.05 0.00 0.88 v _322_/B (sky130_fd_sc_hd__and2_2)
0.05 0.22 1.10 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.05 0.00 1.10 v _326_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.22 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.11 0.00 1.22 ^ _332_/C (sky130_fd_sc_hd__nand3_2)
0.06 0.08 1.30 v _332_/Y (sky130_fd_sc_hd__nand3_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _026_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 1.30 v _448_/D (sky130_fd_sc_hd__dfrtp_2)
1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.11 6.32 library setup time
6.32 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.32 data required time
-1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.02 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _450_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.43 0.44 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.04 0.00 0.44 v _219_/A (sky130_fd_sc_hd__buf_2)
0.09 0.18 0.62 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.09 0.00 0.62 v _321_/C (sky130_fd_sc_hd__and3_2)
0.05 0.25 0.88 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.05 0.00 0.88 v _328_/A (sky130_fd_sc_hd__or2_2)
0.06 0.32 1.20 v _328_/X (sky130_fd_sc_hd__or2_2)
1 0.01 _148_ (net)
0.06 0.00 1.20 v _329_/A2 (sky130_fd_sc_hd__a21oi_2)
0.09 0.14 1.34 ^ _329_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _028_ (net)
0.09 0.00 1.34 ^ _450_/D (sky130_fd_sc_hd__dfrtp_2)
1.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.67 ^ _450_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.07 6.36 library setup time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.36 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.34 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.02 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.43 0.44 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.04 0.00 0.44 v _219_/A (sky130_fd_sc_hd__buf_2)
0.09 0.18 0.62 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.09 0.00 0.62 v _321_/C (sky130_fd_sc_hd__and3_2)
0.05 0.25 0.88 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.05 0.00 0.88 v _322_/B (sky130_fd_sc_hd__and2_2)
0.05 0.22 1.10 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.05 0.00 1.10 v _326_/B (sky130_fd_sc_hd__nand2_2)
0.11 0.12 1.22 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.11 0.00 1.22 ^ _331_/A1 (sky130_fd_sc_hd__a21oi_2)
0.07 0.07 1.29 v _331_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _027_ (net)
0.07 0.00 1.29 v _449_/D (sky130_fd_sc_hd__dfrtp_2)
1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.02 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.oscbuf[1] (net)
0.09 0.00 0.50 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.26 0.28 0.78 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.26 0.00 0.78 ^ _220_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.39 1.18 v _220_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _050_ (net)
0.05 0.00 1.18 v _221_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 1.30 v _221_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _038_ (net)
0.03 0.00 1.30 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.03 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.43 0.44 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.04 0.00 0.44 v _219_/A (sky130_fd_sc_hd__buf_2)
0.09 0.18 0.62 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.09 0.00 0.62 v _321_/C (sky130_fd_sc_hd__and3_2)
0.05 0.25 0.88 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.05 0.00 0.88 v _322_/B (sky130_fd_sc_hd__and2_2)
0.05 0.22 1.10 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.05 0.00 1.10 v _323_/A2 (sky130_fd_sc_hd__o21a_2)
0.03 0.20 1.30 v _323_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.03 0.00 1.30 v _452_/D (sky130_fd_sc_hd__dfrtp_2)
1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.00 6.67 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.32 data required time
-----------------------------------------------------------------------------
6.32 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.03 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.50 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.26 0.28 0.78 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.26 0.00 0.78 ^ _333_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.38 1.17 v _333_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _150_ (net)
0.05 0.00 1.17 v _334_/A (sky130_fd_sc_hd__buf_2)
0.03 0.12 1.29 v _334_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.03 0.00 1.29 v _447_/D (sky130_fd_sc_hd__dfrtp_2)
1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.67 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.29 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.04 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.09 0.00 0.50 v _276_/A (sky130_fd_sc_hd__xor2_2)
0.11 0.24 0.74 v _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.11 0.00 0.74 v _337_/B (sky130_fd_sc_hd__or2_2)
0.06 0.31 1.05 v _337_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _152_ (net)
0.06 0.00 1.05 v _338_/A (sky130_fd_sc_hd__buf_2)
0.02 0.13 1.18 v _338_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _023_ (net)
0.02 0.00 1.18 v _445_/D (sky130_fd_sc_hd__dfrtp_2)
1.18 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.67 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-1.18 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.15 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.09 0.49 0.50 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.oscbuf[1] (net)
0.09 0.00 0.50 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.50 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.12 6.30 library setup time
6.30 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.30 data required time
-0.50 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.81 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Corner: tt
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.42 0.43 v _460_/Q (sky130_fd_sc_hd__dfrtp_2)
1 0.00 pll_control.oscbuf[0] (net)
0.04 0.00 0.43 v _461_/D (sky130_fd_sc_hd__dfrtp_2)
0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.10 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-0.43 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.90 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
======================= Fastest Corner ===================================
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _284_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 2.16 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.06 0.00 2.16 v _306_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.18 2.34 v _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.04 0.00 2.34 v _307_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.42 v _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.02 0.00 2.42 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
2.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-2.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.94 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _458_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _284_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 2.16 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.06 0.00 2.16 v _303_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.18 2.34 v _303_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _131_ (net)
0.04 0.00 2.34 v _304_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.42 v _304_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _036_ (net)
0.02 0.00 2.42 v _458_/D (sky130_fd_sc_hd__dfrtp_2)
2.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _458_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-2.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.94 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _454_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _284_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 2.16 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.06 0.00 2.16 v _317_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.17 2.33 v _317_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _141_ (net)
0.03 0.00 2.33 v _318_/A (sky130_fd_sc_hd__buf_2)
0.02 0.07 2.40 v _318_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _032_ (net)
0.02 0.00 2.40 v _454_/D (sky130_fd_sc_hd__dfrtp_2)
2.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.67 ^ _454_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-2.40 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.96 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _284_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 2.16 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.06 0.00 2.16 v _300_/A2 (sky130_fd_sc_hd__o22a_2)
0.03 0.14 2.30 v _300_/X (sky130_fd_sc_hd__o22a_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _037_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.03 0.00 2.30 v _459_/D (sky130_fd_sc_hd__dfrtp_2)
2.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _459_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.07 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-2.30 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.06 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _455_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _284_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 2.16 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.06 0.00 2.16 v _314_/A1_N (sky130_fd_sc_hd__o2bb2a_2)
0.03 0.16 2.32 ^ _314_/X (sky130_fd_sc_hd__o2bb2a_2)
1 0.01 _033_ (net)
0.03 0.00 2.32 ^ _455_/D (sky130_fd_sc_hd__dfrtp_2)
2.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 6.67 ^ _455_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.03 6.39 library setup time
6.39 data required time
-----------------------------------------------------------------------------
6.39 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-2.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.07 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _453_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _284_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 2.16 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.06 0.00 2.16 v _319_/B (sky130_fd_sc_hd__nand2_2)
0.03 0.06 2.21 ^ _319_/Y (sky130_fd_sc_hd__nand2_2)
1 0.00 _142_ (net)
0.03 0.00 2.21 ^ _320_/B1 (sky130_fd_sc_hd__o21a_2)
0.02 0.06 2.27 ^ _320_/X (sky130_fd_sc_hd__o21a_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _031_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.02 0.00 2.27 ^ _453_/D (sky130_fd_sc_hd__dfrtp_2)
2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.67 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.03 6.39 library setup time
6.39 data required time
-----------------------------------------------------------------------------
6.39 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-2.27 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.11 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _456_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _311_/C1 (sky130_fd_sc_hd__o211a_2)
0.04 0.09 2.13 v _311_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _137_ (net)
0.04 0.00 2.13 v _312_/B (sky130_fd_sc_hd__xnor2_2)
0.03 0.09 2.21 v _312_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.03 0.00 2.21 v _456_/D (sky130_fd_sc_hd__dfrtp_2)
2.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 6.67 ^ _456_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-2.21 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
4.14 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _467_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.20 0.52 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.19 0.00 0.52 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.13 0.17 0.70 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.13 0.00 0.70 ^ _211_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.92 v _211_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _045_ (net)
0.03 0.00 0.92 v _212_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.99 v _212_/X (sky130_fd_sc_hd__buf_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _042_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.02 0.00 0.99 v _467_/D (sky130_fd_sc_hd__dfrtp_2)
0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 6.67 ^ _467_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.36 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _465_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.20 0.52 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.19 0.00 0.52 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.13 0.17 0.70 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.13 0.00 0.70 ^ _215_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.92 v _215_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _047_ (net)
0.03 0.00 0.92 v _216_/A (sky130_fd_sc_hd__buf_2)
0.02 0.07 0.99 v _216_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _040_ (net)
0.02 0.00 0.99 v _465_/D (sky130_fd_sc_hd__dfrtp_2)
0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.67 ^ _465_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _466_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.20 0.52 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.19 0.00 0.52 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.13 0.17 0.70 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.13 0.00 0.70 ^ _213_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.91 v _213_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _046_ (net)
0.03 0.00 0.91 v _214_/A (sky130_fd_sc_hd__buf_2)
0.02 0.07 0.99 v _214_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _041_ (net)
0.02 0.00 0.99 v _466_/D (sky130_fd_sc_hd__dfrtp_2)
0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 6.67 ^ _466_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _464_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.20 0.52 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.19 0.00 0.52 ^ _210_/A (sky130_fd_sc_hd__buf_2)
0.13 0.17 0.70 ^ _210_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _044_ (net)
0.13 0.00 0.70 ^ _217_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.21 0.91 v _217_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _048_ (net)
0.03 0.00 0.91 v _218_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.99 v _218_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _039_ (net)
0.02 0.00 0.99 v _464_/D (sky130_fd_sc_hd__dfrtp_2)
0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _464_/CLK (sky130_fd_sc_hd__dfrtp_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-0.99 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.37 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _451_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.24 0.25 ^ _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.03 0.00 0.25 ^ _219_/A (sky130_fd_sc_hd__buf_2)
0.13 0.14 0.39 ^ _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.13 0.00 0.40 ^ _321_/C (sky130_fd_sc_hd__and3_2)
0.05 0.14 0.54 ^ _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.05 0.00 0.54 ^ _322_/B (sky130_fd_sc_hd__and2_2)
0.05 0.11 0.65 ^ _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.05 0.00 0.65 ^ _324_/B_N (sky130_fd_sc_hd__or2b_2)
0.04 0.18 0.83 v _324_/X (sky130_fd_sc_hd__or2b_2)
1 0.00 _145_ (net)
0.04 0.00 0.83 v _325_/B1 (sky130_fd_sc_hd__o211a_2)
0.03 0.09 0.91 v _325_/X (sky130_fd_sc_hd__o211a_2)
1 0.00 _029_ (net)
0.03 0.00 0.91 v _451_/D (sky130_fd_sc_hd__dfrtp_2)
0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 6.67 ^ _451_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.91 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.44 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _446_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _276_/A (sky130_fd_sc_hd__xor2_2)
0.23 0.24 0.56 ^ _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.23 0.00 0.56 ^ _335_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.22 0.78 v _335_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _151_ (net)
0.04 0.00 0.78 v _336_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.86 v _336_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _024_ (net)
0.02 0.00 0.86 v _446_/D (sky130_fd_sc_hd__dfrtp_2)
0.86 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.67 ^ _446_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-0.86 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.50 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.27 0.28 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.03 0.00 0.28 v _219_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 0.40 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.06 0.00 0.40 v _321_/C (sky130_fd_sc_hd__and3_2)
0.04 0.16 0.56 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.04 0.00 0.56 v _322_/B (sky130_fd_sc_hd__and2_2)
0.04 0.14 0.70 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.04 0.00 0.70 v _326_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.79 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.08 0.00 0.79 ^ _332_/C (sky130_fd_sc_hd__nand3_2)
0.04 0.04 0.83 v _332_/Y (sky130_fd_sc_hd__nand3_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
1 0.00 _026_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.04 0.00 0.83 v _448_/D (sky130_fd_sc_hd__dfrtp_2)
0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.35 data required time
-0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.52 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.27 0.28 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.03 0.00 0.28 v _219_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 0.40 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.06 0.00 0.40 v _321_/C (sky130_fd_sc_hd__and3_2)
0.04 0.16 0.56 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.04 0.00 0.56 v _322_/B (sky130_fd_sc_hd__and2_2)
0.04 0.14 0.70 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.04 0.00 0.70 v _326_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.79 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.08 0.00 0.79 ^ _331_/A1 (sky130_fd_sc_hd__a21oi_2)
0.04 0.03 0.83 v _331_/Y (sky130_fd_sc_hd__a21oi_2)
1 0.00 _027_ (net)
0.04 0.00 0.83 v _449_/D (sky130_fd_sc_hd__dfrtp_2)
0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.35 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.83 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.53 slack (MET)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _450_ (rising edge-triggered flip-flop clocked by pll_control_clock)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.27 0.28 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.03 0.00 0.28 v _219_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 0.40 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.06 0.00 0.40 v _321_/C (sky130_fd_sc_hd__and3_2)
0.04 0.16 0.56 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.04 0.00 0.56 v _322_/B (sky130_fd_sc_hd__and2_2)
0.04 0.14 0.70 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.04 0.00 0.70 v _326_/B (sky130_fd_sc_hd__nand2_2)
0.08 0.09 0.79 ^ _326_/Y (sky130_fd_sc_hd__nand2_2)
3 0.02 _146_ (net)
0.08 0.00 0.79 ^ _329_/A1 (sky130_fd_sc_hd__a21oi_2)
0.04 0.03 0.83 v _329_/Y (sky130_fd_sc_hd__a21oi_2)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
1 0.00 _028_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.04 0.00 0.83 v _450_/D (sky130_fd_sc_hd__dfrtp_2)
0.83 data arrival time
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.67 ^ _450_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.07 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.53 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _452_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _448_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.27 0.28 v _448_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.00 pll_control.count0[0] (net)
0.03 0.00 0.28 v _219_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 0.40 v _219_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _049_ (net)
0.06 0.00 0.40 v _321_/C (sky130_fd_sc_hd__and3_2)
0.04 0.16 0.56 v _321_/X (sky130_fd_sc_hd__and3_2)
3 0.01 _143_ (net)
0.04 0.00 0.56 v _322_/B (sky130_fd_sc_hd__and2_2)
0.04 0.14 0.70 v _322_/X (sky130_fd_sc_hd__and2_2)
3 0.01 _144_ (net)
0.04 0.00 0.70 v _323_/A2 (sky130_fd_sc_hd__o21a_2)
0.02 0.12 0.82 v _323_/X (sky130_fd_sc_hd__o21a_2)
1 0.00 _030_ (net)
0.02 0.00 0.82 v _452_/D (sky130_fd_sc_hd__dfrtp_2)
0.82 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.00 6.67 ^ _452_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
-0.07 6.35 library setup time
6.35 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
6.35 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.82 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.53 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _463_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.20 0.52 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.19 0.00 0.52 ^ _220_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.22 0.75 v _220_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _050_ (net)
0.04 0.00 0.75 v _221_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.83 v _221_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _038_ (net)
0.02 0.00 0.83 v _463_/D (sky130_fd_sc_hd__dfrtp_2)
0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _463_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-0.83 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.53 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _447_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.oscbuf[1] (net)
0.06 0.00 0.32 v _209_/A (sky130_fd_sc_hd__xnor2_2)
0.19 0.20 0.52 ^ _209_/Y (sky130_fd_sc_hd__xnor2_2)
3 0.02 _043_ (net)
0.19 0.00 0.52 ^ _333_/S (sky130_fd_sc_hd__mux2_2)
0.03 0.22 0.74 v _333_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _150_ (net)
0.03 0.00 0.74 v _334_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.82 v _334_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _025_ (net)
0.02 0.00 0.82 v _447_/D (sky130_fd_sc_hd__dfrtp_2)
0.82 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.67 ^ _447_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.06 6.36 library setup time
6.36 data required time
-----------------------------------------------------------------------------
6.36 data required time
-0.82 data arrival time
-----------------------------------------------------------------------------
5.54 slack (MET)
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _445_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _276_/A (sky130_fd_sc_hd__xor2_2)
0.07 0.16 0.48 v _276_/X (sky130_fd_sc_hd__xor2_2)
5 0.02 _105_ (net)
0.07 0.00 0.48 v _337_/B (sky130_fd_sc_hd__or2_2)
0.04 0.18 0.66 v _337_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _152_ (net)
0.04 0.00 0.66 v _338_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 0.74 v _338_/X (sky130_fd_sc_hd__buf_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 _023_ (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.02 0.00 0.74 v _445_/D (sky130_fd_sc_hd__dfrtp_2)
0.74 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.67 ^ _445_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-0.74 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
5.62 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _462_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.31 0.32 v _461_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
3 0.02 pll_control.oscbuf[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.06 0.00 0.32 v _462_/D (sky130_fd_sc_hd__dfrtp_2)
0.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _462_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.08 6.35 library setup time
6.35 data required time
-----------------------------------------------------------------------------
6.35 data required time
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-0.32 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
6.03 slack (MET)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _460_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _461_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _460_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.03 0.26 0.27 v _460_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
1 0.00 pll_control.oscbuf[0] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.03 0.00 0.27 v _461_/D (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
0.27 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _461_/CLK (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.07 6.36 library setup time
6.36 data required time
-----------------------------------------------------------------------------
6.36 data required time
-0.27 data arrival time
-----------------------------------------------------------------------------
6.09 slack (MET)
max_report_end
check_report
===========================================================================
report_checks -unconstrained
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _306_/S (sky130_fd_sc_hd__mux2_2)
0.10 0.63 7.85 v _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.10 0.00 7.85 v _307_/A (sky130_fd_sc_hd__buf_2)
0.05 0.26 8.11 v _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.05 0.00 8.11 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
8.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-8.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.93 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.11 0.51 0.52 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.11 0.00 0.52 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.75 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.09 0.00 0.75 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.14 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.07 0.00 1.14 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.39 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.05 0.00 1.39 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.69 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.05 0.00 1.69 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.27 0.35 2.04 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.27 0.00 2.04 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.21 0.34 2.37 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.21 0.00 2.38 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.66 3.03 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.09 0.00 3.03 v _282_/B (sky130_fd_sc_hd__and4_2)
0.06 0.26 3.29 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.06 0.00 3.29 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.06 0.12 3.42 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.06 0.00 3.42 v _284_/A (sky130_fd_sc_hd__buf_2)
0.08 0.19 3.60 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.08 0.00 3.60 v _306_/S (sky130_fd_sc_hd__mux2_2)
0.05 0.30 3.91 v _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.05 0.00 3.91 v _307_/A (sky130_fd_sc_hd__buf_2)
0.03 0.13 4.03 v _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.03 0.00 4.03 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
4.03 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.10 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.10 0.01 6.68 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.09 6.33 library setup time
6.33 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.33 data required time
-4.03 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
2.30 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.08 0.32 0.33 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6 0.03 pll_control.count0[1] (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 0.33 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.06 0.15 0.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.06 0.00 0.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.05 0.24 0.73 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.05 0.00 0.73 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.04 0.16 0.89 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.04 0.00 0.89 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.04 0.15 1.04 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.04 0.00 1.05 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.19 0.17 1.22 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.19 0.00 1.22 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.16 0.21 1.43 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.16 0.00 1.43 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.06 0.36 1.79 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.06 0.00 1.79 v _282_/B (sky130_fd_sc_hd__and4_2)
0.04 0.16 1.95 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.04 0.00 1.95 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.04 0.08 2.03 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.04 0.00 2.03 v _284_/A (sky130_fd_sc_hd__buf_2)
0.06 0.12 2.16 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.06 0.00 2.16 v _306_/S (sky130_fd_sc_hd__mux2_2)
0.04 0.18 2.34 v _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.04 0.00 2.34 v _307_/A (sky130_fd_sc_hd__buf_2)
0.02 0.08 2.42 v _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.02 0.00 2.42 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
2.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.08 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.09 pll_control.clock (net)
0.08 0.01 6.68 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.06 6.36 library setup time
6.36 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.36 data required time
-2.42 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
3.94 slack (MET)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= Slowest Corner ===================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Startpoint: _449_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_control_clock)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Path Group: pll_control_clock
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 0.01 ^ _449_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.20 1.04 1.05 v _449_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.20 0.00 1.05 v _226_/A (sky130_fd_sc_hd__xor2_2)
0.17 0.43 1.48 v _226_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _055_ (net)
0.17 0.00 1.48 v _237_/A2 (sky130_fd_sc_hd__a211o_2)
0.12 0.75 2.22 v _237_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _066_ (net)
0.12 0.00 2.23 v _242_/A2 (sky130_fd_sc_hd__a21o_2)
0.09 0.47 2.69 v _242_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _071_ (net)
0.09 0.00 2.69 v _247_/A3 (sky130_fd_sc_hd__a32o_2)
0.09 0.54 3.23 v _247_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _076_ (net)
0.09 0.00 3.23 v _250_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.43 0.60 3.83 ^ _250_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _079_ (net)
0.43 0.00 3.83 ^ _263_/A1 (sky130_fd_sc_hd__o31a_2)
0.34 0.66 4.49 ^ _263_/X (sky130_fd_sc_hd__o31a_2)
7 0.04 _092_ (net)
0.34 0.00 4.49 ^ _275_/C_N (sky130_fd_sc_hd__or4bb_2)
0.20 1.56 6.06 v _275_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _104_ (net)
0.20 0.00 6.06 v _282_/B (sky130_fd_sc_hd__and4_2)
0.11 0.56 6.62 v _282_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _111_ (net)
0.11 0.00 6.62 v _283_/B1 (sky130_fd_sc_hd__o31a_2)
0.10 0.24 6.86 v _283_/X (sky130_fd_sc_hd__o31a_2)
2 0.00 _112_ (net)
0.10 0.00 6.86 v _284_/A (sky130_fd_sc_hd__buf_2)
0.15 0.36 7.23 v _284_/X (sky130_fd_sc_hd__buf_2)
7 0.03 _113_ (net)
0.15 0.00 7.23 v _306_/S (sky130_fd_sc_hd__mux2_2)
0.10 0.63 7.85 v _306_/X (sky130_fd_sc_hd__mux2_2)
1 0.00 _133_ (net)
0.10 0.00 7.85 v _307_/A (sky130_fd_sc_hd__buf_2)
0.05 0.26 8.11 v _307_/X (sky130_fd_sc_hd__buf_2)
1 0.00 _035_ (net)
0.05 0.00 8.11 v _457_/D (sky130_fd_sc_hd__dfrtp_2)
8.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
change buf16 to clkbuf16 and reimplement
2022-10-13 08:54:55 -05:00
24 0.08 pll_control.clock (net)
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
0.15 0.01 6.68 ^ _457_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.43 clock uncertainty
0.00 6.43 clock reconvergence pessimism
-0.24 6.18 library setup time
6.18 data required time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
6.18 data required time
-8.11 data arrival time
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
-----------------------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
-1.93 slack (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
No paths found.
======================= Fastest Corner ===================================
No paths found.
check_report_end
check_slew
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= Slowest Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
dco 7 12 -5 (VIOLATED)
_417_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
dco 7 12 -5 (VIOLATED)
_417_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
ringosc.ibufp01/Y 7 24 -17 (VIOLATED)
dco 7 12 -5 (VIOLATED)
_417_/X 7 8 (VIOLATED)
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
max slew violation count 0
max fanout violation count 3
max cap violation count 0
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
============================================================================
check_slew_end
tns_report
===========================================================================
report_tns
============================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
tns -11.25
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
tns_report_end
wns_report
===========================================================================
report_wns
============================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
wns -1.93
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
wns_report_end
worst_slack
===========================================================================
report_worst_slack -max (Setup)
============================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
worst slack -1.93
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
===========================================================================
report_worst_slack -min (Hold)
============================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
worst slack -0.02
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
worst_slack_end
power_report
===========================================================================
report_power
============================================================================
======================= Slowest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Sequential 1.15e-04 9.46e-06 3.37e-07 1.24e-04 28.9%
Combinational 1.33e-04 1.71e-04 1.71e-06 3.05e-04 71.1%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Total 2.47e-04 1.80e-04 2.04e-06 4.30e-04 100.0%
57.5% 42.0% 0.5%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Typical Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Sequential 1.49e-04 1.21e-05 1.84e-10 1.61e-04 29.8%
Combinational 1.62e-04 2.18e-04 1.35e-09 3.80e-04 70.2%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Total 3.11e-04 2.30e-04 1.54e-09 5.41e-04 100.0%
57.5% 42.5% 0.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
======================= Fastest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Sequential 1.74e-04 1.44e-05 3.12e-10 1.88e-04 30.0%
Combinational 1.81e-04 2.58e-04 3.56e-09 4.39e-04 70.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Total 3.55e-04 2.73e-04 3.87e-09 6.27e-04 100.0%
56.5% 43.5% 0.0%
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
power_report_end
area_report
===========================================================================
report_design_area
============================================================================
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Design area 3656 u^2 91% utilization.
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF files for all corners...
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Writing SDF for the ff corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/results/routing/mca/process_corner_max/digital_pll.ff.sdf...
Writing SDF for the ss corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/results/routing/mca/process_corner_max/digital_pll.ss.sdf...
Writing SDF for the tt corner to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/results/routing/mca/process_corner_max/digital_pll.tt.sdf...