mirror of https://github.com/efabless/caravel.git
38 lines
2.9 KiB
Plaintext
38 lines
2.9 KiB
Plaintext
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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
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This program is licensed under the BSD-3 license. See the LICENSE file for details.
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Components of this program may be licensed under more restrictive licenses which must be honored.
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[INFO ODB-0222] Reading LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
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[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
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The LEF parser will ignore this statement.
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To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef at line 930.
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[INFO ODB-0223] Created 13 technology layers
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[INFO ODB-0224] Created 25 technology vias
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[INFO ODB-0225] Created 441 library cells
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[INFO ODB-0226] Finished LEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/tmp/merged.nom.lef
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[INFO ODB-0127] Reading DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
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[INFO ODB-0128] Design: buff_flash_clkrst
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[INFO ODB-0130] Created 32 pins.
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[INFO ODB-0131] Created 73 components and 308 component-terminals.
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[INFO ODB-0132] Created 2 special nets and 278 connections.
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[INFO ODB-0133] Created 30 nets and 30 connections.
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[INFO ODB-0134] Finished DEF file: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/results/routing/buff_flash_clkrst.def
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[INFO]: Setting RC values...
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[INFO PSM-0002] Output voltage file is specified as: /home/hosni/My_forks/FINAL/caravel/openlane/buff_flash_clkrst/runs/22_10_13_10_28/reports/signoff/21-irdrop.rpt.
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[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
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[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
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[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
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[WARNING PSM-0019] Voltage on net VPWR is not explicitly set.
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[WARNING PSM-0022] Using voltage 1.800V for VDD network.
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[WARNING PSM-0063] Specified bump pitches of 140.000 and 140.000 are less than core width of 35.880 or core height of 13.600. Changing bump location to the center of the die at (19.780, 12.240).
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[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
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[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
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[INFO PSM-0031] Number of PDN nodes on net VPWR = 110.
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[INFO PSM-0064] Number of voltage sources = 1.
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[INFO PSM-0040] All PDN stripes on net VPWR are connected.
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########## IR report #################
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Worstcase voltage: 1.80e+00 V
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Average IR drop : 2.19e-10 V
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Worstcase IR drop: 3.61e-10 V
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######################################
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