mirror of https://github.com/efabless/caravel.git
146 lines
5.0 KiB
Plaintext
146 lines
5.0 KiB
Plaintext
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CVC: Circuit Validation Check Version 1.1.0
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CVC: Log output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/reports/signoff/digital_pll.rpt
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CVC: Error output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/reports/signoff/digital_pll.rpt.error.gz
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CVC: Debug output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/reports/signoff/digital_pll.rpt.debug.gz
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CVC: Start: Thu Oct 13 13:18:00 2022
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Using the following parameters for CVC (Circuit Validation Check) from /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/cvcrc
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CVC_TOP = 'digital_pll'
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CVC_NETLIST = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/tmp/signoff/digital_pll.cdl'
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CVC_MODE = 'digital_pll'
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CVC_MODEL_FILE = '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/models'
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CVC_POWER_FILE = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/tmp/signoff/digital_pll.power'
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CVC_FUSE_FILE = ''
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CVC_REPORT_FILE = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/reports/signoff/digital_pll.rpt'
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CVC_REPORT_TITLE = 'CVC $CVC_TOP'
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CVC_CIRCUIT_ERROR_LIMIT = '100'
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CVC_SEARCH_LIMIT = '100'
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CVC_LEAK_LIMIT = '0.0002'
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CVC_SOI = 'false'
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CVC_SCRC = 'false'
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CVC_VTH_GATES = 'false'
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CVC_MIN_VTH_GATES = 'false'
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CVC_IGNORE_VTH_FLOATING = 'false'
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CVC_IGNORE_NO_LEAK_FLOATING = 'false'
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CVC_LEAK_OVERVOLTAGE = 'true'
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CVC_LOGIC_DIODES = 'false'
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CVC_ANALOG_GATES = 'true'
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CVC_BACKUP_RESULTS = 'false'
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CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
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CVC_SHORT_ERROR_THRESHOLD = '0'
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CVC_BIAS_ERROR_THRESHOLD = '0'
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CVC_FORWARD_ERROR_THRESHOLD = '0'
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CVC_FLOATING_ERROR_THRESHOLD = '0'
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CVC_GATE_ERROR_THRESHOLD = '0'
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CVC_LEAK?_ERROR_THRESHOLD = '0'
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CVC_EXPECTED_ERROR_THRESHOLD = '0'
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CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
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CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
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CVC_CELL_ERROR_LIMIT_FILE = ''
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CVC_CELL_CHECKSUM_FILE = ''
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CVC_LARGE_CIRCUIT_SIZE = '10000000'
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CVC_NET_CHECK_FILE = ''
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CVC_MODEL_CHECK_FILE = ''
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End of parameters
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CVC: Reading device model settings...
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CVC: Reading power settings...
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CVC: Parsing netlist /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/tmp/signoff/digital_pll.cdl
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Cdl fixed data size 29257
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Usage CDL: Time: 0 Memory: 6924 I/O: 376 Swap: 0
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CVC: Counting and linking...
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CVC: Assigning IDs ...
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Usage DB: Time: 0 Memory: 7180 I/O: 376 Swap: 0
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CVC: 622(622) instances, 1368(1368) nets, 2706(2706) devices.
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Setting power for mode...
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Setting models...
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CVC: Setting models ...
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Setting model tolerances...
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CVC: Shorting switches...
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model short...
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Shorted 2 short
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Setting instance power...
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CVC: Linking devices...
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Usage EQUIV: Time: 0 Memory: 7808 I/O: 392 Swap: 0
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Power nets 44
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CVC: Shorting non conducting resistors...
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CVC: Calculating resistor voltages...
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Usage RES: Time: 0 Memory: 7808 I/O: 392 Swap: 0
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Power nets 44
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CVC: Calculating min/max voltages...
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Processing trivial nets found 335 trivial nets
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CVC: Ignoring invalid calculations...
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CVC: Removed 0 calculations
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Copying master nets
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CVC: Ignoring non-conducting devices...
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CVC: Ignored 0 devices
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Usage MIN/MAX1: Time: 0 Memory: 7808 I/O: 392 Swap: 0
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Power nets 613
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! Checking forward bias diode errors:
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! Checking nmos source/drain vs bias errors:
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! Checking nmos gate vs source errors:
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! Checking pmos source/drain vs bias errors:
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! Checking pmos gate vs source errors:
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Usage ERROR: Time: 0 Memory: 7808 I/O: 392 Swap: 0
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Saving min/max voltages...
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CVC: Propagating Simulation voltages 1...
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Usage SIM1: Time: 0 Memory: 7808 I/O: 392 Swap: 0
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Power nets 613
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Saving simulation voltages...
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CVC: Propagating Simulation voltages 3...
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Usage SIM2: Time: 0 Memory: 7808 I/O: 392 Swap: 0
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Power nets 613
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Added 0 latch voltages
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CVC: Calculating min/max voltages...
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Processing trivial nets found 335 trivial nets
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CVC: Ignoring invalid calculations...
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CVC: Removed 0 calculations
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Copying master nets
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CVC: Ignoring non-conducting devices...
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CVC: Ignored 0 devices
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Usage MIN/MAX2: Time: 0 Memory: 7808 I/O: 392 Swap: 0
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Power nets 1182
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! Checking overvoltage errors
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! Checking nmos possible leak errors:
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! Checking pmos possible leak errors:
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! Checking mos floating input errors:
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! Checking expected values:
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CVC: Error Counts
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CVC: Fuse Problems: 0
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CVC: Min Voltage Conflicts: 0
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CVC: Max Voltage Conflicts: 0
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CVC: Leaks: 0
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CVC: LDD drain->source: 0
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CVC: HI-Z Inputs: 0
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CVC: Forward Bias Diodes: 0
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CVC: NMOS Source vs Bulk: 0
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CVC: NMOS Gate vs Source: 0
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CVC: NMOS Possible Leaks: 0
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CVC: PMOS Source vs Bulk: 0
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CVC: PMOS Gate vs Source: 0
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CVC: PMOS Possible Leaks: 0
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CVC: Overvoltage-VBG: 0
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CVC: Overvoltage-VBS: 0
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CVC: Overvoltage-VDS: 0
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CVC: Overvoltage-VGS: 0
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CVC: Model errors: 0
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CVC: Unexpected voltage : 0
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CVC: Total: 0
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Usage Total: Time: 0 Memory: 8464 I/O: 432 Swap: 0
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Virtual net update/access 12546/308300
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CVC: Log output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_16/reports/signoff/digital_pll.rpt
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CVC: End: Thu Oct 13 13:18:00 2022
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