mirror of https://github.com/efabless/caravel.git
79 lines
2.8 KiB
ReStructuredText
79 lines
2.8 KiB
ReStructuredText
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CTRL
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====
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Register Listing for CTRL
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-------------------------
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+------------------------------------------+-------------------------------------+
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| Register | Address |
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+==========================================+=====================================+
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| :ref:`CTRL_RESET <CTRL_RESET>` | :ref:`0xf0000000 <CTRL_RESET>` |
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+------------------------------------------+-------------------------------------+
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| :ref:`CTRL_SCRATCH <CTRL_SCRATCH>` | :ref:`0xf0000004 <CTRL_SCRATCH>` |
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+------------------------------------------+-------------------------------------+
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| :ref:`CTRL_BUS_ERRORS <CTRL_BUS_ERRORS>` | :ref:`0xf0000008 <CTRL_BUS_ERRORS>` |
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+------------------------------------------+-------------------------------------+
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CTRL_RESET
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^^^^^^^^^^
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`Address: 0xf0000000 + 0x0 = 0xf0000000`
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.. wavedrom::
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:caption: CTRL_RESET
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{
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"reg": [
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{"name": "soc_rst", "type": 4, "bits": 1},
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{"name": "cpu_rst", "bits": 1},
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{"bits": 30}
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], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
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}
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+-------+---------+------------------------------------------------------------------------+
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| Field | Name | Description |
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+=======+=========+========================================================================+
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| [0] | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset) |
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+-------+---------+------------------------------------------------------------------------+
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| [1] | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) |
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+-------+---------+------------------------------------------------------------------------+
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CTRL_SCRATCH
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^^^^^^^^^^^^
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`Address: 0xf0000000 + 0x4 = 0xf0000004`
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Use this register as a scratch space to verify that software read/write accesses
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to the Wishbone/CSR bus are working correctly. The initial reset value of
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0x1234578 can be used to verify endianness.
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.. wavedrom::
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:caption: CTRL_SCRATCH
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{
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"reg": [
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{"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32}
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], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
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}
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CTRL_BUS_ERRORS
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^^^^^^^^^^^^^^^
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`Address: 0xf0000000 + 0x8 = 0xf0000008`
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Total number of Wishbone bus errors (timeouts) since start.
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.. wavedrom::
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:caption: CTRL_BUS_ERRORS
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{
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"reg": [
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{"name": "bus_errors[31:0]", "bits": 32}
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], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
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}
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