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caravel/maglef/caravel_clocking.mag

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[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
magic
tech sky130A
magscale 1 2
[DATA] Update caravel_clocking module
2021-12-05 11:44:28 -06:00
timestamp 1638662846
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
<< nwell >>
rect -38 10053 18898 10619
rect -38 8965 18898 9531
rect -38 7877 18898 8443
rect -38 6789 18898 7355
rect -38 5701 18898 6267
rect -38 4613 18898 5179
rect -38 3525 18898 4091
rect -38 2437 18898 3003
rect -38 1349 18898 1915
rect -38 261 18898 827
[DATA] Update caravel_clocking module floorplan
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<< pwell >>
[DATA] Update caravel_clocking
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rect 29 -17 63 17
rect 305 -17 339 17
rect 1043 -10 1075 12
rect 1317 -17 1351 17
rect 2513 -17 2547 17
[DATA] Update caravel_clocking module
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rect 3709 -17 3743 17
[DATA] Update caravel_clocking
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rect 4905 -17 4939 17
[DATA] Update caravel_clocking module
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rect 5272 -11 5296 11
rect 5917 -17 5951 17
rect 6100 -17 6134 17
rect 6377 -17 6411 17
rect 7112 -11 7136 11
[DATA] Update caravel_clocking
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rect 7297 -17 7331 17
[DATA] Update caravel_clocking module
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rect 8493 -17 8527 17
rect 9044 -11 9068 11
rect 9412 -17 9446 17
rect 9504 -11 9528 11
[DATA] Update caravel_clocking
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rect 9689 -17 9723 17
rect 10885 -17 10919 17
[DATA] Update caravel_clocking module
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rect 12356 -17 12390 17
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rect 13554 -17 13588 17
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rect 14473 -17 14507 17
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rect 15852 -17 15886 17
rect 16497 -17 16531 17
rect 16591 -10 16623 12
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rect 16865 -17 16899 17
[DATA] Update caravel_clocking module
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rect 17509 -17 17543 17
rect 17876 -11 17900 11
rect 18061 -17 18095 17
[DATA] Update caravel_clocking module floorplan
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rect 18797 -17 18831 17
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
<< obsli1 >>
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rect 0 -17 18860 10897
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
<< obsm1 >>
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rect 0 -48 18860 10928
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
<< metal2 >>
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rect 1398 11200 1454 12000
rect 4250 11200 4306 12000
rect 7102 11200 7158 12000
rect 9954 11200 10010 12000
rect 12806 11200 12862 12000
rect 15658 11200 15714 12000
rect 18510 11200 18566 12000
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
<< obsm2 >>
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rect 296 11144 1342 11257
[DATA] Update caravel_clocking module floorplan
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rect 1510 11144 4194 11257
rect 4362 11144 7046 11257
rect 7214 11144 9898 11257
rect 10066 11144 12750 11257
rect 12918 11144 15602 11257
rect 15770 11144 18454 11257
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
rect 18622 11144 18842 11257
[DATA] Update caravel_clocking
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rect 296 0 18842 11144
rect 4660 -48 4968 0
rect 7760 -48 8068 0
rect 10860 -48 11168 0
rect 13960 -48 14268 0
rect 17060 -48 17368 0
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
<< metal3 >>
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rect 19200 11160 20000 11280
rect 19200 9664 20000 9784
rect 19200 8168 20000 8288
rect 19200 6672 20000 6792
rect 19200 5176 20000 5296
rect 19200 3680 20000 3800
rect 19200 2184 20000 2304
rect 19200 688 20000 808
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
<< obsm3 >>
[DATA] Update caravel_clocking module
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rect 2497 11080 19120 11253
rect 2497 9864 19200 11080
rect 2497 9584 19120 9864
rect 2497 8368 19200 9584
rect 2497 8088 19120 8368
rect 2497 6872 19200 8088
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rect 2497 2384 19200 3600
rect 2497 2104 19120 2384
rect 2497 888 19200 2104
rect 2497 608 19120 888
rect 2497 0 19200 608
[DATA] Update caravel_clocking
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rect 4654 -33 4974 0
rect 7754 -33 8074 0
rect 10854 -33 11174 0
rect 13954 -33 14274 0
rect 17054 -33 17374 0
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
<< metal4 >>
[DATA] Update caravel_clocking
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rect 3104 -48 3424 10928
rect 4654 -48 4974 10928
rect 6204 -48 6524 10928
rect 7754 -48 8074 10928
rect 9304 -48 9624 10928
rect 10854 -48 11174 10928
rect 12404 -48 12724 10928
rect 13954 -48 14274 10928
rect 15504 -48 15824 10928
rect 17054 -48 17374 10928
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
<< metal5 >>
[DATA] Update caravel_clocking
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rect 0 9882 18860 10202
rect 0 8192 18860 8512
rect 0 6502 18860 6822
rect 0 4812 18860 5132
rect 0 3122 18860 3442
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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<< labels >>
[DATA] Update caravel_clocking
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rlabel metal5 s 0 4812 18860 5132 6 VGND
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 1 nsew ground input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal5 s 0 8192 18860 8512 6 VGND
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 1 nsew ground input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 4654 -48 4974 10928 6 VGND
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
port 1 nsew ground input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 7754 -48 8074 10928 6 VGND
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
port 1 nsew ground input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 10854 -48 11174 10928 6 VGND
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
port 1 nsew ground input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 13954 -48 14274 10928 6 VGND
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
port 1 nsew ground input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 17054 -48 17374 10928 6 VGND
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
port 1 nsew ground input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal5 s 0 3122 18860 3442 6 VPWR
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal5 s 0 6502 18860 6822 6 VPWR
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 05:06:23 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal5 s 0 9882 18860 10202 6 VPWR
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 3104 -48 3424 10928 6 VPWR
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 6204 -48 6524 10928 6 VPWR
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 9304 -48 9624 10928 6 VPWR
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 12404 -48 12724 10928 6 VPWR
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking
2021-12-02 14:50:20 -06:00
rlabel metal4 s 15504 -48 15824 10928 6 VPWR
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 2 nsew power input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal2 s 7102 11200 7158 12000 6 core_clk
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 3 nsew signal output
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal2 s 4250 11200 4306 12000 6 ext_clk
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 4 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 688 20000 808 6 ext_clk_sel
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 5 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 11160 20000 11280 6 ext_reset
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 6 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal2 s 15658 11200 15714 12000 6 pll_clk
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 7 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal2 s 18510 11200 18566 12000 6 pll_clk90
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 8 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal2 s 1398 11200 1454 12000 6 resetb
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 9 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal2 s 12806 11200 12862 12000 6 resetb_sync
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 10 nsew signal output
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 6672 20000 6792 6 sel2[0]
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 11 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 8168 20000 8288 6 sel2[1]
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 12 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 9664 20000 9784 6 sel2[2]
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 13 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 2184 20000 2304 6 sel[0]
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 14 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 3680 20000 3800 6 sel[1]
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 15 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal3 s 19200 5176 20000 5296 6 sel[2]
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
port 16 nsew signal input
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
rlabel metal2 s 9954 11200 10010 12000 6 user_clk
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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port 17 nsew signal output
<< properties >>
string LEFclass BLOCK
[DATA] Update caravel_clocking module floorplan
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string FIXED_BBOX 0 0 20000 12000
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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string LEFview TRUE
Corrected bad paths on two layouts in mag/ and most of the layouts in maglef/, all of which were erroneously pointing to paths in either OpenLane or the user's home directory path.
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string GDS_FILE ../gds/caravel_clocking.gds
[DATA] Update caravel_clocking module
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string GDS_END 1197054
string GDS_START 422960
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
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<< end >>