2022-10-13 12:15:05 -05:00
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
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2023-02-27 09:30:03 -06:00
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/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/housekeeping,housekeeping,23_02_27_06_04,flow completed,0h12m8s0ms,0h6m53s0ms,35908.92748256471,0.2260162185,17954.463741282354,25.12,2087.54,4058,0,0,0,0,0,0,0,26,0,-1,-1,550243,65844,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,364134109.0,0.0,47.09,62.8,9.29,31.48,-1,8372,9432,193,1200,0,0,0,9096,164,1,141,326,4526,44,5,170,943,889,21,388,2940,0,3328,210449.33759999997,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,3,1,50,78.2,76.8,0.2,0.31,sky130_fd_sc_hd,20,AREA 0
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