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caravel
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caravel/verilog/gl/digital_pll.v

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Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
module digital_pll (VGND,
VPWR,
dco,
enable,
osc,
resetb,
clockp,
div,
ext_trim);
input VGND;
input VPWR;
input dco;
input enable;
input osc;
input resetb;
output [1:0] clockp;
input [4:0] div;
input [25:0] ext_trim;
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire \pll_control.clock ;
wire \pll_control.count0[0] ;
wire \pll_control.count0[1] ;
wire \pll_control.count0[2] ;
wire \pll_control.count0[3] ;
wire \pll_control.count0[4] ;
wire \pll_control.count1[0] ;
wire \pll_control.count1[1] ;
wire \pll_control.count1[2] ;
wire \pll_control.count1[3] ;
wire \pll_control.count1[4] ;
wire \pll_control.oscbuf[0] ;
wire \pll_control.oscbuf[1] ;
wire \pll_control.oscbuf[2] ;
wire \pll_control.prep[0] ;
wire \pll_control.prep[1] ;
wire \pll_control.prep[2] ;
wire \pll_control.tint[0] ;
wire \pll_control.tint[1] ;
wire \pll_control.tint[2] ;
wire \pll_control.tint[3] ;
wire \pll_control.tint[4] ;
wire \pll_control.tval[0] ;
wire \pll_control.tval[1] ;
wire \ringosc.c[0] ;
wire \ringosc.c[1] ;
wire \ringosc.dstage[0].id.d0 ;
wire \ringosc.dstage[0].id.d1 ;
wire \ringosc.dstage[0].id.d2 ;
wire \ringosc.dstage[0].id.in ;
wire \ringosc.dstage[0].id.out ;
wire \ringosc.dstage[0].id.trim[0] ;
wire \ringosc.dstage[0].id.trim[1] ;
wire \ringosc.dstage[0].id.ts ;
wire \ringosc.dstage[10].id.d0 ;
wire \ringosc.dstage[10].id.d1 ;
wire \ringosc.dstage[10].id.d2 ;
wire \ringosc.dstage[10].id.in ;
wire \ringosc.dstage[10].id.out ;
wire \ringosc.dstage[10].id.trim[0] ;
wire \ringosc.dstage[10].id.trim[1] ;
wire \ringosc.dstage[10].id.ts ;
wire \ringosc.dstage[11].id.d0 ;
wire \ringosc.dstage[11].id.d1 ;
wire \ringosc.dstage[11].id.d2 ;
wire \ringosc.dstage[11].id.out ;
wire \ringosc.dstage[11].id.trim[0] ;
wire \ringosc.dstage[11].id.trim[1] ;
wire \ringosc.dstage[11].id.ts ;
wire \ringosc.dstage[1].id.d0 ;
wire \ringosc.dstage[1].id.d1 ;
wire \ringosc.dstage[1].id.d2 ;
wire \ringosc.dstage[1].id.out ;
wire \ringosc.dstage[1].id.trim[0] ;
wire \ringosc.dstage[1].id.trim[1] ;
wire \ringosc.dstage[1].id.ts ;
wire \ringosc.dstage[2].id.d0 ;
wire \ringosc.dstage[2].id.d1 ;
wire \ringosc.dstage[2].id.d2 ;
wire \ringosc.dstage[2].id.out ;
wire \ringosc.dstage[2].id.trim[0] ;
wire \ringosc.dstage[2].id.trim[1] ;
wire \ringosc.dstage[2].id.ts ;
wire \ringosc.dstage[3].id.d0 ;
wire \ringosc.dstage[3].id.d1 ;
wire \ringosc.dstage[3].id.d2 ;
wire \ringosc.dstage[3].id.out ;
wire \ringosc.dstage[3].id.trim[0] ;
wire \ringosc.dstage[3].id.trim[1] ;
wire \ringosc.dstage[3].id.ts ;
wire \ringosc.dstage[4].id.d0 ;
wire \ringosc.dstage[4].id.d1 ;
wire \ringosc.dstage[4].id.d2 ;
wire \ringosc.dstage[4].id.out ;
wire \ringosc.dstage[4].id.trim[0] ;
wire \ringosc.dstage[4].id.trim[1] ;
wire \ringosc.dstage[4].id.ts ;
wire \ringosc.dstage[5].id.d0 ;
wire \ringosc.dstage[5].id.d1 ;
wire \ringosc.dstage[5].id.d2 ;
wire \ringosc.dstage[5].id.out ;
wire \ringosc.dstage[5].id.trim[0] ;
wire \ringosc.dstage[5].id.trim[1] ;
wire \ringosc.dstage[5].id.ts ;
wire \ringosc.dstage[6].id.d0 ;
wire \ringosc.dstage[6].id.d1 ;
wire \ringosc.dstage[6].id.d2 ;
wire \ringosc.dstage[6].id.out ;
wire \ringosc.dstage[6].id.trim[0] ;
wire \ringosc.dstage[6].id.trim[1] ;
wire \ringosc.dstage[6].id.ts ;
wire \ringosc.dstage[7].id.d0 ;
wire \ringosc.dstage[7].id.d1 ;
wire \ringosc.dstage[7].id.d2 ;
wire \ringosc.dstage[7].id.out ;
wire \ringosc.dstage[7].id.trim[0] ;
wire \ringosc.dstage[7].id.trim[1] ;
wire \ringosc.dstage[7].id.ts ;
wire \ringosc.dstage[8].id.d0 ;
wire \ringosc.dstage[8].id.d1 ;
wire \ringosc.dstage[8].id.d2 ;
wire \ringosc.dstage[8].id.out ;
wire \ringosc.dstage[8].id.trim[0] ;
wire \ringosc.dstage[8].id.trim[1] ;
wire \ringosc.dstage[8].id.ts ;
wire \ringosc.dstage[9].id.d0 ;
wire \ringosc.dstage[9].id.d1 ;
wire \ringosc.dstage[9].id.d2 ;
wire \ringosc.dstage[9].id.trim[0] ;
wire \ringosc.dstage[9].id.trim[1] ;
wire \ringosc.dstage[9].id.ts ;
wire \ringosc.iss.ctrl0 ;
wire \ringosc.iss.d0 ;
wire \ringosc.iss.d1 ;
wire \ringosc.iss.d2 ;
wire \ringosc.iss.one ;
wire \ringosc.iss.reset ;
wire \ringosc.iss.trim[0] ;
wire \ringosc.iss.trim[1] ;
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__177__A (.DIODE(div[0]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__181__A (.DIODE(enable),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__181__B (.DIODE(resetb),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__182__A (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__201__A1 (.DIODE(div[3]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__201__B1 (.DIODE(div[2]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__202__A (.DIODE(div[3]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__204__A1 (.DIODE(div[2]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__207__A (.DIODE(div[1]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__210__A1 (.DIODE(div[1]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__210__B1 (.DIODE(div[0]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__211__A1 (.DIODE(div[1]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__216__A (.DIODE(div[4]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__218__B1 (.DIODE(div[4]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__330__A1 (.DIODE(ext_trim[11]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__330__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__331__A1 (.DIODE(ext_trim[24]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__331__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__332__A1 (.DIODE(ext_trim[10]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__332__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__333__A1 (.DIODE(ext_trim[23]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__333__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__334__A1 (.DIODE(ext_trim[9]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__334__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__335__A1 (.DIODE(ext_trim[22]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__335__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__336__A1 (.DIODE(ext_trim[8]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__336__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__337__A1 (.DIODE(ext_trim[21]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__337__S (.DIODE(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__338__A1 (.DIODE(ext_trim[7]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__338__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__339__A1 (.DIODE(ext_trim[20]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__339__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__340__A1 (.DIODE(ext_trim[6]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__340__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__341__A1 (.DIODE(ext_trim[19]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__341__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__342__A1 (.DIODE(ext_trim[5]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__342__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__343__A1 (.DIODE(ext_trim[18]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__343__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__344__A1 (.DIODE(ext_trim[4]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__344__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__345__A1 (.DIODE(ext_trim[17]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__345__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__346__A1 (.DIODE(ext_trim[3]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__346__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__347__A1 (.DIODE(ext_trim[16]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__347__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__348__A1 (.DIODE(ext_trim[2]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__348__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__349__A1 (.DIODE(ext_trim[15]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__349__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__350__A1 (.DIODE(ext_trim[1]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__350__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__351__A1 (.DIODE(ext_trim[14]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__351__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__352__A1 (.DIODE(ext_trim[0]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__352__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__353__A1 (.DIODE(ext_trim[13]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__353__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__354__A1 (.DIODE(ext_trim[12]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__354__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__355__A1 (.DIODE(ext_trim[25]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__diode_2 ANTENNA__355__S (.DIODE(dco),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__diode_2 ANTENNA__356__D (.DIODE(osc),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_0_109 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_113 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_0_118 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_0_13 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_0_21 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_50 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_75 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_83 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_133 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_10_19 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_27 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_10_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_10_43 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_11_106 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_113 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_117 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_11_32 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_11_45 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_11_54 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_11_57 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_11_88 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_11_96 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_12_103 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_12_24 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_12_53 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_12_67 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_83 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_12_85 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_13_113 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_13_16 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_13_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_13_49 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_55 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_12 FILLER_13_57 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_13_9 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_100 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_14_118 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_14_24 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_83 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_14_85 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_14_89 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_113 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_15_14 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_15_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_50 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_15_77 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_16_24 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_16_41 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_16_99 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_17_110 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_119 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_13 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_17_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_17_39 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_17_53 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_57 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_17_66 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_17_9 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_27 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_83 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_18_85 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_11 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_19_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_19_31 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_53 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_19_57 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_69 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_19_91 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_57 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_1_88 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_20_122 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_20_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_20_16 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_20_27 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_20_32 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_20_57 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_20_61 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_21_110 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_21_134 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_21_26 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_21_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_21_78 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_22_107 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_22_11 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_22_111 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_22_121 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_22_125 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_22_17 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_22_26 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_22_29 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_22_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_22_35 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_12 FILLER_22_39 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_22_51 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_22_55 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_22_57 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_22_65 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_22_83 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_22_94 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_106 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_116 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_26 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_2_29 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_39 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_2_80 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_85 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_2_88 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_3_111 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_12 FILLER_3_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_3_48 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_3_54 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_3_59 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_3_73 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_106 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_4_15 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_19 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_12 FILLER_4_29 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_41 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_4_49 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_4_59 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_63 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_4_8 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_4_87 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_111 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_113 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_133 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_3 FILLER_5_41 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_5_78 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_82 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_5_85 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_107 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_13 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_135 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_22 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_6_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_6_38 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_6_49 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_53 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_63 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_4 FILLER_6_75 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_9 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_6_97 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_24 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_42 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_54 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_7_66 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_7_75 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_103 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_8 FILLER_8_13 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_21 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_29 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__decap_6 FILLER_8_3 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_44 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_2 FILLER_8_63 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_8_9 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_122 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_55 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_72 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__fill_1 FILLER_9_82 (.VGND(VGND),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_40 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_41 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_42 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_43 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_44 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_45 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_66 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_67 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_68 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_69 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_70 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_71 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_72 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_73 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_74 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_75 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_76 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_77 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_78 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_79 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_80 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_81 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_82 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_83 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_84 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_85 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_86 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_87 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_88 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_89 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_90 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_91 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_92 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_93 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_94 (.VGND(VGND),
.VPWR(VPWR));
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_95 (.VGND(VGND),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _164_ (.A(\pll_control.count0[4] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_072_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _165_ (.A(\pll_control.count1[4] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_073_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _166_ (.A(\pll_control.count0[2] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_074_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _167_ (.A(\pll_control.count0[1] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_075_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _168_ (.A(\pll_control.count0[0] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_076_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _169_ (.A(\pll_control.count1[0] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_077_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _170_ (.A(\pll_control.tint[4] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_078_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _171_ (.A(\pll_control.tint[3] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_079_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _172_ (.A(\pll_control.tint[2] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_080_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _173_ (.A(\pll_control.tint[1] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_081_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _174_ (.A(\pll_control.tint[0] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_082_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _175_ (.A(\pll_control.tval[1] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_083_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _176_ (.A(\pll_control.tval[0] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_084_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _177_ (.A(div[0]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_085_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a2bb2o_2 _178_ (.A1_N(\pll_control.oscbuf[1] ),
.A2_N(\pll_control.oscbuf[2] ),
.B1(\pll_control.oscbuf[1] ),
.B2(\pll_control.oscbuf[2] ),
.X(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _179_ (.A(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_087_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _180_ (.A1(\pll_control.count1[4] ),
.A2(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.count0[4] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_071_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nand2_2 _181_ (.A(enable),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(resetb),
.Y(\ringosc.iss.reset ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nor2_2 _182_ (.A(dco),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(\ringosc.iss.reset ),
.Y(_050_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _183_ (.A1(\pll_control.count1[3] ),
.A2(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.count0[3] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_070_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _184_ (.A1(\pll_control.count1[2] ),
.A2(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.count0[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_069_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _185_ (.A1(\pll_control.count1[1] ),
.A2(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.count0[1] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_068_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _186_ (.A1(\pll_control.count1[0] ),
.A2(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.count0[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_067_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _187_ (.A1(\pll_control.prep[1] ),
.A2(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.prep[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_066_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _188_ (.A1(\pll_control.prep[1] ),
.A2(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.prep[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_065_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _189_ (.A(\pll_control.prep[0] ),
.B(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_064_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nor2_2 _190_ (.A(\pll_control.count0[3] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(\pll_control.count1[3] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_088_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a21o_2 _191_ (.A1(\pll_control.count0[3] ),
.A2(\pll_control.count1[3] ),
.B1(_088_),
.X(_089_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nor2_2 _192_ (.A(\pll_control.count0[2] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(\pll_control.count1[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_090_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__nor2_2 _193_ (.A(_076_),
.B(_077_),
.Y(_091_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__o2bb2a_2 _194_ (.A1_N(\pll_control.count0[1] ),
.A2_N(\pll_control.count1[1] ),
.B1(\pll_control.count0[1] ),
.B2(\pll_control.count1[1] ),
.X(_092_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__a22o_2 _195_ (.A1(\pll_control.count0[1] ),
.A2(\pll_control.count1[1] ),
.B1(_091_),
.B2(_092_),
.X(_093_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__inv_2 _196_ (.A(_093_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_094_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o2bb2a_2 _197_ (.A1_N(\pll_control.count0[2] ),
.A2_N(\pll_control.count1[2] ),
.B1(_090_),
.B2(_094_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_095_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a2bb2o_2 _198_ (.A1_N(_089_),
.A2_N(_095_),
.B1(_089_),
.B2(_095_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_096_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a21oi_2 _199_ (.A1(\pll_control.count0[2] ),
.A2(\pll_control.count1[2] ),
.B1(_090_),
.Y(_097_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a2bb2o_2 _200_ (.A1_N(_093_),
.A2_N(_097_),
.B1(_093_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B2(_097_),
.X(_098_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22oi_2 _201_ (.A1(div[3]),
.A2(_096_),
.B1(div[2]),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B2(_098_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.Y(_099_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _202_ (.A(div[3]),
.B(_096_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_100_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _203_ (.A(_100_),
.Y(_101_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o211a_2 _204_ (.A1(div[2]),
.A2(_098_),
.B1(_100_),
.C1(_099_),
.X(_102_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _205_ (.A(_102_),
.Y(_103_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o2bb2ai_2 _206_ (.A1_N(_091_),
.A2_N(_092_),
.B1(_091_),
.B2(_092_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_104_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nand2_2 _207_ (.A(div[1]),
.B(_104_),
.Y(_105_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a21oi_2 _208_ (.A1(_076_),
.A2(_077_),
.B1(_091_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_106_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _209_ (.A(_106_),
.Y(_107_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o221a_2 _210_ (.A1(div[1]),
.A2(_104_),
.B1(div[0]),
.B2(_107_),
.C1(_105_),
.X(_108_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a21oi_2 _211_ (.A1(div[1]),
.A2(_104_),
.B1(_108_),
.Y(_109_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _212_ (.A1(\pll_control.count0[4] ),
.A2(\pll_control.count1[4] ),
.B1(_072_),
.B2(_073_),
.X(_110_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o2bb2a_2 _213_ (.A1_N(\pll_control.count0[3] ),
.A2_N(\pll_control.count1[3] ),
.B1(_088_),
.B2(_095_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_111_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _214_ (.A(_110_),
.B(_111_),
.X(_112_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a21bo_2 _215_ (.A1(_110_),
.A2(_111_),
.B1_N(_112_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_113_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nand2_2 _216_ (.A(div[4]),
.B(_113_),
.Y(_114_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o221a_2 _217_ (.A1(_099_),
.A2(_101_),
.B1(_103_),
.B2(_109_),
.C1(_114_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_115_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o221ai_2 _218_ (.A1(_072_),
.A2(_073_),
.B1(div[4]),
.B2(_113_),
.C1(_112_),
.Y(_116_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _219_ (.A(_115_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(_116_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.X(_117_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _220_ (.A(_117_),
.Y(_118_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _221_ (.A(_081_),
.B(_082_),
.X(_119_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _222_ (.A(_119_),
.Y(_120_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or3_2 _223_ (.A(_079_),
.B(_080_),
.C(_119_),
.X(_015_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or3_2 _224_ (.A(_083_),
.B(_084_),
.C(_015_),
.X(_121_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o2111ai_2 _225_ (.A1(_085_),
.A2(_106_),
.B1(_108_),
.C1(_102_),
.D1(_114_),
.Y(_122_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__and4_2 _226_ (.A(\pll_control.prep[1] ),
.B(_087_),
.C(\pll_control.prep[2] ),
.D(\pll_control.prep[0] ),
.X(_123_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _227_ (.A(\pll_control.tint[1] ),
.B(\pll_control.tint[0] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_124_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _228_ (.A(_124_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_125_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _229_ (.A(\pll_control.tint[3] ),
.B(\pll_control.tint[2] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_126_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _230_ (.A(_126_),
.Y(_127_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _231_ (.A(_124_),
.B(_126_),
.X(_000_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _232_ (.A(\pll_control.tint[4] ),
.B(_000_),
.X(_001_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or3_2 _233_ (.A(\pll_control.tval[1] ),
.B(\pll_control.tval[0] ),
.C(_001_),
.X(_128_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o221a_2 _234_ (.A1(_116_),
.A2(_122_),
.B1(_117_),
.B2(_128_),
.C1(_123_),
.X(_129_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o31a_2 _235_ (.A1(_078_),
.A2(_118_),
.A3(_121_),
.B1(_129_),
.X(_130_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _236_ (.A(_130_),
.Y(_131_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _237_ (.A1(\pll_control.tval[1] ),
.A2(_118_),
.B1(_083_),
.B2(_117_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_132_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o22a_2 _238_ (.A1(_083_),
.A2(_117_),
.B1(_084_),
.B2(_132_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_133_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nor2_2 _239_ (.A(_120_),
.B(_125_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_134_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _240_ (.A1(\pll_control.tint[0] ),
.A2(_118_),
.B1(_082_),
.B2(_117_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_135_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o32a_2 _241_ (.A1(_134_),
.A2(_135_),
.A3(_133_),
.B1(_117_),
.B2(_125_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_136_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a22o_2 _242_ (.A1(\pll_control.tint[2] ),
.A2(_118_),
.B1(_080_),
.B2(_117_),
.X(_137_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o22a_2 _243_ (.A1(_079_),
.A2(_118_),
.B1(\pll_control.tint[3] ),
.B2(_117_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_138_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _244_ (.A(_138_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_139_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o32a_2 _245_ (.A1(_137_),
.A2(_138_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A3(_136_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(_117_),
.B2(_127_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_140_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _246_ (.A(_140_),
.Y(_141_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o22a_2 _247_ (.A1(\pll_control.tint[4] ),
.A2(_118_),
.B1(_078_),
.B2(_117_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_142_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _248_ (.A(_142_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_143_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a221o_2 _249_ (.A1(_141_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(_142_),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B1(_140_),
.B2(_143_),
.C1(_131_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_144_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o21ai_2 _250_ (.A1(_078_),
.A2(_130_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(_144_),
.Y(_063_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _251_ (.A(_136_),
.B(_137_),
.X(_145_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o21ai_2 _252_ (.A1(_080_),
.A2(_117_),
.B1(_145_),
.Y(_146_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _253_ (.A(_146_),
.Y(_147_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a221o_2 _254_ (.A1(_139_),
.A2(_146_),
.B1(_138_),
.B2(_147_),
.C1(_131_),
.X(_148_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o21ai_2 _255_ (.A1(_079_),
.A2(_130_),
.B1(_148_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_062_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nand2_2 _256_ (.A(_136_),
.B(_137_),
.Y(_149_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a32o_2 _257_ (.A1(_130_),
.A2(_145_),
.A3(_149_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.tint[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_131_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_061_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _258_ (.A(_133_),
.B(_135_),
.X(_150_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__mux2_1 _259_ (.A0(\pll_control.tint[0] ),
.A1(_118_),
.S(_133_),
.X(_151_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o211a_2 _260_ (.A1(_082_),
.A2(_117_),
.B1(_130_),
.C1(_151_),
.X(_152_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o2bb2a_2 _261_ (.A1_N(\pll_control.tint[1] ),
.A2_N(_152_),
.B1(\pll_control.tint[1] ),
.B2(_152_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_060_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nand2_2 _262_ (.A(_133_),
.B(_135_),
.Y(_153_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a32o_2 _263_ (.A1(_130_),
.A2(_150_),
.A3(_153_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.tint[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.B2(_131_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_059_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a2bb2o_2 _264_ (.A1_N(_084_),
.A2_N(_132_),
.B1(_084_),
.B2(_132_),
.X(_154_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o22ai_2 _265_ (.A1(_083_),
.A2(_130_),
.B1(_131_),
.B2(_154_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_058_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o22a_2 _266_ (.A1(\pll_control.tval[0] ),
.A2(_130_),
.B1(_084_),
.B2(_131_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_057_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or3_2 _267_ (.A(_075_),
.B(_076_),
.C(_074_),
.X(_155_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__inv_2 _268_ (.A(_155_),
.Y(_156_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nand2_2 _269_ (.A(\pll_control.count0[3] ),
.B(_156_),
.Y(_157_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a21oi_2 _270_ (.A1(_072_),
.A2(_157_),
.B1(_087_),
.Y(_056_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o221a_2 _271_ (.A1(\pll_control.count0[3] ),
.A2(_156_),
.B1(\pll_control.count0[4] ),
.B2(_157_),
.C1(_086_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_055_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__and4_2 _272_ (.A(\pll_control.count0[3] ),
.B(_156_),
.C(\pll_control.count0[4] ),
.D(_086_),
.X(_158_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o21ai_2 _273_ (.A1(_075_),
.A2(_076_),
.B1(_074_),
.Y(_159_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a31o_2 _274_ (.A1(_086_),
.A2(_155_),
.A3(_159_),
.B1(_158_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_054_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o221a_2 _275_ (.A1(_075_),
.A2(_076_),
.B1(\pll_control.count0[1] ),
.B2(\pll_control.count0[0] ),
.C1(_086_),
.X(_160_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _276_ (.A(_158_),
.B(_160_),
.X(_053_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a311o_2 _277_ (.A1(\pll_control.count0[3] ),
.A2(_156_),
.A3(\pll_control.count0[4] ),
.B1(_076_),
.C1(_087_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_052_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _278_ (.A(\pll_control.tint[4] ),
.B(_126_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_004_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _279_ (.A(\pll_control.tint[1] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(_004_),
.X(_007_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _280_ (.A(\pll_control.tint[3] ),
.B(_080_),
.X(_161_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o31a_2 _281_ (.A1(_124_),
.A2(_161_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A3(\pll_control.tint[4] ),
.B1(_004_),
.X(_009_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o31a_2 _282_ (.A1(\pll_control.tint[4] ),
.A2(_161_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A3(\pll_control.tint[1] ),
.B1(_004_),
.X(_013_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o31a_2 _283_ (.A1(\pll_control.tint[4] ),
.A2(_161_),
.A3(_120_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(_004_),
.X(_006_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o21a_2 _284_ (.A1(\pll_control.tint[4] ),
.A2(_161_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(_004_),
.X(_003_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o41a_2 _285_ (.A1(_079_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[2] ),
.A3(\pll_control.tint[4] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A4(_124_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(_003_),
.X(_010_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o41a_2 _286_ (.A1(_079_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[2] ),
.A3(\pll_control.tint[4] ),
.A4(\pll_control.tint[1] ),
.B1(_003_),
.X(_005_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o41a_2 _287_ (.A1(_079_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[2] ),
.A3(\pll_control.tint[4] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A4(_120_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(_003_),
.X(_012_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or2_2 _288_ (.A(_120_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(_004_),
.X(_011_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o31a_2 _289_ (.A1(_079_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[2] ),
.A3(\pll_control.tint[4] ),
.B1(_003_),
.X(_002_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a31o_2 _290_ (.A1(\pll_control.tint[3] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A3(_124_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.tint[4] ),
.X(_008_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__a31o_2 _291_ (.A1(\pll_control.tint[3] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[2] ),
.A3(\pll_control.tint[1] ),
.B1(\pll_control.tint[4] ),
.X(_014_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nand2_2 _292_ (.A(_078_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(_015_),
.Y(_022_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o311a_2 _293_ (.A1(\pll_control.tint[1] ),
.A2(_082_),
.A3(_126_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.tint[4] ),
.C1(_000_),
.X(_024_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or3_2 _294_ (.A(_124_),
.B(_161_),
.C(_078_),
.X(_162_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o311a_2 _295_ (.A1(_078_),
.A2(_126_),
.A3(_081_),
.B1(_162_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.C1(_024_),
.X(_017_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o41a_2 _296_ (.A1(\pll_control.tint[1] ),
.A2(_082_),
.A3(_161_),
.A4(_078_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(_017_),
.X(_025_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__or4_2 _297_ (.A(_079_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(\pll_control.tint[2] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.C(_124_),
.D(_078_),
.X(_163_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o311a_2 _298_ (.A1(_078_),
.A2(_161_),
.A3(_081_),
.B1(_163_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.C1(_025_),
.X(_016_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__and2_2 _299_ (.A(_018_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B(_022_),
.X(_019_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o41a_2 _300_ (.A1(_081_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[0] ),
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
.A3(_078_),
.A4(_161_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(_025_),
.X(_020_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__nor2_2 _301_ (.A(_078_),
.B(_127_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Y(_021_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__and3_2 _302_ (.A(\pll_control.tint[4] ),
.B(_126_),
.C(_161_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_027_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o31a_2 _303_ (.A1(_079_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A2(\pll_control.tint[2] ),
.A3(\pll_control.tint[1] ),
.B1(_027_),
.X(_023_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__o311a_2 _304_ (.A1(_120_),
.A2(_125_),
.A3(_126_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.B1(\pll_control.tint[4] ),
.C1(_000_),
.X(_028_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _305_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_049_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _306_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_048_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _307_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_047_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _308_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_046_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _309_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_045_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _310_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_044_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _311_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_043_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _312_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_042_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _313_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_041_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _314_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_040_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _315_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_039_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _316_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_038_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _317_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_037_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _318_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_036_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _319_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_035_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _320_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_034_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _321_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_033_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _322_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_032_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _323_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_031_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _324_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_030_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _325_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_029_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _326_ (.A(\pll_control.tint[4] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_026_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_1 _327_ (.A(_050_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(_051_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__buf_2 _328_ (.A(\pll_control.clock ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.X(clockp[0]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _329_ (.A0(_015_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(_000_),
.S(\pll_control.tint[4] ),
.X(_018_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _330_ (.A0(_012_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[11]),
.S(dco),
.X(\ringosc.dstage[11].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _331_ (.A0(_027_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[24]),
.S(dco),
.X(\ringosc.dstage[11].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _332_ (.A0(_011_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[10]),
.S(dco),
.X(\ringosc.dstage[10].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _333_ (.A0(_026_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[23]),
.S(dco),
.X(\ringosc.dstage[10].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _334_ (.A0(_010_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[9]),
.S(dco),
.X(\ringosc.dstage[9].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _335_ (.A0(_025_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[22]),
.S(dco),
.X(\ringosc.dstage[9].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _336_ (.A0(_009_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[8]),
.S(dco),
.X(\ringosc.dstage[8].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _337_ (.A0(_024_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[21]),
.S(dco),
.X(\ringosc.dstage[8].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _338_ (.A0(_008_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[7]),
.S(dco),
.X(\ringosc.dstage[7].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _339_ (.A0(_023_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[20]),
.S(dco),
.X(\ringosc.dstage[7].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _340_ (.A0(_007_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[6]),
.S(dco),
.X(\ringosc.dstage[6].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _341_ (.A0(_022_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[19]),
.S(dco),
.X(\ringosc.dstage[6].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _342_ (.A0(_006_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[5]),
.S(dco),
.X(\ringosc.dstage[5].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _343_ (.A0(_021_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[18]),
.S(dco),
.X(\ringosc.dstage[5].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _344_ (.A0(_005_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[4]),
.S(dco),
.X(\ringosc.dstage[4].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _345_ (.A0(_020_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[17]),
.S(dco),
.X(\ringosc.dstage[4].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _346_ (.A0(_004_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[3]),
.S(dco),
.X(\ringosc.dstage[3].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _347_ (.A0(_019_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[16]),
.S(dco),
.X(\ringosc.dstage[3].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _348_ (.A0(_003_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[2]),
.S(dco),
.X(\ringosc.dstage[2].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _349_ (.A0(_017_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[15]),
.S(dco),
.X(\ringosc.dstage[2].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _350_ (.A0(_002_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[1]),
.S(dco),
.X(\ringosc.dstage[1].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _351_ (.A0(_016_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[14]),
.S(dco),
.X(\ringosc.dstage[1].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _352_ (.A0(_001_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[0]),
.S(dco),
.X(\ringosc.dstage[0].id.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _353_ (.A0(_014_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[13]),
.S(dco),
.X(\ringosc.dstage[0].id.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _354_ (.A0(_013_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[12]),
.S(dco),
.X(\ringosc.iss.trim[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__mux2_1 _355_ (.A0(_028_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.A1(ext_trim[25]),
.S(dco),
.X(\ringosc.iss.trim[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _356_ (.D(osc),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.oscbuf[0] ),
.RESET_B(_029_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _357_ (.D(\pll_control.oscbuf[0] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.oscbuf[1] ),
.RESET_B(_030_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _358_ (.D(\pll_control.oscbuf[1] ),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.oscbuf[2] ),
.RESET_B(_031_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _359_ (.D(_052_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count0[0] ),
.RESET_B(_032_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _360_ (.D(_053_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count0[1] ),
.RESET_B(_033_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _361_ (.D(_054_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count0[2] ),
.RESET_B(_034_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _362_ (.D(_055_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count0[3] ),
.RESET_B(_035_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _363_ (.D(_056_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count0[4] ),
.RESET_B(_036_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _364_ (.D(_057_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.tval[0] ),
.RESET_B(_037_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _365_ (.D(_058_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.tval[1] ),
.RESET_B(_038_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _366_ (.D(_059_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.tint[0] ),
.RESET_B(_039_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _367_ (.D(_060_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.tint[1] ),
.RESET_B(_040_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _368_ (.D(_061_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.tint[2] ),
.RESET_B(_041_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _369_ (.D(_062_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.tint[3] ),
.RESET_B(_042_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _370_ (.D(_063_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.tint[4] ),
.RESET_B(_043_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _371_ (.D(_064_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.prep[0] ),
.RESET_B(_044_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _372_ (.D(_065_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.prep[1] ),
.RESET_B(_045_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _373_ (.D(_066_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.prep[2] ),
.RESET_B(_046_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _374_ (.D(_067_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count1[0] ),
.RESET_B(_047_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _375_ (.D(_068_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count1[1] ),
.RESET_B(_048_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _376_ (.D(_069_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count1[2] ),
.RESET_B(_049_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _377_ (.D(_070_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count1[3] ),
.RESET_B(_050_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
sky130_fd_sc_hd__dfrtp_2 _378_ (.D(_071_),
Add initial config for the digital_pll
2021-11-08 05:34:59 -06:00
.Q(\pll_control.count1[4] ),
.RESET_B(_051_),
.CLK(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[0].id.delaybuf0 (.A(\ringosc.dstage[0].id.in ),
.X(\ringosc.dstage[0].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[0].id.delaybuf1 (.A(\ringosc.dstage[0].id.ts ),
.X(\ringosc.dstage[0].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[0].id.delayen0 (.A(\ringosc.dstage[0].id.d2 ),
.TE(\ringosc.dstage[0].id.trim[0] ),
.Z(\ringosc.dstage[0].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[0].id.delayen1 (.A(\ringosc.dstage[0].id.d0 ),
.TE(\ringosc.dstage[0].id.trim[1] ),
.Z(\ringosc.dstage[0].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[0].id.delayenb0 (.A(\ringosc.dstage[0].id.ts ),
.TE_B(\ringosc.dstage[0].id.trim[0] ),
.Z(\ringosc.dstage[0].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[0].id.delayenb1 (.A(\ringosc.dstage[0].id.ts ),
.TE_B(\ringosc.dstage[0].id.trim[1] ),
.Z(\ringosc.dstage[0].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[0].id.delayint0 (.A(\ringosc.dstage[0].id.d1 ),
.Y(\ringosc.dstage[0].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[10].id.delaybuf0 (.A(\ringosc.dstage[10].id.in ),
.X(\ringosc.dstage[10].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[10].id.delaybuf1 (.A(\ringosc.dstage[10].id.ts ),
.X(\ringosc.dstage[10].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[10].id.delayen0 (.A(\ringosc.dstage[10].id.d2 ),
.TE(\ringosc.dstage[10].id.trim[0] ),
.Z(\ringosc.dstage[10].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[10].id.delayen1 (.A(\ringosc.dstage[10].id.d0 ),
.TE(\ringosc.dstage[10].id.trim[1] ),
.Z(\ringosc.dstage[10].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[10].id.delayenb0 (.A(\ringosc.dstage[10].id.ts ),
.TE_B(\ringosc.dstage[10].id.trim[0] ),
.Z(\ringosc.dstage[10].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[10].id.delayenb1 (.A(\ringosc.dstage[10].id.ts ),
.TE_B(\ringosc.dstage[10].id.trim[1] ),
.Z(\ringosc.dstage[10].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[10].id.delayint0 (.A(\ringosc.dstage[10].id.d1 ),
.Y(\ringosc.dstage[10].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[11].id.delaybuf0 (.A(\ringosc.dstage[10].id.out ),
.X(\ringosc.dstage[11].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[11].id.delaybuf1 (.A(\ringosc.dstage[11].id.ts ),
.X(\ringosc.dstage[11].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[11].id.delayen0 (.A(\ringosc.dstage[11].id.d2 ),
.TE(\ringosc.dstage[11].id.trim[0] ),
.Z(\ringosc.dstage[11].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[11].id.delayen1 (.A(\ringosc.dstage[11].id.d0 ),
.TE(\ringosc.dstage[11].id.trim[1] ),
.Z(\ringosc.dstage[11].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[11].id.delayenb0 (.A(\ringosc.dstage[11].id.ts ),
.TE_B(\ringosc.dstage[11].id.trim[0] ),
.Z(\ringosc.dstage[11].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[11].id.delayenb1 (.A(\ringosc.dstage[11].id.ts ),
.TE_B(\ringosc.dstage[11].id.trim[1] ),
.Z(\ringosc.dstage[11].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[11].id.delayint0 (.A(\ringosc.dstage[11].id.d1 ),
.Y(\ringosc.dstage[11].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[1].id.delaybuf0 (.A(\ringosc.dstage[0].id.out ),
.X(\ringosc.dstage[1].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[1].id.delaybuf1 (.A(\ringosc.dstage[1].id.ts ),
.X(\ringosc.dstage[1].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[1].id.delayen0 (.A(\ringosc.dstage[1].id.d2 ),
.TE(\ringosc.dstage[1].id.trim[0] ),
.Z(\ringosc.dstage[1].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[1].id.delayen1 (.A(\ringosc.dstage[1].id.d0 ),
.TE(\ringosc.dstage[1].id.trim[1] ),
.Z(\ringosc.dstage[1].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[1].id.delayenb0 (.A(\ringosc.dstage[1].id.ts ),
.TE_B(\ringosc.dstage[1].id.trim[0] ),
.Z(\ringosc.dstage[1].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[1].id.delayenb1 (.A(\ringosc.dstage[1].id.ts ),
.TE_B(\ringosc.dstage[1].id.trim[1] ),
.Z(\ringosc.dstage[1].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[1].id.delayint0 (.A(\ringosc.dstage[1].id.d1 ),
.Y(\ringosc.dstage[1].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[2].id.delaybuf0 (.A(\ringosc.dstage[1].id.out ),
.X(\ringosc.dstage[2].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[2].id.delaybuf1 (.A(\ringosc.dstage[2].id.ts ),
.X(\ringosc.dstage[2].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[2].id.delayen0 (.A(\ringosc.dstage[2].id.d2 ),
.TE(\ringosc.dstage[2].id.trim[0] ),
.Z(\ringosc.dstage[2].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[2].id.delayen1 (.A(\ringosc.dstage[2].id.d0 ),
.TE(\ringosc.dstage[2].id.trim[1] ),
.Z(\ringosc.dstage[2].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[2].id.delayenb0 (.A(\ringosc.dstage[2].id.ts ),
.TE_B(\ringosc.dstage[2].id.trim[0] ),
.Z(\ringosc.dstage[2].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[2].id.delayenb1 (.A(\ringosc.dstage[2].id.ts ),
.TE_B(\ringosc.dstage[2].id.trim[1] ),
.Z(\ringosc.dstage[2].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[2].id.delayint0 (.A(\ringosc.dstage[2].id.d1 ),
.Y(\ringosc.dstage[2].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[3].id.delaybuf0 (.A(\ringosc.dstage[2].id.out ),
.X(\ringosc.dstage[3].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[3].id.delaybuf1 (.A(\ringosc.dstage[3].id.ts ),
.X(\ringosc.dstage[3].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[3].id.delayen0 (.A(\ringosc.dstage[3].id.d2 ),
.TE(\ringosc.dstage[3].id.trim[0] ),
.Z(\ringosc.dstage[3].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[3].id.delayen1 (.A(\ringosc.dstage[3].id.d0 ),
.TE(\ringosc.dstage[3].id.trim[1] ),
.Z(\ringosc.dstage[3].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[3].id.delayenb0 (.A(\ringosc.dstage[3].id.ts ),
.TE_B(\ringosc.dstage[3].id.trim[0] ),
.Z(\ringosc.dstage[3].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[3].id.delayenb1 (.A(\ringosc.dstage[3].id.ts ),
.TE_B(\ringosc.dstage[3].id.trim[1] ),
.Z(\ringosc.dstage[3].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[3].id.delayint0 (.A(\ringosc.dstage[3].id.d1 ),
.Y(\ringosc.dstage[3].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[4].id.delaybuf0 (.A(\ringosc.dstage[3].id.out ),
.X(\ringosc.dstage[4].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[4].id.delaybuf1 (.A(\ringosc.dstage[4].id.ts ),
.X(\ringosc.dstage[4].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[4].id.delayen0 (.A(\ringosc.dstage[4].id.d2 ),
.TE(\ringosc.dstage[4].id.trim[0] ),
.Z(\ringosc.dstage[4].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[4].id.delayen1 (.A(\ringosc.dstage[4].id.d0 ),
.TE(\ringosc.dstage[4].id.trim[1] ),
.Z(\ringosc.dstage[4].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[4].id.delayenb0 (.A(\ringosc.dstage[4].id.ts ),
.TE_B(\ringosc.dstage[4].id.trim[0] ),
.Z(\ringosc.dstage[4].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[4].id.delayenb1 (.A(\ringosc.dstage[4].id.ts ),
.TE_B(\ringosc.dstage[4].id.trim[1] ),
.Z(\ringosc.dstage[4].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[4].id.delayint0 (.A(\ringosc.dstage[4].id.d1 ),
.Y(\ringosc.dstage[4].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[5].id.delaybuf0 (.A(\ringosc.dstage[4].id.out ),
.X(\ringosc.dstage[5].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[5].id.delaybuf1 (.A(\ringosc.dstage[5].id.ts ),
.X(\ringosc.dstage[5].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[5].id.delayen0 (.A(\ringosc.dstage[5].id.d2 ),
.TE(\ringosc.dstage[5].id.trim[0] ),
.Z(\ringosc.dstage[5].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[5].id.delayen1 (.A(\ringosc.dstage[5].id.d0 ),
.TE(\ringosc.dstage[5].id.trim[1] ),
.Z(\ringosc.dstage[5].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[5].id.delayenb0 (.A(\ringosc.dstage[5].id.ts ),
.TE_B(\ringosc.dstage[5].id.trim[0] ),
.Z(\ringosc.dstage[5].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[5].id.delayenb1 (.A(\ringosc.dstage[5].id.ts ),
.TE_B(\ringosc.dstage[5].id.trim[1] ),
.Z(\ringosc.dstage[5].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[5].id.delayint0 (.A(\ringosc.dstage[5].id.d1 ),
.Y(\ringosc.dstage[5].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[6].id.delaybuf0 (.A(\ringosc.dstage[5].id.out ),
.X(\ringosc.dstage[6].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[6].id.delaybuf1 (.A(\ringosc.dstage[6].id.ts ),
.X(\ringosc.dstage[6].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[6].id.delayen0 (.A(\ringosc.dstage[6].id.d2 ),
.TE(\ringosc.dstage[6].id.trim[0] ),
.Z(\ringosc.dstage[6].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[6].id.delayen1 (.A(\ringosc.dstage[6].id.d0 ),
.TE(\ringosc.dstage[6].id.trim[1] ),
.Z(\ringosc.dstage[6].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[6].id.delayenb0 (.A(\ringosc.dstage[6].id.ts ),
.TE_B(\ringosc.dstage[6].id.trim[0] ),
.Z(\ringosc.dstage[6].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[6].id.delayenb1 (.A(\ringosc.dstage[6].id.ts ),
.TE_B(\ringosc.dstage[6].id.trim[1] ),
.Z(\ringosc.dstage[6].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[6].id.delayint0 (.A(\ringosc.dstage[6].id.d1 ),
.Y(\ringosc.dstage[6].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[7].id.delaybuf0 (.A(\ringosc.dstage[6].id.out ),
.X(\ringosc.dstage[7].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[7].id.delaybuf1 (.A(\ringosc.dstage[7].id.ts ),
.X(\ringosc.dstage[7].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[7].id.delayen0 (.A(\ringosc.dstage[7].id.d2 ),
.TE(\ringosc.dstage[7].id.trim[0] ),
.Z(\ringosc.dstage[7].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[7].id.delayen1 (.A(\ringosc.dstage[7].id.d0 ),
.TE(\ringosc.dstage[7].id.trim[1] ),
.Z(\ringosc.dstage[7].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[7].id.delayenb0 (.A(\ringosc.dstage[7].id.ts ),
.TE_B(\ringosc.dstage[7].id.trim[0] ),
.Z(\ringosc.dstage[7].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[7].id.delayenb1 (.A(\ringosc.dstage[7].id.ts ),
.TE_B(\ringosc.dstage[7].id.trim[1] ),
.Z(\ringosc.dstage[7].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[7].id.delayint0 (.A(\ringosc.dstage[7].id.d1 ),
.Y(\ringosc.dstage[7].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[8].id.delaybuf0 (.A(\ringosc.dstage[7].id.out ),
.X(\ringosc.dstage[8].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[8].id.delaybuf1 (.A(\ringosc.dstage[8].id.ts ),
.X(\ringosc.dstage[8].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[8].id.delayen0 (.A(\ringosc.dstage[8].id.d2 ),
.TE(\ringosc.dstage[8].id.trim[0] ),
.Z(\ringosc.dstage[8].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[8].id.delayen1 (.A(\ringosc.dstage[8].id.d0 ),
.TE(\ringosc.dstage[8].id.trim[1] ),
.Z(\ringosc.dstage[8].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[8].id.delayenb0 (.A(\ringosc.dstage[8].id.ts ),
.TE_B(\ringosc.dstage[8].id.trim[0] ),
.Z(\ringosc.dstage[8].id.out ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[8].id.delayenb1 (.A(\ringosc.dstage[8].id.ts ),
.TE_B(\ringosc.dstage[8].id.trim[1] ),
.Z(\ringosc.dstage[8].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[8].id.delayint0 (.A(\ringosc.dstage[8].id.d1 ),
.Y(\ringosc.dstage[8].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[9].id.delaybuf0 (.A(\ringosc.dstage[8].id.out ),
.X(\ringosc.dstage[9].id.ts ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[9].id.delaybuf1 (.A(\ringosc.dstage[9].id.ts ),
.X(\ringosc.dstage[9].id.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[9].id.delayen0 (.A(\ringosc.dstage[9].id.d2 ),
.TE(\ringosc.dstage[9].id.trim[0] ),
.Z(\ringosc.dstage[10].id.in ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.dstage[9].id.delayen1 (.A(\ringosc.dstage[9].id.d0 ),
.TE(\ringosc.dstage[9].id.trim[1] ),
.Z(\ringosc.dstage[9].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.dstage[9].id.delayenb0 (.A(\ringosc.dstage[9].id.ts ),
.TE_B(\ringosc.dstage[9].id.trim[0] ),
.Z(\ringosc.dstage[10].id.in ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.dstage[9].id.delayenb1 (.A(\ringosc.dstage[9].id.ts ),
.TE_B(\ringosc.dstage[9].id.trim[1] ),
.Z(\ringosc.dstage[9].id.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[9].id.delayint0 (.A(\ringosc.dstage[9].id.d1 ),
.Y(\ringosc.dstage[9].id.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_2 \ringosc.ibufp00 (.A(\ringosc.dstage[0].id.in ),
.Y(\ringosc.c[0] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_8 \ringosc.ibufp01 (.A(\ringosc.c[0] ),
.Y(\pll_control.clock ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_2 \ringosc.ibufp10 (.A(\ringosc.dstage[5].id.out ),
.Y(\ringosc.c[1] ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_8 \ringosc.ibufp11 (.A(\ringosc.c[1] ),
.Y(clockp[1]),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__conb_1 \ringosc.iss.const1 (.HI(\ringosc.iss.one ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__or2_2 \ringosc.iss.ctrlen0 (.A(\ringosc.iss.reset ),
.B(\ringosc.iss.trim[0] ),
.X(\ringosc.iss.ctrl0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkbuf_1 \ringosc.iss.delaybuf0 (.A(\ringosc.dstage[11].id.out ),
.X(\ringosc.iss.d0 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.iss.delayen0 (.A(\ringosc.iss.d2 ),
.TE(\ringosc.iss.trim[0] ),
.Z(\ringosc.dstage[0].id.in ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_2 \ringosc.iss.delayen1 (.A(\ringosc.iss.d0 ),
.TE(\ringosc.iss.trim[1] ),
.Z(\ringosc.iss.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_8 \ringosc.iss.delayenb0 (.A(\ringosc.dstage[11].id.out ),
.TE_B(\ringosc.iss.ctrl0 ),
.Z(\ringosc.dstage[0].id.in ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvn_4 \ringosc.iss.delayenb1 (.A(\ringosc.dstage[11].id.out ),
.TE_B(\ringosc.iss.trim[1] ),
.Z(\ringosc.iss.d1 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__clkinv_1 \ringosc.iss.delayint0 (.A(\ringosc.iss.d1 ),
.Y(\ringosc.iss.d2 ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
sky130_fd_sc_hd__einvp_1 \ringosc.iss.reseten0 (.A(\ringosc.iss.one ),
.TE(\ringosc.iss.reset ),
.Z(\ringosc.dstage[0].id.in ),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
endmodule