2023-03-26 04:56:12 -05:00
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set ::env(DESIGN_NAME) caravel_core
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set ::env(ROUTING_CORES) 36
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set ::env(DESIGN_IS_CORE) 1
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set ::env(BASE_SDC_FILE) "$::env(DESIGN_DIR)/sdc_files/base.sdc"
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set ::env(RCX_SDC_FILE) "$::env(DESIGN_DIR)/sdc_files/rcx.sdc"
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set ::env(VERILOG_FILES) "\
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$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/user_defines.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/caravel_core.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/mgmt_protect.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/digital_pll.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/clock_div.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/gpio_control_block.v \
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$::env(MCW_ROOT)/verilog/rtl/mgmt_core_wrapper.v \
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$::env(MCW_ROOT)/verilog/rtl/mgmt_core.v \
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$::env(MCW_ROOT)/verilog/rtl/ibex_all.v \
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$::env(MCW_ROOT)/verilog/rtl/picorv32.v \
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$::env(MCW_ROOT)/verilog/rtl/VexRiscv_MinDebugCache.v \
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$::env(MCW_ROOT)/verilog/rtl/RAM256.v \
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"
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set ::env(RUN_KLAYOUT) 0
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# clock constraints
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set ::env(CLOCK_PORT) "clock_core"
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set ::env(CLOCK_NET) "caravel_clk"
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set ::env(CLOCK_PERIOD) 25
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# Synthesis
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set ::env(SYNTH_STRATEGY) "DELAY 1"
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set ::env(NO_SYNTH_CELL_LIST) $::env(DESIGN_DIR)/synth_configuration/no_synth.cells
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set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/synth_configuration/drc_exclude.cells
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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# set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
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set ::env(SYNTH_BUFFERING) 0
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set ::env(SYNTH_EXTRA_MAPPING_FILE) "$::env(DESIGN_DIR)/synth_configuration/yosys_mapping.v"
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2023-04-10 09:14:59 -05:00
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set ::env(SYNTH_MAX_FANOUT) 12
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2023-03-26 04:56:12 -05:00
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set ::env(SYNTH_CAP_LOAD) 52
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set ::env(SYNTH_CLOCK_TRANSITION) 0.6
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set ::env(SYNTH_CLOCK_UNCERTAINTY) 0.25
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2023-04-10 09:14:59 -05:00
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set ::env(SYNTH_MAX_TRAN) 0.50
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set ::env(QUIT_ON_SYNTH_CHECKS) 0
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2023-03-26 04:56:12 -05:00
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 3165 4767"
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set ::env(CORE_AREA) "10 10 3155 4757"
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set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/floorplan_configuration/pin_order.cfg
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set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/floorplan_configuration/io.def
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set ::env(FP_PDN_VERTICAL_HALO) "8"
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set ::env(FP_PDN_HORIZONTAL_HALO) "1"
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set ::env(FP_IO_MIN_DISTANCE) 5
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set ::env(FP_IO_VEXTEND) 2
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set ::env(FP_IO_HEXTEND) 2
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set ::env(FP_TAPCELL_DIST) 10
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2023-04-10 09:14:59 -05:00
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set ::env(PL_MACRO_HALO) "-1 -3"
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2023-03-26 04:56:12 -05:00
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# set ::env(CELL_PAD) 0
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## PDN
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set ::env(VSRC_LOC) $::env(DESIGN_DIR)/floorplan_configuration/Vsrc.loc
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set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
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set ::env(PDN_CFG) [glob $::env(DESIGN_DIR)/pdn_configuration/pdn.tcl]
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set ::env(FP_PDN_CHECK_NODES) 0
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set ::env(FP_PDN_CORE_RING) 1
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set ::env(FP_PDN_SKIPTRIM) 0
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set ::env(VDD_NETS) "vccd vccd1 vccd2 vdda1 vdda2 vddio"
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set ::env(GND_NETS) "vssd vssd1 vssd2 vssa1 vssa2 vssio"
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set ::env(FP_PDN_MACRO_HOOKS) {
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2023-04-21 01:17:38 -05:00
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user_id_value vccd vssd VPWR VGND,\
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housekeeping vccd vssd VPWR VGND,\
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mprj vccd1 vssd1 vccd1 vssd1,\
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mprj vccd2 vssd2 vccd2 vssd2,\
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mprj vdda1 vssa1 vdda1 vssa1,\
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mprj vdda2 vssa2 vdda2 vssa2,\
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soc.core.RAM256.BANK128\\\\\\[0\\\\\\].RAM128 vccd vssd VPWR VGND,\
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soc.core.RAM256.BANK128\\\\\\[1\\\\\\].RAM128 vccd vssd VPWR VGND,\
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soc.core.RAM0 vccd vssd vccd1 vssd1,\
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mgmt_buffers.mprj_logic_high_inst vccd1 vssd1 vccd1 vssd1,\
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mgmt_buffers.mprj2_logic_high_inst vccd2 vssd2 vccd2 vssd2,\
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mgmt_buffers.powergood_check vccd vssd vccd vssd,\
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mgmt_buffers.powergood_check vdda1 vssa1 vdda1 vssa1,\
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mgmt_buffers.powergood_check vdda2 vssa2 vdda2 vssa2,\
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gpio_control_bidir_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_bidir_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1a\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1a\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1a\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1a\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1a\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1a\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[6\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[7\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[8\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[9\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_1\\\\\\[10\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[6\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[7\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[8\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[9\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[10\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[11\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[12\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[13\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[14\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_in_2\\\\\\[15\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_bidir_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_bidir_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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gpio_control_bidir_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1,\
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spare_logic\\\\\\[0\\\\\\] vccd vssd vccd vssd,\
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spare_logic\\\\\\[1\\\\\\] vccd vssd vccd vssd,\
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spare_logic\\\\\\[2\\\\\\] vccd vssd vccd vssd,\
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spare_logic\\\\\\[3\\\\\\] vccd vssd vccd vssd,\
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clock_ctrl vccd vssd VPWR VGND,\
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por vddio vssio vdd3v3 vss3v3,\
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por vccd vssd vdd1v8 vss1v8,\
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rstb_level vddio vssio VPWR VGND,\
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rstb_level vccd vssd LVPWR LVGND\
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}
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set ::env(FP_PDN_CORE_RING_VWIDTH) 10
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set ::env(FP_PDN_CORE_RING_HWIDTH) 10
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set ::env(FP_PDN_CORE_RING_VSPACING) 2
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set ::env(FP_PDN_CORE_RING_VOFFSET) 1
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set ::env(FP_PDN_CORE_RING_HSPACING) 2
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set ::env(FP_PDN_CORE_RING_VOFFSET) 0
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set ::env(FP_PDN_CORE_RING_HOFFSET) 0
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set ::env(FP_PDN_VPITCH) 264
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set ::env(FP_PDN_HPITCH) 360
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set ::env(FP_PDN_VSPACING) 19
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set ::env(FP_PDN_HSPACING) 27
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set ::env(FP_PDN_VWIDTH) 3
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set ::env(FP_PDN_HWIDTH) 3
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set ::env(FP_PDN_HOFFSET) 30.65
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set ::env(FP_PDN_VOFFSET) 3.5
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##CTS
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set ::env(CLOCK_TREE_SYNTH) 1
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set ::env(CTS_MAX_CAP) 0.3
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set ::env(CTS_SINK_CLUSTERING_SIZE) 12
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set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) 30
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set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4}
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set ::env(CTS_CLK_MAX_WIRE_LENGTH) 1000
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##PLACEMENT
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set ::env(PL_ROUTABILITY_DRIVEN) 0
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set ::env(PL_TIME_DRIVEN) 1
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set ::env(PL_WIRELENGTH_COEF) 0.01
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set ::env(PL_TARGET_DENSITY) 0.24
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
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set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.03
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set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 0
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set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) 0.1
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set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 1000
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set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 50
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set ::env(PL_RESIZER_MAX_CAP_MARGIN) 50
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##ROUTING
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set ::env(GRT_ALLOW_CONGESTION) 1
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2023-04-21 01:17:38 -05:00
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set ::env(GRT_ADJUSTMENT) 0.10
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2023-03-26 04:56:12 -05:00
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## li1 ,met1,met2,met3,met4,met5
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# set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0.10,0.05,0.10,0.05,0.00"
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# set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0.20,0.10,0.20,0.05,0.00"
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# set ::env(GRT_OVERFLOW_ITERS) 60
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set ::env(GRT_ESTIMATE_PARASITICS) 1
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
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set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.05
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set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) 1
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set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) 600
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2023-04-10 09:14:59 -05:00
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set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) 30
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set ::env(GLB_RESIZER_MAX_CAP_MARGIN) 30
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2023-03-26 04:56:12 -05:00
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## Antenna
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2023-04-10 09:14:59 -05:00
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set ::env(GRT_REPAIR_ANTENNAS) 1
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set ::env(RUN_HEURISTIC_DIODE_INSERTION) 1
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set ::env(HEURISTIC_ANTENNA_THRESHOLD) 80
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set ::env(DIODE_ON_PORTS) "none"
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2023-04-21 01:17:38 -05:00
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set ::env(GRT_ANT_MARGIN) 10
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2023-03-26 04:56:12 -05:00
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set ::env(GRT_ANT_ITERS) 12
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set ::env(GRT_MAX_DIODE_INS_ITERS) 4
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set ::env(DIODE_PADDING) 0
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## MACROS
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set ::env(MACRO_PLACEMENT_CFG_1) [glob $::env(DESIGN_DIR)/floorplan_configuration//macro_placement_1.cfg]
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set ::env(MACRO_PLACEMENT_CFG_2) [glob $::env(DESIGN_DIR)/floorplan_configuration//macro_placement_2.cfg]
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set ::env(MACRO_PLACEMENT_CFG_3) [glob $::env(DESIGN_DIR)/floorplan_configuration//macro_placement_3.cfg]
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
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2023-04-21 01:17:38 -05:00
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$::env(CARAVEL_ROOT)/verilog/rtl/user_id_programming.v \
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2023-03-26 04:56:12 -05:00
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$::env(CARAVEL_ROOT)/verilog/rtl/__user_project_wrapper.v \
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$::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/simple_por.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/xres_buf.v \
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$::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v \
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$::env(CARAVEL_ROOT)/verilog/gl/mprj_io_buffer.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/gpio_defaults_block.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/mprj_logic_high.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/mprj2_logic_high.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/mgmt_protect_hv.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/gpio_logic_high.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/empty_macro.v \
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$::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v \
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$::env(CARAVEL_ROOT)/verilog/rtl/manual_power_connections.v \
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$::env(MCW_ROOT)/verilog/gl/RAM128.v \
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"
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set ::env(EXTRA_LEFS) "\
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2023-04-21 01:17:38 -05:00
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$::env(CARAVEL_ROOT)/lef/user_id_programming.lef \
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2023-03-26 04:56:12 -05:00
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$::env(CARAVEL_ROOT)/lef/user_project_wrapper_empty.lef \
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$::env(CARAVEL_ROOT)/lef/housekeeping.lef \
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$::env(CARAVEL_ROOT)/lef/simple_por.lef \
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$::env(CARAVEL_ROOT)/lef/xres_buf.lef \
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$::env(CARAVEL_ROOT)/lef/spare_logic_block.lef \
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$::env(CARAVEL_ROOT)/lef/mprj_io_buffer.lef \
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$::env(CARAVEL_ROOT)/lef/gpio_defaults_block.lef \
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$::env(CARAVEL_ROOT)/lef/mprj_logic_high.lef \
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$::env(CARAVEL_ROOT)/lef/mprj2_logic_high.lef \
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$::env(CARAVEL_ROOT)/lef/mgmt_protect_hv.lef \
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$::env(CARAVEL_ROOT)/lef/gpio_logic_high.lef \
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$::env(CARAVEL_ROOT)/lef/empty_macro.lef \
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$::env(CARAVEL_ROOT)/lef/caravel_clocking.lef \
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$::env(CARAVEL_ROOT)/lef/manual_power_connections.lef \
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$::env(MCW_ROOT)/lef/RAM128.lef \
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"
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set ::env(EXTRA_GDS_FILES) "\
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2023-04-21 01:17:38 -05:00
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$::env(CARAVEL_ROOT)/gds/user_id_programming.gds \
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2023-03-26 04:56:12 -05:00
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$::env(CARAVEL_ROOT)/gds/user_project_wrapper_empty.gds \
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$::env(CARAVEL_ROOT)/gds/housekeeping.gds \
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$::env(CARAVEL_ROOT)/gds/simple_por.gds \
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$::env(CARAVEL_ROOT)/gds/xres_buf.gds \
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$::env(CARAVEL_ROOT)/gds/spare_logic_block.gds \
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$::env(CARAVEL_ROOT)/gds/mprj_io_buffer.gds \
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$::env(CARAVEL_ROOT)/gds/gpio_defaults_block.gds \
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$::env(CARAVEL_ROOT)/gds/mprj_logic_high.gds \
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$::env(CARAVEL_ROOT)/gds/mprj2_logic_high.gds \
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$::env(CARAVEL_ROOT)/gds/mgmt_protect_hv.gds \
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$::env(CARAVEL_ROOT)/gds/gpio_logic_high.gds \
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$::env(CARAVEL_ROOT)/gds/empty_macro.gds \
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$::env(CARAVEL_ROOT)/gds/caravel_clocking.gds \
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$::env(CARAVEL_ROOT)/gds/manual_power_connections.gds \
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$::env(MCW_ROOT)/gds/RAM128.gds \
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"
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set ::env(EXTRA_LIBS) "\
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$::env(CARAVEL_ROOT)/lib/housekeeping.lib \
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$::env(CARAVEL_ROOT)/lib/gpio_defaults_block.lib \
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$::env(CARAVEL_ROOT)/lib/gpio_logic_high.lib \
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$::env(CARAVEL_ROOT)/lib/mprj_io_buffer.lib \
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$::env(CARAVEL_ROOT)/lib/user_project_wrapper.lib \
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$::env(CARAVEL_ROOT)/lib/caravel_clocking.lib \
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2023-03-27 06:44:22 -05:00
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$::env(MCW_ROOT)/signoff/RAM128/primetime/lib/ff/RAM128.nom.lib \
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2023-03-26 04:56:12 -05:00
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"
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set ::env(STA_WRITE_LIB) 0
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## For faster development
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2023-03-27 06:44:22 -05:00
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set ::env(QUIT_ON_TR_DRC) 1
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2023-03-26 04:56:12 -05:00
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set ::env(QUIT_ON_LVS_ERROR) 0
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set ::env(QUIT_ON_MAGIC_DRC) 0
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set ::env(MAGIC_DEF_LABELS) 0
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set ::env(MAGIC_EXT_USE_GDS) 1
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set ::env(RSZ_DONT_TOUCH_RX) "analog_io|rstb_h|porb_h|serial_clock_out|serial_load_out|ringosc|mgmt_buffers.la_data_out_core|mprj_ack_i_user|mprj_dat_i_user|user_irq_core"
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