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riscv
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caravel
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https://github.com/efabless/caravel.git
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581a22de6a
caravel
/
openlane
/
caravel_clocking
/
pin_order.cfg
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[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
#E
ext_clk_sel
sel.*
ext_reset
#N
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
resetb
ext_clk
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 07:50:43 -06:00
core_clk
user_clk
[DATA] Update caravel_clocking module floorplan
2021-11-18 17:26:29 -06:00
resetb_sync
pll_clk
pll_clk90