caravel/signoff/housekeeping/final_summary_report.csv

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2021-11-15 05:23:54 -06:00
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
0,/home/ma/ef/caravel_openframe/openlane/housekeeping,housekeeping,housekeeping,flow completed,0h39m31s0ms,0h37m42s0ms,64674.9825043381,0.16541171850000005,32337.49125216905,37.46,1616.74,5349,0,0,0,0,0,0,0,42,0,0,-1,446748,59229,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,309469063.0,26.33,38.36,61.77,16.2,33.59,0.98,8470,9604,194,1275,0,0,0,9231,0,0,0,0,0,0,0,4,1067,991,49,388,2156,0,2544,100.0,10.0,10.0,AREA 0,20,50,1,153.6,153.18,0.37799999999999995,0.06,sky130_fd_sc_hd,0,3