caravel/xschem/run_simple_por_lvs.sh

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Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
#!/bin/bash
#---------------------------------------------------------------------------
#
# Run LVS on the simple_por.
#
#---------------------------------------------------------------------------
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
echo ${PDK:=sky130A} > /dev/null
# Extract full layout netlist
cd ../mag
if [ ! -f simple_por.spice ]; then
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
drc off
crashbackups stop
load simple_por
extract do local
extract all
ext2spice lvs
ext2spice
EOF
rm -f *.ext
fi
cd ../xschem
# Generate script for netgen
cat > netgen.tcl << EOF
# Load top level netlist
puts stdout "Reading layout netlist simple_por.spice"
set circuit1 [readnet spice ../mag/simple_por.spice]
puts stdout "Reading schematic netlist simple_por.spice"
set circuit2 [readnet spice simple_por.spice]
# Read additional subcircuits into the netlist of circuit2
puts stdout "Reading standard cell netlists"
readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice \$circuit2
# Run LVS
lvs "\$circuit1 simple_por" "\$circuit2 simple_por" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl simple_por_comp.out
EOF
export NETGEN_COLUMNS=60
netgen -batch source netgen.tcl
rm netgen.tcl
# mv simple_por_comp.out ../signoff/
exit 0