caravel/lef/gpio_control_block.lef

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2021-11-04 09:19:12 -05:00
VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO gpio_control_block
CLASS BLOCK ;
FOREIGN gpio_control_block ;
ORIGIN 0.000 0.000 ;
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SIZE 170.000 BY 65.000 ;
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PIN gpio_defaults[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 4.690 61.000 4.970 65.000 ;
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END
END gpio_defaults[0]
PIN gpio_defaults[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 27.690 61.000 27.970 65.000 ;
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END
END gpio_defaults[10]
PIN gpio_defaults[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 29.990 61.000 30.270 65.000 ;
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END
END gpio_defaults[11]
PIN gpio_defaults[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 32.290 61.000 32.570 65.000 ;
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END
END gpio_defaults[12]
PIN gpio_defaults[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 6.990 61.000 7.270 65.000 ;
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END
END gpio_defaults[1]
PIN gpio_defaults[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 9.290 61.000 9.570 65.000 ;
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END
END gpio_defaults[2]
PIN gpio_defaults[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 11.590 61.000 11.870 65.000 ;
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END
END gpio_defaults[3]
PIN gpio_defaults[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 13.890 61.000 14.170 65.000 ;
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END
END gpio_defaults[4]
PIN gpio_defaults[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 16.190 61.000 16.470 65.000 ;
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END
END gpio_defaults[5]
PIN gpio_defaults[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 18.490 61.000 18.770 65.000 ;
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END
END gpio_defaults[6]
PIN gpio_defaults[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 20.790 61.000 21.070 65.000 ;
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END
END gpio_defaults[7]
PIN gpio_defaults[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 23.090 61.000 23.370 65.000 ;
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END
END gpio_defaults[8]
PIN gpio_defaults[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
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LAYER met2 ;
RECT 25.390 61.000 25.670 65.000 ;
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END
END gpio_defaults[9]
PIN mgmt_gpio_in
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 70.000 4.120 170.000 4.720 ;
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END
END mgmt_gpio_in
PIN mgmt_gpio_oeb
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 8.200 170.000 8.800 ;
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END
END mgmt_gpio_oeb
PIN mgmt_gpio_out
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 10.240 170.000 10.840 ;
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END
END mgmt_gpio_out
PIN one
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 70.000 6.160 170.000 6.760 ;
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END
END one
PIN pad_gpio_ana_en
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 12.280 170.000 12.880 ;
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END
END pad_gpio_ana_en
PIN pad_gpio_ana_pol
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 14.320 170.000 14.920 ;
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END
END pad_gpio_ana_pol
PIN pad_gpio_ana_sel
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 16.360 170.000 16.960 ;
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END
END pad_gpio_ana_sel
PIN pad_gpio_dm[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 18.400 170.000 19.000 ;
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END
END pad_gpio_dm[0]
PIN pad_gpio_dm[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 20.440 170.000 21.040 ;
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END
END pad_gpio_dm[1]
PIN pad_gpio_dm[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 22.480 170.000 23.080 ;
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END
END pad_gpio_dm[2]
PIN pad_gpio_holdover
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 24.520 170.000 25.120 ;
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END
END pad_gpio_holdover
PIN pad_gpio_ib_mode_sel
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 26.560 170.000 27.160 ;
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END
END pad_gpio_ib_mode_sel
PIN pad_gpio_in
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 28.600 170.000 29.200 ;
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END
END pad_gpio_in
PIN pad_gpio_inenb
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 30.640 170.000 31.240 ;
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END
END pad_gpio_inenb
PIN pad_gpio_out
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 32.680 170.000 33.280 ;
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END
END pad_gpio_out
PIN pad_gpio_outenb
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 34.720 170.000 35.320 ;
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END
END pad_gpio_outenb
PIN pad_gpio_slow_sel
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 36.760 170.000 37.360 ;
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END
END pad_gpio_slow_sel
PIN pad_gpio_vtrip_sel
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 38.800 170.000 39.400 ;
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END
END pad_gpio_vtrip_sel
PIN resetn
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 40.840 170.000 41.440 ;
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END
END resetn
PIN resetn_out
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 42.880 170.000 43.480 ;
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END
END resetn_out
PIN serial_clock
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 44.920 170.000 45.520 ;
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END
END serial_clock
PIN serial_clock_out
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 46.960 170.000 47.560 ;
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END
END serial_clock_out
PIN serial_data_in
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 49.000 170.000 49.600 ;
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END
END serial_data_in
PIN serial_data_out
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 51.040 170.000 51.640 ;
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END
END serial_data_out
PIN serial_load
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 53.080 170.000 53.680 ;
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END
END serial_load
PIN serial_load_out
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 55.120 170.000 55.720 ;
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END
END serial_load_out
PIN user_gpio_in
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 57.160 170.000 57.760 ;
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END
END user_gpio_in
PIN user_gpio_oeb
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 59.200 170.000 59.800 ;
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END
END user_gpio_oeb
PIN user_gpio_out
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 61.240 170.000 61.840 ;
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END
END user_gpio_out
PIN vccd
DIRECTION INOUT ;
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USE POWER ;
PORT
LAYER met4 ;
RECT 12.800 2.480 14.400 60.080 ;
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END
PORT
LAYER met4 ;
RECT 37.800 2.480 39.400 60.080 ;
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END
PORT
LAYER met5 ;
RECT 4.360 5.900 50.000 7.500 ;
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END
PORT
LAYER met5 ;
RECT 4.360 22.800 50.000 24.400 ;
END
PORT
LAYER met5 ;
RECT 4.360 39.700 50.000 41.300 ;
END
PORT
LAYER met5 ;
RECT 4.360 56.600 50.000 58.200 ;
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END
END vccd
PIN vccd1
DIRECTION INOUT ;
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USE POWER ;
PORT
LAYER met4 ;
RECT 17.800 2.480 19.400 60.080 ;
END
PORT
LAYER met4 ;
RECT 42.800 2.480 44.400 60.080 ;
END
PORT
LAYER met5 ;
RECT 4.360 11.140 50.000 12.740 ;
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END
PORT
LAYER met5 ;
RECT 4.360 28.040 50.000 29.640 ;
END
PORT
LAYER met5 ;
RECT 4.360 44.940 50.000 46.540 ;
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END
END vccd1
PIN vssd
DIRECTION INOUT ;
USE GROUND ;
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PORT
LAYER met4 ;
RECT 25.300 2.480 26.900 60.080 ;
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END
PORT
LAYER met5 ;
RECT 4.360 14.350 50.000 15.950 ;
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END
PORT
LAYER met5 ;
RECT 4.360 31.250 50.000 32.850 ;
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END
PORT
LAYER met5 ;
RECT 4.360 48.150 50.000 49.750 ;
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END
END vssd
PIN vssd1
DIRECTION INOUT ;
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USE GROUND ;
PORT
LAYER met4 ;
RECT 30.300 2.480 31.900 60.080 ;
END
PORT
LAYER met5 ;
RECT 4.360 19.590 50.000 21.190 ;
END
PORT
LAYER met5 ;
RECT 4.360 36.490 50.000 38.090 ;
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END
PORT
LAYER met5 ;
RECT 4.360 53.390 50.000 54.990 ;
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END
END vssd1
PIN zero
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
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RECT 70.000 2.080 170.000 2.680 ;
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END
END zero
OBS
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RECT 0.000 64.845 49.815 64.930 ;
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RECT 49.815 64.845 169.810 64.930 ;
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RECT 0.000 59.925 169.810 64.845 ;
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RECT 16.795 7.905 169.810 8.075 ;
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2021-11-04 09:19:12 -05:00
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END
END gpio_control_block
END LIBRARY