mirror of https://github.com/efabless/caravel.git
125 lines
3.4 KiB
Tcl
125 lines
3.4 KiB
Tcl
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) mgmt_protect
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set ::env(ROUTING_CORES) 6
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/defines.v\
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$script_dir/../../verilog/rtl/mgmt_protect.v"
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set ::env(RUN_KLAYOUT) 0
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# virtual clock
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set ::env(CLOCK_PERIOD) 8
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set ::env(CLOCK_PORT) ""
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# Synthesis
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
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set ::env(CLOCK_TREE_SYNTH) 0
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 1100 120"
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set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
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set ::env(FP_VERTICAL_HALO) 14
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set ::env(FP_HORIZONTAL_HALO) 14
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set ::env(FP_IO_MIN_DISTANCE) 5
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set ::env(BOTTOM_MARGIN_MULT) 2
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set ::env(TOP_MARGIN_MULT) 2
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set ::env(LEFT_MARGIN_MULT) 12
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set ::env(RIGHT_MARGIN_MULT) 12
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set ::env(FP_IO_VEXTEND) 2
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set ::env(FP_IO_HEXTEND) 2
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set ::env(CELL_PAD) 0
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## PDN
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set ::env(PDN_CFG) $script_dir/pdn.tcl
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set ::env(FP_PDN_CHECK_NODES) 0
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set ::env(FP_PDN_IRDROP) "0"
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set ::env(FP_PDN_AUTO_ADJUST) 0
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set ::env(FP_PDN_VOFFSET) 15
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set ::env(FP_PDN_HOFFSET) 5
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set ::env(FP_PDN_VWIDTH) 0.9
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set ::env(FP_PDN_HWIDTH) 0.9
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set ::env(FP_PDN_VPITCH) 150.5
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set ::env(FP_PDN_HPITCH) 5.44
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set ::env(FP_PDN_VSPACING) 3.2
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set ::env(FP_PDN_CORE_RING) 0
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set ::env(FP_PDN_CORE_RING_VWIDTH) 0.9
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set ::env(FP_PDN_CORE_RING_HWIDTH) 0.9
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set ::env(FP_PDN_CORE_RING_VOFFSET) 7
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set ::env(FP_PDN_CORE_RING_HOFFSET) 7
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set ::env(FP_PDN_CORE_RING_VSPACING) 0.42
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set ::env(FP_PDN_CORE_RING_HSPACING) 0.42
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set ::env(FP_PDN_LOWER_LAYER) met4
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set ::env(FP_PDN_UPPER_LAYER) met3
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set ::env(VDD_NETS) "vccd vccd1 vccd2 vdda1 vdda2"
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set ::env(GND_NETS) "vssd vssd1 vssd2 vssa1 vssa2"
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.17
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 25
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## Routing
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set ::env(GLB_RT_MINLAYER) 2
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set ::env(GLB_RT_MAXLAYER) 5
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set ::env(GLB_RT_ADJUSTMENT) 0.00
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set ::env(GLB_RT_OVERFLOW_ITERS) 250
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set ::env(GLB_RT_ALLOW_CONGESTION) 1
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) 1
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## Internal Macros
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set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$script_dir/../../verilog/rtl/mprj_logic_high.v\
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$script_dir/../../verilog/rtl/mprj2_logic_high.v\
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$script_dir/../../verilog/rtl/mgmt_protect_hv.v"
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set ::env(EXTRA_LEFS) "\
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$script_dir/../../lef/mprj_logic_high.lef\
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$script_dir/../../lef/mprj2_logic_high.lef\
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$script_dir/../../lef/mgmt_protect_hv.lef"
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set ::env(EXTRA_GDS_FILES) "\
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$script_dir/../../gds/mprj_logic_high.gds\
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$script_dir/../../gds/mprj2_logic_high.gds\
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$script_dir/../../gds/mgmt_protect_hv.gds"
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## LVS
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set ::env(QUIT_ON_LVS_ERROR) 0
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