mirror of https://github.com/efabless/caravel.git
61 lines
1.8 KiB
Tcl
61 lines
1.8 KiB
Tcl
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) "housekeeping"
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set ::env(ROUTING_CORES) 6
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set ::env(RUN_KLAYOUT) 0
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/defines.v\
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$script_dir/../../verilog/rtl/housekeeping_spi.v\
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$script_dir/../../verilog/rtl/housekeeping.v"
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set ::env(CLOCK_PORT) "wb_clk_i"
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set ::env(CLOCK_NET) {$::env(CLOCK_PORT) csclk mgmt_gpio_in\[4\]}
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set ::env(BASE_SDC_FILE) $script_dir/base.sdc
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## Synthesis
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set ::env(NO_SYNTH_CELL_LIST) $script_dir/no_synth.list
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set ::env(SYNTH_MAX_FANOUT) 5
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## Floorplan
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 300.230 550.950"
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set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
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set ::env(FP_IO_MIN_DISTANCE) 2
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set ::env(CELL_PAD) 0
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## Routing
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set ::env(GLB_RT_ADJUSTMENT) 0.05
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set ::env(GLB_RT_OVERFLOW_ITERS) 100
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## Placement
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set ::env(PL_TARGET_DENSITY) 0.384
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set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "30"
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## Diode Insertion
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set ::env(DIODE_INSERTION_STRATEGY) "3"
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# Disbale timing checks for now till the issue with the clock gating path is fixed
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# The timing reports show only one violating path from the mgmt_gpio_
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set ::env(QUIT_ON_TIMING_VIOLATIONS) 0
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