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caravel/verilog/rtl/pads.v

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Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
// `default_nettype none
`ifndef TOP_ROUTING
`define USER1_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
.AMUXBUS_B(analog_b),\
.VSSA(vssa1),\
.VDDA(vdda1),\
.VSWITCH(vddio),\
.VDDIO_Q(vddio_q),\
.VCCHIB(vccd),\
.VDDIO(vddio),\
Modified the padframe definition to keep the vccd domain continuous around the entire padframe. The vccd1 and vccd2 domains are local to their respective pads, and any bus routing must be done inside the padframe. This means that all pads operate on global vddio for 3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage domain only goes as far as the input to the GPIO control block.
2021-11-03 09:53:09 -05:00
.VCCD(vccd),\
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.VSSIO(vssio),\
Modified the padframe definition to keep the vccd domain continuous around the entire padframe. The vccd1 and vccd2 domains are local to their respective pads, and any bus routing must be done inside the padframe. This means that all pads operate on global vddio for 3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage domain only goes as far as the input to the GPIO control block.
2021-11-03 09:53:09 -05:00
.VSSD(vssd),\
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 18:38:24 -06:00
.VSSIO_Q(vssio_q),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`define USER2_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
.AMUXBUS_B(analog_b),\
.VSSA(vssa2),\
.VDDA(vdda2),\
.VSWITCH(vddio),\
.VDDIO_Q(vddio_q),\
.VCCHIB(vccd),\
.VDDIO(vddio),\
Modified the padframe definition to keep the vccd domain continuous around the entire padframe. The vccd1 and vccd2 domains are local to their respective pads, and any bus routing must be done inside the padframe. This means that all pads operate on global vddio for 3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage domain only goes as far as the input to the GPIO control block.
2021-11-03 09:53:09 -05:00
.VCCD(vccd),\
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.VSSIO(vssio),\
Modified the padframe definition to keep the vccd domain continuous around the entire padframe. The vccd1 and vccd2 domains are local to their respective pads, and any bus routing must be done inside the padframe. This means that all pads operate on global vddio for 3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage domain only goes as far as the input to the GPIO control block.
2021-11-03 09:53:09 -05:00
.VSSD(vssd),\
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 18:38:24 -06:00
.VSSIO_Q(vssio_q),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`define MGMT_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
.AMUXBUS_B(analog_b),\
.VSSA(vssa),\
.VDDA(vdda),\
.VSWITCH(vddio),\
.VDDIO_Q(vddio_q),\
.VCCHIB(vccd),\
.VDDIO(vddio),\
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 18:38:24 -06:00
.VSSIO_Q(vssio_q),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`else
`define USER1_ABUTMENT_PINS
`define USER2_ABUTMENT_PINS
`define MGMT_ABUTMENT_PINS
`endif
`define HVCLAMP_PINS(H,L) \
.DRN_HVC(H), \
.SRC_BDY_HVC(L)
`define LVCLAMP_PINS(H1,L1,H2,L2,L3) \
.BDY2_B2B(L3), \
.DRN_LVC1(H1), \
.DRN_LVC2(H2), \
.SRC_BDY_LVC1(L1), \
.SRC_BDY_LVC2(L2)
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
`define INPUT_PAD(X,Y,CONB_ONE) \
wire loop_zero_``X; \
wire loop_one_``X; \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 18:38:24 -06:00
.PAD(X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.OUT(loop_zero_``X), \
.OE_N(CONB_ONE), \
.HLD_H_N(loop_one_``X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.ENABLE_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.ENABLE_INP_H(loop_zero_``X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.ENABLE_VDDA_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.INP_DIS(por), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.IB_MODE_SEL(loop_zero_``X), \
.VTRIP_SEL(loop_zero_``X), \
.SLOW(loop_zero_``X), \
.HLD_OVR(loop_zero_``X), \
.ANALOG_EN(loop_zero_``X), \
.ANALOG_SEL(loop_zero_``X), \
.ANALOG_POL(loop_zero_``X), \
.DM({loop_zero_``X, loop_zero_``X, vccd}), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(Y), \
.IN_H(), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X) )
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
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`define OUTPUT_PAD(X,Y,CONB_ONE,INPUT_DIS,OUT_EN_N) \
wire loop_zero_``X; \
wire loop_one_``X; \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 18:38:24 -06:00
.PAD(X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.HLD_H_N(loop_one_``X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.ENABLE_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.ENABLE_INP_H(loop_zero_``X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.ENABLE_VDDA_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.INP_DIS(INPUT_DIS), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.IB_MODE_SEL(loop_zero_``X), \
.VTRIP_SEL(loop_zero_``X), \
.SLOW(loop_zero_``X), \
.HLD_OVR(loop_zero_``X), \
.ANALOG_EN(loop_zero_``X), \
.ANALOG_SEL(loop_zero_``X), \
.ANALOG_POL(loop_zero_``X), \
.DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \
Made several corrections to errors found in the netlists: (1) Fixed rstb_h, which was being input to low-voltage blocks. (2) Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not output from housekeeping as they should be; the solution was to tie the INP_DIS lines low at the pad by connecting them to the TIE_LO_ESD line. This should probably be addressed in housekeeping but would change the current pinout.
2021-11-22 14:21:06 -06:00
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(), \
.IN_H(), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X))
Made several corrections to errors found in the netlists: (1) Fixed rstb_h, which was being input to low-voltage blocks. (2) Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not output from housekeeping as they should be; the solution was to tie the INP_DIS lines low at the pad by connecting them to the TIE_LO_ESD line. This should probably be addressed in housekeeping but would change the current pinout.
2021-11-22 14:21:06 -06:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
`define OUTPUT_NO_INP_DIS_PAD(X,Y,CONB_ONE,OUT_EN_N) \
wire loop_zero_``X; \
wire loop_one_``X; \
Made several corrections to errors found in the netlists: (1) Fixed rstb_h, which was being input to low-voltage blocks. (2) Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not output from housekeeping as they should be; the solution was to tie the INP_DIS lines low at the pad by connecting them to the TIE_LO_ESD line. This should probably be addressed in housekeeping but would change the current pinout.
2021-11-22 14:21:06 -06:00
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 18:38:24 -06:00
.PAD(X), \
Made several corrections to errors found in the netlists: (1) Fixed rstb_h, which was being input to low-voltage blocks. (2) Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not output from housekeeping as they should be; the solution was to tie the INP_DIS lines low at the pad by connecting them to the TIE_LO_ESD line. This should probably be addressed in housekeeping but would change the current pinout.
2021-11-22 14:21:06 -06:00
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.HLD_H_N(loop_one_``X), \
Made several corrections to errors found in the netlists: (1) Fixed rstb_h, which was being input to low-voltage blocks. (2) Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not output from housekeeping as they should be; the solution was to tie the INP_DIS lines low at the pad by connecting them to the TIE_LO_ESD line. This should probably be addressed in housekeeping but would change the current pinout.
2021-11-22 14:21:06 -06:00
.ENABLE_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.ENABLE_INP_H(loop_zero_``X), \
Made several corrections to errors found in the netlists: (1) Fixed rstb_h, which was being input to low-voltage blocks. (2) Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not output from housekeeping as they should be; the solution was to tie the INP_DIS lines low at the pad by connecting them to the TIE_LO_ESD line. This should probably be addressed in housekeeping but would change the current pinout.
2021-11-22 14:21:06 -06:00
.ENABLE_VDDA_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
.INP_DIS(loop_zero_``X), \
.IB_MODE_SEL(loop_zero_``X), \
.VTRIP_SEL(loop_zero_``X), \
.SLOW(loop_zero_``X), \
.HLD_OVR(loop_zero_``X), \
.ANALOG_EN(loop_zero_``X), \
.ANALOG_SEL(loop_zero_``X), \
.ANALOG_POL(loop_zero_``X), \
.DM({CONB_ONE, CONB_ONE, loop_zero_``X}), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(), \
.IN_H(), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X))
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
`define INOUT_PAD(X,Y,CONB_ONE,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \
wire loop_zero_``X; \
wire loop_one_``X; \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
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.PAD(X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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`endif \
.OUT(Y_OUT), \
.OE_N(OUT_EN_N), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
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.HLD_H_N(loop_one_``X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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.ENABLE_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
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.ENABLE_INP_H(loop_zero_``X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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.ENABLE_VDDA_H(porb_h), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
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.ENABLE_VSWITCH_H(loop_zero_``X), \
.ENABLE_VDDIO(CONB_ONE), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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.INP_DIS(INPUT_DIS), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
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.IB_MODE_SEL(loop_zero_``X), \
.VTRIP_SEL(loop_zero_``X), \
.SLOW(loop_zero_``X), \
.HLD_OVR(loop_zero_``X), \
.ANALOG_EN(loop_zero_``X), \
.ANALOG_SEL(loop_zero_``X), \
.ANALOG_POL(loop_zero_``X), \
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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.DM(MODE), \
.PAD_A_NOESD_H(), \
.PAD_A_ESD_0_H(), \
.PAD_A_ESD_1_H(), \
.IN(Y), \
.IN_H(), \
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
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.TIE_HI_ESD(loop_one_``X), \
.TIE_LO_ESD(loop_zero_``X) )
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
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// `default_nettype wire