To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef at line 930.
[INFO PSM-0002] Output voltage file is specified as: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/22-irdrop.rpt.
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net VPWR is not explicitly set.
[WARNING PSM-0022] Using voltage 1.800V for VDD network.
[WARNING PSM-0063] Specified bump pitches of 140.000 and 140.000 are less than core width of 63.940 or core height of 62.560. Changing bump location to the center of the die at (37.490, 36.720).
[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[WARNING PSM-0030] VSRC location at (37.490um, 36.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (21.840um, 21.850um).
[INFO PSM-0031] Number of PDN nodes on net VPWR = 268.
[INFO PSM-0064] Number of voltage sources = 1.
[INFO PSM-0040] All PDN stripes on net VPWR are connected.