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caravel/def/gpio_signal_buffering.def

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Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
VERSION 5.7 ;
NAMESCASESENSITIVE ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "()" ;
DESIGN gpio_signal_buffering ;
TECHNOLOGY sky130A ;
UNITS DISTANCE MICRONS 1000 ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
DIEAREA ( 0 0 ) ( 3588000 5188000 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
VIAS 17 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- via_1785_300_vh
+ RECT met1 ( -892.5 -180 ) ( 892.5 180 )
+ RECT met2 ( -922.5 -150 ) ( 922.5 150 )
+ RECT via ( -715 -75 ) ( -565 75 )
+ RECT via ( -395 -75 ) ( -245 75 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( 245 -75 ) ( 395 75 )
+ RECT via ( 565 -75 ) ( 715 75 ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- via_260_660_vh
+ RECT met1 ( -130 -360 ) ( 130 360 )
+ RECT met2 ( -160 -330 ) ( 160 330 )
+ RECT via ( -75 -235 ) ( 75 -85 )
+ RECT via ( -75 85 ) ( 75 235 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- via_260_260_hv
+ RECT met1 ( -160 -130 ) ( 160 130 )
+ RECT met2 ( -130 -160 ) ( 130 160 )
+ RECT via ( -75 -75 ) ( 75 75 ) ;
- via_1090_260_hv
+ RECT met1 ( -575 -130 ) ( 575 130 )
+ RECT met2 ( -545 -160 ) ( 545 160 )
+ RECT via ( -395 -75 ) ( -245 75 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( 245 -75 ) ( 395 75 ) ;
- via_260_260_vh
+ RECT met1 ( -130 -160 ) ( 130 160 )
+ RECT met2 ( -160 -130 ) ( 160 130 )
+ RECT via ( -75 -75 ) ( 75 75 ) ;
- via2_1785_300_vx
+ RECT met2 ( -892.5 -195 ) ( 892.5 195 )
+ RECT met3 ( -917.5 -175 ) ( 917.5 175 )
+ RECT via2 ( -700 -100 ) ( -500 100 )
+ RECT via2 ( -300 -100 ) ( -100 100 )
+ RECT via2 ( 100 -100 ) ( 300 100 )
+ RECT via2 ( 500 -100 ) ( 700 100 ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- via_260_290_vh
+ RECT met1 ( -130 -175 ) ( 130 175 )
+ RECT met2 ( -160 -145 ) ( 160 145 )
+ RECT via ( -75 -75 ) ( 75 75 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- mcon_170_1090
+ RECT li1 ( -85 -545 ) ( 85 545 )
+ RECT met1 ( -115 -575 ) ( 115 575 )
+ RECT mcon ( -85 -445 ) ( 85 -275 )
+ RECT mcon ( -85 -85 ) ( 85 85 )
+ RECT mcon ( -85 275 ) ( 85 445 ) ;
- via_260_1090_vh
+ RECT met1 ( -130 -575 ) ( 130 575 )
+ RECT met2 ( -160 -545 ) ( 160 545 )
+ RECT via ( -75 -395 ) ( 75 -245 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( -75 245 ) ( 75 395 ) ;
- via_1785_300_hh
+ RECT met1 ( -922.5 -150 ) ( 922.5 150 )
+ RECT met2 ( -922.5 -150 ) ( 922.5 150 )
+ RECT via ( -715 -75 ) ( -565 75 )
+ RECT via ( -395 -75 ) ( -245 75 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( 245 -75 ) ( 395 75 )
+ RECT via ( 565 -75 ) ( 715 75 ) ;
- mcon_1090_170
+ RECT li1 ( -545 -85 ) ( 545 85 )
+ RECT met1 ( -575 -115 ) ( 575 115 )
+ RECT mcon ( -445 -85 ) ( -275 85 )
+ RECT mcon ( -85 -85 ) ( 85 85 )
+ RECT mcon ( 275 -85 ) ( 445 85 ) ;
- via2_300_1785_hx
+ RECT met2 ( -195 -892.5 ) ( 195 892.5 )
+ RECT met3 ( -175 -917.5 ) ( 175 917.5 )
+ RECT via2 ( -100 -700 ) ( 100 -500 )
+ RECT via2 ( -100 -300 ) ( 100 -100 )
+ RECT via2 ( -100 100 ) ( 100 300 )
+ RECT via2 ( -100 500 ) ( 100 700 ) ;
- via_850_260_hv
+ RECT met1 ( -455 -130 ) ( 455 130 )
+ RECT met2 ( -425 -160 ) ( 425 160 )
+ RECT via ( -235 -75 ) ( -85 75 )
+ RECT via ( 85 -75 ) ( 235 75 ) ;
- via_260_850_vh
+ RECT met1 ( -130 -455 ) ( 130 455 )
+ RECT met2 ( -160 -425 ) ( 160 425 )
+ RECT via ( -75 -235 ) ( 75 -85 )
+ RECT via ( -75 85 ) ( 75 235 ) ;
- mcon_170_850
+ RECT li1 ( -85 -425 ) ( 85 425 )
+ RECT met1 ( -115 -455 ) ( 115 455 )
+ RECT mcon ( -85 -265 ) ( 85 -95 )
+ RECT mcon ( -85 95 ) ( 85 265 ) ;
- via_300_1785_vh
+ RECT met1 ( -150 -922.5 ) ( 150 922.5 )
+ RECT met2 ( -180 -892.5 ) ( 180 892.5 )
+ RECT via ( -75 -715 ) ( 75 -565 )
+ RECT via ( -75 -395 ) ( 75 -245 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( -75 245 ) ( 75 395 )
+ RECT via ( -75 565 ) ( 75 715 ) ;
- mcon_850_170
+ RECT li1 ( -425 -85 ) ( 425 85 )
+ RECT met1 ( -455 -115 ) ( 455 115 )
+ RECT mcon ( -265 -85 ) ( -95 85 )
+ RECT mcon ( 95 -85 ) ( 265 85 ) ;
END VIAS
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
COMPONENTS 624 ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_21 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 669460 211685 ) N ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_24 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 669460 217125 ) N ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_1 sky130_fd_sc_hd__buf_8
+ PLACED ( 669460 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_3 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 669000 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_238 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 669000 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_241 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 669000 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_82 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 675440 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_83 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 675440 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_92 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 674980 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_93 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 674980 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_80 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 681420 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_81 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 681420 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_90 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 680960 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_91 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 680960 211685 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_23 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 675440 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_240 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 674980 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_26 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 681420 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_242 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 680960 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_78 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 687400 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_79 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 687400 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_88 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 686940 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_89 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 686940 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_76 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 693380 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_77 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 693380 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_86 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 692920 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_87 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 692920 211685 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_25 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 687400 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_243 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 686940 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_27 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 693380 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_244 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 692920 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_74 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 699360 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_75 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 699360 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_84 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 698900 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_85 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 698900 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_72 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 705340 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_73 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 705340 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_82 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 704880 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_83 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 704880 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_70 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 711320 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_71 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 711320 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_80 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 710860 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_81 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 710860 211685 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_29 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 699360 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_246 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 698900 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_28 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 705340 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_245 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 704880 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_30 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 711320 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_247 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 710860 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_68 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 717300 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_69 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 717300 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_78 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 716840 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_79 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 716840 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_66 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 723280 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_67 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 723280 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_76 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 722820 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_77 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 722820 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_32 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 717300 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_249 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 716840 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_31 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 723280 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_248 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 722820 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_64 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 729260 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_65 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 729260 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_74 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 728800 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_75 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 728800 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_62 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 735240 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_63 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 735240 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_72 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 734780 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_73 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 734780 211685 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_34 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 729260 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_250 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 728800 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_33 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 735240 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_251 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 734780 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_60 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 741220 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_61 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 741220 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_70 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 740760 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_71 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 740760 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_58 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 747200 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_59 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 747200 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_68 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 746740 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_69 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 746740 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_56 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 753180 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_57 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 753180 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_66 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 752720 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_67 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 752720 211685 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_36 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 741220 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_253 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 740760 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_35 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 747200 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_252 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 746740 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_37 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 753180 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_254 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 752720 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_54 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 759160 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_55 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 759160 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_64 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 758700 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_65 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 758700 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_2 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 765140 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_3 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 765140 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_6 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 764680 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_7 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 764680 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_39 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 759160 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_256 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 758700 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_40 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 765140 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_257 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 764680 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_84 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 771120 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_85 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 771120 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_94 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 770660 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_95 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 770660 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_4 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 777100 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_5 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 777100 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_4 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 776640 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_5 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 776640 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_8 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 782620 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_9 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 782620 214405 ) S ;
- sky130_ef_sc_hd__decap_12_38 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 771120 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_255 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 770660 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_42 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 777100 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_259 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 776640 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_258 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 782620 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_6 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 783080 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_7 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 783080 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_10 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 788600 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_11 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 788600 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_8 sky130_fd_sc_hd__buf_8
+ PLACED ( 789060 211685 ) FN ;
- sky130_fd_sc_hd__buf_8_9 sky130_fd_sc_hd__buf_8
+ PLACED ( 789060 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_12 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 794580 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_13 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 794580 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_41 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 783080 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_260 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 788600 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_43 sky130_ef_sc_hd__decap_12
+ PLACED ( 789060 217125 ) N ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_326 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 794580 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_1 sky130_ef_sc_hd__decap_12
+ PLACED ( 2146460 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_86 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2146460 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_96 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2146000 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_97 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2146000 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_88 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2152440 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_89 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2152440 211685 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_98 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2151980 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_99 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2151980 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_22 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2146460 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_239 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2146000 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_2 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2152440 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_218 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2151980 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_90 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2158420 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_91 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2158420 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_100 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2157960 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_101 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2157960 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_92 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2164400 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_93 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2164400 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_104 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2163940 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_105 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2163940 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_94 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2170380 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_95 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2170380 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_102 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2169920 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_103 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2169920 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_3 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2158420 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_219 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2157960 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_4 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2164400 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_220 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2163940 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_0 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2170380 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_2 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2169920 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_96 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2176360 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_98 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2176360 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_106 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2175900 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_109 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2175900 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_97 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2182340 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_99 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2182340 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_107 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2181880 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_110 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2181880 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_100 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2188320 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_103 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2188320 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_108 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2187860 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_111 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2187860 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_6 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2176360 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_222 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2175900 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_7 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2182340 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_223 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2181880 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_8 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2188320 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_224 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2187860 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_101 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2194300 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_104 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2194300 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_112 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2193840 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_114 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2193840 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_102 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2200280 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_105 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2200280 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_113 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2199820 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_115 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2199820 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_106 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2206260 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_107 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2206260 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_116 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2205800 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_117 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2205800 214405 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_9 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2194300 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_225 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2193840 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_10 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2200280 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_226 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2199820 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_5 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2206260 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_221 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2205800 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_108 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2212240 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_109 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2212240 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_118 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2211780 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_119 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2211780 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_110 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2218220 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_111 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2218220 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_120 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2217760 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_121 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2217760 211685 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_11 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2212240 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_227 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2211780 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_13 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2218220 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_229 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2217760 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_112 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2224200 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_113 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2224200 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_122 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2223740 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_123 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2223740 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_114 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2230180 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_115 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2230180 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_124 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2229720 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_125 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2229720 211685 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_12 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2224200 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_228 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2223740 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_14 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2230180 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_230 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2229720 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_15 sky130_ef_sc_hd__decap_12
+ PLACED ( 2236160 217125 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_116 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2236160 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_117 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2236160 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_126 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2235700 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_127 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2235700 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_231 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2235700 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_16 sky130_ef_sc_hd__decap_12
+ PLACED ( 2242140 217125 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_118 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2242140 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_119 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2242140 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_128 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2241680 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_129 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2241680 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_232 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2241680 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_18 sky130_ef_sc_hd__decap_12
+ PLACED ( 2248120 217125 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_120 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2248120 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_121 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2248120 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_130 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2247660 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_131 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2247660 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_234 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2247660 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_17 sky130_ef_sc_hd__decap_12
+ PLACED ( 2254100 217125 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_122 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2254100 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_123 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2254100 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_132 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2253640 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_133 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2253640 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_233 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2253640 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_19 sky130_ef_sc_hd__decap_12
+ PLACED ( 2260080 217125 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_124 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2260080 211685 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_126 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2260080 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_134 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2259620 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_137 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2259620 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_236 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2259620 217125 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_20 sky130_ef_sc_hd__decap_12
+ PLACED ( 2266060 217125 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_125 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2266060 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_127 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2266060 214405 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_135 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2265600 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_138 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2265600 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_235 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2265600 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_136 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2271580 211685 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_139 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2271580 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_237 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2271580 217125 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_128 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1673365 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_129 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1673365 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_140 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1672905 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_309 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1672905 ) E ;
- sky130_ef_sc_hd__decap_12_57 sky130_ef_sc_hd__decap_12
+ PLACED ( 207520 1673365 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_141 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1672905 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_130 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1679345 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_131 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1679345 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_142 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1678885 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_143 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1678885 ) E ;
- sky130_ef_sc_hd__decap_12_56 sky130_ef_sc_hd__decap_12
+ PLACED ( 207520 1679345 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_310 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1678885 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_132 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1685325 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_133 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1685325 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_144 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1684865 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_145 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1684865 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_44 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1685325 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_312 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1684865 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_138 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1691305 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_139 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1691305 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_150 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1690845 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_151 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1690845 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_46 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1691305 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_311 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1690845 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_136 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1697285 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_137 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1697285 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_148 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1696825 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_149 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1696825 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_45 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1697285 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_313 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1696825 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_134 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1703265 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_135 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1703265 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_146 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1702805 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_147 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1702805 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_47 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1703265 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_314 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1702805 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_142 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1709245 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_143 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1709245 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_154 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1708785 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_155 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1708785 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_49 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1709245 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_316 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1708785 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_140 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1715225 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_141 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1715225 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_152 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1714765 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_153 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1714765 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_48 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1715225 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_315 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1714765 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_148 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1721205 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_149 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1721205 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_160 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1720745 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_161 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1720745 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_50 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1721205 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_317 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1720745 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_146 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1727185 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_147 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1727185 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_158 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1726725 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_159 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1726725 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_51 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1727185 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_318 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1726725 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_144 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1733165 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_145 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1733165 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_156 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1732705 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_157 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1732705 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_53 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1733165 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_320 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1732705 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_154 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1739145 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_155 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1739145 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_166 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1738685 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_167 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1738685 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_52 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1739145 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_319 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1738685 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_152 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1745125 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_153 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1745125 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_164 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1744665 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_165 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1744665 ) E ;
Made a minor correction to the layout to remove an extra unused buffer. This does not affect ongoing top-level routing work, but is needed for LVS.
2022-10-16 16:57:14 -05:00
- sky130_ef_sc_hd__decap_12_100 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1745125 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_162 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1744665 ) E ;
- sky130_fd_sc_hd__buf_8_0 sky130_fd_sc_hd__buf_8
+ PLACED ( 204800 1751105 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_151 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1751105 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_163 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1750645 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_323 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1750645 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_54 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1751105 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_321 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1750645 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_156 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1757085 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_157 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1757085 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_170 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204800 1756625 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_171 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 202080 1756625 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_55 sky130_ef_sc_hd__decap_12
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1757085 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_322 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1756625 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_324 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207520 1762605 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_169 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 204800 1762605 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_168 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 202080 1762605 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_262 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2196060 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_261 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 2196060 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_53 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2196060 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_13 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2196520 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_12 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2196520 ) W ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_98 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2196520 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_99 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2202500 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_52 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2202040 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_46 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2202500 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_55 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2202040 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_47 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2202500 ) W ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_54 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2202040 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_96 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2208480 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_264 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2208020 ) FE ;
- sky130_fd_sc_hd__buf_8_49 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2208480 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_57 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2208020 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_48 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2208480 ) W ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_56 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 2208020 ) FE ;
- sky130_ef_sc_hd__decap_12_97 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2214460 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_263 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2214000 ) FE ;
- sky130_fd_sc_hd__buf_8_51 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2214460 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_59 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2214000 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_50 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2214460 ) W ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_58 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 2214000 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_265 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2219980 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_61 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2219980 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_60 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 2219980 ) FE ;
- sky130_ef_sc_hd__decap_12_95 sky130_ef_sc_hd__decap_12
+ PLACED ( 3377865 2220440 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_267 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2225960 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_53 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2220440 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_63 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2225960 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_52 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2220440 ) W ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_62 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 2225960 ) FE ;
- sky130_ef_sc_hd__decap_12_93 sky130_ef_sc_hd__decap_12
+ PLACED ( 3377865 2226420 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_266 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2231940 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_34 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2226420 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_38 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2231940 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_35 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2226420 ) W ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_39 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2231940 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_94 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2232400 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_269 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2237920 ) FE ;
- sky130_fd_sc_hd__buf_8_36 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2232400 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_16 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2237920 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_37 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2232400 ) W ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_17 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2237920 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_91 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2238380 ) FE ;
- sky130_fd_sc_hd__buf_8_14 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2238380 ) E ;
- sky130_fd_sc_hd__buf_8_15 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2238380 ) W ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_92 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2244360 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_18 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2244360 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_19 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2244360 ) W ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_20 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2243900 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_21 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2243900 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_268 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2243900 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_89 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2250340 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_20 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2250340 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_21 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2250340 ) W ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_22 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2249880 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_23 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2249880 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_271 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2249880 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_90 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2256320 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_16 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2256320 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_17 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2256320 ) W ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_18 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2255860 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_19 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2255860 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_270 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2255860 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_88 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2262300 ) FE ;
- sky130_fd_sc_hd__buf_8_22 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2262300 ) E ;
- sky130_fd_sc_hd__buf_8_23 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2262300 ) W ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_24 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2261840 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_25 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2261840 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_325 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2261840 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_26 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2267820 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_27 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2267820 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_273 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2267820 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_297 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 2984730 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_195 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 2984730 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_194 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 2984730 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_179 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 2985190 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_178 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 2985190 ) FW ;
- sky130_ef_sc_hd__decap_12_68 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 2985190 ) E ;
- sky130_ef_sc_hd__decap_12_67 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 2991170 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_176 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 2991170 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_177 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 2991170 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_190 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 2990710 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_192 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 2990710 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_299 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 2990710 ) E ;
- sky130_ef_sc_hd__decap_12_65 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 2997150 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_174 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 2997150 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_175 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 2997150 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_191 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 2996690 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_193 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 2996690 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_298 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 2996690 ) E ;
- sky130_ef_sc_hd__decap_12_66 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3003130 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_172 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3003130 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_173 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3003130 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_188 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3002670 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_189 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3002670 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_300 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3002670 ) E ;
- sky130_ef_sc_hd__decap_12_63 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3009110 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_170 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3009110 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_171 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3009110 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_186 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3008650 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_187 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3008650 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_302 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3008650 ) E ;
- sky130_ef_sc_hd__decap_12_64 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3015090 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_168 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3015090 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_169 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3015090 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_184 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3014630 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_185 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3014630 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_301 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3014630 ) E ;
- sky130_ef_sc_hd__decap_12_61 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3021070 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_166 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3021070 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_167 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3021070 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_182 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3020610 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_183 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3020610 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_304 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3020610 ) E ;
- sky130_ef_sc_hd__decap_12_62 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3027050 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_164 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3027050 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_165 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3027050 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_180 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3026590 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_181 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3026590 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_303 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3026590 ) E ;
- sky130_ef_sc_hd__decap_12_59 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3033030 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_162 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3033030 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_163 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3033030 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_178 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3032570 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_179 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3032570 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_306 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3032570 ) E ;
- sky130_ef_sc_hd__decap_12_60 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3039010 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_160 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3039010 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_161 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3039010 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_176 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3038550 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_177 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3038550 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_305 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3038550 ) E ;
- sky130_ef_sc_hd__decap_12_58 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3044990 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_158 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3044990 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_159 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3044990 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_174 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3044530 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_175 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3044530 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_308 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3044530 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_172 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201970 3050510 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_173 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204690 3050510 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_307 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207410 3050510 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_28 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 3602060 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_274 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3602060 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_272 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 3602060 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_86 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 3602520 ) FE ;
- sky130_fd_sc_hd__buf_8_25 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 3602520 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_29 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 3608040 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_275 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3608040 ) FE ;
- sky130_fd_sc_hd__buf_8_24 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 3602520 ) W ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_1 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 3608040 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_85 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 3608500 ) FE ;
- sky130_fd_sc_hd__buf_8_26 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 3608500 ) E ;
- sky130_fd_sc_hd__buf_8_27 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 3608500 ) W ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_87 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 3614480 ) FE ;
- sky130_fd_sc_hd__buf_8_28 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 3614480 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_0 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3614020 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_30 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 3614020 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_29 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 3614480 ) W ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_31 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 3614020 ) FE ;
- sky130_ef_sc_hd__decap_12_83 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 3620460 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_30 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 3620460 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_32 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 3620000 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_277 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3620000 ) FE ;
- sky130_fd_sc_hd__buf_8_31 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 3620460 ) W ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_33 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 3620000 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_82 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 3626440 ) FE ;
- sky130_fd_sc_hd__buf_8_41 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 3626440 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_34 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 3625980 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_278 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3625980 ) FE ;
- sky130_fd_sc_hd__buf_8_40 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 3626440 ) W ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_35 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 3625980 ) FE ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_84 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 3632420 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_32 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 3632420 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_45 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 3631960 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_276 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3631960 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_33 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 3632420 ) W ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_44 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 3631960 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_36 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 3637940 ) E ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_279 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3637940 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_37 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 3637940 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_200 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204565 4426840 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_201 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201845 4426840 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_291 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207285 4426840 ) E ;
- sky130_ef_sc_hd__decap_12_73 sky130_ef_sc_hd__decap_12
+ PLACED ( 207285 4427300 ) E ;
- sky130_fd_sc_hd__buf_8_185 sky130_fd_sc_hd__buf_8
+ PLACED ( 201845 4427300 ) FW ;
- sky130_fd_sc_hd__buf_8_186 sky130_fd_sc_hd__buf_8
+ PLACED ( 204565 4427300 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_202 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204565 4432820 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_203 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201845 4432820 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_292 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207285 4432820 ) E ;
- sky130_ef_sc_hd__decap_12_72 sky130_ef_sc_hd__decap_12
+ PLACED ( 207285 4433280 ) E ;
- sky130_fd_sc_hd__buf_8_187 sky130_fd_sc_hd__buf_8
+ PLACED ( 201845 4433280 ) FW ;
- sky130_fd_sc_hd__buf_8_188 sky130_fd_sc_hd__buf_8
+ PLACED ( 204565 4433280 ) FE ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_204 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201845 4438800 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_205 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204565 4438800 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_293 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207285 4438800 ) E ;
- sky130_ef_sc_hd__decap_12_71 sky130_ef_sc_hd__decap_12
+ PLACED ( 207285 4439260 ) E ;
- sky130_fd_sc_hd__buf_8_189 sky130_fd_sc_hd__buf_8
+ PLACED ( 204565 4439260 ) FE ;
- sky130_fd_sc_hd__buf_8_190 sky130_fd_sc_hd__buf_8
+ PLACED ( 201845 4439260 ) FW ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_206 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201845 4444780 ) E ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_207 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204565 4444780 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_294 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207285 4444780 ) E ;
- sky130_ef_sc_hd__decap_12_70 sky130_ef_sc_hd__decap_12
+ PLACED ( 207285 4445240 ) E ;
- sky130_fd_sc_hd__buf_8_181 sky130_fd_sc_hd__buf_8
+ PLACED ( 204565 4445240 ) FE ;
- sky130_fd_sc_hd__buf_8_182 sky130_fd_sc_hd__buf_8
+ PLACED ( 201845 4445240 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_196 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201845 4450760 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_197 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204565 4450760 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_296 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207285 4450760 ) E ;
- sky130_ef_sc_hd__decap_12_69 sky130_ef_sc_hd__decap_12
+ PLACED ( 207285 4451220 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_183 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 204565 4451220 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_184 sky130_fd_sc_hd__buf_8
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 201845 4451220 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_295 sky130_fd_sc_hd__tapvpwrvgnd_1
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ PLACED ( 207285 4456740 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_199 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 201845 4456740 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_198 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 204565 4456740 ) FE ;
- sky130_ef_sc_hd__decap_12_75 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 835110 4977915 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_76 sky130_ef_sc_hd__decap_12
+ PLACED ( 841090 4977915 ) S ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_51 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 840630 4977915 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_288 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 834650 4977915 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_74 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 847070 4977915 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_289 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 846610 4977915 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_290 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 852590 4977915 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_38 sky130_fd_sc_hd__buf_8
+ PLACED ( 841090 4980635 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_39 sky130_fd_sc_hd__buf_8
+ PLACED ( 835110 4980635 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_44 sky130_fd_sc_hd__buf_8
+ PLACED ( 841090 4983355 ) FS ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_45 sky130_fd_sc_hd__buf_8
+ PLACED ( 835110 4983355 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_48 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 840630 4980635 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_49 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 840630 4983355 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_50 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 834650 4980635 ) FN ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_287 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 834650 4983355 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_42 sky130_fd_sc_hd__buf_8
+ PLACED ( 847070 4980635 ) FN ;
- sky130_fd_sc_hd__buf_8_43 sky130_fd_sc_hd__buf_8
+ PLACED ( 847070 4983355 ) FS ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_42 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 846610 4980635 ) FN ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_43 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 846610 4983355 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_46 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 852590 4983355 ) S ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_47 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 852590 4980635 ) FN ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_77 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2083290 4979540 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_10 sky130_fd_sc_hd__buf_8
+ PLACED ( 2083290 4984980 ) S ;
- sky130_fd_sc_hd__buf_8_11 sky130_fd_sc_hd__buf_8
+ PLACED ( 2083290 4982260 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_14 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2088810 4982260 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_15 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2088810 4984980 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_40 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2082830 4982260 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_41 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2088810 4979540 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_285 sky130_fd_sc_hd__tapvpwrvgnd_1
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PLACED ( 2082830 4984980 ) FS ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_286 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2082830 4979540 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_280 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3309835 4984570 ) FS ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_212 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3309835 4979130 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_208 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3309835 4981850 ) N ;
- sky130_fd_sc_hd__buf_8_194 sky130_fd_sc_hd__buf_8
+ PLACED ( 3310295 4984570 ) S ;
- sky130_fd_sc_hd__buf_8_180 sky130_fd_sc_hd__buf_8
+ PLACED ( 3310295 4981850 ) N ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_81 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3310295 4979130 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_78 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3322255 4979130 ) S ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_80 sky130_ef_sc_hd__decap_12
+ PLACED ( 3316275 4979130 ) S ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_281 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3315815 4979130 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_283 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3321795 4979130 ) FS ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_191 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3316275 4981850 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_192 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3322255 4981850 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_195 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3316275 4984570 ) S ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_196 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3322255 4984570 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_209 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3315815 4981850 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_210 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3321795 4981850 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_213 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3315815 4984570 ) FS ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_214 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3321795 4984570 ) FS ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_ef_sc_hd__decap_12_79 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3328235 4979130 ) S ;
- sky130_fd_sc_hd__buf_8_193 sky130_fd_sc_hd__buf_8
+ PLACED ( 3328235 4981850 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_197 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3328235 4984570 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_211 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3327775 4981850 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_215 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3327775 4984570 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_216 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3333755 4981850 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_217 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3333755 4984570 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_282 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3327775 4979130 ) FS ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_284 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3333755 4979130 ) FS ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
END COMPONENTS
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
PINS 150 ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 2091990 4989250 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 2086050 4989230 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 849810 4987560 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 843845 4987560 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[12] + NET mgmt_io_in_unbuf[12]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -700 -70 ) ( 700 70 ) + PLACED ( 859845 4977075 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[14] + NET mgmt_io_in_unbuf[14]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -700 -70 ) ( 700 70 ) + PLACED ( 855850 4974835 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[13] + NET mgmt_io_in_unbuf[13]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -700 -70 ) ( 700 70 ) + PLACED ( 857855 4975955 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 3319080 4988795 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 3325055 4988740 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387535 2235397.5 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387545 2241392.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[10] + NET mgmt_io_in_unbuf[10]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 3302387.5 4975605 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387530 3617392.5 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387575 3623377.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[9] + NET mgmt_io_in_unbuf[9]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 3304387.5 4974485 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[8] + NET mgmt_io_in_unbuf[8]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 3306387.5 4973365 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[4] + NET mgmt_io_in_unbuf[4]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368750 2278557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[7] + NET mgmt_io_in_unbuf[7]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3371970 3642887.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[6] + NET mgmt_io_in_unbuf[6]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370850 3640887.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[5] + NET mgmt_io_in_unbuf[5]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3369870 2280557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[0] + NET mgmt_io_in_unbuf[0]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364270 2270557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[1] + NET mgmt_io_in_unbuf[1]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3365390 2272557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[2] + NET mgmt_io_in_unbuf[2]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3366510 2274557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[3] + NET mgmt_io_in_unbuf[3]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367630 2276557.5 ) N ;
- vssd + NET vssd
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ USE GROUND
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 737925 210220 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 731895 210220 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 2208985 210125 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 2203020 210155 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[27] + NET mgmt_io_out_buf[27]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 656242.5 225310 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[28] + NET mgmt_io_out_buf[28]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 658242.5 224470 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[29] + NET mgmt_io_out_buf[29]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 660242.5 223630 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[30] + NET mgmt_io_out_buf[30]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 662242.5 222790 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[20] + NET mgmt_io_out_buf[20]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220345 3057127.5 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200595 1735667.5 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200605 1729702.5 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200490 3023947.5 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200490 3017942.5 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200350 4447777.5 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200335 4441807.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[15] + NET mgmt_io_out_buf[15]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -587.5 ) ( 70 587.5 ) + PLACED ( 214885 4460997.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[16] + NET mgmt_io_out_buf[16]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -587.5 ) ( 70 587.5 ) + PLACED ( 216005 4458997.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[17] + NET mgmt_io_out_buf[17]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 216985 3063127.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[18] + NET mgmt_io_out_buf[18]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218105 3061127.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[19] + NET mgmt_io_out_buf[19]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 219225 3059127.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[26] + NET mgmt_io_out_buf[26]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 226925 1765915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[25] + NET mgmt_io_out_buf[25]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 225805 1767915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[24] + NET mgmt_io_out_buf[24]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 224685 1769915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[23] + NET mgmt_io_out_buf[23]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 223565 1771915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[22] + NET mgmt_io_out_buf[22]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222585 3053127.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[21] + NET mgmt_io_out_buf[21]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 221465 3055127.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[14] + NET mgmt_io_out_unbuf[14]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3368190 1144957.5 ) N ;
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
- mgmt_io_in_buf[4] + NET mgmt_io_in_buf[4]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368890 1181967.5 ) N ;
- mgmt_io_in_buf[11] + NET mgmt_io_in_buf[11]
+ DIRECTION OUTPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3376870 1167967.5 ) N ;
- mgmt_io_in_buf[10] + NET mgmt_io_in_buf[10]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3375610 1169967.5 ) N ;
- mgmt_io_in_buf[9] + NET mgmt_io_in_buf[9]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3374490 1171967.5 ) N ;
- mgmt_io_in_buf[8] + NET mgmt_io_in_buf[8]
+ DIRECTION OUTPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3373370 1173967.5 ) N ;
- mgmt_io_in_buf[7] + NET mgmt_io_in_buf[7]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3372250 1175967.5 ) N ;
- mgmt_io_in_buf[6] + NET mgmt_io_in_buf[6]
+ DIRECTION OUTPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3371130 1177967.5 ) N ;
- mgmt_io_in_buf[5] + NET mgmt_io_in_buf[5]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370010 1179967.5 ) N ;
- mgmt_io_in_buf[0] + NET mgmt_io_in_buf[0]
+ DIRECTION OUTPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364410 1189967.5 ) N ;
- mgmt_io_in_buf[1] + NET mgmt_io_in_buf[1]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3365530 1187967.5 ) N ;
- mgmt_io_in_buf[2] + NET mgmt_io_in_buf[2]
+ DIRECTION OUTPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3366650 1185967.5 ) N ;
- mgmt_io_in_buf[3] + NET mgmt_io_in_buf[3]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367770 1183967.5 ) N ;
- mgmt_io_out_unbuf[26] + NET mgmt_io_out_unbuf[26]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3354750 1120957.5 ) N ;
- mgmt_io_out_unbuf[25] + NET mgmt_io_out_unbuf[25]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3355870 1122957.5 ) N ;
- mgmt_io_out_unbuf[24] + NET mgmt_io_out_unbuf[24]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3356990 1124957.5 ) N ;
- mgmt_io_out_unbuf[23] + NET mgmt_io_out_unbuf[23]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3358110 1126957.5 ) N ;
- mgmt_io_out_unbuf[22] + NET mgmt_io_out_unbuf[22]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3359230 1128957.5 ) N ;
- mgmt_io_out_unbuf[21] + NET mgmt_io_out_unbuf[21]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3360350 1130957.5 ) N ;
- mgmt_io_out_unbuf[20] + NET mgmt_io_out_unbuf[20]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3361470 1132957.5 ) N ;
- mgmt_io_out_unbuf[19] + NET mgmt_io_out_unbuf[19]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3362590 1134957.5 ) N ;
- mgmt_io_out_unbuf[18] + NET mgmt_io_out_unbuf[18]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3363710 1136957.5 ) N ;
- mgmt_io_out_unbuf[17] + NET mgmt_io_out_unbuf[17]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3364830 1138957.5 ) N ;
- mgmt_io_out_unbuf[16] + NET mgmt_io_out_unbuf[16]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3365950 1140957.5 ) N ;
- mgmt_io_out_unbuf[15] + NET mgmt_io_out_unbuf[15]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3367070 1142957.5 ) N ;
- mgmt_io_out_unbuf[27] + NET mgmt_io_out_unbuf[27]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3371550 1150842.5 ) N ;
- mgmt_io_out_unbuf[28] + NET mgmt_io_out_unbuf[28]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3372670 1152842.5 ) N ;
- mgmt_io_out_unbuf[29] + NET mgmt_io_out_unbuf[29]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3373790 1154842.5 ) N ;
- mgmt_io_out_unbuf[30] + NET mgmt_io_out_unbuf[30]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3374910 1156842.5 ) N ;
- mgmt_io_oeb_unbuf[0] + NET mgmt_io_oeb_unbuf[0]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3376030 1158842.5 ) N ;
- mgmt_io_oeb_unbuf[2] + NET mgmt_io_oeb_unbuf[2]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3377710 1160842.5 ) N ;
- mgmt_io_oeb_unbuf[1] + NET mgmt_io_oeb_unbuf[1]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3376870 1159842.5 ) N ;
- mgmt_io_out_unbuf[13] + NET mgmt_io_out_unbuf[13]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3369310 1146957.5 ) N ;
- mgmt_io_out_unbuf[12] + NET mgmt_io_out_unbuf[12]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3370430 1148957.5 ) N ;
- mgmt_io_out_buf[11] + NET mgmt_io_out_buf[11]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 2081307.5 4976305 ) N ;
- mgmt_io_in_buf[30] + NET mgmt_io_in_buf[30]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3375470 1157842.5 ) N ;
- mgmt_io_in_buf[29] + NET mgmt_io_in_buf[29]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3374350 1155842.5 ) N ;
- mgmt_io_in_buf[28] + NET mgmt_io_in_buf[28]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3373230 1153842.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[27] + NET mgmt_io_in_buf[27]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3372110 1151842.5 ) N ;
- mgmt_io_in_buf[12] + NET mgmt_io_in_buf[12]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3370990 1149957.5 ) N ;
- mgmt_io_in_buf[13] + NET mgmt_io_in_buf[13]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3369870 1147957.5 ) N ;
- mgmt_io_in_buf[14] + NET mgmt_io_in_buf[14]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3368750 1145957.5 ) N ;
- mgmt_io_in_buf[15] + NET mgmt_io_in_buf[15]
+ DIRECTION OUTPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3367630 1143957.5 ) N ;
- mgmt_io_in_buf[16] + NET mgmt_io_in_buf[16]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3366510 1141957.5 ) N ;
- mgmt_io_in_buf[17] + NET mgmt_io_in_buf[17]
+ DIRECTION OUTPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3365390 1139957.5 ) N ;
- mgmt_io_in_buf[18] + NET mgmt_io_in_buf[18]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3364270 1137957.5 ) N ;
- mgmt_io_in_buf[19] + NET mgmt_io_in_buf[19]
+ DIRECTION OUTPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3363150 1135957.5 ) N ;
- mgmt_io_in_buf[20] + NET mgmt_io_in_buf[20]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3362030 1133957.5 ) N ;
- mgmt_io_in_buf[21] + NET mgmt_io_in_buf[21]
+ DIRECTION OUTPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3360910 1131957.5 ) N ;
- mgmt_io_in_buf[22] + NET mgmt_io_in_buf[22]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3359790 1129957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[23] + NET mgmt_io_in_buf[23]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3358670 1127957.5 ) N ;
- mgmt_io_in_buf[24] + NET mgmt_io_in_buf[24]
+ DIRECTION OUTPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3357550 1125957.5 ) N ;
- mgmt_io_in_buf[25] + NET mgmt_io_in_buf[25]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3356430 1123957.5 ) N ;
- mgmt_io_in_buf[26] + NET mgmt_io_in_buf[26]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3355310 1121957.5 ) N ;
- mgmt_io_out_unbuf[1] + NET mgmt_io_out_unbuf[1]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364970 1188967.5 ) N ;
- mgmt_io_out_unbuf[2] + NET mgmt_io_out_unbuf[2]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3366090 1186967.5 ) N ;
- mgmt_io_out_unbuf[0] + NET mgmt_io_out_unbuf[0]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3363850 1190967.5 ) N ;
- mgmt_io_out_unbuf[3] + NET mgmt_io_out_unbuf[3]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367210 1184967.5 ) N ;
- mgmt_io_out_unbuf[4] + NET mgmt_io_out_unbuf[4]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368330 1182967.5 ) N ;
- mgmt_io_out_unbuf[5] + NET mgmt_io_out_unbuf[5]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3369450 1180967.5 ) N ;
- mgmt_io_out_unbuf[6] + NET mgmt_io_out_unbuf[6]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370570 1178967.5 ) N ;
- mgmt_io_out_unbuf[7] + NET mgmt_io_out_unbuf[7]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3371690 1176967.5 ) N ;
- mgmt_io_out_unbuf[8] + NET mgmt_io_out_unbuf[8]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3372810 1174967.5 ) N ;
- mgmt_io_out_unbuf[9] + NET mgmt_io_out_unbuf[9]
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3373930 1172967.5 ) N ;
- mgmt_io_out_unbuf[10] + NET mgmt_io_out_unbuf[10]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3375050 1170967.5 ) N ;
- mgmt_io_out_unbuf[11] + NET mgmt_io_out_unbuf[11]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3376310 1168967.5 ) N ;
- mgmt_io_out_buf[0] + NET mgmt_io_out_buf[0]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3363710 2269557.5 ) N ;
- mgmt_io_out_buf[1] + NET mgmt_io_out_buf[1]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364830 2271557.5 ) N ;
- mgmt_io_out_buf[2] + NET mgmt_io_out_buf[2]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3365950 2273557.5 ) N ;
- mgmt_io_out_buf[3] + NET mgmt_io_out_buf[3]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367070 2275557.5 ) N ;
- mgmt_io_out_buf[4] + NET mgmt_io_out_buf[4]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368190 2277557.5 ) N ;
- mgmt_io_out_buf[5] + NET mgmt_io_out_buf[5]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3369310 2279557.5 ) N ;
- mgmt_io_out_buf[6] + NET mgmt_io_out_buf[6]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370290 3639887.5 ) N ;
- mgmt_io_out_buf[7] + NET mgmt_io_out_buf[7]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3371410 3641887.5 ) N ;
- mgmt_io_out_buf[10] + NET mgmt_io_out_buf[10]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 3303387.5 4975045 ) N ;
- mgmt_io_out_buf[9] + NET mgmt_io_out_buf[9]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 3305387.5 4973925 ) N ;
- mgmt_io_out_buf[8] + NET mgmt_io_out_buf[8]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 3307387.5 4972805 ) N ;
- mgmt_io_in_unbuf[11] + NET mgmt_io_in_unbuf[11]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -772.5 -70 ) ( 772.5 70 ) + PLACED ( 2080307.5 4976865 ) N ;
- mgmt_io_out_buf[12] + NET mgmt_io_out_buf[12]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -700 -70 ) ( 700 70 ) + PLACED ( 858845 4976515 ) N ;
- mgmt_io_out_buf[13] + NET mgmt_io_out_buf[13]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -700 -70 ) ( 700 70 ) + PLACED ( 856855 4975395 ) N ;
- mgmt_io_out_buf[14] + NET mgmt_io_out_buf[14]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -700 -70 ) ( 700 70 ) + PLACED ( 854850 4974275 ) N ;
- mgmt_io_in_unbuf[15] + NET mgmt_io_in_unbuf[15]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -587.5 ) ( 70 587.5 ) + PLACED ( 214325 4461997.5 ) N ;
- mgmt_io_in_unbuf[16] + NET mgmt_io_in_unbuf[16]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -587.5 ) ( 70 587.5 ) + PLACED ( 215445 4459997.5 ) N ;
- mgmt_io_in_unbuf[17] + NET mgmt_io_in_unbuf[17]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 216425 3064127.5 ) N ;
- mgmt_io_in_unbuf[18] + NET mgmt_io_in_unbuf[18]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 217545 3062127.5 ) N ;
- mgmt_io_in_unbuf[19] + NET mgmt_io_in_unbuf[19]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218665 3060127.5 ) N ;
- mgmt_io_in_unbuf[20] + NET mgmt_io_in_unbuf[20]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 219785 3058127.5 ) N ;
- mgmt_io_in_unbuf[21] + NET mgmt_io_in_unbuf[21]
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220905 3056127.5 ) N ;
- mgmt_io_in_unbuf[22] + NET mgmt_io_in_unbuf[22]
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222025 3054127.5 ) N ;
- mgmt_io_in_unbuf[23] + NET mgmt_io_in_unbuf[23]
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 223005 1772915 ) N ;
- mgmt_io_in_unbuf[24] + NET mgmt_io_in_unbuf[24]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 224125 1770915 ) N ;
- mgmt_io_in_unbuf[25] + NET mgmt_io_in_unbuf[25]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 225245 1768915 ) N ;
- mgmt_io_in_unbuf[26] + NET mgmt_io_in_unbuf[26]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 226365 1766915 ) N ;
- mgmt_io_oeb_buf[2] + NET mgmt_io_oeb_buf[2]
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 666382.5 220690 ) N ;
- mgmt_io_oeb_buf[1] + NET mgmt_io_oeb_buf[1]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 665382.5 221250 ) N ;
- mgmt_io_oeb_buf[0] + NET mgmt_io_oeb_buf[0]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 664382.5 221810 ) N ;
- mgmt_io_in_unbuf[30] + NET mgmt_io_in_unbuf[30]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 663382.5 222370 ) N ;
- mgmt_io_in_unbuf[29] + NET mgmt_io_in_unbuf[29]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 661382.5 223210 ) N ;
- mgmt_io_in_unbuf[28] + NET mgmt_io_in_unbuf[28]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 659382.5 224050 ) N ;
- mgmt_io_in_unbuf[27] + NET mgmt_io_in_unbuf[27]
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 657382.5 224890 ) N ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
END PINS
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NONDEFAULTRULES 3 ;
- met3_width_1865
+ LAYER met3 WIDTH 1865 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- met3_width_1740
+ LAYER met3 WIDTH 1740 ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- met3_width_1850
+ LAYER met3 WIDTH 1850 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
END NONDEFAULTRULES
Made a minor correction to the layout to remove an extra unused buffer. This does not affect ongoing top-level routing work, but is needed for LVS.
2022-10-16 16:57:14 -05:00
NETS 263 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_29/A ( sky130_fd_sc_hd__buf_8_29 A )
( sky130_fd_sc_hd__buf_8_19 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3384835 3615175 ) mcon_170_1090
NEW met1 ( 3384770 3615710 ) ( 3384890 * )
NEW met2 ( 3373090 3614990 ) ( 3384630 * )
NEW met1 ( 3372830 3615140 ) ( 3372950 * )
NEW met1 ( 3372890 3615050 ) via_260_260_vh
NEW met2 ( 3369280 3614990 ) ( 3372690 * )
NEW met1 ( 3372830 3614960 ) ( 3372950 * )
NEW met1 ( 3372950 2249025 ) ( * 3614820 )
NEW met1 ( 3372950 2248885 ) ( 3373070 * )
NEW met1 ( 3373010 2248795 ) via_260_260_vh ( * 2248735 )
( 3384835 * ) ( * 2248730 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2248820 ) ( 3385190 * )
NEW met2 ( 3384480 2248640 ) ( 3385190 * )
NEW met2 ( 3366060 2248735 ) ( 3372810 * )
NEW met1 ( 3372950 2248705 ) ( 3373070 * )
NEW met1 ( 3384770 3614640 ) ( 3384890 * )
NEW met1 ( 3384830 3615175 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[8] ( sky130_fd_sc_hd__buf_8_19 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3372810 1174320 ) ( * 1177990 )
NEW met1 ( 3372810 1178130 ) ( 3373090 * )
NEW met1 ( 3373090 1178270 ) ( * 2244700 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3372970 2244840 ) ( 3373090 * )
NEW met1 ( 3373030 2244930 ) via_260_260_vh
NEW met1 ( 3372970 2245020 ) ( 3373090 * )
NEW met2 ( 3373230 2244870 ) ( 3384630 * )
NEW met1 ( 3384770 2245590 ) ( 3384890 * )
NEW met1 ( 3384770 2244520 ) ( 3384890 * )
NEW met1 ( 3384830 2245055 ) via_260_1090_vh
NEW met1 ( 3384835 2245055 ) mcon_170_1090
NEW met2 ( 3366060 2244870 ) ( 3372830 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[16] ( sky130_fd_sc_hd__buf_8_109 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3366510 1138860 ) ( * 1142630 )
NEW met1 ( 3366230 1138720 ) ( 3366510 * )
NEW met1 ( 3366230 220650 ) ( * 1138580 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2525810 220510 ) ( 3366230 * )
NEW met1 ( 2525810 217170 ) ( * 220370 )
NEW met1 ( 2427610 217030 ) ( 2525810 * )
NEW met1 ( 2427610 217170 ) ( * 229370 )
NEW met1 ( 2216875 229510 ) ( 2427610 * )
NEW met1 ( 2216675 229450 ) via_260_260_hv ( * 229540 )
( 2216735 * )
NEW met2 ( 2216615 229680 ) ( * 232415 )
NEW met2 ( 2216615 229360 ) ( 2216735 * )
NEW met2 ( 2216615 213370 ) ( * 229220 )
NEW met1 ( 2216550 213290 ) ( 2216670 * )
NEW met1 ( 2216550 212460 ) ( 2216670 * )
NEW met1 ( 2216610 212875 ) via_260_850_vh
NEW met1 ( 2216615 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[8] ( sky130_fd_sc_hd__buf_8_18 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3373370 1173320 ) ( * 2245320 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3373250 2245460 ) ( 3373370 * )
NEW met1 ( 3373310 2245550 ) via_260_260_vh
NEW met1 ( 3373250 2245640 ) ( 3373370 * )
NEW met2 ( 3373510 2245490 ) ( 3381775 * ) ( * 2245500 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2245590 ) ( 3382130 * )
NEW met2 ( 3381420 2245410 ) ( 3382130 * )
NEW met2 ( 3366060 2245490 ) ( 3373110 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_28/X ( sky130_fd_sc_hd__buf_8_28 X )
( sky130_fd_sc_hd__buf_8_18 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3381775 3615625 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3373370 3615610 ) ( 3381280 * )
NEW met1 ( 3373110 3615760 ) ( 3373230 * )
NEW met1 ( 3373170 3615670 ) via_260_260_vh
NEW met2 ( 3369280 3615610 ) ( 3372970 * )
NEW met1 ( 3373110 3615580 ) ( 3373230 * )
NEW met1 ( 3373230 2249875 ) ( * 3615440 )
NEW met1 ( 3373230 2249735 ) ( 3373350 * )
NEW met1 ( 3373290 2249645 ) via_260_260_vh
NEW met2 ( 3366060 2249705 ) ( 3373090 * )
NEW met2 ( 3373490 2249705 ) ( 3381570 * )
NEW met1 ( 3381710 2250220 ) ( 3381830 * )
NEW met1 ( 3381710 2249150 ) ( 3381830 * )
NEW met1 ( 3381770 2249685 ) via_260_1090_vh
NEW met1 ( 3381775 2249685 ) mcon_170_1090
NEW met1 ( 3373230 2249555 ) ( 3373350 * )
NEW met2 ( 3381420 3615710 ) ( 3382130 * )
NEW met2 ( 3381420 3615530 ) ( 3382130 * ) ;
- sky130_fd_sc_hd__buf_8_29/X ( sky130_fd_sc_hd__buf_8_29 X )
( sky130_fd_sc_hd__buf_8_197 A )
+ ROUTED met1 ( 3384835 3618855 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3384480 3618940 ) ( 3385190 * )
NEW met2 ( 3384480 3618760 ) ( 3385190 * )
NEW met2 ( 3373070 3618855 ) ( 3384340 * )
NEW met1 ( 3372810 3619005 ) ( 3372930 * )
NEW met1 ( 3372810 3619145 ) ( * 4973085 )
NEW met1 ( 3333385 4973225 ) ( 3372810 * )
NEW met1 ( 3333185 4973165 ) via_260_260_hv ( * 4973255 )
( 3333245 * )
NEW met2 ( 3333245 4973395 ) ( * 4985865 )
NEW met2 ( 3332585 4986005 ) ( 3333535 * )
NEW met2 ( 3333060 4986095 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 3332585 4986185 ) ( 3333535 * )
NEW met1 ( 3333070 4973225 ) ( 3332985 * )
NEW met2 ( 3333125 4973075 ) ( 3333245 * )
NEW met2 ( 3333245 4972915 ) ( * 4972935 )
NEW met2 ( 3372870 3618915 ) via_260_260_vh
NEW met2 ( 3369280 3618855 ) ( 3372670 * )
NEW met1 ( 3372810 3618825 ) ( 3372930 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[27] ( sky130_fd_sc_hd__buf_8_119 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3372110 1148620 ) ( * 1152370 )
NEW met1 ( 3371830 1148480 ) ( 3372110 * )
NEW met1 ( 3371830 216450 ) ( * 1148340 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2531410 216310 ) ( 3371830 * )
NEW met1 ( 2531410 214370 ) ( * 216170 )
NEW met1 ( 2422010 214230 ) ( 2531410 * )
NEW met1 ( 2422010 214370 ) ( * 225170 )
NEW met1 ( 2246775 225310 ) ( 2422010 * )
NEW met1 ( 2246575 225250 ) via_260_260_hv ( * 225340 )
( 2246635 * )
NEW met2 ( 2246515 225480 ) ( * 232415 )
NEW met2 ( 2246515 225160 ) ( 2246635 * )
NEW met2 ( 2246515 213370 ) ( * 225020 )
NEW met1 ( 2246450 213290 ) ( 2246570 * )
NEW met1 ( 2246450 212460 ) ( 2246570 * )
NEW met1 ( 2246510 212875 ) via_260_850_vh
NEW met1 ( 2246515 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[15] ( sky130_fd_sc_hd__buf_8_108 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3367070 220090 ) ( * 1143610 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2526650 219950 ) ( 3367070 * )
NEW met1 ( 2526650 216890 ) ( * 219810 )
NEW met1 ( 2426770 216750 ) ( 2526650 * )
NEW met1 ( 2426770 216890 ) ( * 228810 )
NEW met1 ( 2217845 228950 ) ( 2426770 * )
NEW met1 ( 2217645 228890 ) via_260_260_hv ( * 228980 )
( 2217705 * )
NEW met2 ( 2217585 229120 ) ( * 232415 )
NEW met2 ( 2217585 228800 ) ( 2217705 * )
NEW met2 ( 2217585 216170 ) ( * 228660 )
NEW met2 ( 2217090 216030 ) ( 2218040 * )
NEW met2 ( 2217565 215940 ) via_1090_260_hv
NEW li1 ( 2217105 215965 ) ( 2218025 * )
NEW li1 ( 2217565 215935 ) mcon_1090_170
NEW met2 ( 2217090 215850 ) ( 2218040 * ) ;
- sky130_fd_sc_hd__buf_8_40/A ( sky130_fd_sc_hd__buf_8_40 A )
( sky130_fd_sc_hd__buf_8_17 X )
+ ROUTED met1 ( 3384835 3627135 ) mcon_170_1090
NEW met1 ( 3384770 3627670 ) ( 3384890 * )
NEW met2 ( 3375330 3626950 ) ( 3384630 * )
NEW met1 ( 3375070 3627100 ) ( 3375190 * )
NEW met1 ( 3375130 3627010 ) via_260_260_vh
NEW met2 ( 3369280 3626950 ) ( 3374930 * )
NEW met1 ( 3375070 3626920 ) ( 3375190 * )
NEW met1 ( 3375190 2260985 ) ( * 3626780 )
NEW met1 ( 3375190 2260845 ) ( 3375310 * )
NEW met1 ( 3375250 2260755 ) via_260_260_vh ( * 2260695 )
( 3384835 * ) ( * 2260690 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2260780 ) ( 3385190 * )
NEW met2 ( 3384480 2260600 ) ( 3385190 * )
NEW met2 ( 3366060 2260695 ) ( 3375050 * )
NEW met1 ( 3375190 2260665 ) ( 3375310 * )
NEW met1 ( 3384770 3626600 ) ( 3384890 * )
NEW met1 ( 3384830 3627135 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[10] ( sky130_fd_sc_hd__buf_8_17 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3375050 1170320 ) ( * 1173970 )
NEW met1 ( 3375050 1174110 ) ( 3375330 * )
NEW met1 ( 3375330 1174250 ) ( * 2256660 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3375210 2256800 ) ( 3375330 * )
NEW met1 ( 3375270 2256890 ) via_260_260_vh
NEW met1 ( 3375210 2256980 ) ( 3375330 * )
NEW met2 ( 3375470 2256830 ) ( 3384630 * )
NEW met1 ( 3384770 2257550 ) ( 3384890 * )
NEW met1 ( 3384770 2256480 ) ( 3384890 * )
NEW met1 ( 3384830 2257015 ) via_260_1090_vh
NEW met1 ( 3384835 2257015 ) mcon_170_1090
NEW met2 ( 3366060 2256830 ) ( 3375070 * ) ;
- sky130_fd_sc_hd__buf_8_28/A ( sky130_fd_sc_hd__buf_8_28 A )
( sky130_fd_sc_hd__buf_8_193 X )
+ ROUTED met1 ( 3381775 3619805 ) mcon_170_1090
NEW met1 ( 3381710 3620340 ) ( 3381830 * )
NEW met2 ( 3373350 3619825 ) ( 3381570 * )
NEW met1 ( 3373090 3619975 ) ( 3373210 * )
NEW met1 ( 3373090 3620115 ) ( * 4973365 )
NEW met1 ( 3332765 4973505 ) ( 3373090 * )
NEW met1 ( 3332565 4973445 ) via_260_260_hv ( * 4973535 )
( 3332625 * )
NEW met2 ( 3332625 4973675 ) ( * 4982545 )
NEW met1 ( 3332555 4983455 ) ( 3332675 * )
NEW met1 ( 3332555 4982625 ) ( 3332675 * )
NEW met1 ( 3332615 4983040 ) via_260_850_vh
NEW met1 ( 3332610 4983040 ) mcon_170_850
NEW met2 ( 3332505 4973355 ) ( 3332625 * )
NEW met2 ( 3332625 4972915 ) ( * 4973215 )
NEW met2 ( 3373150 3619885 ) via_260_260_vh
NEW met2 ( 3369280 3619825 ) ( 3372950 * )
NEW met1 ( 3373090 3619795 ) ( 3373210 * )
NEW met1 ( 3381710 3619270 ) ( 3381830 * )
NEW met1 ( 3381770 3619805 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[14] ( sky130_fd_sc_hd__buf_8_39 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 840715 4974835 ) ( 856480 * )
NEW met1 ( 840515 4974895 ) via_260_260_hv ( * 4974985 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 840575 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 840455 4975125 ) ( * 4981590 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met2 ( 839960 4981730 ) ( 840910 * )
NEW met2 ( 840435 4981820 ) via_1090_260_hv mcon_1090_170
( * 4981795 ) ( 840895 * )
NEW met2 ( 839960 4981910 ) ( 840910 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 840455 4974805 ) ( 840575 * )
NEW met2 ( 840455 4974470 ) ( * 4974665 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[26] ( sky130_fd_sc_hd__buf_8_129 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 226925 1678030 ) ( * 1766580 )
NEW met1 ( 226805 1677890 ) ( 226925 * )
NEW met1 ( 226865 1677800 ) via_260_260_vh ( * 1677740 )
( 227030 * )
NEW met2 ( 203765 1677740 ) ( 226665 * )
NEW met2 ( 203270 1677735 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1677825 ) ( 203625 * )
NEW met2 ( 202915 1677645 ) ( 203625 * )
NEW met1 ( 226805 1677710 ) ( 226925 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[28] ( sky130_fd_sc_hd__buf_8_118 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3372670 215890 ) ( * 1153380 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2532250 215750 ) ( 3372670 * )
NEW met1 ( 2532250 214090 ) ( * 215610 )
NEW met1 ( 2421170 213950 ) ( 2532250 * )
NEW met1 ( 2421170 214090 ) ( * 224610 )
NEW met1 ( 2247745 224750 ) ( 2421170 * )
NEW met1 ( 2247545 224690 ) via_260_260_hv ( * 224780 )
( 2247605 * )
NEW met2 ( 2247485 224920 ) ( * 232415 )
NEW met2 ( 2247485 224600 ) ( 2247605 * )
NEW met2 ( 2247485 216170 ) ( * 224460 )
NEW met2 ( 2246990 216030 ) ( 2247940 * )
NEW met2 ( 2247465 215940 ) via_1090_260_hv
NEW li1 ( 2247005 215965 ) ( 2247925 * )
NEW li1 ( 2247465 215935 ) mcon_1090_170
NEW met2 ( 2246990 215850 ) ( 2247940 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[17] ( sky130_fd_sc_hd__buf_8_107 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3365390 1137410 ) ( * 1140620 )
NEW met1 ( 3365110 1137270 ) ( 3365390 * )
NEW met1 ( 3365110 221490 ) ( * 1137130 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2524690 221350 ) ( 3365110 * )
NEW met1 ( 2524690 217730 ) ( * 221210 )
NEW met1 ( 2428730 217590 ) ( 2524690 * )
NEW met1 ( 2428730 217730 ) ( * 230210 )
NEW met1 ( 2210895 230350 ) ( 2428730 * )
NEW met1 ( 2210695 230290 ) via_260_260_hv ( * 230380 )
( 2210755 * )
NEW met2 ( 2210635 230520 ) ( * 232415 )
NEW met2 ( 2210635 230200 ) ( 2210755 * )
NEW met2 ( 2210635 213370 ) ( * 230060 )
NEW met1 ( 2210570 213290 ) ( 2210690 * )
NEW met1 ( 2210570 212460 ) ( 2210690 * )
NEW met1 ( 2210630 212875 ) via_260_850_vh
NEW met1 ( 2210635 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[2] ( sky130_fd_sc_hd__buf_8_49 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3366650 1185320 ) ( * 2209440 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3366530 2209580 ) ( 3366650 * )
NEW met1 ( 3366590 2209670 ) via_260_260_vh
NEW met1 ( 3366530 2209760 ) ( 3366650 * )
NEW met2 ( 3366790 2209610 ) ( 3381775 * ) ( * 2209620 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 2209710 ) ( 3382130 * )
NEW met2 ( 3381420 2209530 ) ( 3382130 * )
NEW met2 ( 3366060 2209610 ) ( 3366390 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[2] ( sky130_fd_sc_hd__buf_8_49 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3366510 2214115 ) ( * 2275205 )
NEW met1 ( 3366510 2213975 ) ( 3366630 * )
NEW met1 ( 3366570 2213885 ) via_260_260_vh ( * 2213825 )
( 3381570 * )
NEW met1 ( 3381710 2214340 ) ( 3381830 * )
NEW met1 ( 3381710 2213270 ) ( 3381830 * )
NEW met1 ( 3381770 2213805 ) via_260_1090_vh
NEW met1 ( 3381775 2213805 ) mcon_170_1090
NEW met2 ( 3366060 2213825 ) ( 3366370 * )
NEW met1 ( 3366510 2213795 ) ( 3366630 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[10] ( sky130_fd_sc_hd__buf_8_16 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3375610 1169320 ) ( * 2257280 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3375490 2257420 ) ( 3375610 * )
NEW met1 ( 3375550 2257510 ) via_260_260_vh
NEW met1 ( 3375490 2257600 ) ( 3375610 * )
NEW met2 ( 3375750 2257450 ) ( 3381775 * ) ( * 2257460 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 2257550 ) ( 3382130 * )
NEW met2 ( 3381420 2257370 ) ( 3382130 * )
NEW met2 ( 3366060 2257450 ) ( 3375350 * ) ;
- sky130_fd_sc_hd__buf_8_41/X ( sky130_fd_sc_hd__buf_8_41 X )
( sky130_fd_sc_hd__buf_8_16 A )
+ ROUTED met1 ( 3381775 3627585 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3375610 3627570 ) ( 3381280 * )
NEW met1 ( 3375350 3627720 ) ( 3375470 * )
NEW met1 ( 3375410 3627630 ) via_260_260_vh
NEW met2 ( 3369280 3627570 ) ( 3375210 * )
NEW met1 ( 3375350 3627540 ) ( 3375470 * )
NEW met1 ( 3375470 2261835 ) ( * 3627400 )
NEW met1 ( 3375470 2261695 ) ( 3375590 * )
NEW met1 ( 3375530 2261605 ) via_260_260_vh
NEW met2 ( 3366060 2261665 ) ( 3375330 * )
NEW met2 ( 3375730 2261665 ) ( 3381570 * )
NEW met1 ( 3381710 2262180 ) ( 3381830 * )
NEW met1 ( 3381710 2261110 ) ( 3381830 * )
NEW met1 ( 3381770 2261645 ) via_260_1090_vh
NEW met1 ( 3381775 2261645 ) mcon_170_1090
NEW met1 ( 3375470 2261515 ) ( 3375590 * )
NEW met2 ( 3381420 3627670 ) ( 3382130 * )
NEW met2 ( 3381420 3627490 ) ( 3382130 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[7] ( sky130_fd_sc_hd__buf_8_27 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3371410 3640020 ) ( * 3642535 )
NEW met1 ( 3371410 3639880 ) ( 3371690 * )
NEW met1 ( 3371690 3613165 ) ( * 3639740 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3371690 3613025 ) ( 3371810 * )
NEW met1 ( 3371750 3612935 ) via_260_260_vh ( * 3612875 )
( 3384835 * ) ( * 3612870 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 3612960 ) ( 3385190 * )
NEW met2 ( 3384480 3612780 ) ( 3385190 * )
NEW met2 ( 3369280 3612875 ) ( 3371550 * )
NEW met1 ( 3371690 3612845 ) ( 3371810 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[13] ( sky130_fd_sc_hd__buf_8_38 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 846575 4975955 ) ( 858485 * )
NEW met1 ( 846375 4976015 ) via_260_260_hv ( * 4976105 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 846435 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 846435 4976245 ) ( * 4981590 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met2 ( 845940 4981730 ) ( 846890 * )
NEW met2 ( 846415 4981820 ) via_1090_260_hv mcon_1090_170
( * 4981795 ) ( 846875 * )
NEW met2 ( 845940 4981910 ) ( 846890 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 846315 4975925 ) ( 846435 * )
NEW met2 ( 846435 4975345 ) ( * 4975785 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[23] ( sky130_fd_sc_hd__buf_8_139 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 223005 1770920 ) ( * 1773580 )
NEW met1 ( 223005 1770780 ) ( 223285 * )
NEW met1 ( 223285 1696940 ) ( * 1770640 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 223165 1696800 ) ( 223285 * )
NEW met1 ( 223225 1696710 ) via_260_260_vh ( * 1696650 )
( 223770 * )
NEW met2 ( 206535 1696650 ) ( 223025 * )
NEW met1 ( 206275 1697165 ) ( 206395 * )
NEW met1 ( 206275 1696095 ) ( 206395 * )
NEW met1 ( 206335 1696630 ) via_260_1090_vh
NEW met1 ( 206330 1696630 ) mcon_170_1090
NEW met1 ( 223165 1696620 ) ( 223285 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[26] ( sky130_fd_sc_hd__buf_8_128 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 226365 1764980 ) ( * 1767580 )
NEW met1 ( 226365 1764840 ) ( 226645 * )
NEW met1 ( 226645 1679000 ) ( * 1764700 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 226525 1678860 ) ( 226645 * )
NEW met1 ( 226585 1678770 ) via_260_260_vh ( * 1678710 )
( 227030 * )
NEW met2 ( 206535 1678710 ) ( 226385 * )
NEW met1 ( 206275 1679225 ) ( 206395 * )
NEW met1 ( 206275 1678155 ) ( 206395 * )
NEW met1 ( 206335 1678690 ) via_260_1090_vh
NEW met1 ( 206330 1678690 ) mcon_170_1090
NEW met1 ( 226525 1678680 ) ( 226645 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[27] ( sky130_fd_sc_hd__buf_8_117 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3371550 216730 ) ( * 1151370 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2531130 216590 ) ( 3371550 * )
NEW met1 ( 2531130 214650 ) ( * 216450 )
NEW met1 ( 2422290 214510 ) ( 2531130 * )
NEW met1 ( 2422290 214650 ) ( * 225450 )
NEW met1 ( 2241765 225590 ) ( 2422290 * )
NEW met1 ( 2241565 225530 ) via_260_260_hv ( * 225620 )
( 2241625 * )
NEW met2 ( 2241505 225760 ) ( * 232415 )
NEW met2 ( 2241505 225440 ) ( 2241625 * )
NEW met2 ( 2241505 216170 ) ( * 225300 )
NEW met2 ( 2241010 216030 ) ( 2241960 * )
NEW met2 ( 2241485 215940 ) via_1090_260_hv
NEW li1 ( 2241025 215965 ) ( 2241945 * )
NEW li1 ( 2241485 215935 ) mcon_1090_170
NEW met2 ( 2241010 215850 ) ( 2241960 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[16] ( sky130_fd_sc_hd__buf_8_106 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3365950 220930 ) ( * 1141620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2525530 220790 ) ( 3365950 * )
NEW met1 ( 2525530 217450 ) ( * 220650 )
NEW met1 ( 2427890 217310 ) ( 2525530 * )
NEW met1 ( 2427890 217450 ) ( * 229650 )
NEW met1 ( 2211865 229790 ) ( 2427890 * )
NEW met1 ( 2211665 229730 ) via_260_260_hv ( * 229820 )
( 2211725 * )
NEW met2 ( 2211605 229960 ) ( * 232415 )
NEW met2 ( 2211605 229640 ) ( 2211725 * )
NEW met2 ( 2211605 216170 ) ( * 229500 )
NEW met2 ( 2211110 216030 ) ( 2212060 * )
NEW met2 ( 2211585 215940 ) via_1090_260_hv
NEW li1 ( 2211125 215965 ) ( 2212045 * )
NEW li1 ( 2211585 215935 ) mcon_1090_170
NEW met2 ( 2211110 215850 ) ( 2212060 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[2] ( sky130_fd_sc_hd__buf_8_48 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3365950 2270970 ) ( * 2274205 )
NEW met1 ( 3365950 2270830 ) ( 3366230 * )
NEW met1 ( 3366230 2213145 ) ( * 2270690 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3366230 2213005 ) ( 3366350 * )
NEW met1 ( 3366290 2212915 ) via_260_260_vh ( * 2212855 )
( 3384835 * ) ( * 2212850 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2212940 ) ( 3385190 * )
NEW met2 ( 3384480 2212760 ) ( 3385190 * )
NEW met2 ( 3366060 2212855 ) ( 3366090 * )
NEW met1 ( 3366230 2212825 ) ( 3366350 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[2] ( sky130_fd_sc_hd__buf_8_48 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3366090 1186320 ) ( * 1189860 )
NEW met1 ( 3366090 1190000 ) ( 3366370 * )
NEW met1 ( 3366370 1190140 ) ( * 2208820 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3366250 2208960 ) ( 3366370 * )
NEW met1 ( 3366310 2209050 ) via_260_260_vh
NEW met1 ( 3366250 2209140 ) ( 3366370 * )
NEW met2 ( 3366510 2208990 ) ( 3384630 * )
NEW met1 ( 3384770 2209710 ) ( 3384890 * )
NEW met1 ( 3384770 2208640 ) ( 3384890 * )
NEW met1 ( 3384830 2209175 ) via_260_1090_vh
NEW met1 ( 3384835 2209175 ) mcon_170_1090
NEW met2 ( 3366060 2208990 ) ( 3366110 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_59/X ( sky130_fd_sc_hd__buf_8_59 X )
( sky130_fd_sc_hd__buf_8_151 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 748345 215935 ) mcon_170_850
NEW met1 ( 748280 216350 ) ( 748400 * )
NEW met2 ( 748330 216430 ) ( * 226820 )
NEW met2 ( 748330 226960 ) ( 748450 * )
NEW met2 ( 748390 227050 ) via_260_260_hv
NEW met2 ( 748330 227140 ) ( 748450 * )
NEW met2 ( 748330 227280 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 212225 226990 ) ( 748190 * )
NEW met1 ( 212225 227130 ) ( * 1751445 )
NEW met1 ( 212225 1751585 ) ( 212345 * )
NEW met1 ( 212285 1751675 ) via_260_260_vh
NEW met1 ( 212225 1751765 ) ( 212345 * )
NEW met2 ( 212485 1751615 ) ( 223670 * )
NEW met2 ( 203475 1751615 ) ( 212085 * )
NEW met1 ( 203215 1752335 ) ( 203335 * )
NEW met1 ( 203215 1751265 ) ( 203335 * )
NEW met1 ( 203275 1751800 ) via_260_1090_vh
NEW met1 ( 203270 1751800 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 748280 215520 ) ( 748400 * )
NEW met1 ( 748340 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_59/A ( sky130_fd_sc_hd__buf_8_59 A )
( sky130_fd_sc_hd__buf_8_113 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 752525 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 752050 216030 ) ( 753000 * )
NEW met2 ( 752545 216170 ) ( * 226840 )
NEW met2 ( 752545 226980 ) ( 752665 * )
NEW met2 ( 752605 227070 ) via_260_260_hv
NEW met2 ( 752545 227160 ) ( 752665 * )
NEW met2 ( 752545 227300 ) ( * 232275 )
NEW met1 ( 752805 227130 ) ( 2225390 * ) ( * 227190 )
via_260_260_hv ( * 227280 ) ( 2225450 * )
NEW met2 ( 2225330 227420 ) ( * 232415 )
NEW met2 ( 2225330 227100 ) ( 2225450 * )
NEW met2 ( 2225330 216430 ) ( * 226960 )
NEW met1 ( 2225280 216350 ) ( 2225400 * )
NEW met1 ( 2225280 215520 ) ( 2225400 * )
NEW met1 ( 2225340 215935 ) via_260_850_vh
NEW met1 ( 2225345 215935 ) mcon_170_850
NEW met2 ( 752050 215850 ) ( 753000 * )
NEW li1 ( 752065 215965 ) ( 752985 * ) ;
- sky130_fd_sc_hd__buf_8_37/X ( sky130_fd_sc_hd__buf_8_37 X )
( sky130_fd_sc_hd__buf_8_24 A )
+ ROUTED met1 ( 3384835 2236775 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3384480 2236860 ) ( 3385190 * )
NEW met2 ( 3384480 2236680 ) ( 3385190 * )
NEW met2 ( 3370970 2236775 ) ( 3384340 * )
NEW met1 ( 3370710 2236925 ) ( 3370830 * )
NEW met1 ( 3370710 2237065 ) ( * 3602860 )
NEW met1 ( 3370590 3603000 ) ( 3370710 * )
NEW met1 ( 3370650 3603090 ) via_260_260_vh
NEW met1 ( 3370590 3603180 ) ( 3370710 * )
NEW met1 ( 3370710 3603320 ) ( * 3603205 )
NEW met2 ( 3370850 3603030 ) ( 3384630 * )
NEW met1 ( 3384770 3603750 ) ( 3384890 * )
NEW met1 ( 3384770 3602680 ) ( 3384890 * )
NEW met1 ( 3384830 3603215 ) via_260_1090_vh
NEW met1 ( 3384835 3603215 ) mcon_170_1090
NEW met2 ( 3370400 3603030 ) ( 3370450 * )
NEW met2 ( 3370770 2236835 ) via_260_260_vh
NEW met2 ( 3366060 2236775 ) ( 3370570 * )
NEW met1 ( 3370710 2236745 ) ( 3370830 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[6] ( sky130_fd_sc_hd__buf_8_37 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3370570 1178320 ) ( * 1181790 )
NEW met1 ( 3370570 1181930 ) ( 3370850 * )
NEW met1 ( 3370850 1182070 ) ( * 2232740 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3370730 2232880 ) ( 3370850 * )
NEW met1 ( 3370790 2232970 ) via_260_260_vh
NEW met1 ( 3370730 2233060 ) ( 3370850 * )
NEW met2 ( 3370990 2232910 ) ( 3384630 * )
NEW met1 ( 3384770 2233630 ) ( 3384890 * )
NEW met1 ( 3384770 2232560 ) ( 3384890 * )
NEW met1 ( 3384830 2233095 ) via_260_1090_vh
NEW met1 ( 3384835 2233095 ) mcon_170_1090
NEW met2 ( 3366060 2232910 ) ( 3370590 * ) ;
- sky130_fd_sc_hd__buf_8_27/A ( sky130_fd_sc_hd__buf_8_27 A )
( sky130_fd_sc_hd__buf_8_15 X )
+ ROUTED met1 ( 3384835 3609195 ) mcon_170_1090
NEW met1 ( 3384770 3609730 ) ( 3384890 * )
NEW met2 ( 3371970 3609010 ) ( 3384630 * )
NEW met1 ( 3371710 3609160 ) ( 3371830 * )
NEW met1 ( 3371770 3609070 ) via_260_260_vh
NEW met2 ( 3369280 3609010 ) ( 3371570 * )
NEW met1 ( 3371710 3608980 ) ( 3371830 * )
NEW met1 ( 3371830 2243045 ) ( * 3608840 )
NEW met1 ( 3371830 2242905 ) ( 3371950 * )
NEW met1 ( 3371890 2242815 ) via_260_260_vh ( * 2242755 )
( 3384835 * ) ( * 2242750 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2242840 ) ( 3385190 * )
NEW met2 ( 3384480 2242660 ) ( 3385190 * )
NEW met2 ( 3366060 2242755 ) ( 3371690 * )
NEW met1 ( 3371830 2242725 ) ( 3371950 * )
NEW met1 ( 3384770 3608660 ) ( 3384890 * )
NEW met1 ( 3384830 3609195 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[7] ( sky130_fd_sc_hd__buf_8_15 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3371690 1176320 ) ( * 1179900 )
NEW met1 ( 3371690 1180040 ) ( 3371970 * )
NEW met1 ( 3371970 1180180 ) ( * 2238720 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3371850 2238860 ) ( 3371970 * )
NEW met1 ( 3371910 2238950 ) via_260_260_vh
NEW met1 ( 3371850 2239040 ) ( 3371970 * )
NEW met2 ( 3372110 2238890 ) ( 3384630 * )
NEW met1 ( 3384770 2239610 ) ( 3384890 * )
NEW met1 ( 3384770 2238540 ) ( 3384890 * )
NEW met1 ( 3384830 2239075 ) via_260_1090_vh
NEW met1 ( 3384835 2239075 ) mcon_170_1090
NEW met2 ( 3366060 2238890 ) ( 3371710 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[7] ( sky130_fd_sc_hd__buf_8_26 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3371970 3614135 ) ( * 3643535 )
NEW met1 ( 3371970 3613995 ) ( 3372090 * )
NEW met1 ( 3372030 3613905 ) via_260_260_vh ( * 3613845 )
( 3381570 * )
NEW met1 ( 3381710 3614360 ) ( 3381830 * )
NEW met1 ( 3381710 3613290 ) ( 3381830 * )
NEW met1 ( 3381770 3613825 ) via_260_1090_vh
NEW met1 ( 3381775 3613825 ) mcon_170_1090
NEW met2 ( 3369280 3613845 ) ( 3371830 * )
NEW met1 ( 3371970 3613815 ) ( 3372090 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_171/X ( sky130_fd_sc_hd__buf_8_171 X )
( sky130_fd_sc_hd__buf_8_149 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 3010255 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3010340 ) ( 206575 * )
NEW met2 ( 206715 3010240 ) ( 217545 * )
NEW met1 ( 217685 3010390 ) ( 217805 * )
NEW met1 ( 217745 3010300 ) via_260_260_vh
NEW met1 ( 217685 3010210 ) ( 217805 * )
NEW met1 ( 217685 1726840 ) ( * 3010070 )
NEW met1 ( 217565 1726700 ) ( 217685 * )
NEW met1 ( 217625 1726610 ) via_260_260_vh ( * 1726550 )
( 223670 * )
NEW met2 ( 206535 1726550 ) ( 217425 * )
NEW met1 ( 206275 1727065 ) ( 206395 * )
NEW met1 ( 206275 1725995 ) ( 206395 * )
NEW met1 ( 206335 1726530 ) via_260_1090_vh
NEW met1 ( 206330 1726530 ) mcon_170_1090
NEW met1 ( 217565 1726520 ) ( 217685 * )
NEW met2 ( 217945 3010240 ) ( 221530 * )
NEW met2 ( 205865 3010160 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[23] ( sky130_fd_sc_hd__buf_8_138 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 223565 1695970 ) ( * 1772580 )
NEW met1 ( 223445 1695830 ) ( 223565 * )
NEW met1 ( 223505 1695740 ) via_260_260_vh ( * 1695680 )
( 223770 * )
NEW met2 ( 203765 1695680 ) ( 223305 * )
NEW met2 ( 203270 1695675 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1695765 ) ( 203625 * )
NEW met2 ( 202915 1695585 ) ( 203625 * )
NEW met1 ( 223445 1695650 ) ( 223565 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_unbuf[2] ( sky130_fd_sc_hd__buf_8_127 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3377710 212315 ) ( * 1161380 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 2537290 212175 ) ( 3377710 * )
NEW met1 ( 2537290 211850 ) ( * 212035 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2416130 211710 ) ( 2537290 * )
NEW met1 ( 2416130 211850 ) ( * 220970 )
NEW met1 ( 2271665 221110 ) ( 2416130 * )
NEW met1 ( 2271465 221050 ) via_260_260_hv ( * 221140 )
( 2271525 * )
NEW met2 ( 2271405 221280 ) ( * 232415 )
NEW met2 ( 2271405 220960 ) ( 2271525 * )
NEW met2 ( 2271405 216170 ) ( * 220820 )
NEW met2 ( 2270910 216030 ) ( 2271860 * )
NEW met2 ( 2271385 215940 ) via_1090_260_hv
NEW li1 ( 2270925 215965 ) ( 2271845 * )
NEW li1 ( 2271385 215935 ) mcon_1090_170
NEW met2 ( 2270910 215850 ) ( 2271860 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[12] ( sky130_fd_sc_hd__buf_8_116 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3370990 1146540 ) ( * 1150610 )
NEW met1 ( 3370710 1146400 ) ( 3370990 * )
NEW met1 ( 3370710 217290 ) ( * 1146260 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2530290 217150 ) ( 3370710 * )
NEW met1 ( 2530290 214930 ) ( * 217010 )
NEW met1 ( 2423130 214790 ) ( 2530290 * )
NEW met1 ( 2423130 214930 ) ( * 226010 )
NEW met1 ( 2240795 226150 ) ( 2423130 * )
NEW met1 ( 2240595 226090 ) via_260_260_hv ( * 226180 )
( 2240655 * )
NEW met2 ( 2240535 226320 ) ( * 232415 )
NEW met2 ( 2240535 226000 ) ( 2240655 * )
NEW met2 ( 2240535 213370 ) ( * 225860 )
NEW met1 ( 2240470 213290 ) ( 2240590 * )
NEW met1 ( 2240470 212460 ) ( 2240590 * )
NEW met1 ( 2240530 212875 ) via_260_850_vh
NEW met1 ( 2240535 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[17] ( sky130_fd_sc_hd__buf_8_105 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3364830 221770 ) ( * 1139620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2524410 221630 ) ( 3364830 * )
NEW met1 ( 2524410 218010 ) ( * 221490 )
NEW met1 ( 2429010 217870 ) ( 2524410 * )
NEW met1 ( 2429010 218010 ) ( * 230490 )
NEW met1 ( 2205885 230630 ) ( 2429010 * )
NEW met1 ( 2205685 230570 ) via_260_260_hv ( * 230660 )
( 2205745 * )
NEW met2 ( 2205625 230800 ) ( * 232415 )
NEW met2 ( 2205625 230480 ) ( 2205745 * )
NEW met2 ( 2205625 216170 ) ( * 230340 )
NEW met2 ( 2205130 216030 ) ( 2206080 * )
NEW met2 ( 2205605 215940 ) via_1090_260_hv
NEW li1 ( 2205145 215965 ) ( 2206065 * )
NEW li1 ( 2205605 215935 ) mcon_1090_170
NEW met2 ( 2205130 215850 ) ( 2206080 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[1] ( sky130_fd_sc_hd__buf_8_47 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3364830 2268860 ) ( * 2272205 )
NEW met1 ( 3364830 2268720 ) ( 3365110 * )
NEW met1 ( 3365110 2207165 ) ( * 2268580 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3365110 2207025 ) ( 3365230 * )
NEW met1 ( 3365170 2206935 ) via_260_260_vh ( * 2206875 )
( 3384835 * ) ( * 2206870 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2206960 ) ( 3385190 * )
NEW met2 ( 3384480 2206780 ) ( 3385190 * )
NEW met2 ( 3364935 2206875 ) ( 3364970 * )
NEW met1 ( 3365110 2206845 ) ( 3365230 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[1] ( sky130_fd_sc_hd__buf_8_47 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3364970 1188320 ) ( * 1191590 )
NEW met1 ( 3364970 1191730 ) ( 3365250 * )
NEW met1 ( 3365250 1191870 ) ( * 2202840 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3365130 2202980 ) ( 3365250 * )
NEW met1 ( 3365190 2203070 ) via_260_260_vh
NEW met1 ( 3365130 2203160 ) ( 3365250 * )
NEW met2 ( 3365390 2203010 ) ( 3384630 * )
NEW met1 ( 3384770 2203730 ) ( 3384890 * )
NEW met1 ( 3384770 2202660 ) ( 3384890 * )
NEW met1 ( 3384830 2203195 ) via_260_1090_vh
NEW met1 ( 3384835 2203195 ) mcon_170_1090
NEW met2 ( 3364970 2203010 ) ( 3364990 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_69/X ( sky130_fd_sc_hd__buf_8_69 X )
( sky130_fd_sc_hd__buf_8_148 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 718445 215935 ) mcon_170_850
NEW met1 ( 718380 216350 ) ( 718500 * )
NEW met2 ( 718430 216430 ) ( * 230460 )
NEW met2 ( 718430 230600 ) ( 718550 * )
NEW met2 ( 718490 230690 ) via_260_260_hv
NEW met2 ( 718430 230780 ) ( 718550 * )
NEW met2 ( 718430 230920 ) ( * 232275 )
NEW met1 ( 701365 230630 ) ( 718290 * )
NEW met1 ( 701365 230770 ) ( * 231050 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 217825 231190 ) ( 701365 * )
NEW met1 ( 217825 231330 ) ( * 1721545 )
NEW met1 ( 217825 1721685 ) ( 217945 * )
NEW met1 ( 217885 1721775 ) via_260_260_vh
NEW met1 ( 217825 1721865 ) ( 217945 * )
NEW met2 ( 218085 1721715 ) ( 223670 * )
NEW met2 ( 203475 1721715 ) ( 217685 * )
NEW met1 ( 203215 1722435 ) ( 203335 * )
NEW met1 ( 203215 1721365 ) ( 203335 * )
NEW met1 ( 203275 1721900 ) via_260_1090_vh
NEW met1 ( 203270 1721900 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 718380 215520 ) ( 718500 * )
NEW met1 ( 718440 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_69/A ( sky130_fd_sc_hd__buf_8_69 A )
( sky130_fd_sc_hd__buf_8_104 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 722625 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 722150 216030 ) ( 723100 * )
NEW met2 ( 722645 216170 ) ( * 230480 )
NEW met2 ( 722645 230620 ) ( 722765 * )
NEW met2 ( 722705 230710 ) via_260_260_hv
NEW met2 ( 722645 230800 ) ( 722765 * )
NEW met2 ( 722645 230940 ) ( * 232275 )
NEW met1 ( 722905 230770 ) ( 784805 * )
NEW met1 ( 784805 230910 ) ( * 231190 )
NEW met1 ( 784805 231330 ) ( 2195490 * ) ( * 231390 )
via_260_260_hv ( * 231480 ) ( 2195550 * )
NEW met2 ( 2195430 231620 ) ( * 232415 )
NEW met2 ( 2195430 231300 ) ( 2195550 * )
NEW met2 ( 2195430 216430 ) ( * 231160 )
NEW met1 ( 2195380 216350 ) ( 2195500 * )
NEW met1 ( 2195380 215520 ) ( 2195500 * )
NEW met1 ( 2195440 215935 ) via_260_850_vh
NEW met1 ( 2195445 215935 ) mcon_170_850
NEW met2 ( 722150 215850 ) ( 723100 * )
NEW li1 ( 722165 215965 ) ( 723085 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_58/X ( sky130_fd_sc_hd__buf_8_58 X )
( sky130_fd_sc_hd__buf_8_112 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 751575 212875 ) mcon_170_850
NEW met1 ( 751510 213290 ) ( 751630 * )
NEW met2 ( 751575 213370 ) ( * 227400 )
NEW met2 ( 751575 227540 ) ( 751695 * )
NEW met2 ( 751635 227630 ) via_260_260_hv
NEW met2 ( 751575 227720 ) ( 751695 * )
NEW met2 ( 751575 227860 ) ( * 232275 )
NEW met1 ( 751835 227690 ) ( 2224770 * ) ( * 227750 )
via_260_260_hv ( * 227840 ) ( 2224830 * )
NEW met2 ( 2224710 227980 ) ( * 232415 )
NEW met2 ( 2224710 227660 ) ( 2224830 * )
NEW met2 ( 2224710 213110 ) ( * 227520 )
NEW met2 ( 2224420 212970 ) ( 2225370 * )
NEW met2 ( 2224895 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2224420 212790 ) ( 2225370 * )
NEW met1 ( 751510 212460 ) ( 751630 * )
NEW met1 ( 751570 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_58/A ( sky130_fd_sc_hd__buf_8_58 A )
( sky130_fd_sc_hd__buf_8_152 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 747895 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 747420 212970 ) ( 748370 * )
NEW met2 ( 747710 213110 ) ( * 227380 )
NEW met2 ( 747710 227520 ) ( 747830 * )
NEW met2 ( 747770 227610 ) via_260_260_hv
NEW met2 ( 747710 227700 ) ( 747830 * )
NEW met2 ( 747710 227840 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 213065 227550 ) ( 747570 * )
NEW met1 ( 213065 227690 ) ( * 1746085 )
NEW met1 ( 213065 1746225 ) ( 213185 * )
NEW met1 ( 213125 1746315 ) via_260_260_vh
NEW met1 ( 213065 1746405 ) ( 213185 * )
NEW met2 ( 213325 1746255 ) ( 223670 * )
NEW met2 ( 206825 1746255 ) ( 212925 * )
NEW met2 ( 206330 1746265 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1746355 ) ( 206685 * )
NEW met2 ( 205975 1746175 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 747420 212790 ) ( 748370 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[6] ( sky130_fd_sc_hd__buf_8_36 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3371130 1177320 ) ( * 2233360 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3371010 2233500 ) ( 3371130 * )
NEW met1 ( 3371070 2233590 ) via_260_260_vh
NEW met1 ( 3371010 2233680 ) ( 3371130 * )
NEW met2 ( 3371270 2233530 ) ( 3381775 * ) ( * 2233540 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 2233630 ) ( 3382130 * )
NEW met2 ( 3381420 2233450 ) ( 3382130 * )
NEW met2 ( 3366060 2233530 ) ( 3370870 * ) ;
- sky130_fd_sc_hd__buf_8_36/A ( sky130_fd_sc_hd__buf_8_36 A )
( sky130_fd_sc_hd__buf_8_25 X )
+ ROUTED met1 ( 3381775 2237725 ) mcon_170_1090
NEW met1 ( 3381710 2238260 ) ( 3381830 * )
NEW met2 ( 3371250 2237745 ) ( 3381570 * )
NEW met1 ( 3370990 2237895 ) ( 3371110 * )
NEW met1 ( 3370990 2238035 ) ( * 3603480 )
NEW met1 ( 3370870 3603620 ) ( 3370990 * )
NEW met1 ( 3370930 3603710 ) via_260_260_vh
NEW met1 ( 3370870 3603800 ) ( 3370990 * )
NEW met2 ( 3371130 3603650 ) ( 3381775 * ) ( * 3603660 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 3603750 ) ( 3382130 * )
NEW met2 ( 3381420 3603570 ) ( 3382130 * )
NEW met2 ( 3370400 3603650 ) ( 3370730 * )
NEW met2 ( 3371050 2237805 ) via_260_260_vh
NEW met2 ( 3366060 2237745 ) ( 3370850 * )
NEW met1 ( 3370990 2237715 ) ( 3371110 * )
NEW met1 ( 3381710 2237190 ) ( 3381830 * )
NEW met1 ( 3381770 2237725 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[7] ( sky130_fd_sc_hd__buf_8_14 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3372250 1175320 ) ( * 2239340 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3372130 2239480 ) ( 3372250 * )
NEW met1 ( 3372190 2239570 ) via_260_260_vh
NEW met1 ( 3372130 2239660 ) ( 3372250 * )
NEW met2 ( 3372390 2239510 ) ( 3381775 * ) ( * 2239520 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 2239610 ) ( 3382130 * )
NEW met2 ( 3381420 2239430 ) ( 3382130 * )
NEW met2 ( 3366060 2239510 ) ( 3371990 * ) ;
- sky130_fd_sc_hd__buf_8_26/X ( sky130_fd_sc_hd__buf_8_26 X )
( sky130_fd_sc_hd__buf_8_14 A )
+ ROUTED met1 ( 3381775 3609645 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3372250 3609630 ) ( 3381280 * )
NEW met1 ( 3371990 3609780 ) ( 3372110 * )
NEW met1 ( 3372050 3609690 ) via_260_260_vh
NEW met2 ( 3369280 3609630 ) ( 3371850 * )
NEW met1 ( 3371990 3609600 ) ( 3372110 * )
NEW met1 ( 3372110 2244015 ) ( * 3609460 )
NEW met1 ( 3372110 2243875 ) ( 3372230 * )
NEW met1 ( 3372170 2243785 ) via_260_260_vh ( * 2243725 )
( 3381570 * )
NEW met1 ( 3381710 2244240 ) ( 3381830 * )
NEW met1 ( 3381710 2243170 ) ( 3381830 * )
NEW met1 ( 3381770 2243705 ) via_260_1090_vh
NEW met1 ( 3381775 2243705 ) mcon_170_1090
NEW met2 ( 3366060 2243725 ) ( 3371970 * )
NEW met1 ( 3372110 2243695 ) ( 3372230 * )
NEW met2 ( 3381420 3609730 ) ( 3382130 * )
NEW met2 ( 3381420 3609550 ) ( 3382130 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[6] ( sky130_fd_sc_hd__buf_8_25 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3370850 3608155 ) ( * 3641535 )
NEW met1 ( 3370850 3608015 ) ( 3370970 * )
NEW met1 ( 3370910 3607925 ) via_260_260_vh ( * 3607865 )
( 3381570 * )
NEW met1 ( 3381710 3608380 ) ( 3381830 * )
NEW met1 ( 3381710 3607310 ) ( 3381830 * )
NEW met1 ( 3381770 3607845 ) via_260_1090_vh
NEW met1 ( 3381775 3607845 ) mcon_170_1090
NEW met2 ( 3370400 3607865 ) ( 3370710 * )
NEW met1 ( 3370850 3607835 ) ( 3370970 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_170/A ( sky130_fd_sc_hd__buf_8_170 A )
( sky130_fd_sc_hd__buf_8_148 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3009805 ) mcon_170_1090
NEW met1 ( 203105 3010340 ) ( 203225 * )
NEW met2 ( 203365 3009620 ) ( 217825 * )
NEW met1 ( 217965 3009770 ) ( 218085 * )
NEW met1 ( 218025 3009680 ) via_260_260_vh
NEW met1 ( 217965 3009590 ) ( 218085 * )
NEW met1 ( 217965 1725870 ) ( * 3009450 )
NEW met1 ( 217845 1725730 ) ( 217965 * )
NEW met1 ( 217905 1725640 ) via_260_260_vh ( * 1725580 )
( 223670 * )
NEW met2 ( 203765 1725580 ) ( 217705 * )
NEW met2 ( 203270 1725575 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1725665 ) ( 203625 * )
NEW met2 ( 202915 1725485 ) ( 203625 * )
NEW met1 ( 217845 1725550 ) ( 217965 * )
NEW met2 ( 218225 3009620 ) ( 221530 * )
NEW met1 ( 203105 3009270 ) ( 203225 * )
NEW met1 ( 203165 3009805 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_178/A ( sky130_fd_sc_hd__buf_8_178 A )
( sky130_fd_sc_hd__buf_8_137 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 2985885 ) mcon_170_1090
NEW met1 ( 203105 2986420 ) ( 203225 * )
NEW met2 ( 203365 2985700 ) ( 222305 * )
NEW met1 ( 222445 2985850 ) ( 222565 * )
NEW met1 ( 222505 2985760 ) via_260_260_vh
NEW met1 ( 222445 2985670 ) ( 222565 * )
NEW met1 ( 222445 1701950 ) ( * 2985530 )
NEW met1 ( 222325 1701810 ) ( 222445 * )
NEW met1 ( 222385 1701720 ) via_260_260_vh ( * 1701660 )
( 223670 * )
NEW met2 ( 203765 1701660 ) ( 222185 * )
NEW met2 ( 203270 1701655 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1701745 ) ( 203625 * )
NEW met2 ( 202915 1701565 ) ( 203625 * )
NEW met1 ( 222325 1701630 ) ( 222445 * )
NEW met2 ( 222705 2985700 ) ( 222650 * )
NEW met1 ( 203105 2985350 ) ( 203225 * )
NEW met1 ( 203165 2985885 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_unbuf[0] ( sky130_fd_sc_hd__buf_8_126 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3376030 213370 ) ( * 1159370 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2535610 213230 ) ( 3376030 * )
NEW met1 ( 2535610 212410 ) ( * 213090 )
NEW met1 ( 2417810 212270 ) ( 2535610 * )
NEW met1 ( 2417810 212410 ) ( * 222090 )
NEW met1 ( 2265565 222230 ) ( 2417810 * )
NEW met1 ( 2265365 222170 ) via_260_260_hv ( * 222260 )
( 2265425 * )
NEW met2 ( 2265425 222400 ) ( * 232415 )
NEW met2 ( 2265305 222080 ) ( 2265425 * )
NEW met2 ( 2265425 216170 ) ( * 221940 )
NEW met2 ( 2264930 216030 ) ( 2265880 * )
NEW met2 ( 2265405 215940 ) via_1090_260_hv
NEW li1 ( 2264945 215965 ) ( 2265865 * )
NEW li1 ( 2265405 215935 ) mcon_1090_170
NEW met2 ( 2264930 215850 ) ( 2265880 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[12] ( sky130_fd_sc_hd__buf_8_115 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3370430 217570 ) ( * 1149610 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2530010 217430 ) ( 3370430 * )
NEW met1 ( 2530010 215210 ) ( * 217290 )
NEW met1 ( 2423410 215070 ) ( 2530010 * )
NEW met1 ( 2423410 215210 ) ( * 226290 )
NEW met1 ( 2235785 226430 ) ( 2423410 * )
NEW met1 ( 2235585 226370 ) via_260_260_hv ( * 226460 )
( 2235645 * )
NEW met2 ( 2235525 226600 ) ( * 232415 )
NEW met2 ( 2235525 226280 ) ( 2235645 * )
NEW met2 ( 2235525 216170 ) ( * 226140 )
NEW met2 ( 2235030 216030 ) ( 2235980 * )
NEW met2 ( 2235505 215940 ) via_1090_260_hv
NEW li1 ( 2235045 215965 ) ( 2235965 * )
NEW li1 ( 2235505 215935 ) mcon_1090_170
NEW met2 ( 2235030 215850 ) ( 2235980 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[18] ( sky130_fd_sc_hd__buf_8_104 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3363710 222610 ) ( * 1137620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2523290 222470 ) ( 3363710 * )
NEW met1 ( 2523290 218570 ) ( * 222330 )
NEW met1 ( 2430130 218430 ) ( 2523290 * )
NEW met1 ( 2430130 218570 ) ( * 231330 )
NEW met1 ( 2199905 231470 ) ( 2430130 * )
NEW met1 ( 2199705 231410 ) via_260_260_hv ( * 231500 )
( 2199765 * )
NEW met2 ( 2199645 231640 ) ( * 232415 )
NEW met2 ( 2199645 231320 ) ( 2199765 * )
NEW met2 ( 2199645 216170 ) ( * 231180 )
NEW met2 ( 2199150 216030 ) ( 2200100 * )
NEW met2 ( 2199625 215940 ) via_1090_260_hv
NEW li1 ( 2199165 215965 ) ( 2200085 * )
NEW li1 ( 2199625 215935 ) mcon_1090_170
NEW met2 ( 2199150 215850 ) ( 2200100 * ) ;
- sky130_fd_sc_hd__buf_8_183/X ( sky130_fd_sc_hd__buf_8_183 X )
( sky130_fd_sc_hd__buf_8_159 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206095 4452365 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205740 4452450 ) ( 206450 * )
NEW met2 ( 206590 4452350 ) ( 210965 * )
NEW met1 ( 211105 4452500 ) ( 211225 * )
NEW met1 ( 211165 4452410 ) via_260_260_vh
NEW met1 ( 211105 4452320 ) ( 211225 * )
NEW met1 ( 211105 3050625 ) ( * 4452180 )
NEW met1 ( 210985 3050485 ) ( 211105 * )
NEW met1 ( 211045 3050395 ) via_260_260_vh ( * 3050335 )
( 221530 * )
NEW met2 ( 206425 3050335 ) ( 210845 * )
NEW met1 ( 206165 3050850 ) ( 206285 * )
NEW met1 ( 206165 3049780 ) ( 206285 * )
NEW met1 ( 206225 3050315 ) via_260_1090_vh
NEW met1 ( 206220 3050315 ) mcon_170_1090
NEW met1 ( 210985 3050305 ) ( 211105 * )
NEW met2 ( 211365 4452350 ) ( 216065 * )
NEW met2 ( 205740 4452270 ) ( 206450 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[1] ( sky130_fd_sc_hd__buf_8_46 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3365530 1187320 ) ( * 2203460 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3365410 2203600 ) ( 3365530 * )
NEW met1 ( 3365470 2203690 ) via_260_260_vh
NEW met1 ( 3365410 2203780 ) ( 3365530 * )
NEW met2 ( 3365670 2203630 ) ( 3381775 * ) ( * 2203640 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2203730 ) ( 3382130 * )
NEW met2 ( 3381420 2203550 ) ( 3382130 * )
NEW met2 ( 3364970 2203630 ) ( 3365270 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[1] ( sky130_fd_sc_hd__buf_8_46 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3365390 2208135 ) ( * 2273205 )
NEW met1 ( 3365390 2207995 ) ( 3365510 * )
NEW met1 ( 3365450 2207905 ) via_260_260_vh ( * 2207845 )
( 3381570 * )
NEW met1 ( 3381710 2208360 ) ( 3381830 * )
NEW met1 ( 3381710 2207290 ) ( 3381830 * )
NEW met1 ( 3381770 2207825 ) via_260_1090_vh
NEW met1 ( 3381775 2207825 ) mcon_170_1090
NEW met2 ( 3364935 2207845 ) ( 3365250 * )
NEW met1 ( 3365390 2207815 ) ( 3365510 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_93/A ( sky130_fd_sc_hd__buf_8_93 A )
( sky130_fd_sc_hd__buf_8_79 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2165095 212875 ) mcon_1090_170
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2164620 212970 ) ( 2165570 * )
NEW met2 ( 2164910 213110 ) ( * 235920 )
NEW met2 ( 2164910 236060 ) ( 2165030 * )
NEW met2 ( 2164970 236150 ) via_260_260_hv
NEW met2 ( 2164910 236240 ) ( 2165030 * )
NEW met2 ( 2164910 236380 ) ( * 236325 )
NEW met1 ( 780045 236090 ) ( 2164770 * )
NEW met1 ( 780045 233990 ) ( * 235950 )
NEW met1 ( 704315 233850 ) ( 780045 * )
NEW met1 ( 704315 233990 ) ( * 235950 )
NEW met1 ( 692035 236090 ) ( 704315 * )
NEW met1 ( 691835 236030 ) via_260_260_hv ( * 236120 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 691895 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 691775 236260 ) ( * 236190 )
NEW met2 ( 691775 235940 ) ( 691895 * )
NEW met2 ( 691775 213370 ) ( * 235800 )
NEW met1 ( 691710 213290 ) ( 691830 * )
NEW met1 ( 691710 212460 ) ( 691830 * )
NEW met1 ( 691770 212875 ) via_260_850_vh
NEW met1 ( 691775 212875 ) mcon_170_850
NEW met2 ( 2164620 212790 ) ( 2165570 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_79/A ( sky130_fd_sc_hd__buf_8_79 A )
( sky130_fd_sc_hd__buf_8_132 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 688095 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 687620 212970 ) ( 688570 * )
NEW met2 ( 687910 213110 ) ( * 235780 )
NEW met2 ( 687910 235920 ) ( 688030 * )
NEW met2 ( 687970 236010 ) via_260_260_hv
NEW met2 ( 687910 236100 ) ( 688030 * )
NEW met2 ( 687910 236240 ) ( * 236165 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 224265 235950 ) ( 687770 * )
NEW met1 ( 224265 236090 ) ( * 1686285 )
NEW met1 ( 224265 1686425 ) ( 224385 * )
NEW met1 ( 224325 1686515 ) via_260_260_vh
NEW met1 ( 224265 1686605 ) ( 224385 * )
NEW met2 ( 224525 1686455 ) ( 224735 * )
NEW met2 ( 206825 1686455 ) ( 224125 * )
NEW met2 ( 206330 1686465 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1686555 ) ( 206685 * )
NEW met2 ( 205975 1686375 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 687620 212790 ) ( 688570 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_68/X ( sky130_fd_sc_hd__buf_8_68 X )
( sky130_fd_sc_hd__buf_8_101 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 721675 212875 ) mcon_170_850
NEW met1 ( 721610 213290 ) ( 721730 * )
NEW met2 ( 721675 213370 ) ( * 230760 )
NEW met2 ( 721675 230900 ) ( 721795 * )
NEW met2 ( 721735 230990 ) via_260_260_hv
NEW met2 ( 721675 231080 ) ( 721795 * )
NEW met2 ( 721675 231220 ) ( * 232275 )
NEW met1 ( 721935 231050 ) ( 784245 * )
NEW met1 ( 784245 231190 ) ( * 231750 )
NEW met1 ( 784245 231890 ) ( 2194870 * ) ( * 231950 )
via_260_260_hv ( * 232040 ) ( 2194930 * )
NEW met2 ( 2194810 232180 ) ( * 232415 )
NEW met2 ( 2194810 231860 ) ( 2194930 * )
NEW met2 ( 2194810 213110 ) ( * 231720 )
NEW met2 ( 2194520 212970 ) ( 2195470 * )
NEW met2 ( 2194995 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2194520 212790 ) ( 2195470 * )
NEW met1 ( 721610 212460 ) ( 721730 * )
NEW met1 ( 721670 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_68/A ( sky130_fd_sc_hd__buf_8_68 A )
( sky130_fd_sc_hd__buf_8_141 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 717995 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 717520 212970 ) ( 718470 * )
NEW met2 ( 717810 213110 ) ( * 230740 )
NEW met2 ( 717810 230880 ) ( 717930 * )
NEW met2 ( 717870 230970 ) via_260_260_hv
NEW met2 ( 717810 231060 ) ( 717930 * )
NEW met2 ( 717810 231200 ) ( * 232275 )
NEW met1 ( 701665 230910 ) ( 717670 * )
NEW met1 ( 701665 231050 ) ( * 231610 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 218665 231750 ) ( 701665 * )
NEW met1 ( 218665 231890 ) ( * 1716185 )
NEW met1 ( 218665 1716325 ) ( 218785 * )
NEW met1 ( 218725 1716415 ) via_260_260_vh
NEW met1 ( 218665 1716505 ) ( 218785 * )
NEW met2 ( 218925 1716355 ) ( 223670 * )
NEW met2 ( 206825 1716355 ) ( 218525 * )
NEW met2 ( 206330 1716365 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1716455 ) ( 206685 * )
NEW met2 ( 205975 1716275 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 717520 212790 ) ( 718470 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_57/X ( sky130_fd_sc_hd__buf_8_57 X )
( sky130_fd_sc_hd__buf_8_157 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 754325 215935 ) mcon_170_850
NEW met1 ( 754260 216350 ) ( 754380 * )
NEW met2 ( 754310 216430 ) ( * 225980 )
NEW met2 ( 754310 226120 ) ( 754430 * )
NEW met2 ( 754370 226210 ) via_260_260_hv
NEW met2 ( 754310 226300 ) ( 754430 * )
NEW met2 ( 754310 226440 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 211105 226150 ) ( 754170 * )
NEW met1 ( 211105 226290 ) ( * 1757425 )
NEW met1 ( 211105 1757565 ) ( 211225 * )
NEW met1 ( 211165 1757655 ) via_260_260_vh
NEW met1 ( 211105 1757745 ) ( 211225 * )
NEW met2 ( 211365 1757595 ) ( 223670 * )
NEW met2 ( 203475 1757595 ) ( 210965 * )
NEW met1 ( 203215 1758315 ) ( 203335 * )
NEW met1 ( 203215 1757245 ) ( 203335 * )
NEW met1 ( 203275 1757780 ) via_260_1090_vh
NEW met1 ( 203270 1757780 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 754260 215520 ) ( 754380 * )
NEW met1 ( 754320 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_57/A ( sky130_fd_sc_hd__buf_8_57 A )
( sky130_fd_sc_hd__buf_8_115 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 758505 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 758030 216030 ) ( 758980 * )
NEW met2 ( 758525 216170 ) ( * 226000 )
NEW met2 ( 758525 226140 ) ( 758645 * )
NEW met2 ( 758585 226230 ) via_260_260_hv
NEW met2 ( 758525 226320 ) ( 758645 * )
NEW met2 ( 758525 226460 ) ( * 232275 )
NEW met1 ( 758785 226290 ) ( 2231370 * ) ( * 226350 )
via_260_260_hv ( * 226440 ) ( 2231430 * )
NEW met2 ( 2231310 226580 ) ( * 232415 )
NEW met2 ( 2231310 226260 ) ( 2231430 * )
NEW met2 ( 2231310 216430 ) ( * 226120 )
NEW met1 ( 2231260 216350 ) ( 2231380 * )
NEW met1 ( 2231260 215520 ) ( 2231380 * )
NEW met1 ( 2231320 215935 ) via_260_850_vh
NEW met1 ( 2231325 215935 ) mcon_170_850
NEW met2 ( 758030 215850 ) ( 758980 * )
NEW li1 ( 758045 215965 ) ( 758965 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[5] ( sky130_fd_sc_hd__buf_8_35 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3369310 2276960 ) ( * 2280205 )
NEW met1 ( 3369310 2276820 ) ( 3369590 * )
NEW met1 ( 3369590 2231085 ) ( * 2276680 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3369590 2230945 ) ( 3369710 * )
NEW met1 ( 3369650 2230855 ) via_260_260_vh ( * 2230795 )
( 3384835 * ) ( * 2230790 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2230880 ) ( 3385190 * )
NEW met2 ( 3384480 2230700 ) ( 3385190 * )
NEW met2 ( 3366060 2230795 ) ( 3369450 * )
NEW met1 ( 3369590 2230765 ) ( 3369710 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[5] ( sky130_fd_sc_hd__buf_8_35 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3369450 1180320 ) ( * 1183780 )
NEW met1 ( 3369450 1183920 ) ( 3369730 * )
NEW met1 ( 3369730 1184060 ) ( * 2226760 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3369610 2226900 ) ( 3369730 * )
NEW met1 ( 3369670 2226990 ) via_260_260_vh
NEW met1 ( 3369610 2227080 ) ( 3369730 * )
NEW met2 ( 3369870 2226930 ) ( 3384630 * )
NEW met1 ( 3384770 2227650 ) ( 3384890 * )
NEW met1 ( 3384770 2226580 ) ( 3384890 * )
NEW met1 ( 3384830 2227115 ) via_260_1090_vh
NEW met1 ( 3384835 2227115 ) mcon_170_1090
NEW met2 ( 3366060 2226930 ) ( 3369470 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[0] ( sky130_fd_sc_hd__buf_8_13 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3364410 1189320 ) ( * 2197480 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3364290 2197620 ) ( 3364410 * )
NEW met1 ( 3364350 2197710 ) via_260_260_vh
NEW met1 ( 3364290 2197800 ) ( 3364410 * )
NEW met2 ( 3364550 2197650 ) ( 3381775 * ) ( * 2197660 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2197750 ) ( 3382130 * )
NEW met2 ( 3381420 2197570 ) ( 3382130 * )
NEW met2 ( 3363820 2197650 ) ( 3364150 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[0] ( sky130_fd_sc_hd__buf_8_13 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3364270 2202155 ) ( * 2271205 )
NEW met1 ( 3364270 2202015 ) ( 3364390 * )
NEW met1 ( 3364330 2201925 ) via_260_260_vh ( * 2201865 )
( 3381570 * )
NEW met1 ( 3381710 2202380 ) ( 3381830 * )
NEW met1 ( 3381710 2201310 ) ( 3381830 * )
NEW met1 ( 3381770 2201845 ) via_260_1090_vh
NEW met1 ( 3381775 2201845 ) mcon_170_1090
NEW met2 ( 3363820 2201865 ) ( 3364130 * )
NEW met1 ( 3364270 2201835 ) ( 3364390 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[6] ( sky130_fd_sc_hd__buf_8_24 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3370290 3638110 ) ( * 3640535 )
NEW met1 ( 3370290 3637970 ) ( 3370570 * )
NEW met1 ( 3370570 3607185 ) ( * 3637830 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3370570 3607045 ) ( 3370690 * )
NEW met1 ( 3370630 3606955 ) via_260_260_vh ( * 3606895 )
( 3384835 * ) ( * 3606890 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 3606980 ) ( 3385190 * )
NEW met2 ( 3384480 3606800 ) ( 3385190 * )
NEW met2 ( 3370400 3606895 ) ( 3370430 * )
NEW met1 ( 3370570 3606865 ) ( 3370690 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_169/X ( sky130_fd_sc_hd__buf_8_169 X )
( sky130_fd_sc_hd__buf_8_147 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 3016235 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3016320 ) ( 206575 * )
NEW met2 ( 206715 3016220 ) ( 216425 * )
NEW met1 ( 216565 3016370 ) ( 216685 * )
NEW met1 ( 216625 3016280 ) via_260_260_vh
NEW met1 ( 216565 3016190 ) ( 216685 * )
NEW met1 ( 216565 1732820 ) ( * 3016050 )
NEW met1 ( 216445 1732680 ) ( 216565 * )
NEW met1 ( 216505 1732590 ) via_260_260_vh ( * 1732530 )
( 223670 * )
NEW met2 ( 206535 1732530 ) ( 216305 * )
NEW met1 ( 206275 1733045 ) ( 206395 * )
NEW met1 ( 206275 1731975 ) ( 206395 * )
NEW met1 ( 206335 1732510 ) via_260_1090_vh
NEW met1 ( 206330 1732510 ) mcon_170_1090
NEW met1 ( 216445 1732500 ) ( 216565 * )
NEW met2 ( 216825 3016220 ) ( 221530 * )
NEW met2 ( 205865 3016140 ) ( 206575 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_179/X ( sky130_fd_sc_hd__buf_8_179 X )
( sky130_fd_sc_hd__buf_8_136 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 2986335 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 2986420 ) ( 206575 * )
NEW met2 ( 206715 2986320 ) ( 222025 * )
NEW met1 ( 222165 2986470 ) ( 222285 * )
NEW met1 ( 222225 2986380 ) via_260_260_vh
NEW met1 ( 222165 2986290 ) ( 222285 * )
NEW met1 ( 222165 1702920 ) ( * 2986150 )
NEW met1 ( 222045 1702780 ) ( 222165 * )
NEW met1 ( 222105 1702690 ) via_260_260_vh ( * 1702630 )
( 223670 * )
NEW met2 ( 206535 1702630 ) ( 221905 * )
NEW met1 ( 206275 1703145 ) ( 206395 * )
NEW met1 ( 206275 1702075 ) ( 206395 * )
NEW met1 ( 206335 1702610 ) via_260_1090_vh
NEW met1 ( 206330 1702610 ) mcon_170_1090
NEW met1 ( 222045 1702600 ) ( 222165 * )
NEW met2 ( 222425 2986320 ) ( 222650 * )
NEW met2 ( 205865 2986240 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_unbuf[1] ( sky130_fd_sc_hd__buf_8_125 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3376870 212810 ) ( * 1160380 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2536450 212670 ) ( 3376870 * )
NEW met1 ( 2536450 212130 ) ( * 212530 )
NEW met1 ( 2416970 211990 ) ( 2536450 * )
NEW met1 ( 2416970 212130 ) ( * 221530 )
NEW met1 ( 2270695 221670 ) ( 2416970 * )
NEW met1 ( 2270495 221610 ) via_260_260_hv ( * 221700 )
( 2270555 * )
NEW met2 ( 2270435 221840 ) ( * 232415 )
NEW met2 ( 2270435 221520 ) ( 2270555 * )
NEW met2 ( 2270435 214240 ) ( * 221380 )
NEW met2 ( 2270435 214100 ) ( 2271070 * )
NEW met2 ( 2271070 213110 ) ( * 213960 )
NEW met2 ( 2270410 212970 ) ( 2271360 * )
NEW met2 ( 2270885 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2270410 212790 ) ( 2271360 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[13] ( sky130_fd_sc_hd__buf_8_114 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3369870 1144770 ) ( * 1148610 )
NEW met1 ( 3369590 1144630 ) ( 3369870 * )
NEW met1 ( 3369590 218130 ) ( * 1144490 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2529170 217990 ) ( 3369590 * )
NEW met1 ( 2529170 215490 ) ( * 217850 )
NEW met1 ( 2424250 215350 ) ( 2529170 * )
NEW met1 ( 2424250 215490 ) ( * 226850 )
NEW met1 ( 2234815 226990 ) ( 2424250 * )
NEW met1 ( 2234615 226930 ) via_260_260_hv ( * 227020 )
( 2234675 * )
NEW met2 ( 2234555 227160 ) ( * 232415 )
NEW met2 ( 2234555 226840 ) ( 2234675 * )
NEW met2 ( 2234555 213370 ) ( * 226700 )
NEW met1 ( 2234490 213290 ) ( 2234610 * )
NEW met1 ( 2234490 212460 ) ( 2234610 * )
NEW met1 ( 2234550 212875 ) via_260_850_vh
NEW met1 ( 2234555 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[19] ( sky130_fd_sc_hd__buf_8_103 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3362590 223450 ) ( * 1135620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2522170 223310 ) ( 3362590 * )
NEW met1 ( 2522170 219130 ) ( * 223170 )
NEW met1 ( 2431250 218990 ) ( 2522170 * )
NEW met1 ( 2431250 219130 ) ( * 232170 )
NEW met1 ( 2193805 232310 ) ( 2431250 * )
NEW met1 ( 2193605 232250 ) via_260_260_hv ( * 232340 )
( 2193665 * )
NEW met2 ( 2193665 232480 ) ( * 232415 )
NEW met2 ( 2193545 232160 ) ( 2193665 * )
NEW met2 ( 2193665 216170 ) ( * 232020 )
NEW met2 ( 2193170 216030 ) ( 2194120 * )
NEW met2 ( 2193645 215940 ) via_1090_260_hv
NEW li1 ( 2193185 215965 ) ( 2194105 * )
NEW li1 ( 2193645 215935 ) mcon_1090_170
NEW met2 ( 2193170 215850 ) ( 2194120 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[17] ( sky130_fd_sc_hd__buf_8_169 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 216425 3061815 ) ( * 3064710 )
NEW met1 ( 216425 3061675 ) ( 216705 * )
NEW met1 ( 216705 3020725 ) ( * 3061535 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 216585 3020585 ) ( 216705 * )
NEW met1 ( 216645 3020495 ) via_260_260_vh ( * 3020435 )
( 221530 * )
NEW met2 ( 206425 3020435 ) ( 216445 * )
NEW met1 ( 206165 3020950 ) ( 206285 * )
NEW met1 ( 206165 3019880 ) ( 206285 * )
NEW met1 ( 206225 3020415 ) via_260_1090_vh
NEW met1 ( 206220 3020415 ) mcon_170_1090
NEW met1 ( 216585 3020405 ) ( 216705 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_184/A ( sky130_fd_sc_hd__buf_8_184 A )
( sky130_fd_sc_hd__buf_8_158 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203035 4451915 ) mcon_170_1090
NEW met1 ( 202980 4452450 ) ( 203100 * )
NEW met2 ( 203240 4451730 ) ( 211245 * )
NEW met1 ( 211385 4451880 ) ( 211505 * )
NEW met1 ( 211445 4451790 ) via_260_260_vh
NEW met1 ( 211385 4451700 ) ( 211505 * )
NEW met1 ( 211385 3049655 ) ( * 4451560 )
NEW met1 ( 211265 3049515 ) ( 211385 * )
NEW met1 ( 211325 3049425 ) via_260_260_vh ( * 3049365 )
( 221530 * )
NEW met2 ( 203655 3049365 ) ( 211125 * )
NEW met2 ( 203160 3049360 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3049450 ) ( 203515 * )
NEW met2 ( 202805 3049270 ) ( 203515 * )
NEW met1 ( 211265 3049335 ) ( 211385 * )
NEW met2 ( 211645 4451730 ) ( 216065 * )
NEW met1 ( 202980 4451380 ) ( 203100 * )
NEW met1 ( 203040 4451915 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[0] ( sky130_fd_sc_hd__buf_8_12 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3363710 2266920 ) ( * 2270205 )
NEW met1 ( 3363710 2266780 ) ( 3363990 * )
NEW met1 ( 3363990 2201185 ) ( * 2266640 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3363990 2201045 ) ( 3364110 * )
NEW met1 ( 3364050 2200955 ) via_260_260_vh ( * 2200895 )
( 3384835 * ) ( * 2200890 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2200980 ) ( 3385190 * )
NEW met2 ( 3384480 2200800 ) ( 3385190 * )
NEW met2 ( 3363820 2200895 ) ( 3363850 * )
NEW met1 ( 3363990 2200865 ) ( 3364110 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[0] ( sky130_fd_sc_hd__buf_8_12 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3363850 1190320 ) ( * 1194030 )
NEW met1 ( 3363850 1194170 ) ( 3364130 * )
NEW met1 ( 3364130 1194310 ) ( * 2196860 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3364010 2197000 ) ( 3364130 * )
NEW met1 ( 3364070 2197090 ) via_260_260_vh
NEW met1 ( 3364010 2197180 ) ( 3364130 * )
NEW met2 ( 3364270 2197030 ) ( 3384630 * )
NEW met1 ( 3384770 2197750 ) ( 3384890 * )
NEW met1 ( 3384770 2196680 ) ( 3384890 * )
NEW met1 ( 3384830 2197215 ) via_260_1090_vh
NEW met1 ( 3384835 2197215 ) mcon_170_1090
NEW met2 ( 3363820 2197030 ) ( 3363870 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[26] ( sky130_fd_sc_hd__buf_8_89 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3355310 1118560 ) ( * 1122660 )
NEW met1 ( 3355030 1118420 ) ( 3355310 * )
NEW met1 ( 3355030 229050 ) ( * 1118280 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2514610 228910 ) ( 3355030 * )
NEW met1 ( 2514610 222770 ) ( * 228770 )
NEW met1 ( 2438810 222630 ) ( 2514610 * )
NEW met1 ( 2438810 222770 ) ( * 237770 )
NEW met1 ( 2157075 237910 ) ( 2438810 * )
NEW met1 ( 2156875 237850 ) via_260_260_hv ( * 237940 )
( 2156935 * )
NEW met2 ( 2156815 238080 ) ( * 238015 )
NEW met2 ( 2156815 237760 ) ( 2156935 * )
NEW met2 ( 2156815 213370 ) ( * 237620 )
NEW met1 ( 2156750 213290 ) ( 2156870 * )
NEW met1 ( 2156750 212460 ) ( 2156870 * )
NEW met1 ( 2156810 212875 ) via_260_850_vh
NEW met1 ( 2156815 212875 ) mcon_170_850 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_78/X ( sky130_fd_sc_hd__buf_8_78 X )
( sky130_fd_sc_hd__buf_8_138 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 688545 215935 ) mcon_170_850
NEW met1 ( 688480 216350 ) ( 688600 * )
NEW met2 ( 688530 216430 ) ( * 235220 )
NEW met2 ( 688530 235360 ) ( 688650 * )
NEW met2 ( 688590 235450 ) via_260_260_hv
NEW met2 ( 688530 235540 ) ( 688650 * )
NEW met2 ( 688530 235680 ) ( * 235745 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 223425 235390 ) ( 688390 * )
NEW met1 ( 223425 235530 ) ( * 1691645 )
NEW met1 ( 223425 1691785 ) ( 223545 * )
NEW met1 ( 223485 1691875 ) via_260_260_vh
NEW met1 ( 223425 1691965 ) ( 223545 * )
NEW met2 ( 223685 1691815 ) ( 223675 * )
NEW met2 ( 203475 1691815 ) ( 223285 * )
NEW met1 ( 203215 1692535 ) ( 203335 * )
NEW met1 ( 203215 1691465 ) ( 203335 * )
NEW met1 ( 203275 1692000 ) via_260_1090_vh
NEW met1 ( 203270 1692000 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 688480 215520 ) ( 688600 * )
NEW met1 ( 688540 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_92/X ( sky130_fd_sc_hd__buf_8_92 X )
( sky130_fd_sc_hd__buf_8_78 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2165545 215935 ) mcon_170_850
NEW met1 ( 2165480 216350 ) ( 2165600 * )
NEW met2 ( 2165530 216430 ) ( * 235360 )
NEW met2 ( 2165530 235500 ) ( 2165650 * )
NEW met2 ( 2165590 235590 ) via_260_260_hv
NEW met2 ( 2165530 235680 ) ( 2165650 * )
NEW met2 ( 2165530 235820 ) ( * 235745 )
NEW met1 ( 780605 235530 ) ( 2165390 * )
NEW met1 ( 780605 233710 ) ( * 235390 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 703755 233570 ) ( 780605 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 703755 233710 ) ( * 235390 )
NEW met1 ( 693005 235530 ) ( 703755 * )
NEW met1 ( 692805 235470 ) via_260_260_hv ( * 235560 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 692865 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 692745 235700 ) ( * 235625 )
NEW met2 ( 692745 235380 ) ( 692865 * )
NEW met2 ( 692745 216170 ) ( * 235240 )
NEW met2 ( 692250 216030 ) ( 693200 * )
NEW met2 ( 692725 215940 ) via_1090_260_hv
NEW li1 ( 692265 215965 ) ( 693185 * )
NEW li1 ( 692725 215935 ) mcon_1090_170
NEW met2 ( 692250 215850 ) ( 693200 * )
NEW met1 ( 2165480 215520 ) ( 2165600 * )
NEW met1 ( 2165540 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_67/X ( sky130_fd_sc_hd__buf_8_67 X )
( sky130_fd_sc_hd__buf_8_102 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 727655 212875 ) mcon_170_850
NEW met1 ( 727590 213290 ) ( 727710 * )
NEW met2 ( 727655 213370 ) ( * 230200 )
NEW met2 ( 727655 230340 ) ( 727775 * )
NEW met2 ( 727715 230430 ) via_260_260_hv
NEW met2 ( 727655 230520 ) ( 727775 * )
NEW met2 ( 727655 230660 ) ( * 232275 )
NEW met1 ( 727915 230490 ) ( 785085 * )
NEW met1 ( 785085 230630 ) ( * 230910 )
NEW met1 ( 785085 231050 ) ( 2200850 * ) ( * 231110 )
via_260_260_hv ( * 231200 ) ( 2200910 * )
NEW met2 ( 2200790 231340 ) ( * 232415 )
NEW met2 ( 2200790 231020 ) ( 2200910 * )
NEW met2 ( 2200790 213110 ) ( * 230880 )
NEW met2 ( 2200500 212970 ) ( 2201450 * )
NEW met2 ( 2200975 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2200500 212790 ) ( 2201450 * )
NEW met1 ( 727590 212460 ) ( 727710 * )
NEW met1 ( 727650 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_67/A ( sky130_fd_sc_hd__buf_8_67 A )
( sky130_fd_sc_hd__buf_8_149 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 723975 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 723500 212970 ) ( 724450 * )
NEW met2 ( 723790 213110 ) ( * 230180 )
NEW met2 ( 723790 230320 ) ( 723910 * )
NEW met2 ( 723850 230410 ) via_260_260_hv
NEW met2 ( 723790 230500 ) ( 723910 * )
NEW met2 ( 723790 230640 ) ( * 232275 )
NEW met1 ( 701085 230350 ) ( 723650 * )
NEW met1 ( 701085 230490 ) ( * 230770 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 217545 230910 ) ( 701085 * )
NEW met1 ( 217545 231050 ) ( * 1722165 )
NEW met1 ( 217545 1722305 ) ( 217665 * )
NEW met1 ( 217605 1722395 ) via_260_260_vh
NEW met1 ( 217545 1722485 ) ( 217665 * )
NEW met2 ( 217805 1722335 ) ( 223670 * )
NEW met2 ( 206825 1722335 ) ( 217405 * )
NEW met2 ( 206330 1722345 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1722435 ) ( 206685 * )
NEW met2 ( 205975 1722255 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 723500 212790 ) ( 724450 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_56/X ( sky130_fd_sc_hd__buf_8_56 X )
( sky130_fd_sc_hd__buf_8_114 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 757555 212875 ) mcon_170_850
NEW met1 ( 757490 213290 ) ( 757610 * )
NEW met2 ( 757555 213370 ) ( * 226560 )
NEW met2 ( 757555 226700 ) ( 757675 * )
NEW met2 ( 757615 226790 ) via_260_260_hv
NEW met2 ( 757555 226880 ) ( 757675 * )
NEW met2 ( 757555 227020 ) ( * 232275 )
NEW met1 ( 757815 226850 ) ( 2230750 * ) ( * 226910 )
via_260_260_hv ( * 227000 ) ( 2230810 * )
NEW met2 ( 2230690 227140 ) ( * 232415 )
NEW met2 ( 2230690 226820 ) ( 2230810 * )
NEW met2 ( 2230690 213110 ) ( * 226680 )
NEW met2 ( 2230400 212970 ) ( 2231350 * )
NEW met2 ( 2230875 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2230400 212790 ) ( 2231350 * )
NEW met1 ( 757490 212460 ) ( 757610 * )
NEW met1 ( 757550 212875 ) via_260_850_vh ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_0/X ( sky130_fd_sc_hd__buf_8_0 X )
( sky130_fd_sc_hd__buf_8_56 A )
+ ROUTED met1 ( 206280 1752250 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205925 1752335 ) ( 206635 * )
NEW met2 ( 206775 1752235 ) ( 211805 * )
NEW met1 ( 211945 1752385 ) ( 212065 * )
NEW met1 ( 212005 1752295 ) via_260_260_vh
NEW met1 ( 211945 1752205 ) ( 212065 * )
NEW met1 ( 211945 226850 ) ( * 1752065 )
NEW met1 ( 211945 226710 ) ( 753750 * ) ( * 226770 )
via_260_260_hv ( * 226860 ) ( 753810 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 753690 227000 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met2 ( 753690 226680 ) ( 753810 * )
NEW met2 ( 753690 213110 ) ( * 226540 )
NEW met2 ( 753400 212970 ) ( 754350 * )
NEW met2 ( 753875 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 753400 212790 ) ( 754350 * )
NEW met2 ( 212205 1752235 ) ( 223670 * )
NEW met2 ( 205925 1752155 ) ( 206635 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[5] ( sky130_fd_sc_hd__buf_8_34 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3370010 1179320 ) ( * 2227380 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 3369890 2227520 ) ( 3370010 * )
NEW met1 ( 3369950 2227610 ) via_260_260_vh
NEW met1 ( 3369890 2227700 ) ( 3370010 * )
NEW met2 ( 3370150 2227550 ) ( 3381775 * ) ( * 2227560 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 2227650 ) ( 3382130 * )
NEW met2 ( 3381420 2227470 ) ( 3382130 * )
NEW met2 ( 3366060 2227550 ) ( 3369750 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[5] ( sky130_fd_sc_hd__buf_8_34 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 3369870 2232055 ) ( * 2281205 )
NEW met1 ( 3369870 2231915 ) ( 3369990 * )
NEW met1 ( 3369930 2231825 ) via_260_260_vh ( * 2231765 )
( 3381570 * )
NEW met1 ( 3381710 2232280 ) ( 3381830 * )
NEW met1 ( 3381710 2231210 ) ( 3381830 * )
NEW met1 ( 3381770 2231745 ) via_260_1090_vh
NEW met1 ( 3381775 2231745 ) mcon_170_1090
NEW met2 ( 3366060 2231765 ) ( 3369730 * )
NEW met1 ( 3369870 2231735 ) ( 3369990 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_33/A ( sky130_fd_sc_hd__buf_8_33 A )
( sky130_fd_sc_hd__buf_8_23 X )
+ ROUTED met1 ( 3384835 3633115 ) mcon_170_1090
NEW met1 ( 3384770 3633650 ) ( 3384890 * )
NEW met2 ( 3376590 3632930 ) ( 3384630 * )
NEW met1 ( 3376330 3633080 ) ( 3376450 * )
NEW met1 ( 3376390 3632990 ) via_260_260_vh
NEW met1 ( 3376330 3632900 ) ( 3376450 * )
NEW met1 ( 3376450 2266965 ) ( * 3632760 )
NEW met1 ( 3376450 2266825 ) ( 3376570 * )
NEW met1 ( 3376510 2266735 ) via_260_260_vh ( * 2266675 )
( 3384835 * ) ( * 2266670 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2266760 ) ( 3385190 * )
NEW met2 ( 3384480 2266580 ) ( 3385190 * )
NEW met2 ( 3366060 2266675 ) ( 3376310 * )
NEW met1 ( 3376450 2266645 ) ( 3376570 * )
NEW met1 ( 3384770 3632580 ) ( 3384890 * )
NEW met1 ( 3384830 3633115 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[11] ( sky130_fd_sc_hd__buf_8_23 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3376310 1168320 ) ( * 1171970 )
NEW met1 ( 3376310 1172110 ) ( 3376590 * )
NEW met1 ( 3376590 1172250 ) ( * 2262640 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3376470 2262780 ) ( 3376590 * )
NEW met1 ( 3376530 2262870 ) via_260_260_vh
NEW met1 ( 3376470 2262960 ) ( 3376590 * )
NEW met2 ( 3376730 2262810 ) ( 3384630 * )
NEW met1 ( 3384770 2263530 ) ( 3384890 * )
NEW met1 ( 3384770 2262460 ) ( 3384890 * )
NEW met1 ( 3384830 2262995 ) via_260_1090_vh
NEW met1 ( 3384835 2262995 ) mcon_170_1090
NEW met2 ( 3376110 2262810 ) ( 3376330 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[14] ( sky130_fd_sc_hd__buf_8_45 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 852135 4974275 ) ( 855480 * )
NEW met1 ( 852135 4974415 ) ( 852135 * )
NEW met1 ( 839745 4974555 ) ( 852135 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 839545 4974615 ) via_260_260_hv ( * 4974705 )
( 839605 * )
NEW met2 ( 839485 4974845 ) ( * 4984390 )
NEW met1 ( 839420 4985300 ) ( 839540 * )
NEW met1 ( 839420 4984470 ) ( 839540 * )
NEW met1 ( 839480 4984885 ) via_260_850_vh
NEW met1 ( 839485 4984885 ) mcon_170_850
NEW met2 ( 839485 4974525 ) ( 839605 * )
NEW met2 ( 839485 4974470 ) ( * 4974385 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[22] ( sky130_fd_sc_hd__buf_8_179 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 222025 3051675 ) ( * 3054710 )
NEW met1 ( 222025 3051535 ) ( 222305 * )
NEW met1 ( 222305 2990825 ) ( * 3051395 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 222185 2990685 ) ( 222305 * )
NEW met1 ( 222245 2990595 ) via_260_260_vh ( * 2990535 )
( 222650 * )
NEW met2 ( 206425 2990535 ) ( 222045 * )
NEW met1 ( 206165 2991050 ) ( 206285 * )
NEW met1 ( 206165 2989980 ) ( 206285 * )
NEW met1 ( 206225 2990515 ) via_260_1090_vh
NEW met1 ( 206220 2990515 ) mcon_170_1090
NEW met1 ( 222185 2990505 ) ( 222305 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_158/A ( sky130_fd_sc_hd__buf_8_158 A )
( sky130_fd_sc_hd__buf_8_157 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3045685 ) mcon_170_1090
NEW met1 ( 203105 3046220 ) ( 203225 * )
NEW met2 ( 203365 3045500 ) ( 211105 * )
NEW met1 ( 211245 3045650 ) ( 211365 * )
NEW met1 ( 211305 3045560 ) via_260_260_vh
NEW met1 ( 211245 3045470 ) ( 211365 * )
NEW met1 ( 211245 1761750 ) ( * 3045330 )
NEW met1 ( 211125 1761610 ) ( 211245 * )
NEW met1 ( 211185 1761520 ) via_260_260_vh ( * 1761460 )
( 223670 * )
NEW met2 ( 203765 1761460 ) ( 210985 * )
NEW met2 ( 203270 1761455 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1761545 ) ( 203625 * )
NEW met2 ( 202915 1761365 ) ( 203625 * )
NEW met1 ( 211125 1761430 ) ( 211245 * )
NEW met2 ( 211505 3045500 ) ( 221530 * )
NEW met1 ( 203105 3045150 ) ( 203225 * )
NEW met1 ( 203165 3045685 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_168/A ( sky130_fd_sc_hd__buf_8_168 A )
( sky130_fd_sc_hd__buf_8_146 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3015785 ) mcon_170_1090
NEW met1 ( 203105 3016320 ) ( 203225 * )
NEW met2 ( 203365 3015600 ) ( 216705 * )
NEW met1 ( 216845 3015750 ) ( 216965 * )
NEW met1 ( 216905 3015660 ) via_260_260_vh
NEW met1 ( 216845 3015570 ) ( 216965 * )
NEW met1 ( 216845 1731850 ) ( * 3015430 )
NEW met1 ( 216725 1731710 ) ( 216845 * )
NEW met1 ( 216785 1731620 ) via_260_260_vh ( * 1731560 )
( 223670 * )
NEW met2 ( 203765 1731560 ) ( 216585 * )
NEW met2 ( 203270 1731555 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1731645 ) ( 203625 * )
NEW met2 ( 202915 1731465 ) ( 203625 * )
NEW met1 ( 216725 1731530 ) ( 216845 * )
NEW met2 ( 217105 3015600 ) ( 221530 * )
NEW met1 ( 203105 3015250 ) ( 203225 * )
NEW met1 ( 203165 3015785 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_176/A ( sky130_fd_sc_hd__buf_8_176 A )
( sky130_fd_sc_hd__buf_8_135 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 2991865 ) mcon_170_1090
NEW met1 ( 203105 2992400 ) ( 203225 * )
NEW met2 ( 203365 2991680 ) ( 221185 * )
NEW met1 ( 221325 2991830 ) ( 221445 * )
NEW met1 ( 221385 2991740 ) via_260_260_vh
NEW met1 ( 221325 2991650 ) ( 221445 * )
NEW met1 ( 221325 1707930 ) ( * 2991510 )
NEW met1 ( 221205 1707790 ) ( 221325 * )
NEW met1 ( 221265 1707700 ) via_260_260_vh ( * 1707640 )
( 223670 * )
NEW met2 ( 203765 1707640 ) ( 221065 * )
NEW met2 ( 203270 1707635 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1707725 ) ( 203625 * )
NEW met2 ( 202915 1707545 ) ( 203625 * )
NEW met1 ( 221205 1707610 ) ( 221325 * )
NEW met2 ( 221585 2991680 ) ( 221605 * )
NEW met1 ( 203105 2991330 ) ( 203225 * )
NEW met1 ( 203165 2991865 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[30] ( sky130_fd_sc_hd__buf_8_124 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3375470 1154640 ) ( * 1158380 )
NEW met1 ( 3375190 1154500 ) ( 3375470 * )
NEW met1 ( 3375190 213930 ) ( * 1154360 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2534770 213790 ) ( 3375190 * )
NEW met1 ( 2534770 212690 ) ( * 213650 )
NEW met1 ( 2418650 212550 ) ( 2534770 * )
NEW met1 ( 2418650 212690 ) ( * 222650 )
NEW met1 ( 2264715 222790 ) ( 2418650 * )
NEW met1 ( 2264515 222730 ) via_260_260_hv ( * 222820 )
( 2264575 * )
NEW met2 ( 2264455 222960 ) ( * 232415 )
NEW met2 ( 2264455 222640 ) ( 2264575 * )
NEW met2 ( 2264455 213370 ) ( * 222500 )
NEW met1 ( 2264390 213290 ) ( 2264510 * )
NEW met1 ( 2264390 212460 ) ( 2264510 * )
NEW met1 ( 2264450 212875 ) via_260_850_vh
NEW met1 ( 2264455 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[13] ( sky130_fd_sc_hd__buf_8_113 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3369310 218410 ) ( * 1147600 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2528890 218270 ) ( 3369310 * )
NEW met1 ( 2528890 215770 ) ( * 218130 )
NEW met1 ( 2424530 215630 ) ( 2528890 * )
NEW met1 ( 2424530 215770 ) ( * 227130 )
NEW met1 ( 2229805 227270 ) ( 2424530 * )
NEW met1 ( 2229605 227210 ) via_260_260_hv ( * 227300 )
( 2229665 * )
NEW met2 ( 2229545 227440 ) ( * 232415 )
NEW met2 ( 2229545 227120 ) ( 2229665 * )
NEW met2 ( 2229545 216170 ) ( * 226980 )
NEW met2 ( 2229050 216030 ) ( 2230000 * )
NEW met2 ( 2229525 215940 ) via_1090_260_hv
NEW li1 ( 2229065 215965 ) ( 2229985 * )
NEW li1 ( 2229525 215935 ) mcon_1090_170
NEW met2 ( 2229050 215850 ) ( 2230000 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[18] ( sky130_fd_sc_hd__buf_8_102 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3364270 1135130 ) ( * 1138610 )
NEW met1 ( 3363990 1134990 ) ( 3364270 * )
NEW met1 ( 3363990 222330 ) ( * 1134850 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2523570 222190 ) ( 3363990 * )
NEW met1 ( 2523570 218290 ) ( * 222050 )
NEW met1 ( 2429850 218150 ) ( 2523570 * )
NEW met1 ( 2429850 218290 ) ( * 231050 )
NEW met1 ( 2204915 231190 ) ( 2429850 * )
NEW met1 ( 2204715 231130 ) via_260_260_hv ( * 231220 )
( 2204775 * )
NEW met2 ( 2204655 231360 ) ( * 232415 )
NEW met2 ( 2204655 231040 ) ( 2204775 * )
NEW met2 ( 2204655 213370 ) ( * 230900 )
NEW met1 ( 2204590 213290 ) ( 2204710 * )
NEW met1 ( 2204590 212460 ) ( 2204710 * )
NEW met1 ( 2204650 212875 ) via_260_850_vh
NEW met1 ( 2204655 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[17] ( sky130_fd_sc_hd__buf_8_168 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 216985 3019755 ) ( * 3063710 )
NEW met1 ( 216865 3019615 ) ( 216985 * )
NEW met1 ( 216925 3019525 ) via_260_260_vh ( * 3019465 )
( 221530 * )
NEW met2 ( 203655 3019465 ) ( 216725 * )
NEW met2 ( 203160 3019460 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3019550 ) ( 203515 * )
NEW met2 ( 202805 3019370 ) ( 203515 * )
NEW met1 ( 216865 3019435 ) ( 216985 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[20] ( sky130_fd_sc_hd__buf_8_99 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3361470 224290 ) ( * 1133620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2521050 224150 ) ( 3361470 * )
NEW met1 ( 2521050 219690 ) ( * 224010 )
NEW met1 ( 2432370 219550 ) ( 2521050 * )
NEW met1 ( 2432370 219690 ) ( * 233010 )
NEW met1 ( 2187945 233150 ) ( 2432370 * )
NEW met1 ( 2187745 233090 ) via_260_260_hv ( * 233180 )
( 2187805 * )
NEW met2 ( 2187685 233320 ) ( * 233295 )
NEW met2 ( 2187685 233000 ) ( 2187805 * )
NEW met2 ( 2187685 216170 ) ( * 232860 )
NEW met2 ( 2187190 216030 ) ( 2188140 * )
NEW met2 ( 2187665 215940 ) via_1090_260_hv
NEW li1 ( 2187205 215965 ) ( 2188125 * )
NEW li1 ( 2187665 215935 ) mcon_1090_170
NEW met2 ( 2187190 215850 ) ( 2188140 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[25] ( sky130_fd_sc_hd__buf_8_88 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3355870 228490 ) ( * 1123630 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2515450 228350 ) ( 3355870 * )
NEW met1 ( 2515450 222490 ) ( * 228210 )
NEW met1 ( 2437970 222350 ) ( 2515450 * )
NEW met1 ( 2437970 222490 ) ( * 237210 )
NEW met1 ( 2158045 237350 ) ( 2437970 * )
NEW met1 ( 2157845 237290 ) via_260_260_hv ( * 237380 )
( 2157905 * )
NEW met2 ( 2157785 237520 ) ( * 237505 )
NEW met2 ( 2157785 237200 ) ( 2157905 * )
NEW met2 ( 2157785 216170 ) ( * 237060 )
NEW met2 ( 2157290 216030 ) ( 2158240 * )
NEW met2 ( 2157765 215940 ) via_1090_260_hv
NEW li1 ( 2157305 215965 ) ( 2158225 * )
NEW li1 ( 2157765 215935 ) mcon_1090_170
NEW met2 ( 2157290 215850 ) ( 2158240 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_77/X ( sky130_fd_sc_hd__buf_8_77 X )
( sky130_fd_sc_hd__buf_8_137 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 694525 215935 ) mcon_170_850
NEW met1 ( 694460 216350 ) ( 694580 * )
NEW met2 ( 694510 216430 ) ( * 234380 )
NEW met2 ( 694510 234520 ) ( 694630 * )
NEW met2 ( 694570 234610 ) via_260_260_hv
NEW met2 ( 694510 234700 ) ( 694630 * )
NEW met2 ( 694510 234840 ) ( * 234800 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 222305 234550 ) ( 694370 * )
NEW met1 ( 222305 234690 ) ( * 1697625 )
NEW met1 ( 222305 1697765 ) ( 222425 * )
NEW met1 ( 222365 1697855 ) via_260_260_vh
NEW met1 ( 222305 1697945 ) ( 222425 * )
NEW met2 ( 222565 1697795 ) ( 223670 * )
NEW met2 ( 203475 1697795 ) ( 222165 * )
NEW met1 ( 203215 1698515 ) ( 203335 * )
NEW met1 ( 203215 1697445 ) ( 203335 * )
NEW met1 ( 203275 1697980 ) via_260_1090_vh
NEW met1 ( 203270 1697980 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 694460 215520 ) ( 694580 * )
NEW met1 ( 694520 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_94/X ( sky130_fd_sc_hd__buf_8_94 X )
( sky130_fd_sc_hd__buf_8_77 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2171525 215935 ) mcon_170_850
NEW met1 ( 2171460 216350 ) ( 2171580 * )
NEW met2 ( 2171510 216430 ) ( * 234520 )
NEW met2 ( 2171510 234660 ) ( 2171630 * )
NEW met2 ( 2171570 234750 ) via_260_260_hv
NEW met2 ( 2171510 234840 ) ( 2171630 * )
NEW met2 ( 2171510 234980 ) ( * 234920 )
NEW met1 ( 781445 234690 ) ( 2171370 * )
NEW met1 ( 781445 233150 ) ( * 234550 )
NEW met1 ( 703185 233010 ) ( 781445 * )
NEW met1 ( 703185 233150 ) ( * 234550 )
NEW met1 ( 698985 234690 ) ( 703185 * )
NEW met1 ( 698785 234630 ) via_260_260_hv ( * 234720 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 698845 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 698725 234860 ) ( * 234835 )
NEW met2 ( 698725 234540 ) ( 698845 * )
NEW met2 ( 698725 216170 ) ( * 234400 )
NEW met2 ( 698230 216030 ) ( 699180 * )
NEW met2 ( 698705 215940 ) via_1090_260_hv
NEW li1 ( 698245 215965 ) ( 699165 * )
NEW li1 ( 698705 215935 ) mcon_1090_170
NEW met2 ( 698230 215850 ) ( 699180 * )
NEW met1 ( 2171460 215520 ) ( 2171580 * )
NEW met1 ( 2171520 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_66/X ( sky130_fd_sc_hd__buf_8_66 X )
( sky130_fd_sc_hd__buf_8_146 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 724425 215935 ) mcon_170_850
NEW met1 ( 724360 216350 ) ( 724480 * )
NEW met2 ( 724410 216430 ) ( * 229900 )
NEW met2 ( 724410 230040 ) ( 724530 * )
NEW met2 ( 724470 230130 ) via_260_260_hv
NEW met2 ( 724410 230220 ) ( 724530 * )
NEW met2 ( 724410 230360 ) ( * 232275 )
NEW met1 ( 700770 230070 ) ( 724270 * )
NEW met1 ( 700770 230210 ) ( 700770 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 216705 230350 ) ( 700770 * )
NEW met1 ( 216705 230490 ) ( * 1727525 )
NEW met1 ( 216705 1727665 ) ( 216825 * )
NEW met1 ( 216765 1727755 ) via_260_260_vh
NEW met1 ( 216705 1727845 ) ( 216825 * )
NEW met2 ( 216965 1727695 ) ( 223670 * )
NEW met2 ( 203475 1727695 ) ( 216565 * )
NEW met1 ( 203215 1728415 ) ( 203335 * )
NEW met1 ( 203215 1727345 ) ( 203335 * )
NEW met1 ( 203275 1727880 ) via_260_1090_vh
NEW met1 ( 203270 1727880 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 724360 215520 ) ( 724480 * )
NEW met1 ( 724420 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_66/A ( sky130_fd_sc_hd__buf_8_66 A )
( sky130_fd_sc_hd__buf_8_105 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 728605 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 728130 216030 ) ( 729080 * )
NEW met2 ( 728625 216170 ) ( * 229920 )
NEW met2 ( 728625 230060 ) ( 728745 * )
NEW met2 ( 728685 230150 ) via_260_260_hv
NEW met2 ( 728625 230240 ) ( 728745 * )
NEW met2 ( 728625 230380 ) ( * 232275 )
NEW met1 ( 728885 230210 ) ( 785430 * )
NEW met1 ( 785430 230350 ) ( 785430 * )
NEW met1 ( 785430 230490 ) ( 2201470 * ) ( * 230550 )
via_260_260_hv ( * 230640 ) ( 2201530 * )
NEW met2 ( 2201410 230780 ) ( * 232415 )
NEW met2 ( 2201410 230460 ) ( 2201530 * )
NEW met2 ( 2201410 216430 ) ( * 230320 )
NEW met1 ( 2201360 216350 ) ( 2201480 * )
NEW met1 ( 2201360 215520 ) ( 2201480 * )
NEW met1 ( 2201420 215935 ) via_260_850_vh
NEW met1 ( 2201425 215935 ) mcon_170_850
NEW met2 ( 728130 215850 ) ( 729080 * )
NEW li1 ( 728145 215965 ) ( 729065 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[27] ( sky130_fd_sc_hd__buf_8_55 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 655685 225310 ) ( 760350 * ) ( * 225370 )
via_260_260_hv ( * 225460 ) ( 760410 * )
NEW met2 ( 760290 225600 ) ( * 232275 )
NEW met2 ( 760290 225280 ) ( 760410 * )
NEW met2 ( 760290 216430 ) ( * 225140 )
NEW met1 ( 760240 216350 ) ( 760360 * )
NEW met1 ( 760240 215520 ) ( 760360 * )
NEW met1 ( 760300 215935 ) via_260_850_vh
NEW met1 ( 760305 215935 ) mcon_170_850 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_55/A ( sky130_fd_sc_hd__buf_8_55 A )
( sky130_fd_sc_hd__buf_8_117 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 764485 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 764010 216030 ) ( 764960 * )
NEW met2 ( 764505 216170 ) ( * 225160 )
NEW met2 ( 764505 225300 ) ( 764625 * )
NEW met2 ( 764565 225390 ) via_260_260_hv
NEW met2 ( 764505 225480 ) ( 764625 * )
NEW met2 ( 764505 225620 ) ( * 232275 )
NEW met1 ( 764765 225450 ) ( 2237350 * ) ( * 225510 )
via_260_260_hv ( * 225600 ) ( 2237410 * )
NEW met2 ( 2237290 225740 ) ( * 232415 )
NEW met2 ( 2237290 225420 ) ( 2237410 * )
NEW met2 ( 2237290 216430 ) ( * 225280 )
NEW met1 ( 2237240 216350 ) ( 2237360 * )
NEW met1 ( 2237240 215520 ) ( 2237360 * )
NEW met1 ( 2237300 215935 ) via_260_850_vh
NEW met1 ( 2237305 215935 ) mcon_170_850
NEW met2 ( 764010 215850 ) ( 764960 * )
NEW li1 ( 764025 215965 ) ( 764945 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[11] ( sky130_fd_sc_hd__buf_8_22 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3376870 1167320 ) ( * 2263260 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3376750 2263400 ) ( 3376870 * )
NEW met1 ( 3376810 2263490 ) via_260_260_vh
NEW met1 ( 3376750 2263580 ) ( 3376870 * )
NEW met2 ( 3377010 2263430 ) ( 3381775 * ) ( * 2263440 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 2263530 ) ( 3382130 * )
NEW met2 ( 3381420 2263350 ) ( 3382130 * )
NEW met2 ( 3366060 2263430 ) ( 3376610 * ) ;
- sky130_fd_sc_hd__buf_8_32/X ( sky130_fd_sc_hd__buf_8_32 X )
( sky130_fd_sc_hd__buf_8_22 A )
+ ROUTED met1 ( 3381775 3633565 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3376870 3633550 ) ( 3381280 * )
NEW met1 ( 3376610 3633700 ) ( 3376730 * )
NEW met1 ( 3376670 3633610 ) via_260_260_vh
NEW met2 ( 3376335 3633550 ) ( 3376470 * )
NEW met1 ( 3376610 3633520 ) ( 3376730 * )
NEW met1 ( 3376730 2267935 ) ( * 3633380 )
NEW met1 ( 3376730 2267795 ) ( 3376850 * )
NEW met1 ( 3376790 2267705 ) via_260_260_vh ( * 2267645 )
( 3381570 * )
NEW met1 ( 3381710 2268160 ) ( 3381830 * )
NEW met1 ( 3381710 2267090 ) ( 3381830 * )
NEW met1 ( 3381770 2267625 ) via_260_1090_vh
NEW met1 ( 3381775 2267625 ) mcon_170_1090
NEW met2 ( 3366060 2267645 ) ( 3376590 * )
NEW met1 ( 3376730 2267615 ) ( 3376850 * )
NEW met2 ( 3381420 3633650 ) ( 3382130 * )
NEW met2 ( 3381420 3633470 ) ( 3382130 * ) ;
- sky130_fd_sc_hd__buf_8_33/X ( sky130_fd_sc_hd__buf_8_33 X )
( sky130_fd_sc_hd__buf_8_194 A )
+ ROUTED met1 ( 3384835 3636795 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3384480 3636880 ) ( 3385190 * )
NEW met2 ( 3384480 3636700 ) ( 3385190 * )
NEW met2 ( 3376570 3636795 ) ( 3384340 * )
NEW met1 ( 3376310 3636945 ) ( 3376430 * )
NEW met1 ( 3376310 3637085 ) ( * 4976445 )
NEW met1 ( 3315445 4976585 ) ( 3376310 * )
NEW met1 ( 3315245 4976525 ) via_260_260_hv ( * 4976615 )
( 3315305 * )
NEW met2 ( 3315305 4976755 ) ( * 4985865 )
NEW met2 ( 3314645 4986005 ) ( 3315595 * )
NEW met2 ( 3315120 4986095 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 3314645 4986185 ) ( 3315595 * )
NEW met2 ( 3315185 4976435 ) ( 3315305 * )
NEW met2 ( 3315305 4972915 ) ( * 4976295 )
NEW met2 ( 3376370 3636855 ) via_260_260_vh
NEW met2 ( 3376220 3636795 ) ( 3376170 * )
NEW met1 ( 3376310 3636765 ) ( 3376430 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[13] ( sky130_fd_sc_hd__buf_8_44 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 854285 4975395 ) ( 857485 * )
NEW met1 ( 854285 4975535 ) ( 854285 * )
NEW met1 ( 845725 4975675 ) ( 854285 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 845525 4975735 ) via_260_260_hv ( * 4975825 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 845585 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 845465 4975965 ) ( * 4984390 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met1 ( 845400 4985300 ) ( 845520 * )
NEW met1 ( 845400 4984470 ) ( 845520 * )
NEW met1 ( 845460 4984885 ) via_260_850_vh
NEW met1 ( 845465 4984885 ) mcon_170_850
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 845465 4975645 ) ( 845585 * )
NEW met2 ( 845465 4975345 ) ( * 4975505 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_11/X ( sky130_fd_sc_hd__buf_8_11 X )
( sky130_fd_sc_hd__buf_8_180 A )
+ ROUTED met1 ( 2087665 4983450 ) mcon_170_850
NEW met1 ( 2087610 4983865 ) ( 2087730 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2087680 4976895 ) ( * 4982955 )
NEW met2 ( 2087560 4976755 ) ( 2087680 * )
NEW met2 ( 2087620 4976665 ) via_260_260_hv ( * 4976725 )
( 3310410 * ) ( * 4976785 ) via_260_260_hv ( * 4976875 )
( 3310470 * )
NEW met2 ( 3310470 4977015 ) ( * 4982805 )
NEW met2 ( 3310015 4982945 ) ( 3310965 * )
NEW met2 ( 3310490 4983035 ) via_1090_260_hv mcon_1090_170
( * 4983010 ) ( 3310950 * )
NEW met2 ( 3310015 4983125 ) ( 3310965 * )
NEW met2 ( 3310350 4976695 ) ( 3310470 * )
NEW met2 ( 3310470 4972915 ) ( * 4976555 )
NEW met2 ( 2087560 4976575 ) ( 2087680 * )
NEW met2 ( 2087680 4976500 ) ( * 4976435 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met1 ( 2087610 4983035 ) ( 2087730 * )
NEW met1 ( 2087670 4983450 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[11] ( sky130_fd_sc_hd__buf_8_11 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 2079605 4976865 ) ( 2083405 * ) ( * 4976925 )
via_260_260_hv ( * 4977015 ) ( 2083465 * )
NEW met2 ( 2083465 4977155 ) ( * 4983215 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met2 ( 2083010 4983355 ) ( 2083960 * )
NEW met2 ( 2083485 4983445 ) via_1090_260_hv mcon_1090_170
( * 4983420 ) ( 2083945 * )
NEW met2 ( 2083010 4983535 ) ( 2083960 * )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
NEW met2 ( 2083345 4976835 ) ( 2083465 * )
NEW met2 ( 2083465 4976135 ) ( * 4976695 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_159/X ( sky130_fd_sc_hd__buf_8_159 X )
( sky130_fd_sc_hd__buf_8_156 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 3046135 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3046220 ) ( 206575 * )
NEW met2 ( 206715 3046120 ) ( 210825 * )
NEW met1 ( 210965 3046270 ) ( 211085 * )
NEW met1 ( 211025 3046180 ) via_260_260_vh
NEW met1 ( 210965 3046090 ) ( 211085 * )
NEW met1 ( 210965 1762720 ) ( * 3045950 )
NEW met1 ( 210845 1762580 ) ( 210965 * )
NEW met1 ( 210905 1762490 ) via_260_260_vh ( * 1762430 )
( 223670 * )
NEW met2 ( 206535 1762430 ) ( 210705 * )
NEW met1 ( 206275 1762945 ) ( 206395 * )
NEW met1 ( 206275 1761875 ) ( 206395 * )
NEW met1 ( 206335 1762410 ) via_260_1090_vh
NEW met1 ( 206330 1762410 ) mcon_170_1090
NEW met1 ( 210845 1762400 ) ( 210965 * )
NEW met2 ( 211225 3046120 ) ( 221530 * )
NEW met2 ( 205865 3046040 ) ( 206575 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_166/A ( sky130_fd_sc_hd__buf_8_166 A )
( sky130_fd_sc_hd__buf_8_145 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3021765 ) mcon_170_1090
NEW met1 ( 203105 3022300 ) ( 203225 * )
NEW met2 ( 203365 3021580 ) ( 215585 * )
NEW met1 ( 215725 3021730 ) ( 215845 * )
NEW met1 ( 215785 3021640 ) via_260_260_vh
NEW met1 ( 215725 3021550 ) ( 215845 * )
NEW met1 ( 215725 1737830 ) ( * 3021410 )
NEW met1 ( 215605 1737690 ) ( 215725 * )
NEW met1 ( 215665 1737600 ) via_260_260_vh ( * 1737540 )
( 223670 * )
NEW met2 ( 203765 1737540 ) ( 215465 * )
NEW met2 ( 203270 1737535 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1737625 ) ( 203625 * )
NEW met2 ( 202915 1737445 ) ( 203625 * )
NEW met1 ( 215605 1737510 ) ( 215725 * )
NEW met2 ( 215985 3021580 ) ( 221530 * )
NEW met1 ( 203105 3021230 ) ( 203225 * )
NEW met1 ( 203165 3021765 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_177/X ( sky130_fd_sc_hd__buf_8_177 X )
( sky130_fd_sc_hd__buf_8_134 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 2992315 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 2992400 ) ( 206575 * )
NEW met2 ( 206715 2992300 ) ( 220905 * )
NEW met1 ( 221045 2992450 ) ( 221165 * )
NEW met1 ( 221105 2992360 ) via_260_260_vh
NEW met1 ( 221045 2992270 ) ( 221165 * )
NEW met1 ( 221045 1708900 ) ( * 2992130 )
NEW met1 ( 220925 1708760 ) ( 221045 * )
NEW met1 ( 220985 1708670 ) via_260_260_vh ( * 1708610 )
( 223670 * )
NEW met2 ( 206535 1708610 ) ( 220785 * )
NEW met1 ( 206275 1709125 ) ( 206395 * )
NEW met1 ( 206275 1708055 ) ( 206395 * )
NEW met1 ( 206335 1708590 ) via_260_1090_vh
NEW met1 ( 206330 1708590 ) mcon_170_1090
NEW met1 ( 220925 1708580 ) ( 221045 * )
NEW met2 ( 221305 2992300 ) ( 221605 * )
NEW met2 ( 205865 2992220 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[30] ( sky130_fd_sc_hd__buf_8_123 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3374910 214210 ) ( * 1157380 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2534490 214070 ) ( 3374910 * )
NEW met1 ( 2534490 212970 ) ( * 213930 )
NEW met1 ( 2418930 212830 ) ( 2534490 * )
NEW met1 ( 2418930 212970 ) ( * 222930 )
NEW met1 ( 2259705 223070 ) ( 2418930 * )
NEW met1 ( 2259505 223010 ) via_260_260_hv ( * 223100 )
( 2259565 * )
NEW met2 ( 2259445 223240 ) ( * 232415 )
NEW met2 ( 2259445 222920 ) ( 2259565 * )
NEW met2 ( 2259445 216170 ) ( * 222780 )
NEW met2 ( 2258950 216030 ) ( 2259900 * )
NEW met2 ( 2259425 215940 ) via_1090_260_hv
NEW li1 ( 2258965 215965 ) ( 2259885 * )
NEW li1 ( 2259425 215935 ) mcon_1090_170
NEW met2 ( 2258950 215850 ) ( 2259900 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[14] ( sky130_fd_sc_hd__buf_8_112 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3368750 1142640 ) ( * 1146600 )
NEW met1 ( 3368470 1142500 ) ( 3368750 * )
NEW met1 ( 3368470 218970 ) ( * 1142360 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2528050 218830 ) ( 3368470 * )
NEW met1 ( 2528050 216050 ) ( * 218690 )
NEW met1 ( 2425370 215910 ) ( 2528050 * )
NEW met1 ( 2425370 216050 ) ( * 227690 )
NEW met1 ( 2228835 227830 ) ( 2425370 * )
NEW met1 ( 2228635 227770 ) via_260_260_hv ( * 227860 )
( 2228695 * )
NEW met2 ( 2228575 228000 ) ( * 232415 )
NEW met2 ( 2228575 227680 ) ( 2228695 * )
NEW met2 ( 2228575 213370 ) ( * 227540 )
NEW met1 ( 2228510 213290 ) ( 2228630 * )
NEW met1 ( 2228510 212460 ) ( 2228630 * )
NEW met1 ( 2228570 212875 ) via_260_850_vh
NEW met1 ( 2228575 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[19] ( sky130_fd_sc_hd__buf_8_101 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3363150 1133180 ) ( * 1136610 )
NEW met1 ( 3362870 1133040 ) ( 3363150 * )
NEW met1 ( 3362870 223170 ) ( * 1132900 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2522450 223030 ) ( 3362870 * )
NEW met1 ( 2522450 218850 ) ( * 222890 )
NEW met1 ( 2430970 218710 ) ( 2522450 * )
NEW met1 ( 2430970 218850 ) ( * 231890 )
NEW met1 ( 2198935 232030 ) ( 2430970 * )
NEW met1 ( 2198735 231970 ) via_260_260_hv ( * 232060 )
( 2198795 * )
NEW met2 ( 2198675 232200 ) ( * 232415 )
NEW met2 ( 2198675 231880 ) ( 2198795 * )
NEW met2 ( 2198675 213370 ) ( * 231740 )
NEW met1 ( 2198610 213290 ) ( 2198730 * )
NEW met1 ( 2198610 212460 ) ( 2198730 * )
NEW met1 ( 2198670 212875 ) via_260_850_vh
NEW met1 ( 2198675 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[22] ( sky130_fd_sc_hd__buf_8_178 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 222585 2989855 ) ( * 3053710 )
NEW met1 ( 222465 2989715 ) ( 222585 * )
NEW met1 ( 222525 2989625 ) via_260_260_vh ( * 2989565 )
( 222650 * )
NEW met2 ( 203655 2989565 ) ( 222325 * )
NEW met2 ( 203160 2989560 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 2989650 ) ( 203515 * )
NEW met2 ( 202805 2989470 ) ( 203515 * )
NEW met1 ( 222465 2989535 ) ( 222585 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_186/X ( sky130_fd_sc_hd__buf_8_186 X )
( sky130_fd_sc_hd__buf_8_167 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206095 4428445 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205740 4428530 ) ( 206450 * )
NEW met2 ( 206590 4428430 ) ( 215445 * )
NEW met1 ( 215585 4428580 ) ( 215705 * )
NEW met1 ( 215645 4428490 ) via_260_260_vh
NEW met1 ( 215585 4428400 ) ( 215705 * )
NEW met1 ( 215585 3026705 ) ( * 4428260 )
NEW met1 ( 215465 3026565 ) ( 215585 * )
NEW met1 ( 215525 3026475 ) via_260_260_vh ( * 3026415 )
( 221530 * )
NEW met2 ( 206425 3026415 ) ( 215325 * )
NEW met1 ( 206165 3026930 ) ( 206285 * )
NEW met1 ( 206165 3025860 ) ( 206285 * )
NEW met1 ( 206225 3026395 ) via_260_1090_vh
NEW met1 ( 206220 3026395 ) mcon_170_1090
NEW met1 ( 215465 3026385 ) ( 215585 * )
NEW met2 ( 215845 4428430 ) ( 216065 * )
NEW met2 ( 205740 4428350 ) ( 206450 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_39/X ( sky130_fd_sc_hd__buf_8_39 X )
( sky130_fd_sc_hd__buf_8_189 A )
+ ROUTED met1 ( 836255 4981825 ) mcon_170_850
NEW met1 ( 836190 4982240 ) ( 836310 * )
NEW met2 ( 836240 4975145 ) ( * 4981330 )
NEW met2 ( 836240 4975005 ) ( 836360 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 213485 4974975 ) ( 836300 * ) ( * 4974915 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 213485 4444895 ) ( * 4974835 )
NEW met1 ( 213365 4444755 ) ( 213485 * )
NEW met1 ( 213425 4444665 ) via_260_260_vh ( * 4444605 )
( 216065 * )
NEW met2 ( 206300 4444605 ) ( 213225 * )
NEW met1 ( 206040 4445120 ) ( 206160 * )
NEW met1 ( 206040 4444050 ) ( 206160 * )
NEW met1 ( 206100 4444585 ) via_260_1090_vh
NEW met1 ( 206095 4444585 ) mcon_170_1090
NEW met1 ( 213365 4444575 ) ( 213485 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 836240 4974825 ) ( 836360 * )
NEW met2 ( 836240 4974470 ) ( * 4974685 )
NEW met1 ( 836190 4981410 ) ( 836310 * )
NEW met1 ( 836250 4981825 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[21] ( sky130_fd_sc_hd__buf_8_98 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3360350 225130 ) ( * 1131630 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2519930 224990 ) ( 3360350 * )
NEW met1 ( 2519930 220250 ) ( * 224850 )
NEW met1 ( 2433490 220110 ) ( 2519930 * )
NEW met1 ( 2433490 220250 ) ( * 233850 )
NEW met1 ( 2181845 233990 ) ( 2433490 * )
NEW met1 ( 2181645 233930 ) via_260_260_hv ( * 234020 )
( 2181705 * )
NEW met2 ( 2181705 234160 ) ( * 234130 )
NEW met2 ( 2181585 233840 ) ( 2181705 * )
NEW met2 ( 2181705 216170 ) ( * 233700 )
NEW met2 ( 2181210 216030 ) ( 2182160 * )
NEW met2 ( 2181685 215940 ) via_1090_260_hv
NEW li1 ( 2181225 215965 ) ( 2182145 * )
NEW li1 ( 2181685 215935 ) mcon_1090_170
NEW met2 ( 2181210 215850 ) ( 2182160 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_95/A ( sky130_fd_sc_hd__buf_8_95 A )
( sky130_fd_sc_hd__buf_8_76 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2171075 212875 ) mcon_1090_170
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2170600 212970 ) ( 2171550 * )
NEW met2 ( 2170890 213110 ) ( * 235080 )
NEW met2 ( 2170890 235220 ) ( 2171010 * )
NEW met2 ( 2170950 235310 ) via_260_260_hv
NEW met2 ( 2170890 235400 ) ( 2171010 * )
NEW met2 ( 2170890 235540 ) ( * 235470 )
NEW met1 ( 780885 235250 ) ( 2170750 * )
NEW met1 ( 780885 233430 ) ( * 235110 )
NEW met1 ( 703475 233290 ) ( 780885 * )
NEW met1 ( 703475 233430 ) ( * 235110 )
NEW met1 ( 698015 235250 ) ( 703475 * )
NEW met1 ( 697815 235190 ) via_260_260_hv ( * 235280 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 697875 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 697755 235420 ) ( * 235400 )
NEW met2 ( 697755 235100 ) ( 697875 * )
NEW met2 ( 697755 213370 ) ( * 234960 )
NEW met1 ( 697690 213290 ) ( 697810 * )
NEW met1 ( 697690 212460 ) ( 697810 * )
NEW met1 ( 697750 212875 ) via_260_850_vh
NEW met1 ( 697755 212875 ) mcon_170_850
NEW met2 ( 2170600 212790 ) ( 2171550 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_76/A ( sky130_fd_sc_hd__buf_8_76 A )
( sky130_fd_sc_hd__buf_8_139 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 694075 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 693600 212970 ) ( 694550 * )
NEW met2 ( 693890 213110 ) ( * 234940 )
NEW met2 ( 693890 235080 ) ( 694010 * )
NEW met2 ( 693950 235170 ) via_260_260_hv
NEW met2 ( 693890 235260 ) ( 694010 * )
NEW met2 ( 693890 235400 ) ( * 235380 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 223145 235110 ) ( 693750 * )
NEW met1 ( 223145 235250 ) ( * 1692265 )
NEW met1 ( 223145 1692405 ) ( 223265 * )
NEW met1 ( 223205 1692495 ) via_260_260_vh
NEW met1 ( 223145 1692585 ) ( 223265 * )
NEW met2 ( 223405 1692435 ) ( 223675 * )
NEW met2 ( 206825 1692435 ) ( 223005 * )
NEW met2 ( 206330 1692445 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1692535 ) ( 206685 * )
NEW met2 ( 205975 1692355 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 693600 212790 ) ( 694550 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_65/X ( sky130_fd_sc_hd__buf_8_65 X )
( sky130_fd_sc_hd__buf_8_145 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 730405 215935 ) mcon_170_850
NEW met1 ( 730340 216350 ) ( 730460 * )
NEW met2 ( 730390 216430 ) ( * 229340 )
NEW met2 ( 730390 229480 ) ( 730510 * )
NEW met2 ( 730450 229570 ) via_260_260_hv
NEW met2 ( 730390 229660 ) ( 730510 * )
NEW met2 ( 730390 229800 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 215585 229510 ) ( 730250 * )
NEW met1 ( 215585 229650 ) ( * 1733505 )
NEW met1 ( 215585 1733645 ) ( 215705 * )
NEW met1 ( 215645 1733735 ) via_260_260_vh
NEW met1 ( 215585 1733825 ) ( 215705 * )
NEW met2 ( 215845 1733675 ) ( 223670 * )
NEW met2 ( 203475 1733675 ) ( 215445 * )
NEW met1 ( 203215 1734395 ) ( 203335 * )
NEW met1 ( 203215 1733325 ) ( 203335 * )
NEW met1 ( 203275 1733860 ) via_260_1090_vh
NEW met1 ( 203270 1733860 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 730340 215520 ) ( 730460 * )
NEW met1 ( 730400 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_65/A ( sky130_fd_sc_hd__buf_8_65 A )
( sky130_fd_sc_hd__buf_8_106 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 734585 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 734110 216030 ) ( 735060 * )
NEW met2 ( 734605 216170 ) ( * 229360 )
NEW met2 ( 734605 229500 ) ( 734725 * )
NEW met2 ( 734665 229590 ) via_260_260_hv
NEW met2 ( 734605 229680 ) ( 734725 * )
NEW met2 ( 734605 229820 ) ( * 232275 )
NEW met1 ( 734865 229650 ) ( 2207450 * ) ( * 229710 )
via_260_260_hv ( * 229800 ) ( 2207510 * )
NEW met2 ( 2207390 229940 ) ( * 232415 )
NEW met2 ( 2207390 229620 ) ( 2207510 * )
NEW met2 ( 2207390 216430 ) ( * 229480 )
NEW met1 ( 2207340 216350 ) ( 2207460 * )
NEW met1 ( 2207340 215520 ) ( 2207460 * )
NEW met1 ( 2207400 215935 ) via_260_850_vh
NEW met1 ( 2207405 215935 ) mcon_170_850
NEW met2 ( 734110 215850 ) ( 735060 * )
NEW li1 ( 734125 215965 ) ( 735045 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_54/X ( sky130_fd_sc_hd__buf_8_54 X )
( sky130_fd_sc_hd__buf_8_116 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 763535 212875 ) mcon_170_850
NEW met1 ( 763470 213290 ) ( 763590 * )
NEW met2 ( 763535 213370 ) ( * 225720 )
NEW met2 ( 763535 225860 ) ( 763655 * )
NEW met2 ( 763595 225950 ) via_260_260_hv
NEW met2 ( 763535 226040 ) ( 763655 * )
NEW met2 ( 763535 226180 ) ( * 232275 )
NEW met1 ( 763795 226010 ) ( 2236730 * ) ( * 226070 )
via_260_260_hv ( * 226160 ) ( 2236790 * )
NEW met2 ( 2236670 226300 ) ( * 232415 )
NEW met2 ( 2236670 225980 ) ( 2236790 * )
NEW met2 ( 2236670 213110 ) ( * 225840 )
NEW met2 ( 2236380 212970 ) ( 2237330 * )
NEW met2 ( 2236855 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2236380 212790 ) ( 2237330 * )
NEW met1 ( 763470 212460 ) ( 763590 * )
NEW met1 ( 763530 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_54/A ( sky130_fd_sc_hd__buf_8_54 A )
( sky130_fd_sc_hd__buf_8_156 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 759855 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 759380 212970 ) ( 760330 * )
NEW met2 ( 759670 213110 ) ( * 225700 )
NEW met2 ( 759670 225840 ) ( 759790 * )
NEW met2 ( 759730 225930 ) via_260_260_hv
NEW met2 ( 759670 226020 ) ( 759790 * )
NEW met2 ( 759670 226160 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 210825 225870 ) ( 759530 * )
NEW met1 ( 210825 226010 ) ( * 1758045 )
NEW met1 ( 210825 1758185 ) ( 210945 * )
NEW met1 ( 210885 1758275 ) via_260_260_vh
NEW met1 ( 210825 1758365 ) ( 210945 * )
NEW met2 ( 211085 1758215 ) ( 223670 * )
NEW met2 ( 206825 1758215 ) ( 210685 * )
NEW met2 ( 206330 1758225 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1758315 ) ( 206685 * )
NEW met2 ( 205975 1758135 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 759380 212790 ) ( 760330 * ) ;
- sky130_fd_sc_hd__buf_8_31/A ( sky130_fd_sc_hd__buf_8_31 A )
( sky130_fd_sc_hd__buf_8_21 X )
+ ROUTED met1 ( 3384835 3621155 ) mcon_170_1090
NEW met1 ( 3384770 3621690 ) ( 3384890 * )
NEW met2 ( 3374210 3620970 ) ( 3384630 * )
NEW met1 ( 3373950 3621120 ) ( 3374070 * )
NEW met1 ( 3374010 3621030 ) via_260_260_vh
NEW met2 ( 3369280 3620970 ) ( 3373810 * )
NEW met1 ( 3373950 3620940 ) ( 3374070 * )
NEW met1 ( 3374070 2255005 ) ( * 3620800 )
NEW met1 ( 3374070 2254865 ) ( 3374190 * )
NEW met1 ( 3374130 2254775 ) via_260_260_vh ( * 2254715 )
( 3384835 * ) ( * 2254710 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2254800 ) ( 3385190 * )
NEW met2 ( 3384480 2254620 ) ( 3385190 * )
NEW met2 ( 3366060 2254715 ) ( 3373930 * )
NEW met1 ( 3374070 2254685 ) ( 3374190 * )
NEW met1 ( 3384770 3620620 ) ( 3384890 * )
NEW met1 ( 3384830 3621155 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[9] ( sky130_fd_sc_hd__buf_8_21 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3373930 1172320 ) ( * 1176060 )
NEW met1 ( 3373930 1176200 ) ( 3374210 * )
NEW met1 ( 3374210 1176340 ) ( * 2250680 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3374090 2250820 ) ( 3374210 * )
NEW met1 ( 3374150 2250910 ) via_260_260_vh
NEW met1 ( 3374090 2251000 ) ( 3374210 * )
NEW met2 ( 3374350 2250850 ) ( 3384630 * )
NEW met1 ( 3384770 2251570 ) ( 3384890 * )
NEW met1 ( 3384770 2250500 ) ( 3384890 * )
NEW met1 ( 3384830 2251035 ) via_260_1090_vh
NEW met1 ( 3384835 2251035 ) mcon_170_1090
NEW met2 ( 3366060 2250850 ) ( 3373950 * ) ;
- sky130_fd_sc_hd__buf_8_32/A ( sky130_fd_sc_hd__buf_8_32 A )
( sky130_fd_sc_hd__buf_8_180 X )
+ ROUTED met1 ( 3381775 3637745 ) mcon_170_1090
NEW met1 ( 3381710 3638280 ) ( 3381830 * )
NEW met2 ( 3376850 3637765 ) ( 3381570 * )
NEW met1 ( 3376590 3637795 ) ( 3376710 * )
NEW met1 ( 3376590 3637935 ) ( * 4976725 )
NEW met1 ( 3314825 4976865 ) ( 3376590 * )
NEW met1 ( 3314625 4976805 ) via_260_260_hv ( * 4976895 )
( 3314685 * )
NEW met2 ( 3314685 4977035 ) ( * 4982545 )
NEW met1 ( 3314615 4983455 ) ( 3314735 * )
NEW met1 ( 3314615 4982625 ) ( 3314735 * )
NEW met1 ( 3314675 4983040 ) via_260_850_vh
NEW met1 ( 3314670 4983040 ) mcon_170_850
NEW met2 ( 3314565 4976715 ) ( 3314685 * )
NEW met2 ( 3314685 4972915 ) ( * 4976575 )
NEW met2 ( 3376650 3637705 ) via_260_260_vh
NEW met2 ( 3376220 3637765 ) ( 3376450 * )
NEW met1 ( 3376590 3637615 ) ( 3376710 * )
NEW met1 ( 3381710 3637210 ) ( 3381830 * )
NEW met1 ( 3381770 3637745 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[12] ( sky130_fd_sc_hd__buf_8_43 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 851705 4976515 ) ( 859475 * )
NEW met1 ( 851505 4976575 ) via_260_260_hv ( * 4976665 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( 851565 * )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
NEW met2 ( 851445 4976805 ) ( * 4984390 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 851380 4985300 ) ( 851500 * )
NEW met1 ( 851380 4984470 ) ( 851500 * )
NEW met1 ( 851440 4984885 ) via_260_850_vh
NEW met1 ( 851445 4984885 ) mcon_170_850
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
NEW met2 ( 851445 4976485 ) ( 851565 * )
NEW met2 ( 851445 4975560 ) ( * 4976345 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[11] ( sky130_fd_sc_hd__buf_8_10 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2080605 4976305 ) ( 2084375 * ) ( * 4976365 )
via_260_260_hv ( * 4976455 ) ( 2084435 * )
NEW met2 ( 2084435 4976595 ) ( * 4986015 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met1 ( 2084380 4986925 ) ( 2084500 * )
NEW met1 ( 2084380 4986095 ) ( 2084500 * )
NEW met1 ( 2084440 4986510 ) via_260_850_vh
NEW met1 ( 2084435 4986510 ) mcon_170_850
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2084315 4976275 ) ( 2084435 * )
NEW met2 ( 2084435 4976135 ) ( 2084435 * ) ;
- sky130_fd_sc_hd__buf_8_10/A ( sky130_fd_sc_hd__buf_8_10 A )
( sky130_fd_sc_hd__buf_8_194 X )
+ ROUTED met1 ( 2088115 4986510 ) mcon_1090_170
via_1090_260_hv
NEW met2 ( 2087640 4986595 ) ( 2088590 * )
NEW met2 ( 2087640 4986415 ) ( 2088590 * )
NEW met2 ( 2088300 4976615 ) ( * 4986275 )
NEW met2 ( 2088180 4976475 ) ( 2088300 * )
NEW met1 ( 2088125 4976445 ) ( 2088240 * ) ( * 4976385 )
via_260_260_hv
NEW met1 ( 2088440 4976445 ) ( 3311380 * ) ( * 4976505 )
via_260_260_hv ( * 4976595 ) ( 3311440 * )
NEW met2 ( 3311440 4976735 ) ( * 4985605 )
NEW met1 ( 3311385 4986515 ) ( 3311505 * )
NEW met1 ( 3311385 4985685 ) ( 3311505 * )
NEW met1 ( 3311445 4986100 ) via_260_850_vh
NEW met1 ( 3311440 4986100 ) mcon_170_850
NEW met2 ( 3311320 4976415 ) ( 3311440 * )
NEW met2 ( 3311440 4972915 ) ( * 4976275 )
NEW met2 ( 2088180 4976295 ) ( 2088300 * )
NEW met2 ( 2088300 4976135 ) ( * 4976155 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_165/X ( sky130_fd_sc_hd__buf_8_165 X )
( sky130_fd_sc_hd__buf_8_155 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 3028195 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3028280 ) ( 206575 * )
NEW met2 ( 206715 3028180 ) ( 214185 * )
NEW met1 ( 214325 3028330 ) ( 214445 * )
NEW met1 ( 214385 3028240 ) via_260_260_vh
NEW met1 ( 214325 3028150 ) ( 214445 * )
NEW met1 ( 214325 1744660 ) ( * 3028010 )
NEW met1 ( 214205 1744520 ) ( 214325 * )
NEW met1 ( 214265 1744430 ) via_260_260_vh
NEW met2 ( 206535 1744490 ) ( 214065 * )
NEW met1 ( 206275 1745005 ) ( 206395 * )
NEW met1 ( 206275 1743935 ) ( 206395 * )
NEW met1 ( 206335 1744470 ) via_260_1090_vh
NEW met1 ( 206330 1744470 ) mcon_170_1090
NEW met2 ( 214465 1744490 ) ( 223670 * )
NEW met1 ( 214205 1744340 ) ( 214325 * )
NEW met2 ( 214585 3028180 ) ( 221530 * )
NEW met2 ( 205865 3028100 ) ( 206575 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_167/X ( sky130_fd_sc_hd__buf_8_167 X )
( sky130_fd_sc_hd__buf_8_144 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 3022215 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3022300 ) ( 206575 * )
NEW met2 ( 206715 3022200 ) ( 215305 * )
NEW met1 ( 215445 3022350 ) ( 215565 * )
NEW met1 ( 215505 3022260 ) via_260_260_vh
NEW met1 ( 215445 3022170 ) ( 215565 * )
NEW met1 ( 215445 1738800 ) ( * 3022030 )
NEW met1 ( 215325 1738660 ) ( 215445 * )
NEW met1 ( 215385 1738570 ) via_260_260_vh ( * 1738510 )
( 223670 * )
NEW met2 ( 206535 1738510 ) ( 215185 * )
NEW met1 ( 206275 1739025 ) ( 206395 * )
NEW met1 ( 206275 1737955 ) ( 206395 * )
NEW met1 ( 206335 1738490 ) via_260_1090_vh
NEW met1 ( 206330 1738490 ) mcon_170_1090
NEW met1 ( 215325 1738480 ) ( 215445 * )
NEW met2 ( 215705 3022200 ) ( 221530 * )
NEW met2 ( 205865 3022120 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[24] ( sky130_fd_sc_hd__buf_8_133 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 224685 1689990 ) ( * 1770580 )
NEW met1 ( 224565 1689850 ) ( 224685 * )
NEW met1 ( 224625 1689760 ) via_260_260_vh ( * 1689700 )
( 224840 * )
NEW met2 ( 203765 1689700 ) ( 224425 * )
NEW met2 ( 203270 1689695 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1689785 ) ( 203625 * )
NEW met2 ( 202915 1689605 ) ( 203625 * )
NEW met1 ( 224565 1689670 ) ( 224685 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[29] ( sky130_fd_sc_hd__buf_8_122 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3374350 1152580 ) ( * 1156380 )
NEW met1 ( 3374070 1152440 ) ( 3374350 * )
NEW met1 ( 3374070 214770 ) ( * 1152300 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2533650 214630 ) ( 3374070 * )
NEW met1 ( 2533650 213250 ) ( * 214490 )
NEW met1 ( 2419765 213110 ) ( 2533650 * )
NEW met1 ( 2419765 213250 ) ( * 223490 )
NEW met1 ( 2258735 223630 ) ( 2419770 * )
NEW met1 ( 2258535 223570 ) via_260_260_hv ( * 223660 )
( 2258595 * )
NEW met2 ( 2258475 223800 ) ( * 232415 )
NEW met2 ( 2258475 223480 ) ( 2258595 * )
NEW met2 ( 2258475 213370 ) ( * 223340 )
NEW met1 ( 2258410 213290 ) ( 2258530 * )
NEW met1 ( 2258410 212460 ) ( 2258530 * )
NEW met1 ( 2258470 212875 ) via_260_850_vh
NEW met1 ( 2258475 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[14] ( sky130_fd_sc_hd__buf_8_111 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3368190 219250 ) ( * 1145620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2527770 219110 ) ( 3368190 * )
NEW met1 ( 2527770 216330 ) ( * 218970 )
NEW met1 ( 2425650 216190 ) ( 2527770 * )
NEW met1 ( 2425650 216330 ) ( * 227970 )
NEW met1 ( 2223825 228110 ) ( 2425650 * )
NEW met1 ( 2223625 228050 ) via_260_260_hv ( * 228140 )
( 2223685 * )
NEW met2 ( 2223565 228280 ) ( * 232415 )
NEW met2 ( 2223565 227960 ) ( 2223685 * )
NEW met2 ( 2223565 216170 ) ( * 227820 )
NEW met2 ( 2223070 216030 ) ( 2224020 * )
NEW met2 ( 2223545 215940 ) via_1090_260_hv
NEW li1 ( 2223085 215965 ) ( 2224005 * )
NEW li1 ( 2223545 215935 ) mcon_1090_170
NEW met2 ( 2223070 215850 ) ( 2224020 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[20] ( sky130_fd_sc_hd__buf_8_100 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3362030 1131000 ) ( * 1134640 )
NEW met1 ( 3361750 1130860 ) ( 3362030 * )
NEW met1 ( 3361750 224010 ) ( * 1130720 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2521330 223870 ) ( 3361750 * )
NEW met1 ( 2521330 219410 ) ( * 223730 )
NEW met1 ( 2432090 219270 ) ( 2521330 * )
NEW met1 ( 2432090 219410 ) ( * 232730 )
NEW met1 ( 2192955 232870 ) ( 2432090 * )
NEW met1 ( 2192755 232810 ) via_260_260_hv ( * 232900 )
( 2192815 * )
NEW met2 ( 2192695 233040 ) ( * 232940 )
NEW met2 ( 2192695 232720 ) ( 2192815 * )
NEW met2 ( 2192695 213370 ) ( * 232580 )
NEW met1 ( 2192630 213290 ) ( 2192750 * )
NEW met1 ( 2192630 212460 ) ( 2192750 * )
NEW met1 ( 2192690 212875 ) via_260_850_vh
NEW met1 ( 2192695 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[21] ( sky130_fd_sc_hd__buf_8_177 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 220905 3053865 ) ( * 3056710 )
NEW met1 ( 220905 3053725 ) ( 221185 * )
NEW met1 ( 221185 2996805 ) ( * 3053585 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 221065 2996665 ) ( 221185 * )
NEW met1 ( 221125 2996575 ) via_260_260_vh ( * 2996515 )
( 221535 * )
NEW met2 ( 206425 2996515 ) ( 220925 * )
NEW met1 ( 206165 2997030 ) ( 206285 * )
NEW met1 ( 206165 2995960 ) ( 206285 * )
NEW met1 ( 206225 2996495 ) via_260_1090_vh
NEW met1 ( 206220 2996495 ) mcon_170_1090
NEW met1 ( 221065 2996485 ) ( 221185 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_185/A ( sky130_fd_sc_hd__buf_8_185 A )
( sky130_fd_sc_hd__buf_8_166 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203035 4427995 ) mcon_170_1090
NEW met1 ( 202980 4428530 ) ( 203100 * )
NEW met2 ( 203240 4427810 ) ( 215725 * )
NEW met1 ( 215865 4427960 ) ( 215985 * )
NEW met1 ( 215925 4427870 ) via_260_260_vh
NEW met1 ( 215865 4427780 ) ( 215985 * )
NEW met1 ( 215865 3025735 ) ( * 4427640 )
NEW met1 ( 215745 3025595 ) ( 215865 * )
NEW met1 ( 215805 3025505 ) via_260_260_vh ( * 3025445 )
( 221530 * )
NEW met2 ( 203655 3025445 ) ( 215605 * )
NEW met2 ( 203160 3025440 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3025530 ) ( 203515 * )
NEW met2 ( 202805 3025350 ) ( 203515 * )
NEW met1 ( 215745 3025415 ) ( 215865 * )
NEW met2 ( 216125 4427810 ) ( 216065 * )
NEW met1 ( 202980 4427460 ) ( 203100 * )
NEW met1 ( 203040 4427995 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[15] ( sky130_fd_sc_hd__buf_8_188 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 214325 4460485 ) ( * 4462515 )
NEW met1 ( 214325 4460345 ) ( 214605 * )
NEW met1 ( 214605 4438795 ) ( * 4460205 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 214485 4438655 ) ( 214605 * )
NEW met1 ( 214545 4438565 ) via_260_260_vh
NEW met2 ( 206300 4438625 ) ( 214345 * )
NEW met1 ( 206040 4439140 ) ( 206160 * )
NEW met1 ( 206040 4438070 ) ( 206160 * )
NEW met1 ( 206100 4438605 ) via_260_1090_vh
NEW met1 ( 206095 4438605 ) mcon_170_1090
NEW met2 ( 214745 4438625 ) ( 216065 * )
NEW met1 ( 214485 4438475 ) ( 214605 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[4] ( sky130_fd_sc_hd__buf_8_53 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3368890 1181320 ) ( * 2221400 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3368770 2221540 ) ( 3368890 * )
NEW met1 ( 3368830 2221630 ) via_260_260_vh
NEW met1 ( 3368770 2221720 ) ( 3368890 * )
NEW met2 ( 3369030 2221570 ) ( 3381775 * ) ( * 2221580 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2221670 ) ( 3382130 * )
NEW met2 ( 3381420 2221490 ) ( 3382130 * )
NEW met2 ( 3366060 2221570 ) ( 3368630 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[4] ( sky130_fd_sc_hd__buf_8_53 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3368750 2226075 ) ( * 2279205 )
NEW met1 ( 3368750 2225935 ) ( 3368870 * )
NEW met1 ( 3368810 2225845 ) via_260_260_vh ( * 2225785 )
( 3381570 * )
NEW met1 ( 3381710 2226300 ) ( 3381830 * )
NEW met1 ( 3381710 2225230 ) ( 3381830 * )
NEW met1 ( 3381770 2225765 ) via_260_1090_vh
NEW met1 ( 3381775 2225765 ) mcon_170_1090
NEW met2 ( 3366060 2225785 ) ( 3368610 * )
NEW met1 ( 3368750 2225755 ) ( 3368870 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[21] ( sky130_fd_sc_hd__buf_8_97 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3360910 1128980 ) ( * 1132610 )
NEW met1 ( 3360630 1128840 ) ( 3360910 * )
NEW met1 ( 3360630 224850 ) ( * 1128700 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2520210 224710 ) ( 3360630 * )
NEW met1 ( 2520210 219970 ) ( * 224570 )
NEW met1 ( 2433210 219830 ) ( 2520210 * )
NEW met1 ( 2433210 219970 ) ( * 233570 )
NEW met1 ( 2186975 233710 ) ( 2433210 * )
NEW met1 ( 2186775 233650 ) via_260_260_hv ( * 233740 )
( 2186835 * )
NEW met2 ( 2186715 233880 ) ( * 233800 )
NEW met2 ( 2186715 233560 ) ( 2186835 * )
NEW met2 ( 2186715 213370 ) ( * 233420 )
NEW met1 ( 2186650 213290 ) ( 2186770 * )
NEW met1 ( 2186650 212460 ) ( 2186770 * )
NEW met1 ( 2186710 212875 ) via_260_850_vh
NEW met1 ( 2186715 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[26] ( sky130_fd_sc_hd__buf_8_86 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3354750 229330 ) ( * 1121680 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2514330 229190 ) ( 3354750 * )
NEW met1 ( 2514330 223050 ) ( * 229050 )
NEW met1 ( 2439090 222910 ) ( 2514330 * )
NEW met1 ( 2439090 223050 ) ( * 238050 )
NEW met1 ( 2152065 238190 ) ( 2439090 * )
NEW met1 ( 2151865 238130 ) via_260_260_hv ( * 238220 )
( 2151925 * )
NEW met2 ( 2151805 238360 ) ( * 238295 )
NEW met2 ( 2151805 238040 ) ( 2151925 * )
NEW met2 ( 2151805 216170 ) ( * 237900 )
NEW met2 ( 2151310 216030 ) ( 2152260 * )
NEW met2 ( 2151785 215940 ) via_1090_260_hv
NEW li1 ( 2151325 215965 ) ( 2152245 * )
NEW li1 ( 2151785 215935 ) mcon_1090_170
NEW met2 ( 2151310 215850 ) ( 2152260 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_75/X ( sky130_fd_sc_hd__buf_8_75 X )
( sky130_fd_sc_hd__buf_8_135 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 700505 215935 ) mcon_170_850
NEW met1 ( 700440 216350 ) ( 700560 * )
NEW met2 ( 700490 216430 ) ( * 233540 )
NEW met2 ( 700490 233680 ) ( 700610 * )
NEW met2 ( 700550 233770 ) via_260_260_hv
NEW met2 ( 700490 233860 ) ( 700610 * )
NEW met2 ( 700490 234000 ) ( * 233990 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 221185 233710 ) ( 700350 * )
NEW met1 ( 221185 233850 ) ( * 1703605 )
NEW met1 ( 221185 1703745 ) ( 221305 * )
NEW met1 ( 221245 1703835 ) via_260_260_vh
NEW met1 ( 221185 1703925 ) ( 221305 * )
NEW met2 ( 221445 1703775 ) ( 223670 * )
NEW met2 ( 203475 1703775 ) ( 221045 * )
NEW met1 ( 203215 1704495 ) ( 203335 * )
NEW met1 ( 203215 1703425 ) ( 203335 * )
NEW met1 ( 203275 1703960 ) via_260_1090_vh
NEW met1 ( 203270 1703960 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 700440 215520 ) ( 700560 * )
NEW met1 ( 700500 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_98/X ( sky130_fd_sc_hd__buf_8_98 X )
( sky130_fd_sc_hd__buf_8_75 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2177505 215935 ) mcon_170_850
NEW met1 ( 2177440 216350 ) ( 2177560 * )
NEW met2 ( 2177490 216430 ) ( * 233680 )
NEW met2 ( 2177490 233820 ) ( 2177610 * )
NEW met2 ( 2177550 233910 ) via_260_260_hv
NEW met2 ( 2177490 234000 ) ( 2177610 * )
NEW met2 ( 2177490 234140 ) ( * 234110 )
NEW met1 ( 782285 233850 ) ( 2177350 * )
NEW met1 ( 782285 232590 ) ( * 233710 )
NEW met1 ( 704845 232450 ) ( 782285 * )
NEW met1 ( 704645 232390 ) via_260_260_hv ( * 232480 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 704705 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 704705 232620 ) ( * 232610 )
NEW met2 ( 704585 232300 ) ( 704705 * )
NEW met2 ( 704705 216170 ) ( * 232160 )
NEW met2 ( 704210 216030 ) ( 705160 * )
NEW met2 ( 704685 215940 ) via_1090_260_hv
NEW li1 ( 704225 215965 ) ( 705145 * )
NEW li1 ( 704685 215935 ) mcon_1090_170
NEW met2 ( 704210 215850 ) ( 705160 * )
NEW met1 ( 2177440 215520 ) ( 2177560 * )
NEW met1 ( 2177500 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_64/X ( sky130_fd_sc_hd__buf_8_64 X )
( sky130_fd_sc_hd__buf_8_107 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 733635 212875 ) mcon_170_850
NEW met1 ( 733570 213290 ) ( 733690 * )
NEW met2 ( 733635 213370 ) ( * 229640 )
NEW met2 ( 733635 229780 ) ( 733755 * )
NEW met2 ( 733695 229870 ) via_260_260_hv
NEW met2 ( 733635 229960 ) ( 733755 * )
NEW met2 ( 733635 230100 ) ( * 232275 )
NEW met1 ( 733895 229930 ) ( 785935 * )
NEW met1 ( 785935 230070 ) ( 785935 * )
NEW met1 ( 785935 230210 ) ( 2206830 * ) ( * 230270 )
via_260_260_hv ( * 230360 ) ( 2206890 * )
NEW met2 ( 2206770 230500 ) ( * 232415 )
NEW met2 ( 2206770 230180 ) ( 2206890 * )
NEW met2 ( 2206770 213110 ) ( * 230040 )
NEW met2 ( 2206480 212970 ) ( 2207430 * )
NEW met2 ( 2206955 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2206480 212790 ) ( 2207430 * )
NEW met1 ( 733570 212460 ) ( 733690 * )
NEW met1 ( 733630 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_64/A ( sky130_fd_sc_hd__buf_8_64 A )
( sky130_fd_sc_hd__buf_8_147 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 729955 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 729480 212970 ) ( 730430 * )
NEW met2 ( 729770 213110 ) ( * 229620 )
NEW met2 ( 729770 229760 ) ( 729890 * )
NEW met2 ( 729830 229850 ) via_260_260_hv
NEW met2 ( 729770 229940 ) ( 729890 * )
NEW met2 ( 729770 230080 ) ( * 232275 )
NEW met1 ( 700475 229790 ) ( 729630 * )
NEW met1 ( 700475 229930 ) ( 700475 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 216425 230070 ) ( 700475 * )
NEW met1 ( 216425 230210 ) ( * 1728145 )
NEW met1 ( 216425 1728285 ) ( 216545 * )
NEW met1 ( 216485 1728375 ) via_260_260_vh
NEW met1 ( 216425 1728465 ) ( 216545 * )
NEW met2 ( 216685 1728315 ) ( 223670 * )
NEW met2 ( 206825 1728315 ) ( 216285 * )
NEW met2 ( 206330 1728325 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1728415 ) ( 206685 * )
NEW met2 ( 205975 1728235 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 729480 212790 ) ( 730430 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[9] ( sky130_fd_sc_hd__buf_8_20 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3374490 1171320 ) ( * 2251300 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3374370 2251440 ) ( 3374490 * )
NEW met1 ( 3374430 2251530 ) via_260_260_vh
NEW met1 ( 3374370 2251620 ) ( 3374490 * )
NEW met2 ( 3374630 2251470 ) ( 3381775 * ) ( * 2251480 )
via_850_260_hv mcon_850_170
NEW met2 ( 3381420 2251570 ) ( 3382130 * )
NEW met2 ( 3381420 2251390 ) ( 3382130 * )
NEW met2 ( 3366060 2251470 ) ( 3374230 * ) ;
- sky130_fd_sc_hd__buf_8_30/X ( sky130_fd_sc_hd__buf_8_30 X )
( sky130_fd_sc_hd__buf_8_20 A )
+ ROUTED met1 ( 3381775 3621605 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3374490 3621590 ) ( 3381280 * )
NEW met1 ( 3374230 3621740 ) ( 3374350 * )
NEW met1 ( 3374290 3621650 ) via_260_260_vh
NEW met2 ( 3369280 3621590 ) ( 3374090 * )
NEW met1 ( 3374230 3621560 ) ( 3374350 * )
NEW met1 ( 3374350 2255975 ) ( * 3621420 )
NEW met1 ( 3374350 2255835 ) ( 3374470 * )
NEW met1 ( 3374410 2255745 ) via_260_260_vh ( * 2255685 )
( 3381570 * )
NEW met1 ( 3381710 2256200 ) ( 3381830 * )
NEW met1 ( 3381710 2255130 ) ( 3381830 * )
NEW met1 ( 3381770 2255665 ) via_260_1090_vh
NEW met1 ( 3381775 2255665 ) mcon_170_1090
NEW met2 ( 3366060 2255685 ) ( 3374210 * )
NEW met1 ( 3374350 2255655 ) ( 3374470 * )
NEW met2 ( 3381420 3621690 ) ( 3382130 * )
NEW met2 ( 3381420 3621510 ) ( 3382130 * ) ;
- sky130_fd_sc_hd__buf_8_31/X ( sky130_fd_sc_hd__buf_8_31 X )
( sky130_fd_sc_hd__buf_8_196 A )
+ ROUTED met1 ( 3384835 3624835 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3384480 3624920 ) ( 3385190 * )
NEW met2 ( 3384480 3624740 ) ( 3385190 * )
NEW met2 ( 3374190 3624835 ) ( 3384340 * )
NEW met1 ( 3373930 3624985 ) ( 3374050 * )
NEW met1 ( 3373930 3625125 ) ( * 4974205 )
NEW met1 ( 3327405 4974345 ) ( 3373930 * )
NEW met1 ( 3327205 4974285 ) via_260_260_hv ( * 4974375 )
( 3327265 * )
NEW met2 ( 3327265 4974515 ) ( * 4985865 )
NEW met2 ( 3326605 4986005 ) ( 3327555 * )
NEW met2 ( 3327080 4986095 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 3326605 4986185 ) ( 3327555 * )
NEW met2 ( 3327145 4974195 ) ( 3327265 * )
NEW met2 ( 3327265 4972915 ) ( * 4974055 )
NEW met2 ( 3373990 3624895 ) via_260_260_vh
NEW met2 ( 3369280 3624835 ) ( 3373790 * )
NEW met1 ( 3373930 3624805 ) ( 3374050 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[12] ( sky130_fd_sc_hd__buf_8_42 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 852675 4977075 ) ( 860475 * )
NEW met1 ( 852475 4977135 ) via_260_260_hv ( * 4977225 )
( 852535 * )
NEW met2 ( 852415 4977365 ) ( * 4981590 )
NEW met2 ( 851920 4981730 ) ( 852870 * )
NEW met2 ( 852395 4981820 ) via_1090_260_hv mcon_1090_170
( * 4981795 ) ( 852855 * )
NEW met2 ( 851920 4981910 ) ( 852870 * )
NEW met2 ( 852415 4977045 ) ( 852535 * )
NEW met2 ( 852415 4975560 ) ( * 4976905 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_164/A ( sky130_fd_sc_hd__buf_8_164 A )
( sky130_fd_sc_hd__buf_8_154 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3027745 ) mcon_170_1090
NEW met1 ( 203105 3028280 ) ( 203225 * )
NEW met2 ( 203365 3027560 ) ( 214465 * )
NEW met1 ( 214605 3027710 ) ( 214725 * )
NEW met1 ( 214665 3027620 ) via_260_260_vh
NEW met1 ( 214605 3027530 ) ( 214725 * )
NEW met1 ( 214605 1743810 ) ( * 3027390 )
NEW met1 ( 214485 1743670 ) ( 214605 * )
NEW met1 ( 214545 1743580 ) via_260_260_vh ( * 1743520 )
( 223670 * )
NEW met2 ( 203765 1743520 ) ( 214345 * )
NEW met2 ( 203270 1743515 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1743605 ) ( 203625 * )
NEW met2 ( 202915 1743425 ) ( 203625 * )
NEW met1 ( 214485 1743490 ) ( 214605 * )
NEW met2 ( 214865 3027560 ) ( 221530 * )
NEW met1 ( 203105 3027210 ) ( 203225 * )
NEW met1 ( 203165 3027745 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_175/X ( sky130_fd_sc_hd__buf_8_175 X )
( sky130_fd_sc_hd__buf_8_143 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 2998295 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 2998380 ) ( 206575 * )
NEW met2 ( 206715 2998280 ) ( 219785 * )
NEW met1 ( 219925 2998430 ) ( 220045 * )
NEW met1 ( 219985 2998340 ) via_260_260_vh
NEW met1 ( 219925 2998250 ) ( 220045 * )
NEW met1 ( 219925 1714880 ) ( * 2998110 )
NEW met1 ( 219805 1714740 ) ( 219925 * )
NEW met1 ( 219865 1714650 ) via_260_260_vh ( * 1714590 )
( 223670 * )
NEW met2 ( 206535 1714590 ) ( 219665 * )
NEW met1 ( 206275 1715105 ) ( 206395 * )
NEW met1 ( 206275 1714035 ) ( 206395 * )
NEW met1 ( 206335 1714570 ) via_260_1090_vh
NEW met1 ( 206330 1714570 ) mcon_170_1090
NEW met1 ( 219805 1714560 ) ( 219925 * )
NEW met2 ( 220185 2998280 ) ( 221530 * )
NEW met2 ( 205865 2998200 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[24] ( sky130_fd_sc_hd__buf_8_132 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 224125 1769045 ) ( * 1771580 )
NEW met1 ( 224125 1768905 ) ( 224405 * )
NEW met1 ( 224405 1690960 ) ( * 1768765 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 224285 1690820 ) ( 224405 * )
NEW met1 ( 224345 1690730 ) via_260_260_vh ( * 1690670 )
( 224840 * )
NEW met2 ( 206535 1690670 ) ( 224145 * )
NEW met1 ( 206275 1691185 ) ( 206395 * )
NEW met1 ( 206275 1690115 ) ( 206395 * )
NEW met1 ( 206335 1690650 ) via_260_1090_vh
NEW met1 ( 206330 1690650 ) mcon_170_1090
NEW met1 ( 224285 1690640 ) ( 224405 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[28] ( sky130_fd_sc_hd__buf_8_121 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3373230 1150660 ) ( * 1154370 )
NEW met1 ( 3372950 1150520 ) ( 3373230 * )
NEW met1 ( 3372950 215610 ) ( * 1150380 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2532530 215470 ) ( 3372950 * )
NEW met1 ( 2532530 213810 ) ( * 215330 )
NEW met1 ( 2420890 213670 ) ( 2532530 * )
NEW met1 ( 2420890 213810 ) ( * 224330 )
NEW met1 ( 2252755 224470 ) ( 2420890 * )
NEW met1 ( 2252555 224410 ) via_260_260_hv ( * 224500 )
( 2252615 * )
NEW met2 ( 2252495 224640 ) ( * 232415 )
NEW met2 ( 2252495 224320 ) ( 2252615 * )
NEW met2 ( 2252495 213370 ) ( * 224180 )
NEW met1 ( 2252430 213290 ) ( 2252550 * )
NEW met1 ( 2252430 212460 ) ( 2252550 * )
NEW met1 ( 2252490 212875 ) via_260_850_vh
NEW met1 ( 2252495 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[15] ( sky130_fd_sc_hd__buf_8_110 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3367630 1140910 ) ( * 1144620 )
NEW met1 ( 3367350 1140770 ) ( 3367630 * )
NEW met1 ( 3367350 219810 ) ( * 1140630 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2526930 219670 ) ( 3367350 * )
NEW met1 ( 2526930 216610 ) ( * 219530 )
NEW met1 ( 2426490 216470 ) ( 2526930 * )
NEW met1 ( 2426490 216610 ) ( * 228530 )
NEW met1 ( 2222855 228670 ) ( 2426490 * )
NEW met1 ( 2222655 228610 ) via_260_260_hv ( * 228700 )
( 2222715 * )
NEW met2 ( 2222595 228840 ) ( * 232415 )
NEW met2 ( 2222595 228520 ) ( 2222715 * )
NEW met2 ( 2222595 213370 ) ( * 228380 )
NEW met1 ( 2222530 213290 ) ( 2222650 * )
NEW met1 ( 2222530 212460 ) ( 2222650 * )
NEW met1 ( 2222590 212875 ) via_260_850_vh
NEW met1 ( 2222595 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[21] ( sky130_fd_sc_hd__buf_8_176 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 221465 2995835 ) ( * 3055710 )
NEW met1 ( 221345 2995695 ) ( 221465 * )
NEW met1 ( 221405 2995605 ) via_260_260_vh ( * 2995545 )
( 221535 * )
NEW met2 ( 203655 2995545 ) ( 221205 * )
NEW met2 ( 203160 2995540 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 2995630 ) ( 203515 * )
NEW met2 ( 202805 2995450 ) ( 203515 * )
NEW met1 ( 221345 2995515 ) ( 221465 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_188/X ( sky130_fd_sc_hd__buf_8_188 X )
( sky130_fd_sc_hd__buf_8_165 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206095 4434425 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205740 4434510 ) ( 206450 * )
NEW met2 ( 206590 4434410 ) ( 214325 * )
NEW met1 ( 214465 4434560 ) ( 214585 * )
NEW met1 ( 214525 4434470 ) via_260_260_vh
NEW met1 ( 214465 4434380 ) ( 214585 * )
NEW met1 ( 214465 3032565 ) ( * 4434240 )
NEW met1 ( 214345 3032425 ) ( 214465 * )
NEW met1 ( 214405 3032335 ) via_260_260_vh
NEW met2 ( 206425 3032395 ) ( 214205 * )
NEW met1 ( 206165 3032910 ) ( 206285 * )
NEW met1 ( 206165 3031840 ) ( 206285 * )
NEW met1 ( 206225 3032375 ) via_260_1090_vh
NEW met1 ( 206220 3032375 ) mcon_170_1090
NEW met2 ( 214605 3032395 ) ( 221530 * )
NEW met1 ( 214345 3032245 ) ( 214465 * )
NEW met2 ( 214725 4434410 ) ( 216065 * )
NEW met2 ( 205740 4434330 ) ( 206450 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[15] ( sky130_fd_sc_hd__buf_8_187 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 214885 4437945 ) ( * 4461515 )
NEW met1 ( 214765 4437805 ) ( 214885 * )
NEW met1 ( 214825 4437715 ) via_260_260_vh ( * 4437655 )
( 216065 * )
NEW met2 ( 203530 4437655 ) ( 214625 * )
NEW met2 ( 203035 4437650 ) via_850_260_hv mcon_850_170
NEW met2 ( 202680 4437740 ) ( 203390 * )
NEW met2 ( 202680 4437560 ) ( 203390 * )
NEW met1 ( 214765 4437625 ) ( 214885 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[4] ( sky130_fd_sc_hd__buf_8_52 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3368190 2275080 ) ( * 2278205 )
NEW met1 ( 3368190 2274940 ) ( 3368470 * )
NEW met1 ( 3368470 2225105 ) ( * 2274800 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3368470 2224965 ) ( 3368590 * )
NEW met1 ( 3368530 2224875 ) via_260_260_vh ( * 2224815 )
( 3384835 * ) ( * 2224810 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2224900 ) ( 3385190 * )
NEW met2 ( 3384480 2224720 ) ( 3385190 * )
NEW met2 ( 3366060 2224815 ) ( 3368330 * )
NEW met1 ( 3368470 2224785 ) ( 3368590 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[4] ( sky130_fd_sc_hd__buf_8_52 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3368330 1182320 ) ( * 1185810 )
NEW met1 ( 3368330 1185950 ) ( 3368610 * )
NEW met1 ( 3368610 1186090 ) ( * 2220780 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3368490 2220920 ) ( 3368610 * )
NEW met1 ( 3368550 2221010 ) via_260_260_vh
NEW met1 ( 3368490 2221100 ) ( 3368610 * )
NEW met2 ( 3368750 2220950 ) ( 3384630 * )
NEW met1 ( 3384770 2221670 ) ( 3384890 * )
NEW met1 ( 3384770 2220600 ) ( 3384890 * )
NEW met1 ( 3384830 2221135 ) via_260_1090_vh
NEW met1 ( 3384835 2221135 ) mcon_170_1090
NEW met2 ( 3366060 2220950 ) ( 3368350 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[22] ( sky130_fd_sc_hd__buf_8_96 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3359790 1127080 ) ( * 1130630 )
NEW met1 ( 3359510 1126940 ) ( 3359790 * )
NEW met1 ( 3359510 225690 ) ( * 1126800 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2519090 225550 ) ( 3359510 * )
NEW met1 ( 2519090 220530 ) ( * 225410 )
NEW met1 ( 2434330 220390 ) ( 2519090 * )
NEW met1 ( 2434330 220530 ) ( * 234410 )
NEW met1 ( 2180995 234550 ) ( 2434330 * )
NEW met1 ( 2180795 234490 ) via_260_260_hv ( * 234580 )
( 2180855 * )
NEW met2 ( 2180735 234720 ) ( * 234635 )
NEW met2 ( 2180735 234400 ) ( 2180855 * )
NEW met2 ( 2180735 213370 ) ( * 234260 )
NEW met1 ( 2180670 213290 ) ( 2180790 * )
NEW met1 ( 2180670 212460 ) ( 2180790 * )
NEW met1 ( 2180730 212875 ) via_260_850_vh
NEW met1 ( 2180735 212875 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_85/X ( sky130_fd_sc_hd__buf_8_85 X )
( sky130_fd_sc_hd__buf_8_121 A )
+ ROUTED met1 ( 775495 212875 ) mcon_170_850
NEW met1 ( 775430 213290 ) ( 775550 * )
NEW met2 ( 775495 213370 ) ( * 224040 )
NEW met2 ( 775495 224180 ) ( 775615 * )
NEW met2 ( 775555 224270 ) via_260_260_hv
NEW met2 ( 775495 224360 ) ( 775615 * )
NEW met2 ( 775495 224500 ) ( * 232275 )
NEW met1 ( 775755 224330 ) ( 2248690 * ) ( * 224390 )
via_260_260_hv ( * 224480 ) ( 2248750 * )
NEW met2 ( 2248630 224620 ) ( * 232415 )
NEW met2 ( 2248630 224300 ) ( 2248750 * )
NEW met2 ( 2248630 213110 ) ( * 224160 )
NEW met2 ( 2248340 212970 ) ( 2249290 * )
NEW met2 ( 2248815 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2248340 212790 ) ( 2249290 * )
NEW met1 ( 775430 212460 ) ( 775550 * )
NEW met1 ( 775490 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[28] ( sky130_fd_sc_hd__buf_8_85 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 658825 224050 ) ( 662305 * )
NEW met1 ( 662305 224190 ) ( 771690 * ) ( * 224250 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv ( * 224340 ) ( 771750 * )
NEW met2 ( 771630 224480 ) ( * 232275 )
NEW met2 ( 771630 224160 ) ( 771750 * )
NEW met2 ( 771630 213110 ) ( * 224020 )
NEW met2 ( 771340 212970 ) ( 772290 * )
NEW met2 ( 771815 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 771340 212790 ) ( 772290 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_96/A ( sky130_fd_sc_hd__buf_8_96 A )
( sky130_fd_sc_hd__buf_8_74 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2177055 212875 ) mcon_1090_170
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2176580 212970 ) ( 2177530 * )
NEW met2 ( 2176870 213110 ) ( * 234240 )
NEW met2 ( 2176870 234380 ) ( 2176990 * )
NEW met2 ( 2176930 234470 ) via_260_260_hv
NEW met2 ( 2176870 234560 ) ( 2176990 * )
NEW met2 ( 2176870 234700 ) ( * 234605 )
NEW met1 ( 781725 234410 ) ( 2176730 * )
NEW met1 ( 781725 232870 ) ( * 234270 )
NEW met1 ( 703995 232730 ) ( 781725 * )
NEW met1 ( 703795 232670 ) via_260_260_hv ( * 232760 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 703855 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 703735 232900 ) ( * 232820 )
NEW met2 ( 703735 232580 ) ( 703855 * )
NEW met2 ( 703735 213370 ) ( * 232440 )
NEW met1 ( 703670 213290 ) ( 703790 * )
NEW met1 ( 703670 212460 ) ( 703790 * )
NEW met1 ( 703730 212875 ) via_260_850_vh
NEW met1 ( 703735 212875 ) mcon_170_850
NEW met2 ( 2176580 212790 ) ( 2177530 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_74/A ( sky130_fd_sc_hd__buf_8_74 A )
( sky130_fd_sc_hd__buf_8_136 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 700055 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 699580 212970 ) ( 700530 * )
NEW met2 ( 699870 213110 ) ( * 234100 )
NEW met2 ( 699870 234240 ) ( 699990 * )
NEW met2 ( 699930 234330 ) via_260_260_hv
NEW met2 ( 699870 234420 ) ( 699990 * )
NEW met2 ( 699870 234560 ) ( * 234445 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 222025 234270 ) ( 699730 * )
NEW met1 ( 222025 234410 ) ( * 1698245 )
NEW met1 ( 222025 1698385 ) ( 222145 * )
NEW met1 ( 222085 1698475 ) via_260_260_vh
NEW met1 ( 222025 1698565 ) ( 222145 * )
NEW met2 ( 222285 1698415 ) ( 223670 * )
NEW met2 ( 206825 1698415 ) ( 221885 * )
NEW met2 ( 206330 1698425 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1698515 ) ( 206685 * )
NEW met2 ( 205975 1698335 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 699580 212790 ) ( 700530 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_63/X ( sky130_fd_sc_hd__buf_8_63 X )
( sky130_fd_sc_hd__buf_8_154 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 736385 215935 ) mcon_170_850
NEW met1 ( 736320 216350 ) ( 736440 * )
NEW met2 ( 736370 216430 ) ( * 228500 )
NEW met2 ( 736370 228640 ) ( 736490 * )
NEW met2 ( 736430 228730 ) via_260_260_hv
NEW met2 ( 736370 228820 ) ( 736490 * )
NEW met2 ( 736370 228960 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 214465 228670 ) ( 736230 * )
NEW met1 ( 214465 228810 ) ( * 1739485 )
NEW met1 ( 214465 1739625 ) ( 214585 * )
NEW met1 ( 214525 1739715 ) via_260_260_vh
NEW met1 ( 214465 1739805 ) ( 214585 * )
NEW met2 ( 214725 1739655 ) ( 223670 * )
NEW met2 ( 203475 1739655 ) ( 214325 * )
NEW met1 ( 203215 1740375 ) ( 203335 * )
NEW met1 ( 203215 1739305 ) ( 203335 * )
NEW met1 ( 203275 1739840 ) via_260_1090_vh
NEW met1 ( 203270 1739840 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 736320 215520 ) ( 736440 * )
NEW met1 ( 736380 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_63/A ( sky130_fd_sc_hd__buf_8_63 A )
( sky130_fd_sc_hd__buf_8_108 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 740565 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 740090 216030 ) ( 741040 * )
NEW met2 ( 740585 216170 ) ( * 228520 )
NEW met2 ( 740585 228660 ) ( 740705 * )
NEW met2 ( 740645 228750 ) via_260_260_hv
NEW met2 ( 740585 228840 ) ( 740705 * )
NEW met2 ( 740585 228980 ) ( * 232275 )
NEW met1 ( 740845 228810 ) ( 2213430 * ) ( * 228870 )
via_260_260_hv ( * 228960 ) ( 2213490 * )
NEW met2 ( 2213370 229100 ) ( * 232415 )
NEW met2 ( 2213370 228780 ) ( 2213490 * )
NEW met2 ( 2213370 216430 ) ( * 228640 )
NEW met1 ( 2213320 216350 ) ( 2213440 * )
NEW met1 ( 2213320 215520 ) ( 2213440 * )
NEW met1 ( 2213380 215935 ) via_260_850_vh
NEW met1 ( 2213385 215935 ) mcon_170_850
NEW met2 ( 740090 215850 ) ( 741040 * )
NEW li1 ( 740105 215965 ) ( 741025 * ) ;
- sky130_fd_sc_hd__buf_8_30/A ( sky130_fd_sc_hd__buf_8_30 A )
( sky130_fd_sc_hd__buf_8_192 X )
+ ROUTED met1 ( 3381775 3625785 ) mcon_170_1090
NEW met1 ( 3381710 3626320 ) ( 3381830 * )
NEW met2 ( 3374470 3625805 ) ( 3381570 * )
NEW met1 ( 3374210 3625955 ) ( 3374330 * )
NEW met1 ( 3374210 3626095 ) ( * 4974485 )
NEW met1 ( 3326785 4974625 ) ( 3374210 * )
NEW met1 ( 3326585 4974565 ) via_260_260_hv ( * 4974655 )
( 3326645 * )
NEW met2 ( 3326645 4974795 ) ( * 4982545 )
NEW met1 ( 3326575 4983455 ) ( 3326695 * )
NEW met1 ( 3326575 4982625 ) ( 3326695 * )
NEW met1 ( 3326635 4983040 ) via_260_850_vh
NEW met1 ( 3326630 4983040 ) mcon_170_850
NEW met2 ( 3326525 4974475 ) ( 3326645 * )
NEW met2 ( 3326645 4972915 ) ( * 4974335 )
NEW met2 ( 3374270 3625865 ) via_260_260_vh
NEW met2 ( 3369280 3625805 ) ( 3374070 * )
NEW met1 ( 3374210 3625775 ) ( 3374330 * )
NEW met1 ( 3381710 3625250 ) ( 3381830 * )
NEW met1 ( 3381770 3625785 ) via_260_1090_vh ;
- sky130_fd_sc_hd__buf_8_41/A ( sky130_fd_sc_hd__buf_8_41 A )
( sky130_fd_sc_hd__buf_8_191 X )
+ ROUTED met1 ( 3381775 3631765 ) mcon_170_1090
NEW met1 ( 3381710 3632300 ) ( 3381830 * )
NEW met2 ( 3375590 3631785 ) ( 3381570 * )
NEW met1 ( 3375330 3631935 ) ( 3375450 * )
NEW met1 ( 3375330 3632075 ) ( * 4975605 )
NEW met1 ( 3320805 4975745 ) ( 3375330 * )
NEW met1 ( 3320605 4975685 ) via_260_260_hv ( * 4975775 )
( 3320665 * )
NEW met2 ( 3320665 4975915 ) ( * 4982545 )
NEW met1 ( 3320595 4983455 ) ( 3320715 * )
NEW met1 ( 3320595 4982625 ) ( 3320715 * )
NEW met1 ( 3320655 4983040 ) via_260_850_vh
NEW met1 ( 3320650 4983040 ) mcon_170_850
NEW met2 ( 3320545 4975595 ) ( 3320665 * )
NEW met2 ( 3320665 4972915 ) ( * 4975455 )
NEW met2 ( 3375390 3631845 ) via_260_260_vh
NEW met2 ( 3369280 3631785 ) ( 3375190 * )
NEW met1 ( 3375330 3631755 ) ( 3375450 * )
NEW met1 ( 3381710 3631230 ) ( 3381830 * )
NEW met1 ( 3381770 3631765 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_162/A ( sky130_fd_sc_hd__buf_8_162 A )
( sky130_fd_sc_hd__buf_8_153 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3033725 ) mcon_170_1090
NEW met1 ( 203105 3034260 ) ( 203225 * )
NEW met2 ( 203365 3033540 ) ( 213345 * )
NEW met1 ( 213485 3033690 ) ( 213605 * )
NEW met1 ( 213545 3033600 ) via_260_260_vh
NEW met1 ( 213485 3033510 ) ( 213605 * )
NEW met1 ( 213485 1749790 ) ( * 3033370 )
NEW met1 ( 213365 1749650 ) ( 213485 * )
NEW met1 ( 213425 1749560 ) via_260_260_vh ( * 1749500 )
( 223670 * )
NEW met2 ( 203765 1749500 ) ( 213225 * )
NEW met2 ( 203270 1749495 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1749585 ) ( 203625 * )
NEW met2 ( 202915 1749405 ) ( 203625 * )
NEW met1 ( 213365 1749470 ) ( 213485 * )
NEW met2 ( 213745 3033540 ) ( 221530 * )
NEW met1 ( 203105 3033190 ) ( 203225 * )
NEW met1 ( 203165 3033725 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_174/A ( sky130_fd_sc_hd__buf_8_174 A )
( sky130_fd_sc_hd__buf_8_142 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 2997845 ) mcon_170_1090
NEW met1 ( 203105 2998380 ) ( 203225 * )
NEW met2 ( 203365 2997660 ) ( 220065 * )
NEW met1 ( 220205 2997810 ) ( 220325 * )
NEW met1 ( 220265 2997720 ) via_260_260_vh
NEW met1 ( 220205 2997630 ) ( 220325 * )
NEW met1 ( 220205 1713910 ) ( * 2997490 )
NEW met1 ( 220085 1713770 ) ( 220205 * )
NEW met1 ( 220145 1713680 ) via_260_260_vh ( * 1713620 )
( 223670 * )
NEW met2 ( 203765 1713620 ) ( 219945 * )
NEW met2 ( 203270 1713615 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1713705 ) ( 203625 * )
NEW met2 ( 202915 1713525 ) ( 203625 * )
NEW met1 ( 220085 1713590 ) ( 220205 * )
NEW met2 ( 220465 2997660 ) ( 221530 * )
NEW met1 ( 203105 2997310 ) ( 203225 * )
NEW met1 ( 203165 2997845 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[25] ( sky130_fd_sc_hd__buf_8_131 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 225805 1684010 ) ( * 1768580 )
NEW met1 ( 225685 1683870 ) ( 225805 * )
NEW met1 ( 225745 1683780 ) via_260_260_vh ( * 1683720 )
( 225905 * )
NEW met2 ( 203765 1683720 ) ( 225545 * )
NEW met2 ( 203270 1683715 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1683805 ) ( 203625 * )
NEW met2 ( 202915 1683625 ) ( 203625 * )
NEW met1 ( 225685 1683690 ) ( 225805 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[29] ( sky130_fd_sc_hd__buf_8_120 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3373790 215050 ) ( * 1155370 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2533370 214910 ) ( 3373790 * )
NEW met1 ( 2533370 213530 ) ( * 214770 )
NEW met1 ( 2420050 213390 ) ( 2533370 * )
NEW met1 ( 2420050 213530 ) ( * 223770 )
NEW met1 ( 2253605 223910 ) ( 2420050 * )
NEW met1 ( 2253405 223850 ) via_260_260_hv ( * 223940 )
( 2253465 * )
NEW met2 ( 2253465 224080 ) ( * 232415 )
NEW met2 ( 2253345 223760 ) ( 2253465 * )
NEW met2 ( 2253465 216170 ) ( * 223620 )
NEW met2 ( 2252970 216030 ) ( 2253920 * )
NEW met2 ( 2253445 215940 ) via_1090_260_hv
NEW li1 ( 2252985 215965 ) ( 2253905 * )
NEW li1 ( 2253445 215935 ) mcon_1090_170
NEW met2 ( 2252970 215850 ) ( 2253920 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[20] ( sky130_fd_sc_hd__buf_8_175 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 219785 3055855 ) ( * 3058710 )
NEW met1 ( 219785 3055715 ) ( 220065 * )
NEW met1 ( 220065 3002785 ) ( * 3055575 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 219945 3002645 ) ( 220065 * )
NEW met1 ( 220005 3002555 ) via_260_260_vh ( * 3002495 )
( 221530 * )
NEW met2 ( 206425 3002495 ) ( 219805 * )
NEW met1 ( 206165 3003010 ) ( 206285 * )
NEW met1 ( 206165 3001940 ) ( 206285 * )
NEW met1 ( 206225 3002475 ) via_260_1090_vh
NEW met1 ( 206220 3002475 ) mcon_170_1090
NEW met1 ( 219945 3002465 ) ( 220065 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_187/A ( sky130_fd_sc_hd__buf_8_187 A )
( sky130_fd_sc_hd__buf_8_164 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203035 4433975 ) mcon_170_1090
NEW met1 ( 202980 4434510 ) ( 203100 * )
NEW met2 ( 203240 4433790 ) ( 214605 * )
NEW met1 ( 214745 4433940 ) ( 214865 * )
NEW met1 ( 214805 4433850 ) via_260_260_vh
NEW met1 ( 214745 4433760 ) ( 214865 * )
NEW met1 ( 214745 3031715 ) ( * 4433620 )
NEW met1 ( 214625 3031575 ) ( 214745 * )
NEW met1 ( 214685 3031485 ) via_260_260_vh ( * 3031425 )
( 221530 * )
NEW met2 ( 203655 3031425 ) ( 214485 * )
NEW met2 ( 203160 3031420 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3031510 ) ( 203515 * )
NEW met2 ( 202805 3031330 ) ( 203515 * )
NEW met1 ( 214625 3031395 ) ( 214745 * )
NEW met2 ( 215005 4433790 ) ( 216065 * )
NEW met1 ( 202980 4433440 ) ( 203100 * )
NEW met1 ( 203040 4433975 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[16] ( sky130_fd_sc_hd__buf_8_186 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 215445 4458450 ) ( * 4460515 )
NEW met1 ( 215445 4458310 ) ( 215725 * )
NEW met1 ( 215725 4432935 ) ( * 4458170 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 215605 4432795 ) ( 215725 * )
NEW met1 ( 215665 4432705 ) via_260_260_vh ( * 4432645 )
( 216065 * )
NEW met2 ( 206300 4432645 ) ( 215465 * )
NEW met1 ( 206040 4433160 ) ( 206160 * )
NEW met1 ( 206040 4432090 ) ( 206160 * )
NEW met1 ( 206100 4432625 ) via_260_1090_vh
NEW met1 ( 206095 4432625 ) mcon_170_1090
NEW met1 ( 215605 4432615 ) ( 215725 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[8] ( sky130_fd_sc_hd__buf_8_197 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3306685 4972805 ) ( 3310240 * )
NEW met1 ( 3310240 4972945 ) ( 3310240 * )
NEW met1 ( 3310240 4973085 ) ( 3329320 * ) ( * 4973145 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv ( * 4973235 ) ( 3329380 * )
NEW met2 ( 3329380 4973375 ) ( * 4985605 )
NEW met1 ( 3329325 4986515 ) ( 3329445 * )
NEW met1 ( 3329325 4985685 ) ( 3329445 * )
NEW met1 ( 3329385 4986100 ) via_260_850_vh
NEW met1 ( 3329380 4986100 ) mcon_170_850
NEW met2 ( 3329260 4973055 ) ( 3329380 * )
NEW met2 ( 3329380 4972915 ) ( 3329380 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[3] ( sky130_fd_sc_hd__buf_8_51 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3367770 1183320 ) ( * 2215420 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3367650 2215560 ) ( 3367770 * )
NEW met1 ( 3367710 2215650 ) via_260_260_vh
NEW met1 ( 3367650 2215740 ) ( 3367770 * )
NEW met2 ( 3367910 2215590 ) ( 3381775 * ) ( * 2215600 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2215690 ) ( 3382130 * )
NEW met2 ( 3381420 2215510 ) ( 3382130 * )
NEW met2 ( 3366060 2215590 ) ( 3367510 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[3] ( sky130_fd_sc_hd__buf_8_51 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3367630 2220095 ) ( * 2277205 )
NEW met1 ( 3367630 2219955 ) ( 3367750 * )
NEW met1 ( 3367690 2219865 ) via_260_260_vh ( * 2219805 )
( 3381570 * )
NEW met1 ( 3381710 2220320 ) ( 3381830 * )
NEW met1 ( 3381710 2219250 ) ( 3381830 * )
NEW met1 ( 3381770 2219785 ) via_260_1090_vh
NEW met1 ( 3381775 2219785 ) mcon_170_1090
NEW met2 ( 3366060 2219805 ) ( 3367490 * )
NEW met1 ( 3367630 2219775 ) ( 3367750 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[23] ( sky130_fd_sc_hd__buf_8_95 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3358670 1125100 ) ( * 1128650 )
NEW met1 ( 3358390 1124960 ) ( 3358670 * )
NEW met1 ( 3358390 226530 ) ( * 1124820 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2517970 226390 ) ( 3358390 * )
NEW met1 ( 2517970 221090 ) ( * 226250 )
NEW met1 ( 2435450 220950 ) ( 2517970 * )
NEW met1 ( 2435450 221090 ) ( * 235250 )
NEW met1 ( 2175015 235390 ) ( 2435450 * )
NEW met1 ( 2174815 235330 ) via_260_260_hv ( * 235420 )
( 2174875 * )
NEW met2 ( 2174755 235560 ) ( * 235460 )
NEW met2 ( 2174755 235240 ) ( 2174875 * )
NEW met2 ( 2174755 213370 ) ( * 235100 )
NEW met1 ( 2174690 213290 ) ( 2174810 * )
NEW met1 ( 2174690 212460 ) ( 2174810 * )
NEW met1 ( 2174750 212875 ) via_260_850_vh
NEW met1 ( 2174755 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[29] ( sky130_fd_sc_hd__buf_8_84 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 659685 223630 ) ( 772310 * ) ( * 223690 )
via_260_260_hv ( * 223780 ) ( 772370 * )
NEW met2 ( 772250 223920 ) ( * 232275 )
NEW met2 ( 772250 223600 ) ( 772370 * )
NEW met2 ( 772250 216430 ) ( * 223460 )
NEW met1 ( 772200 216350 ) ( 772320 * )
NEW met1 ( 772200 215520 ) ( 772320 * )
NEW met1 ( 772260 215935 ) via_260_850_vh
NEW met1 ( 772265 215935 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_84/A ( sky130_fd_sc_hd__buf_8_84 A )
( sky130_fd_sc_hd__buf_8_120 X )
+ ROUTED met1 ( 776445 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 775970 216030 ) ( 776920 * )
NEW met2 ( 776465 216170 ) ( * 223480 )
NEW met2 ( 776345 223620 ) ( 776465 * )
NEW met2 ( 776405 223710 ) via_260_260_hv
NEW met2 ( 776345 223800 ) ( 776465 * )
NEW met2 ( 776465 223940 ) ( * 232275 )
NEW met1 ( 776605 223770 ) ( 2249310 * ) ( * 223830 )
via_260_260_hv ( * 223920 ) ( 2249370 * )
NEW met2 ( 2249250 224060 ) ( * 232415 )
NEW met2 ( 2249250 223740 ) ( 2249370 * )
NEW met2 ( 2249250 216430 ) ( * 223600 )
NEW met1 ( 2249200 216350 ) ( 2249320 * )
NEW met1 ( 2249200 215520 ) ( 2249320 * )
NEW met1 ( 2249260 215935 ) via_260_850_vh
NEW met1 ( 2249265 215935 ) mcon_170_850
NEW met2 ( 775970 215850 ) ( 776920 * )
NEW li1 ( 775985 215965 ) ( 776905 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_73/X ( sky130_fd_sc_hd__buf_8_73 X )
( sky130_fd_sc_hd__buf_8_142 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 706485 215935 ) mcon_170_850
NEW met1 ( 706420 216350 ) ( 706540 * )
NEW met2 ( 706470 216430 ) ( * 231580 )
NEW met2 ( 706470 231720 ) ( 706590 * )
NEW met2 ( 706530 231810 ) via_260_260_hv
NEW met2 ( 706470 231900 ) ( 706590 * )
NEW met2 ( 706470 232040 ) ( * 232080 )
NEW met1 ( 702560 231750 ) ( 706330 * )
NEW met1 ( 702560 231890 ) ( * 232730 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 220065 232870 ) ( 702560 * )
NEW met1 ( 220065 233010 ) ( * 1709585 )
NEW met1 ( 220065 1709725 ) ( 220185 * )
NEW met1 ( 220125 1709815 ) via_260_260_vh
NEW met1 ( 220065 1709905 ) ( 220185 * )
NEW met2 ( 220325 1709755 ) ( 223670 * )
NEW met2 ( 203475 1709755 ) ( 219925 * )
NEW met1 ( 203215 1710475 ) ( 203335 * )
NEW met1 ( 203215 1709405 ) ( 203335 * )
NEW met1 ( 203275 1709940 ) via_260_1090_vh
NEW met1 ( 203270 1709940 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 706420 215520 ) ( 706540 * )
NEW met1 ( 706480 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_99/X ( sky130_fd_sc_hd__buf_8_99 X )
( sky130_fd_sc_hd__buf_8_73 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2183485 215935 ) mcon_170_850
NEW met1 ( 2183420 216350 ) ( 2183540 * )
NEW met2 ( 2183470 216430 ) ( * 232840 )
NEW met2 ( 2183470 232980 ) ( 2183590 * )
NEW met2 ( 2183530 233070 ) via_260_260_hv
NEW met2 ( 2183470 233160 ) ( 2183590 * )
NEW met2 ( 2183470 233300 ) ( * 233240 )
NEW met1 ( 783125 233010 ) ( 2183330 * )
NEW met1 ( 783125 232030 ) ( * 232870 )
NEW met1 ( 710945 231890 ) ( 783125 * )
NEW met1 ( 710745 231830 ) via_260_260_hv ( * 231920 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 710805 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 710685 232060 ) ( * 232120 )
NEW met2 ( 710685 231740 ) ( 710805 * )
NEW met2 ( 710685 216170 ) ( * 231600 )
NEW met2 ( 710190 216030 ) ( 711140 * )
NEW met2 ( 710665 215940 ) via_1090_260_hv
NEW li1 ( 710205 215965 ) ( 711125 * )
NEW li1 ( 710665 215935 ) mcon_1090_170
NEW met2 ( 710190 215850 ) ( 711140 * )
NEW met1 ( 2183420 215520 ) ( 2183540 * )
NEW met1 ( 2183480 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_62/X ( sky130_fd_sc_hd__buf_8_62 X )
( sky130_fd_sc_hd__buf_8_109 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 739615 212875 ) mcon_170_850
NEW met1 ( 739550 213290 ) ( 739670 * )
NEW met2 ( 739615 213370 ) ( * 229080 )
NEW met2 ( 739615 229220 ) ( 739735 * )
NEW met2 ( 739675 229310 ) via_260_260_hv
NEW met2 ( 739615 229400 ) ( 739735 * )
NEW met2 ( 739615 229540 ) ( * 232275 )
NEW met1 ( 739875 229370 ) ( 2212810 * ) ( * 229430 )
via_260_260_hv ( * 229520 ) ( 2212870 * )
NEW met2 ( 2212750 229660 ) ( * 232415 )
NEW met2 ( 2212750 229340 ) ( 2212870 * )
NEW met2 ( 2212750 213110 ) ( * 229200 )
NEW met2 ( 2212460 212970 ) ( 2213410 * )
NEW met2 ( 2212935 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2212460 212790 ) ( 2213410 * )
NEW met1 ( 739550 212460 ) ( 739670 * )
NEW met1 ( 739610 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_62/A ( sky130_fd_sc_hd__buf_8_62 A )
( sky130_fd_sc_hd__buf_8_144 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 735935 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 735460 212970 ) ( 736410 * )
NEW met2 ( 735750 213110 ) ( * 229060 )
NEW met2 ( 735750 229200 ) ( 735870 * )
NEW met2 ( 735810 229290 ) via_260_260_hv
NEW met2 ( 735750 229380 ) ( 735870 * )
NEW met2 ( 735750 229520 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 215305 229230 ) ( 735610 * )
NEW met1 ( 215305 229370 ) ( * 1734125 )
NEW met1 ( 215305 1734265 ) ( 215425 * )
NEW met1 ( 215365 1734355 ) via_260_260_vh
NEW met1 ( 215305 1734445 ) ( 215425 * )
NEW met2 ( 215565 1734295 ) ( 223670 * )
NEW met2 ( 206825 1734295 ) ( 215165 * )
NEW met2 ( 206330 1734305 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1734395 ) ( 206685 * )
NEW met2 ( 205975 1734215 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 735460 212790 ) ( 736410 * ) ;
- sky130_fd_sc_hd__buf_8_40/X ( sky130_fd_sc_hd__buf_8_40 X )
( sky130_fd_sc_hd__buf_8_195 A )
+ ROUTED met1 ( 3384835 3630815 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3384480 3630900 ) ( 3385190 * )
NEW met2 ( 3384480 3630720 ) ( 3385190 * )
NEW met2 ( 3375310 3630815 ) ( 3384340 * )
NEW met1 ( 3375050 3630965 ) ( 3375170 * )
NEW met1 ( 3375050 3631105 ) ( * 4975325 )
NEW met1 ( 3321425 4975465 ) ( 3375050 * )
NEW met1 ( 3321225 4975405 ) via_260_260_hv ( * 4975495 )
( 3321285 * )
NEW met2 ( 3321285 4975635 ) ( * 4985865 )
NEW met2 ( 3320625 4986005 ) ( 3321575 * )
NEW met2 ( 3321100 4986095 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 3320625 4986185 ) ( 3321575 * )
NEW met2 ( 3321165 4975315 ) ( 3321285 * )
NEW met2 ( 3321285 4972915 ) ( * 4975175 )
NEW met2 ( 3375110 3630875 ) via_260_260_vh
NEW met2 ( 3369280 3630815 ) ( 3374910 * )
NEW met1 ( 3375050 3630785 ) ( 3375170 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[20] ( sky130_fd_sc_hd__buf_8_174 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 220345 3001815 ) ( * 3057710 )
NEW met1 ( 220225 3001675 ) ( 220345 * )
NEW met1 ( 220285 3001585 ) via_260_260_vh ( * 3001525 )
( 221530 * )
NEW met2 ( 203655 3001525 ) ( 220085 * )
NEW met2 ( 203160 3001520 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3001610 ) ( 203515 * )
NEW met2 ( 202805 3001430 ) ( 203515 * )
NEW met1 ( 220225 3001495 ) ( 220345 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[16] ( sky130_fd_sc_hd__buf_8_185 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 216005 4431965 ) ( * 4459515 )
NEW met1 ( 215885 4431825 ) ( 216005 * )
NEW met1 ( 215945 4431735 ) via_260_260_vh ( * 4431675 )
( 216065 * )
NEW met2 ( 203530 4431675 ) ( 215745 * )
NEW met2 ( 203035 4431670 ) via_850_260_hv mcon_850_170
NEW met2 ( 202680 4431760 ) ( 203390 * )
NEW met2 ( 202680 4431580 ) ( 203390 * )
NEW met1 ( 215885 4431645 ) ( 216005 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[9] ( sky130_fd_sc_hd__buf_8_196 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3304685 4973925 ) ( 3308420 * )
NEW met1 ( 3308420 4974065 ) ( 3308420 * )
NEW met1 ( 3308420 4974205 ) ( 3323340 * ) ( * 4974265 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv ( * 4974355 ) ( 3323400 * )
NEW met2 ( 3323400 4974495 ) ( * 4985605 )
NEW met1 ( 3323345 4986515 ) ( 3323465 * )
NEW met1 ( 3323345 4985685 ) ( 3323465 * )
NEW met1 ( 3323405 4986100 ) via_260_850_vh
NEW met1 ( 3323400 4986100 ) mcon_170_850
NEW met2 ( 3323280 4974175 ) ( 3323400 * )
NEW met2 ( 3323400 4972915 ) ( * 4974035 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_163/X ( sky130_fd_sc_hd__buf_8_163 X )
( sky130_fd_sc_hd__buf_8_152 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 3034175 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3034260 ) ( 206575 * )
NEW met2 ( 206715 3034160 ) ( 213065 * )
NEW met1 ( 213205 3034310 ) ( 213325 * )
NEW met1 ( 213265 3034220 ) via_260_260_vh
NEW met1 ( 213205 3034130 ) ( 213325 * )
NEW met1 ( 213205 1750760 ) ( * 3033990 )
NEW met1 ( 213085 1750620 ) ( 213205 * )
NEW met1 ( 213145 1750530 ) via_260_260_vh ( * 1750470 )
( 223670 * )
NEW met2 ( 206535 1750470 ) ( 212945 * )
NEW met1 ( 206275 1750985 ) ( 206395 * )
NEW met1 ( 206275 1749915 ) ( 206395 * )
NEW met1 ( 206335 1750450 ) via_260_1090_vh
NEW met1 ( 206330 1750450 ) mcon_170_1090
NEW met1 ( 213085 1750440 ) ( 213205 * )
NEW met2 ( 213465 3034160 ) ( 221530 * )
NEW met2 ( 205865 3034080 ) ( 206575 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_172/X ( sky130_fd_sc_hd__buf_8_172 X )
( sky130_fd_sc_hd__buf_8_141 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206220 3004275 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3004360 ) ( 206575 * )
NEW met2 ( 206715 3004260 ) ( 218665 * )
NEW met1 ( 218805 3004410 ) ( 218925 * )
NEW met1 ( 218865 3004320 ) via_260_260_vh
NEW met1 ( 218805 3004230 ) ( 218925 * )
NEW met1 ( 218805 1720860 ) ( * 3004090 )
NEW met1 ( 218685 1720720 ) ( 218805 * )
NEW met1 ( 218745 1720630 ) via_260_260_vh ( * 1720570 )
( 223670 * )
NEW met2 ( 206535 1720570 ) ( 218545 * )
NEW met1 ( 206275 1721085 ) ( 206395 * )
NEW met1 ( 206275 1720015 ) ( 206395 * )
NEW met1 ( 206335 1720550 ) via_260_1090_vh
NEW met1 ( 206330 1720550 ) mcon_170_1090
NEW met1 ( 218685 1720540 ) ( 218805 * )
NEW met2 ( 219065 3004260 ) ( 221530 * )
NEW met2 ( 205865 3004180 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[25] ( sky130_fd_sc_hd__buf_8_130 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 225245 1766985 ) ( * 1769580 )
NEW met1 ( 225245 1766845 ) ( 225525 * )
NEW met1 ( 225525 1684860 ) ( * 1766705 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 225405 1684720 ) ( 225525 * )
NEW met1 ( 225465 1684630 ) via_260_260_vh
NEW met2 ( 206535 1684690 ) ( 225265 * )
NEW met1 ( 206275 1685205 ) ( 206395 * )
NEW met1 ( 206275 1684135 ) ( 206395 * )
NEW met1 ( 206335 1684670 ) via_260_1090_vh
NEW met1 ( 206330 1684670 ) mcon_170_1090
NEW met2 ( 225665 1684690 ) ( 225905 * )
NEW met1 ( 225405 1684540 ) ( 225525 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_189/X ( sky130_fd_sc_hd__buf_8_189 X )
( sky130_fd_sc_hd__buf_8_163 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206095 4440405 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205740 4440490 ) ( 206450 * )
NEW met2 ( 206590 4440390 ) ( 213205 * )
NEW met1 ( 213345 4440540 ) ( 213465 * )
NEW met1 ( 213405 4440450 ) via_260_260_vh
NEW met1 ( 213345 4440360 ) ( 213465 * )
NEW met1 ( 213345 3038665 ) ( * 4440220 )
NEW met1 ( 213225 3038525 ) ( 213345 * )
NEW met1 ( 213285 3038435 ) via_260_260_vh ( * 3038375 )
( 221530 * )
NEW met2 ( 206425 3038375 ) ( 213085 * )
NEW met1 ( 206165 3038890 ) ( 206285 * )
NEW met1 ( 206165 3037820 ) ( 206285 * )
NEW met1 ( 206225 3038355 ) via_260_1090_vh
NEW met1 ( 206220 3038355 ) mcon_170_1090
NEW met1 ( 213225 3038345 ) ( 213345 * )
NEW met2 ( 213605 4440390 ) ( 216065 * )
NEW met2 ( 205740 4440310 ) ( 206450 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[3] ( sky130_fd_sc_hd__buf_8_50 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3367070 2273180 ) ( * 2276205 )
NEW met1 ( 3367070 2273040 ) ( 3367350 * )
NEW met1 ( 3367350 2219125 ) ( * 2272900 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3367350 2218985 ) ( 3367470 * )
NEW met1 ( 3367410 2218895 ) via_260_260_vh ( * 2218835 )
( 3384835 * ) ( * 2218830 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2218920 ) ( 3385190 * )
NEW met2 ( 3384480 2218740 ) ( 3385190 * )
NEW met2 ( 3366060 2218835 ) ( 3367210 * )
NEW met1 ( 3367350 2218805 ) ( 3367470 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[3] ( sky130_fd_sc_hd__buf_8_50 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3367210 1184320 ) ( * 1188030 )
NEW met1 ( 3367210 1188170 ) ( 3367490 * )
NEW met1 ( 3367490 1188310 ) ( * 2214800 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3367370 2214940 ) ( 3367490 * )
NEW met1 ( 3367430 2215030 ) via_260_260_vh
NEW met1 ( 3367370 2215120 ) ( 3367490 * )
NEW met2 ( 3367630 2214970 ) ( 3384630 * )
NEW met1 ( 3384770 2215690 ) ( 3384890 * )
NEW met1 ( 3384770 2214620 ) ( 3384890 * )
NEW met1 ( 3384830 2215155 ) via_260_1090_vh
NEW met1 ( 3384835 2215155 ) mcon_170_1090
NEW met2 ( 3366060 2214970 ) ( 3367230 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[22] ( sky130_fd_sc_hd__buf_8_94 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3359230 225970 ) ( * 1129610 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2518810 225830 ) ( 3359230 * )
NEW met1 ( 2518810 220810 ) ( * 225690 )
NEW met1 ( 2434610 220670 ) ( 2518810 * )
NEW met1 ( 2434610 220810 ) ( * 234690 )
NEW met1 ( 2175985 234830 ) ( 2434610 * )
NEW met1 ( 2175785 234770 ) via_260_260_hv ( * 234860 )
( 2175845 * )
NEW met2 ( 2175725 235000 ) ( * 234940 )
NEW met2 ( 2175725 234680 ) ( 2175845 * )
NEW met2 ( 2175725 216170 ) ( * 234540 )
NEW met2 ( 2175230 216030 ) ( 2176180 * )
NEW met2 ( 2175705 215940 ) via_1090_260_hv
NEW li1 ( 2175245 215965 ) ( 2176165 * )
NEW li1 ( 2175705 215935 ) mcon_1090_170
NEW met2 ( 2175230 215850 ) ( 2176180 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_83/X ( sky130_fd_sc_hd__buf_8_83 X )
( sky130_fd_sc_hd__buf_8_131 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 676585 215935 ) mcon_170_850
NEW met1 ( 676520 216350 ) ( 676640 * )
NEW met2 ( 676570 216430 ) ( * 236900 )
NEW met2 ( 676570 237040 ) ( 676690 * )
NEW met2 ( 676630 237130 ) via_260_260_hv
NEW met2 ( 676570 237220 ) ( 676690 * )
NEW met2 ( 676570 237360 ) ( * 237330 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 225665 237070 ) ( 676430 * )
NEW met1 ( 225665 237210 ) ( * 1679685 )
NEW met1 ( 225665 1679825 ) ( 225785 * )
NEW met1 ( 225725 1679915 ) via_260_260_vh
NEW met1 ( 225665 1680005 ) ( 225785 * )
NEW met2 ( 225925 1679855 ) ( 225960 * )
NEW met2 ( 203475 1679855 ) ( 225525 * )
NEW met1 ( 203215 1680575 ) ( 203335 * )
NEW met1 ( 203215 1679505 ) ( 203335 * )
NEW met1 ( 203275 1680040 ) via_260_1090_vh
NEW met1 ( 203270 1680040 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 676520 215520 ) ( 676640 * )
NEW met1 ( 676580 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_88/X ( sky130_fd_sc_hd__buf_8_88 X )
( sky130_fd_sc_hd__buf_8_83 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2153585 215935 ) mcon_170_850
NEW met1 ( 2153520 216350 ) ( 2153640 * )
NEW met2 ( 2153570 216430 ) ( * 237040 )
NEW met2 ( 2153570 237180 ) ( 2153690 * )
NEW met2 ( 2153630 237270 ) via_260_260_hv
NEW met2 ( 2153570 237360 ) ( 2153690 * )
NEW met2 ( 2153570 237500 ) ( * 237455 )
NEW met1 ( 778925 237210 ) ( 2153430 * )
NEW met1 ( 778925 234830 ) ( * 237070 )
NEW met1 ( 705435 234690 ) ( 778925 * )
NEW met1 ( 705435 234830 ) ( * 237070 )
NEW met1 ( 681045 237210 ) ( 705435 * )
NEW met1 ( 680845 237150 ) via_260_260_hv ( * 237240 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 680905 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 680785 237380 ) ( * 237330 )
NEW met2 ( 680785 237060 ) ( 680905 * )
NEW met2 ( 680785 216170 ) ( * 236920 )
NEW met2 ( 680290 216030 ) ( 681240 * )
NEW met2 ( 680765 215940 ) via_1090_260_hv
NEW li1 ( 680305 215965 ) ( 681225 * )
NEW li1 ( 680765 215935 ) mcon_1090_170
NEW met2 ( 680290 215850 ) ( 681240 * )
NEW met1 ( 2153520 215520 ) ( 2153640 * )
NEW met1 ( 2153580 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_97/A ( sky130_fd_sc_hd__buf_8_97 A )
( sky130_fd_sc_hd__buf_8_72 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2183035 212875 ) mcon_1090_170
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2182560 212970 ) ( 2183510 * )
NEW met2 ( 2182850 213110 ) ( * 233400 )
NEW met2 ( 2182850 233540 ) ( 2182970 * )
NEW met2 ( 2182910 233630 ) via_260_260_hv
NEW met2 ( 2182850 233720 ) ( 2182970 * )
NEW met2 ( 2182850 233860 ) ( * 233775 )
NEW met1 ( 782565 233570 ) ( 2182710 * )
NEW met1 ( 782565 232310 ) ( * 233430 )
NEW met1 ( 709975 232170 ) ( 782565 * )
NEW met1 ( 709775 232110 ) via_260_260_hv ( * 232200 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 709835 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 709715 232340 ) ( * 232240 )
NEW met2 ( 709715 232020 ) ( 709835 * )
NEW met2 ( 709715 213370 ) ( * 231880 )
NEW met1 ( 709650 213290 ) ( 709770 * )
NEW met1 ( 709650 212460 ) ( 709770 * )
NEW met1 ( 709710 212875 ) via_260_850_vh
NEW met1 ( 709715 212875 ) mcon_170_850
NEW met2 ( 2182560 212790 ) ( 2183510 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_72/A ( sky130_fd_sc_hd__buf_8_72 A )
( sky130_fd_sc_hd__buf_8_134 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 706035 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 705560 212970 ) ( 706510 * )
NEW met2 ( 705850 213110 ) ( * 231860 )
NEW met2 ( 705850 232000 ) ( 705970 * )
NEW met2 ( 705910 232090 ) via_260_260_hv
NEW met2 ( 705850 232180 ) ( 705970 * )
NEW met2 ( 705850 232320 ) ( * 232245 )
NEW met1 ( 702855 232030 ) ( 705710 * )
NEW met1 ( 702855 232170 ) ( * 233290 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 220905 233430 ) ( 702855 * )
NEW met1 ( 220905 233570 ) ( * 1704225 )
NEW met1 ( 220905 1704365 ) ( 221025 * )
NEW met1 ( 220965 1704455 ) via_260_260_vh
NEW met1 ( 220905 1704545 ) ( 221025 * )
NEW met2 ( 221165 1704395 ) ( 223670 * )
NEW met2 ( 206825 1704395 ) ( 220765 * )
NEW met2 ( 206330 1704405 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1704495 ) ( 206685 * )
NEW met2 ( 205975 1704315 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 705560 212790 ) ( 706510 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_61/X ( sky130_fd_sc_hd__buf_8_61 X )
( sky130_fd_sc_hd__buf_8_153 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 742365 215935 ) mcon_170_850
NEW met1 ( 742300 216350 ) ( 742420 * )
NEW met2 ( 742350 216430 ) ( * 227660 )
NEW met2 ( 742350 227800 ) ( 742470 * )
NEW met2 ( 742410 227890 ) via_260_260_hv
NEW met2 ( 742350 227980 ) ( 742470 * )
NEW met2 ( 742350 228120 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 213345 227830 ) ( 742210 * )
NEW met1 ( 213345 227970 ) ( * 1745465 )
NEW met1 ( 213345 1745605 ) ( 213465 * )
NEW met1 ( 213405 1745695 ) via_260_260_vh
NEW met1 ( 213345 1745785 ) ( 213465 * )
NEW met2 ( 213605 1745635 ) ( 223670 * )
NEW met2 ( 203475 1745635 ) ( 213205 * )
NEW met1 ( 203215 1746355 ) ( 203335 * )
NEW met1 ( 203215 1745285 ) ( 203335 * )
NEW met1 ( 203275 1745820 ) via_260_1090_vh
NEW met1 ( 203270 1745820 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 742300 215520 ) ( 742420 * )
NEW met1 ( 742360 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_61/A ( sky130_fd_sc_hd__buf_8_61 A )
( sky130_fd_sc_hd__buf_8_111 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 746545 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 746070 216030 ) ( 747020 * )
NEW met2 ( 746565 216170 ) ( * 227680 )
NEW met2 ( 746565 227820 ) ( 746685 * )
NEW met2 ( 746625 227910 ) via_260_260_hv
NEW met2 ( 746565 228000 ) ( 746685 * )
NEW met2 ( 746565 228140 ) ( * 232275 )
NEW met1 ( 746825 227970 ) ( 2219410 * ) ( * 228030 )
via_260_260_hv ( * 228120 ) ( 2219470 * )
NEW met2 ( 2219350 228260 ) ( * 232415 )
NEW met2 ( 2219350 227940 ) ( 2219470 * )
NEW met2 ( 2219350 216430 ) ( * 227800 )
NEW met1 ( 2219300 216350 ) ( 2219420 * )
NEW met1 ( 2219300 215520 ) ( 2219420 * )
NEW met1 ( 2219360 215935 ) via_260_850_vh
NEW met1 ( 2219365 215935 ) mcon_170_850
NEW met2 ( 746070 215850 ) ( 747020 * )
NEW li1 ( 746085 215965 ) ( 747005 * ) ;
- sky130_fd_sc_hd__buf_8_160/A ( sky130_fd_sc_hd__buf_8_160 A )
( sky130_fd_sc_hd__buf_8_151 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3039705 ) mcon_170_1090
NEW met1 ( 203105 3040240 ) ( 203225 * )
NEW met2 ( 203365 3039520 ) ( 212225 * )
NEW met1 ( 212365 3039670 ) ( 212485 * )
NEW met1 ( 212425 3039580 ) via_260_260_vh
NEW met1 ( 212365 3039490 ) ( 212485 * )
NEW met1 ( 212365 1755770 ) ( * 3039350 )
NEW met1 ( 212245 1755630 ) ( 212365 * )
NEW met1 ( 212305 1755540 ) via_260_260_vh ( * 1755480 )
( 223670 * )
NEW met2 ( 203765 1755480 ) ( 212105 * )
NEW met2 ( 203270 1755475 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1755565 ) ( 203625 * )
NEW met2 ( 202915 1755385 ) ( 203625 * )
NEW met1 ( 212245 1755450 ) ( 212365 * )
NEW met2 ( 212625 3039520 ) ( 221530 * )
NEW met1 ( 203105 3039170 ) ( 203225 * )
NEW met1 ( 203165 3039705 ) via_260_1090_vh ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_173/A ( sky130_fd_sc_hd__buf_8_173 A )
( sky130_fd_sc_hd__buf_8_140 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203160 3003825 ) mcon_170_1090
NEW met1 ( 203105 3004360 ) ( 203225 * )
NEW met2 ( 203365 3003640 ) ( 218945 * )
NEW met1 ( 219085 3003790 ) ( 219205 * )
NEW met1 ( 219145 3003700 ) via_260_260_vh
NEW met1 ( 219085 3003610 ) ( 219205 * )
NEW met1 ( 219085 1719890 ) ( * 3003470 )
NEW met1 ( 218965 1719750 ) ( 219085 * )
NEW met1 ( 219025 1719660 ) via_260_260_vh ( * 1719600 )
( 223670 * )
NEW met2 ( 203765 1719600 ) ( 218825 * )
NEW met2 ( 203270 1719595 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1719685 ) ( 203625 * )
NEW met2 ( 202915 1719505 ) ( 203625 * )
NEW met1 ( 218965 1719570 ) ( 219085 * )
NEW met2 ( 219345 3003640 ) ( 221530 * )
NEW met1 ( 203105 3003290 ) ( 203225 * )
NEW met1 ( 203165 3003825 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[19] ( sky130_fd_sc_hd__buf_8_173 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 219225 3007795 ) ( * 3059710 )
NEW met1 ( 219105 3007655 ) ( 219225 * )
NEW met1 ( 219165 3007565 ) via_260_260_vh ( * 3007505 )
( 221530 * )
NEW met2 ( 203655 3007505 ) ( 218965 * )
NEW met2 ( 203160 3007500 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3007590 ) ( 203515 * )
NEW met2 ( 202805 3007410 ) ( 203515 * )
NEW met1 ( 219105 3007475 ) ( 219225 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_190/A ( sky130_fd_sc_hd__buf_8_190 A )
( sky130_fd_sc_hd__buf_8_162 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203035 4439955 ) mcon_170_1090
NEW met1 ( 202980 4440490 ) ( 203100 * )
NEW met2 ( 203240 4439770 ) ( 213485 * )
NEW met1 ( 213625 4439920 ) ( 213745 * )
NEW met1 ( 213685 4439830 ) via_260_260_vh
NEW met1 ( 213625 4439740 ) ( 213745 * )
NEW met1 ( 213625 3037695 ) ( * 4439600 )
NEW met1 ( 213505 3037555 ) ( 213625 * )
NEW met1 ( 213565 3037465 ) via_260_260_vh ( * 3037405 )
( 221530 * )
NEW met2 ( 203655 3037405 ) ( 213365 * )
NEW met2 ( 203160 3037400 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3037490 ) ( 203515 * )
NEW met2 ( 202805 3037310 ) ( 203515 * )
NEW met1 ( 213505 3037375 ) ( 213625 * )
NEW met2 ( 213885 4439770 ) ( 216065 * )
NEW met1 ( 202980 4439420 ) ( 203100 * )
NEW met1 ( 203040 4439955 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_43/A ( sky130_fd_sc_hd__buf_8_43 A )
( sky130_fd_sc_hd__buf_8_184 X )
+ ROUTED met1 ( 847765 4984885 ) mcon_1090_170
via_1090_260_hv
NEW met2 ( 847290 4984970 ) ( 848240 * )
NEW met2 ( 847290 4984790 ) ( 848240 * )
NEW met2 ( 847580 4977105 ) ( * 4984650 )
NEW met2 ( 847580 4976965 ) ( 847700 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 211525 4976935 ) ( 847640 * ) ( * 4976875 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_260_260_hv
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 211525 4455885 ) ( * 4976795 )
NEW met1 ( 211405 4455745 ) ( 211525 * )
NEW met1 ( 211465 4455655 ) via_260_260_vh ( * 4455595 )
( 216065 * )
NEW met2 ( 203530 4455595 ) ( 211265 * )
NEW met2 ( 203035 4455590 ) via_850_260_hv mcon_850_170
NEW met2 ( 202680 4455680 ) ( 203390 * )
NEW met2 ( 202680 4455500 ) ( 203390 * )
NEW met1 ( 211405 4455565 ) ( 211525 * )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met2 ( 847580 4976785 ) ( 847700 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 847580 4975345 ) ( * 4976645 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[10] ( sky130_fd_sc_hd__buf_8_195 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3302685 4975045 ) ( 3306190 * )
NEW met1 ( 3306190 4975185 ) ( 3306190 * )
NEW met1 ( 3306190 4975325 ) ( 3317360 * ) ( * 4975385 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv ( * 4975475 ) ( 3317420 * )
NEW met2 ( 3317420 4975615 ) ( * 4985605 )
NEW met1 ( 3317365 4986515 ) ( 3317485 * )
NEW met1 ( 3317365 4985685 ) ( 3317485 * )
NEW met1 ( 3317425 4986100 ) via_260_850_vh
NEW met1 ( 3317420 4986100 ) mcon_170_850
NEW met2 ( 3317300 4975295 ) ( 3317420 * )
NEW met2 ( 3317420 4972915 ) ( * 4975155 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[24] ( sky130_fd_sc_hd__buf_8_93 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3357550 1123220 ) ( * 1126670 )
NEW met1 ( 3357270 1123080 ) ( 3357550 * )
NEW met1 ( 3357270 227370 ) ( * 1122940 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2516850 227230 ) ( 3357270 * )
NEW met1 ( 2516850 221650 ) ( * 227090 )
NEW met1 ( 2436570 221510 ) ( 2516850 * )
NEW met1 ( 2436570 221650 ) ( * 236090 )
NEW met1 ( 2169035 236230 ) ( 2436570 * )
NEW met1 ( 2168835 236170 ) via_260_260_hv ( * 236260 )
( 2168895 * )
NEW met2 ( 2168775 236400 ) ( * 236330 )
NEW met2 ( 2168775 236080 ) ( 2168895 * )
NEW met2 ( 2168775 213370 ) ( * 235940 )
NEW met1 ( 2168710 213290 ) ( 2168830 * )
NEW met1 ( 2168710 212460 ) ( 2168830 * )
NEW met1 ( 2168770 212875 ) via_260_850_vh
NEW met1 ( 2168775 212875 ) mcon_170_850 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_89/A ( sky130_fd_sc_hd__buf_8_89 A )
( sky130_fd_sc_hd__buf_8_82 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2153135 212875 ) mcon_1090_170
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2152660 212970 ) ( 2153610 * )
NEW met2 ( 2152950 213110 ) ( * 237600 )
NEW met2 ( 2152950 237740 ) ( 2153070 * )
NEW met2 ( 2153010 237830 ) via_260_260_hv
NEW met2 ( 2152950 237920 ) ( 2153070 * )
NEW met2 ( 2152950 238060 ) ( * 237980 )
NEW met1 ( 778365 237770 ) ( 2152810 * )
NEW met1 ( 778365 235110 ) ( * 237630 )
NEW met1 ( 705995 234970 ) ( 778365 * )
NEW met1 ( 705995 235110 ) ( * 237630 )
NEW met1 ( 680075 237770 ) ( 705995 * )
NEW met1 ( 679875 237710 ) via_260_260_hv ( * 237800 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 679935 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 679815 237940 ) ( * 237855 )
NEW met2 ( 679815 237620 ) ( 679935 * )
NEW met2 ( 679815 213370 ) ( * 237480 )
NEW met1 ( 679750 213290 ) ( 679870 * )
NEW met1 ( 679750 212460 ) ( 679870 * )
NEW met1 ( 679810 212875 ) via_260_850_vh
NEW met1 ( 679815 212875 ) mcon_170_850
NEW met2 ( 2152660 212790 ) ( 2153610 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_82/A ( sky130_fd_sc_hd__buf_8_82 A )
( sky130_fd_sc_hd__buf_8_128 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 676135 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 675660 212970 ) ( 676610 * )
NEW met2 ( 675950 213110 ) ( * 237460 )
NEW met2 ( 675950 237600 ) ( 676070 * )
NEW met2 ( 676010 237690 ) via_260_260_hv
NEW met2 ( 675950 237780 ) ( 676070 * )
NEW met2 ( 675950 237920 ) ( * 237830 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 226505 237630 ) ( 675810 * )
NEW met1 ( 226505 237770 ) ( * 1674325 )
NEW met1 ( 226505 1674465 ) ( 226625 * )
NEW met1 ( 226565 1674555 ) via_260_260_vh
NEW met1 ( 226505 1674645 ) ( 226625 * )
NEW met2 ( 226765 1674495 ) ( 227030 * )
NEW met2 ( 206825 1674495 ) ( 226365 * )
NEW met2 ( 206330 1674505 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1674595 ) ( 206685 * )
NEW met2 ( 205975 1674415 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 675660 212790 ) ( 676610 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_71/X ( sky130_fd_sc_hd__buf_8_71 X )
( sky130_fd_sc_hd__buf_8_140 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 712465 215935 ) mcon_170_850
NEW met1 ( 712400 216350 ) ( 712520 * )
NEW met2 ( 712450 216430 ) ( * 231020 )
NEW met2 ( 712450 231160 ) ( 712570 * )
NEW met2 ( 712510 231250 ) via_260_260_hv
NEW met2 ( 712450 231340 ) ( 712570 * )
NEW met2 ( 712450 231480 ) ( * 231435 )
NEW met1 ( 701945 231190 ) ( 712310 * )
NEW met1 ( 701945 231330 ) ( * 231890 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 218945 232030 ) ( 701945 * )
NEW met1 ( 218945 232170 ) ( * 1715565 )
NEW met1 ( 218945 1715705 ) ( 219065 * )
NEW met1 ( 219005 1715795 ) via_260_260_vh
NEW met1 ( 218945 1715885 ) ( 219065 * )
NEW met2 ( 219205 1715735 ) ( 223670 * )
NEW met2 ( 202915 1715735 ) ( 218805 * )
NEW met1 ( 203215 1716455 ) ( 203335 * )
NEW met1 ( 203425 1715735 ) ( 203335 * )
NEW met1 ( 203215 1715385 ) ( 203335 * )
NEW met1 ( 203275 1715520 ) via_260_290_vh
NEW met1 ( 203215 1715735 ) ( 203115 * )
NEW met1 ( 203275 1716135 ) via_260_660_vh
NEW met1 ( 203270 1715920 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 712400 215520 ) ( 712520 * )
NEW met1 ( 712460 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_71/A ( sky130_fd_sc_hd__buf_8_71 A )
( sky130_fd_sc_hd__buf_8_103 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 716645 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 716170 216030 ) ( 717120 * )
NEW met2 ( 716665 216170 ) ( * 231040 )
NEW met2 ( 716545 231180 ) ( 716665 * )
NEW met2 ( 716605 231270 ) via_260_260_hv
NEW met2 ( 716545 231360 ) ( 716665 * )
NEW met2 ( 716665 231500 ) ( * 231455 )
NEW met1 ( 716805 231330 ) ( 783965 * )
NEW met1 ( 783965 231470 ) ( * 232030 )
NEW met1 ( 783965 232170 ) ( 2189510 * ) ( * 232230 )
via_260_260_hv ( * 232320 ) ( 2189570 * )
NEW met2 ( 2189450 232460 ) ( * 232415 )
NEW met2 ( 2189450 232140 ) ( 2189570 * )
NEW met2 ( 2189450 216430 ) ( * 232000 )
NEW met1 ( 2189400 216350 ) ( 2189520 * )
NEW met1 ( 2189400 215520 ) ( 2189520 * )
NEW met1 ( 2189460 215935 ) via_260_850_vh
NEW met1 ( 2189465 215935 ) mcon_170_850
NEW met2 ( 716170 215850 ) ( 717120 * )
NEW li1 ( 716185 215965 ) ( 717105 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_60/X ( sky130_fd_sc_hd__buf_8_60 X )
( sky130_fd_sc_hd__buf_8_110 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 745595 212875 ) mcon_170_850
NEW met1 ( 745530 213290 ) ( 745650 * )
NEW met2 ( 745595 213370 ) ( * 228240 )
NEW met2 ( 745595 228380 ) ( 745715 * )
NEW met2 ( 745655 228470 ) via_260_260_hv
NEW met2 ( 745595 228560 ) ( 745715 * )
NEW met2 ( 745595 228700 ) ( * 232275 )
NEW met1 ( 745855 228530 ) ( 2218790 * ) ( * 228590 )
via_260_260_hv ( * 228680 ) ( 2218850 * )
NEW met2 ( 2218730 228820 ) ( * 232415 )
NEW met2 ( 2218730 228500 ) ( 2218850 * )
NEW met2 ( 2218730 213110 ) ( * 228360 )
NEW met2 ( 2218440 212970 ) ( 2219390 * )
NEW met2 ( 2218915 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2218440 212790 ) ( 2219390 * )
NEW met1 ( 745530 212460 ) ( 745650 * )
NEW met1 ( 745590 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_60/A ( sky130_fd_sc_hd__buf_8_60 A )
( sky130_fd_sc_hd__buf_8_155 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 741915 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 741440 212970 ) ( 742390 * )
NEW met2 ( 741730 213110 ) ( * 228220 )
NEW met2 ( 741730 228360 ) ( 741850 * )
NEW met2 ( 741790 228450 ) via_260_260_hv
NEW met2 ( 741730 228540 ) ( 741850 * )
NEW met2 ( 741730 228680 ) ( * 232275 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 214185 228390 ) ( 741590 * )
NEW met1 ( 214185 228530 ) ( * 1740105 )
NEW met1 ( 214185 1740245 ) ( 214305 * )
NEW met1 ( 214245 1740335 ) via_260_260_vh
NEW met1 ( 214185 1740425 ) ( 214305 * )
NEW met2 ( 214445 1740275 ) ( 223670 * )
NEW met2 ( 206825 1740275 ) ( 214045 * )
NEW met2 ( 206330 1740285 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1740375 ) ( 206685 * )
NEW met2 ( 205975 1740195 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 741440 212790 ) ( 742390 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[19] ( sky130_fd_sc_hd__buf_8_172 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 218665 3057740 ) ( * 3060710 )
NEW met1 ( 218665 3057600 ) ( 218945 * )
NEW met1 ( 218945 3008765 ) ( * 3057460 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 218825 3008625 ) ( 218945 * )
NEW met1 ( 218885 3008535 ) via_260_260_vh ( * 3008475 )
( 221530 * )
NEW met2 ( 206425 3008475 ) ( 218685 * )
NEW met1 ( 206165 3008990 ) ( 206285 * )
NEW met1 ( 206165 3007920 ) ( 206285 * )
NEW met1 ( 206225 3008455 ) via_260_1090_vh
NEW met1 ( 206220 3008455 ) mcon_170_1090
NEW met1 ( 218825 3008445 ) ( 218945 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_181/X ( sky130_fd_sc_hd__buf_8_181 X )
( sky130_fd_sc_hd__buf_8_161 A )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 206095 4446385 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205740 4446470 ) ( 206450 * )
NEW met2 ( 206590 4446370 ) ( 212085 * )
NEW met1 ( 212225 4446520 ) ( 212345 * )
NEW met1 ( 212285 4446430 ) via_260_260_vh
NEW met1 ( 212225 4446340 ) ( 212345 * )
NEW met1 ( 212225 3044525 ) ( * 4446200 )
NEW met1 ( 212105 3044385 ) ( 212225 * )
NEW met1 ( 212165 3044295 ) via_260_260_vh
NEW met2 ( 206425 3044355 ) ( 211965 * )
NEW met1 ( 206165 3044870 ) ( 206285 * )
NEW met1 ( 206165 3043800 ) ( 206285 * )
NEW met1 ( 206225 3044335 ) via_260_1090_vh
NEW met1 ( 206220 3044335 ) mcon_170_1090
NEW met2 ( 212365 3044355 ) ( 221530 * )
NEW met1 ( 212105 3044205 ) ( 212225 * )
NEW met2 ( 212485 4446370 ) ( 216065 * )
NEW met2 ( 205740 4446290 ) ( 206450 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_42/X ( sky130_fd_sc_hd__buf_8_42 X )
( sky130_fd_sc_hd__buf_8_183 A )
+ ROUTED met1 ( 848215 4981825 ) mcon_170_850
NEW met1 ( 848150 4982240 ) ( 848270 * )
NEW met2 ( 848200 4977385 ) ( * 4981330 )
NEW met2 ( 848200 4977245 ) ( 848320 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 211245 4977215 ) ( 848260 * ) ( * 4977155 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_260_260_hv
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 211245 4456855 ) ( * 4977075 )
NEW met1 ( 211125 4456715 ) ( 211245 * )
NEW met1 ( 211185 4456625 ) via_260_260_vh ( * 4456565 )
( 216065 * )
NEW met2 ( 206300 4456565 ) ( 210985 * )
NEW met1 ( 206040 4457080 ) ( 206160 * )
NEW met1 ( 206040 4456010 ) ( 206160 * )
NEW met1 ( 206100 4456545 ) via_260_1090_vh
NEW met1 ( 206095 4456545 ) mcon_170_1090
NEW met1 ( 211125 4456535 ) ( 211245 * )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met2 ( 848200 4977065 ) ( 848320 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 848200 4975345 ) ( * 4976925 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met1 ( 848150 4981410 ) ( 848270 * )
NEW met1 ( 848210 4981825 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[23] ( sky130_fd_sc_hd__buf_8_92 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3358110 226810 ) ( * 1127640 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2517690 226670 ) ( 3358110 * )
NEW met1 ( 2517690 221370 ) ( * 226530 )
NEW met1 ( 2435730 221230 ) ( 2517690 * )
NEW met1 ( 2435730 221370 ) ( * 235530 )
NEW met1 ( 2170005 235670 ) ( 2435730 * )
NEW met1 ( 2169805 235610 ) via_260_260_hv ( * 235700 )
( 2169865 * )
NEW met2 ( 2169745 235840 ) ( * 235860 )
NEW met2 ( 2169745 235520 ) ( 2169865 * )
NEW met2 ( 2169745 216170 ) ( * 235380 )
NEW met2 ( 2169250 216030 ) ( 2170200 * )
NEW met2 ( 2169725 215940 ) via_1090_260_hv
NEW li1 ( 2169265 215965 ) ( 2170185 * )
NEW li1 ( 2169725 215935 ) mcon_1090_170
NEW met2 ( 2169250 215850 ) ( 2170200 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_81/X ( sky130_fd_sc_hd__buf_8_81 X )
( sky130_fd_sc_hd__buf_8_133 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 682565 215935 ) mcon_170_850
NEW met1 ( 682500 216350 ) ( 682620 * )
NEW met2 ( 682550 216430 ) ( * 236060 )
NEW met2 ( 682550 236200 ) ( 682670 * )
NEW met2 ( 682610 236290 ) via_260_260_hv
NEW met2 ( 682550 236380 ) ( 682670 * )
NEW met2 ( 682550 236520 ) ( * 236475 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 224545 236230 ) ( 682410 * )
NEW met1 ( 224545 236370 ) ( * 1685665 )
NEW met1 ( 224545 1685805 ) ( 224665 * )
NEW met1 ( 224605 1685895 ) via_260_260_vh
NEW met1 ( 224545 1685985 ) ( 224665 * )
NEW met2 ( 224805 1685835 ) ( 224735 * )
NEW met2 ( 203475 1685835 ) ( 224405 * )
NEW met1 ( 203215 1686555 ) ( 203335 * )
NEW met1 ( 203215 1685485 ) ( 203335 * )
NEW met1 ( 203275 1686020 ) via_260_1090_vh
NEW met1 ( 203270 1686020 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 682500 215520 ) ( 682620 * )
NEW met1 ( 682560 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_91/X ( sky130_fd_sc_hd__buf_8_91 X )
( sky130_fd_sc_hd__buf_8_81 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2159565 215935 ) mcon_170_850
NEW met1 ( 2159500 216350 ) ( 2159620 * )
NEW met2 ( 2159550 216430 ) ( * 236200 )
NEW met2 ( 2159550 236340 ) ( 2159670 * )
NEW met2 ( 2159610 236430 ) via_260_260_hv
NEW met2 ( 2159550 236520 ) ( 2159670 * )
NEW met2 ( 2159550 236660 ) ( * 236635 )
NEW met1 ( 779765 236370 ) ( 2159410 * )
NEW met1 ( 779765 234270 ) ( * 236230 )
NEW met1 ( 704595 234130 ) ( 779765 * )
NEW met1 ( 704595 234270 ) ( * 236230 )
NEW met1 ( 687025 236370 ) ( 704595 * )
NEW met1 ( 686825 236310 ) via_260_260_hv ( * 236400 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 686885 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 686765 236540 ) ( * 236450 )
NEW met2 ( 686765 236220 ) ( 686885 * )
NEW met2 ( 686765 216170 ) ( * 236080 )
NEW met2 ( 686270 216030 ) ( 687220 * )
NEW met2 ( 686745 215940 ) via_1090_260_hv
NEW li1 ( 686285 215965 ) ( 687205 * )
NEW li1 ( 686745 215935 ) mcon_1090_170
NEW met2 ( 686270 215850 ) ( 687220 * )
NEW met1 ( 2159500 215520 ) ( 2159620 * )
NEW met1 ( 2159560 215935 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_70/X ( sky130_fd_sc_hd__buf_8_70 X )
( sky130_fd_sc_hd__buf_8_100 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 715695 212875 ) mcon_170_850
NEW met1 ( 715630 213290 ) ( 715750 * )
NEW met2 ( 715695 213370 ) ( * 231320 )
NEW met2 ( 715695 231460 ) ( 715815 * )
NEW met2 ( 715755 231550 ) via_260_260_hv
NEW met2 ( 715695 231640 ) ( 715815 * )
NEW met2 ( 715695 231780 ) ( * 231710 )
NEW met1 ( 715955 231610 ) ( 783405 * )
NEW met1 ( 783405 231750 ) ( * 232590 )
NEW met1 ( 783405 232730 ) ( 2188890 * ) ( * 232790 )
via_260_260_hv ( * 232880 ) ( 2188950 * )
NEW met2 ( 2188830 233020 ) ( * 232930 )
NEW met2 ( 2188830 232700 ) ( 2188950 * )
NEW met2 ( 2188830 213110 ) ( * 232560 )
NEW met2 ( 2188540 212970 ) ( 2189490 * )
NEW met2 ( 2189015 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2188540 212790 ) ( 2189490 * )
NEW met1 ( 715630 212460 ) ( 715750 * )
NEW met1 ( 715690 212875 ) via_260_850_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_70/A ( sky130_fd_sc_hd__buf_8_70 A )
( sky130_fd_sc_hd__buf_8_143 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 712015 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 711540 212970 ) ( 712490 * )
NEW met2 ( 711830 213110 ) ( * 231300 )
NEW met2 ( 711830 231440 ) ( 711950 * )
NEW met2 ( 711890 231530 ) via_260_260_hv
NEW met2 ( 711830 231620 ) ( 711950 * )
NEW met2 ( 711830 231760 ) ( * 231680 )
NEW met1 ( 702240 231470 ) ( 711690 * )
NEW met1 ( 702240 231610 ) ( * 232450 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 219785 232590 ) ( 702240 * )
NEW met1 ( 219785 232730 ) ( * 1710205 )
NEW met1 ( 219785 1710345 ) ( 219905 * )
NEW met1 ( 219845 1710435 ) via_260_260_vh
NEW met1 ( 219785 1710525 ) ( 219905 * )
NEW met2 ( 220045 1710375 ) ( 223670 * )
NEW met2 ( 206825 1710375 ) ( 219645 * )
NEW met2 ( 206330 1710385 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1710475 ) ( 206685 * )
NEW met2 ( 205975 1710295 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 711540 212790 ) ( 712490 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[18] ( sky130_fd_sc_hd__buf_8_171 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 217545 3059755 ) ( * 3062710 )
NEW met1 ( 217545 3059615 ) ( 217825 * )
NEW met1 ( 217825 3014745 ) ( * 3059475 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 217705 3014605 ) ( 217825 * )
NEW met1 ( 217765 3014515 ) via_260_260_vh ( * 3014455 )
( 221530 * )
NEW met2 ( 206425 3014455 ) ( 217565 * )
NEW met1 ( 206165 3014970 ) ( 206285 * )
NEW met1 ( 206165 3013900 ) ( 206285 * )
NEW met1 ( 206225 3014435 ) via_260_1090_vh
NEW met1 ( 206220 3014435 ) mcon_170_1090
NEW met1 ( 217705 3014425 ) ( 217825 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_182/A ( sky130_fd_sc_hd__buf_8_182 A )
( sky130_fd_sc_hd__buf_8_160 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 203035 4445935 ) mcon_170_1090
NEW met1 ( 202980 4446470 ) ( 203100 * )
NEW met2 ( 203240 4445750 ) ( 212365 * )
NEW met1 ( 212505 4445900 ) ( 212625 * )
NEW met1 ( 212565 4445810 ) via_260_260_vh
NEW met1 ( 212505 4445720 ) ( 212625 * )
NEW met1 ( 212505 3043675 ) ( * 4445580 )
NEW met1 ( 212385 3043535 ) ( 212505 * )
NEW met1 ( 212445 3043445 ) via_260_260_vh ( * 3043385 )
( 221530 * )
NEW met2 ( 203655 3043385 ) ( 212245 * )
NEW met2 ( 203160 3043380 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3043470 ) ( 203515 * )
NEW met2 ( 202805 3043290 ) ( 203515 * )
NEW met1 ( 212385 3043355 ) ( 212505 * )
NEW met2 ( 212765 4445750 ) ( 216065 * )
NEW met1 ( 202980 4445400 ) ( 203100 * )
NEW met1 ( 203040 4445935 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_44/A ( sky130_fd_sc_hd__buf_8_44 A )
( sky130_fd_sc_hd__buf_8_182 X )
+ ROUTED met1 ( 841785 4984885 ) mcon_1090_170
via_1090_260_hv
NEW met2 ( 841310 4984970 ) ( 842260 * )
NEW met2 ( 841310 4984790 ) ( 842260 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 841600 4975985 ) ( * 4984650 )
NEW met2 ( 841600 4975845 ) ( 841720 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 212645 4975815 ) ( 841660 * ) ( * 4975755 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_260_260_hv
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 212645 4449905 ) ( * 4975675 )
NEW met1 ( 212525 4449765 ) ( 212645 * )
NEW met1 ( 212585 4449675 ) via_260_260_vh ( * 4449615 )
( 216065 * )
NEW met2 ( 203530 4449615 ) ( 212385 * )
NEW met2 ( 203035 4449610 ) via_850_260_hv mcon_850_170
NEW met2 ( 202680 4449700 ) ( 203390 * )
NEW met2 ( 202680 4449520 ) ( 203390 * )
NEW met1 ( 212525 4449585 ) ( 212645 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 841600 4975665 ) ( 841720 * )
NEW met2 ( 841600 4974470 ) ( * 4975525 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[8] ( sky130_fd_sc_hd__buf_8_193 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3305685 4973365 ) ( 3328350 * ) ( * 4973425 )
via_260_260_hv ( * 4973515 ) ( 3328410 * )
NEW met2 ( 3328410 4973655 ) ( * 4982805 )
NEW met2 ( 3327955 4982945 ) ( 3328905 * )
NEW met2 ( 3328430 4983035 ) via_1090_260_hv mcon_1090_170
( * 4983010 ) ( 3328890 * )
NEW met2 ( 3327955 4983125 ) ( 3328905 * )
NEW met2 ( 3328290 4973335 ) ( 3328410 * )
NEW met2 ( 3328410 4972915 ) ( * 4973195 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[24] ( sky130_fd_sc_hd__buf_8_91 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3356990 227650 ) ( * 1125620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2516570 227510 ) ( 3356990 * )
NEW met1 ( 2516570 221930 ) ( * 227370 )
NEW met1 ( 2436850 221790 ) ( 2516570 * )
NEW met1 ( 2436850 221930 ) ( * 236370 )
NEW met1 ( 2164025 236510 ) ( 2436850 * )
NEW met1 ( 2163825 236450 ) via_260_260_hv ( * 236540 )
( 2163885 * )
NEW met2 ( 2163765 236680 ) ( * 236650 )
NEW met2 ( 2163765 236360 ) ( 2163885 * )
NEW met2 ( 2163765 216170 ) ( * 236220 )
NEW met2 ( 2163270 216030 ) ( 2164220 * )
NEW met2 ( 2163745 215940 ) via_1090_260_hv
NEW li1 ( 2163285 215965 ) ( 2164205 * )
NEW li1 ( 2163745 215935 ) mcon_1090_170
NEW met2 ( 2163270 215850 ) ( 2164220 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_90/A ( sky130_fd_sc_hd__buf_8_90 A )
( sky130_fd_sc_hd__buf_8_80 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2159115 212875 ) mcon_1090_170
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2158640 212970 ) ( 2159590 * )
NEW met2 ( 2158930 213110 ) ( * 236760 )
NEW met2 ( 2158930 236900 ) ( 2159050 * )
NEW met2 ( 2158990 236990 ) via_260_260_hv
NEW met2 ( 2158930 237080 ) ( 2159050 * )
NEW met2 ( 2158930 237220 ) ( * 237165 )
NEW met1 ( 779205 236930 ) ( 2158790 * )
NEW met1 ( 779205 234550 ) ( * 236790 )
NEW met1 ( 705155 234410 ) ( 779205 * )
NEW met1 ( 705155 234550 ) ( * 236790 )
NEW met1 ( 686055 236930 ) ( 705155 * )
NEW met1 ( 685855 236870 ) via_260_260_hv ( * 236960 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( 685915 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 685795 237100 ) ( * 237015 )
NEW met2 ( 685795 236780 ) ( 685915 * )
NEW met2 ( 685795 213370 ) ( * 236640 )
NEW met1 ( 685730 213290 ) ( 685850 * )
NEW met1 ( 685730 212460 ) ( 685850 * )
NEW met1 ( 685790 212875 ) via_260_850_vh
NEW met1 ( 685795 212875 ) mcon_170_850
NEW met2 ( 2158640 212790 ) ( 2159590 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_80/A ( sky130_fd_sc_hd__buf_8_80 A )
( sky130_fd_sc_hd__buf_8_130 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 682115 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 681640 212970 ) ( 682590 * )
NEW met2 ( 681930 213110 ) ( * 236620 )
NEW met2 ( 681930 236760 ) ( 682050 * )
NEW met2 ( 681990 236850 ) via_260_260_hv
NEW met2 ( 681930 236940 ) ( 682050 * )
NEW met2 ( 681930 237080 ) ( * 236980 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 225385 236790 ) ( 681790 * )
NEW met1 ( 225385 236930 ) ( * 1680305 )
NEW met1 ( 225385 1680445 ) ( 225505 * )
NEW met1 ( 225445 1680535 ) via_260_260_vh
NEW met1 ( 225385 1680625 ) ( 225505 * )
NEW met2 ( 225645 1680475 ) ( 225960 * )
NEW met2 ( 206825 1680475 ) ( 225245 * )
NEW met2 ( 206330 1680485 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1680575 ) ( 206685 * )
NEW met2 ( 205975 1680395 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 681640 212790 ) ( 682590 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[18] ( sky130_fd_sc_hd__buf_8_170 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 218105 3013775 ) ( * 3061710 )
NEW met1 ( 217985 3013635 ) ( 218105 * )
NEW met1 ( 218045 3013545 ) via_260_260_vh ( * 3013485 )
( 221530 * )
NEW met2 ( 203655 3013485 ) ( 217845 * )
NEW met2 ( 203160 3013480 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3013570 ) ( 203515 * )
NEW met2 ( 202805 3013390 ) ( 203515 * )
NEW met1 ( 217985 3013455 ) ( 218105 * ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_38/X ( sky130_fd_sc_hd__buf_8_38 X )
( sky130_fd_sc_hd__buf_8_181 A )
+ ROUTED met1 ( 842235 4981825 ) mcon_170_850
NEW met1 ( 842170 4982240 ) ( 842290 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 842220 4976265 ) ( * 4981330 )
NEW met2 ( 842220 4976125 ) ( 842340 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 212365 4976095 ) ( 842280 * ) ( * 4976035 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_260_260_hv
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 212365 4450755 ) ( * 4975955 )
NEW met1 ( 212245 4450615 ) ( 212365 * )
NEW met1 ( 212305 4450525 ) via_260_260_vh
NEW met2 ( 206300 4450585 ) ( 212105 * )
NEW met1 ( 206040 4451100 ) ( 206160 * )
NEW met1 ( 206040 4450030 ) ( 206160 * )
NEW met1 ( 206100 4450565 ) via_260_1090_vh
NEW met1 ( 206095 4450565 ) mcon_170_1090
NEW met2 ( 212505 4450585 ) ( 216065 * )
NEW met1 ( 212245 4450435 ) ( 212365 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 842220 4975945 ) ( 842340 * )
NEW met2 ( 842220 4974470 ) ( * 4975805 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
NEW met1 ( 842170 4981410 ) ( 842290 * )
NEW met1 ( 842230 4981825 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[9] ( sky130_fd_sc_hd__buf_8_192 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3303685 4974485 ) ( 3322370 * ) ( * 4974545 )
via_260_260_hv ( * 4974635 ) ( 3322430 * )
NEW met2 ( 3322430 4974775 ) ( * 4982805 )
NEW met2 ( 3321975 4982945 ) ( 3322925 * )
NEW met2 ( 3322450 4983035 ) via_1090_260_hv mcon_1090_170
( * 4983010 ) ( 3322910 * )
NEW met2 ( 3321975 4983125 ) ( 3322925 * )
NEW met2 ( 3322310 4974455 ) ( 3322430 * )
NEW met2 ( 3322430 4972915 ) ( * 4974315 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[25] ( sky130_fd_sc_hd__buf_8_90 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3356430 1121160 ) ( * 1124620 )
NEW met1 ( 3356150 1121020 ) ( 3356430 * )
NEW met1 ( 3356150 228210 ) ( * 1120880 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2515730 228070 ) ( 3356150 * )
NEW met1 ( 2515730 222210 ) ( * 227930 )
NEW met1 ( 2437690 222070 ) ( 2515730 * )
NEW met1 ( 2437690 222210 ) ( * 236930 )
NEW met1 ( 2163055 237070 ) ( 2437690 * )
NEW met1 ( 2162855 237010 ) via_260_260_hv ( * 237100 )
( 2162915 * )
NEW met2 ( 2162795 237240 ) ( * 237155 )
NEW met2 ( 2162795 236920 ) ( 2162915 * )
NEW met2 ( 2162795 213370 ) ( * 236780 )
NEW met1 ( 2162730 213290 ) ( 2162850 * )
NEW met1 ( 2162730 212460 ) ( 2162850 * )
NEW met1 ( 2162790 212875 ) via_260_850_vh
NEW met1 ( 2162795 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[10] ( sky130_fd_sc_hd__buf_8_191 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3301685 4975605 ) ( 3316390 * ) ( * 4975665 )
via_260_260_hv ( * 4975755 ) ( 3316450 * )
NEW met2 ( 3316450 4975895 ) ( * 4982805 )
NEW met2 ( 3315995 4982945 ) ( 3316945 * )
NEW met2 ( 3316470 4983035 ) via_1090_260_hv mcon_1090_170
( * 4983010 ) ( 3316930 * )
NEW met2 ( 3315995 4983125 ) ( 3316945 * )
NEW met2 ( 3316330 4975575 ) ( 3316450 * )
NEW met2 ( 3316450 4972915 ) ( * 4975435 ) ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_45/A ( sky130_fd_sc_hd__buf_8_45 A )
( sky130_fd_sc_hd__buf_8_190 X )
+ ROUTED met1 ( 835805 4984885 ) mcon_1090_170
via_1090_260_hv
NEW met2 ( 835330 4984970 ) ( 836280 * )
NEW met2 ( 835330 4984790 ) ( 836280 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 835620 4974865 ) ( * 4984650 )
NEW met2 ( 835620 4974725 ) ( 835740 * )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 213765 4974695 ) ( 835680 * ) ( * 4974635 )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
via_260_260_hv
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
NEW met1 ( 213765 4443925 ) ( * 4974555 )
NEW met1 ( 213645 4443785 ) ( 213765 * )
NEW met1 ( 213705 4443695 ) via_260_260_vh ( * 4443635 )
( 216065 * )
NEW met2 ( 203530 4443635 ) ( 213505 * )
NEW met2 ( 203035 4443630 ) via_850_260_hv mcon_850_170
NEW met2 ( 202680 4443720 ) ( 203390 * )
NEW met2 ( 202680 4443540 ) ( 203390 * )
NEW met1 ( 213645 4443605 ) ( 213765 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 835620 4974545 ) ( 835740 * )
NEW met2 ( 835620 4974470 ) ( * 4974405 ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[2] ( sky130_fd_sc_hd__buf_8_9 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 665825 220690 ) ( 669260 * )
NEW met1 ( 669260 220830 ) ( 790250 * ) ( * 220890 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv ( * 220980 ) ( 790310 * )
NEW met2 ( 790190 221120 ) ( * 232275 )
NEW met2 ( 790190 220800 ) ( 790310 * )
NEW met2 ( 790190 216430 ) ( * 220660 )
NEW met1 ( 790140 216350 ) ( 790260 * )
NEW met1 ( 790140 215520 ) ( 790260 * )
NEW met1 ( 790200 215935 ) via_260_850_vh
NEW met1 ( 790205 215935 ) mcon_170_850 ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
- sky130_fd_sc_hd__buf_8_9/A ( sky130_fd_sc_hd__buf_8_9 A )
( sky130_fd_sc_hd__buf_8_127 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 794385 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 793910 216030 ) ( 794860 * )
NEW met2 ( 794405 216170 ) ( * 220680 )
NEW met2 ( 794405 220820 ) ( 794525 * )
NEW met2 ( 794465 220910 ) via_260_260_hv
NEW met2 ( 794405 221000 ) ( 794525 * )
NEW met2 ( 794405 221140 ) ( * 232275 )
NEW met1 ( 794665 220970 ) ( 2267250 * ) ( * 221030 )
via_260_260_hv ( * 221120 ) ( 2267310 * )
NEW met2 ( 2267190 221260 ) ( * 232415 )
NEW met2 ( 2267190 220940 ) ( 2267310 * )
NEW met2 ( 2267190 216430 ) ( * 220800 )
NEW met1 ( 2267140 216350 ) ( 2267260 * )
NEW met1 ( 2267140 215520 ) ( 2267260 * )
NEW met1 ( 2267200 215935 ) via_260_850_vh
NEW met1 ( 2267205 215935 ) mcon_170_850
NEW met2 ( 793910 215850 ) ( 794860 * )
NEW li1 ( 793925 215965 ) ( 794845 * ) ;
- vssd ( sky130_fd_sc_hd__tapvpwrvgnd_1_217 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_215 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_197 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_197 VNB )
( sky130_fd_sc_hd__buf_8_196 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_196 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_214 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_213 VGND )
( sky130_fd_sc_hd__buf_8_195 VNB )
( sky130_fd_sc_hd__buf_8_195 VGND )
( sky130_fd_sc_hd__buf_8_194 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_194 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_280 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_15 VGND )
( sky130_fd_sc_hd__buf_8_10 VNB )
( sky130_fd_sc_hd__buf_8_10 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_285 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_44 VGND )
( sky130_fd_sc_hd__buf_8_43 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_284 VGND )
( sky130_fd_sc_hd__buf_8_45 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_216 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_282 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_211 VGND )
( sky130_fd_sc_hd__buf_8_193 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_79 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_193 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_79 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_192 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_192 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_78 VNB )
( sky130_ef_sc_hd__decap_12_78 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_210 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_209 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_191 VNB )
( sky130_fd_sc_hd__buf_8_191 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_283 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_281 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_80 VNB )
( sky130_ef_sc_hd__decap_12_80 VGND )
( sky130_ef_sc_hd__decap_12_81 VNB )
( sky130_ef_sc_hd__decap_12_81 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_180 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_180 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_208 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_212 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_41 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_14 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_11 VNB )
( sky130_fd_sc_hd__buf_8_11 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_77 VNB )
( sky130_ef_sc_hd__decap_12_77 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_286 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_40 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_47 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_46 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_290 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_43 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_42 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_43 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_42 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_42 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_289 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_74 VGND )
( sky130_ef_sc_hd__decap_12_74 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_49 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_48 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_44 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_38 VNB )
( sky130_fd_sc_hd__buf_8_38 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_51 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_76 VNB )
( sky130_ef_sc_hd__decap_12_76 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_287 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_50 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_45 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_39 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_39 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_288 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_75 VGND )
( sky130_ef_sc_hd__decap_12_75 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_295 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_198 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_199 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_183 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_69 VNB )
( sky130_ef_sc_hd__decap_12_69 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_296 VGND )
( sky130_fd_sc_hd__buf_8_181 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_70 VNB )
( sky130_ef_sc_hd__decap_12_70 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_184 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_184 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_183 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_197 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_196 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_182 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_182 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_181 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_294 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_189 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_71 VNB )
( sky130_ef_sc_hd__decap_12_71 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_293 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_207 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_206 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_190 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_190 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_189 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_205 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_204 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_188 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_72 VNB )
( sky130_ef_sc_hd__decap_12_72 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_292 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_188 VNB )
( sky130_fd_sc_hd__buf_8_187 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_187 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_203 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_202 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_186 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_73 VNB )
( sky130_ef_sc_hd__decap_12_73 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_291 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_186 VNB )
( sky130_fd_sc_hd__buf_8_185 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_185 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_201 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_200 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_37 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_36 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_279 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_44 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_33 VGND )
( sky130_fd_sc_hd__buf_8_40 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_33 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_45 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_32 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_84 VGND )
( sky130_fd_sc_hd__buf_8_32 VNB )
( sky130_fd_sc_hd__buf_8_40 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_41 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_41 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_82 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_276 VGND )
( sky130_ef_sc_hd__decap_12_84 VNB )
( sky130_ef_sc_hd__decap_12_82 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_31 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_35 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_34 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_33 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_31 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_32 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_30 VNB )
( sky130_fd_sc_hd__buf_8_30 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_83 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_278 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_277 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_83 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_31 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_29 VGND )
( sky130_fd_sc_hd__buf_8_29 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_30 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_28 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_28 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_87 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_0 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_87 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_27 VGND )
( sky130_fd_sc_hd__buf_8_27 VNB )
( sky130_fd_sc_hd__buf_8_26 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_26 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_85 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_1 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_29 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_85 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_275 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_24 VGND )
( sky130_fd_sc_hd__buf_8_24 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_25 VNB )
( sky130_fd_sc_hd__buf_8_25 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_86 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_272 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_28 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_86 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_274 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_307 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_173 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_159 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_58 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_172 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_308 VGND )
( sky130_fd_sc_hd__buf_8_158 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_58 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_305 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_60 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_161 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_60 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_175 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_174 VGND )
( sky130_fd_sc_hd__buf_8_159 VNB )
( sky130_fd_sc_hd__buf_8_158 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_177 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_176 VGND )
( sky130_fd_sc_hd__buf_8_160 VGND )
( sky130_fd_sc_hd__buf_8_161 VNB )
( sky130_fd_sc_hd__buf_8_160 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_306 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_59 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_163 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_59 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_179 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_178 VGND )
( sky130_fd_sc_hd__buf_8_162 VGND )
( sky130_fd_sc_hd__buf_8_163 VNB )
( sky130_fd_sc_hd__buf_8_162 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_303 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_62 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_165 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_62 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_181 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_180 VGND )
( sky130_fd_sc_hd__buf_8_164 VGND )
( sky130_fd_sc_hd__buf_8_165 VNB )
( sky130_fd_sc_hd__buf_8_164 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_304 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_167 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_61 VNB )
( sky130_ef_sc_hd__decap_12_61 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_183 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_182 VGND )
( sky130_fd_sc_hd__buf_8_167 VNB )
( sky130_fd_sc_hd__buf_8_166 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_166 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_301 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_64 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_169 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_64 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_185 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_184 VGND )
( sky130_fd_sc_hd__buf_8_168 VGND )
( sky130_fd_sc_hd__buf_8_169 VNB )
( sky130_fd_sc_hd__buf_8_168 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_302 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_63 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_171 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_63 VGND )
( sky130_ef_sc_hd__decap_12_66 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_172 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_66 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_187 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_170 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_186 VGND )
( sky130_fd_sc_hd__buf_8_171 VNB )
( sky130_fd_sc_hd__buf_8_170 VNB )
( sky130_fd_sc_hd__buf_8_173 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_173 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_172 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_300 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_298 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_65 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_175 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_65 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_189 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_188 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_193 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_191 VGND )
( sky130_fd_sc_hd__buf_8_174 VGND )
( sky130_fd_sc_hd__buf_8_175 VNB )
( sky130_fd_sc_hd__buf_8_174 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_299 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_67 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_177 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_67 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_192 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_190 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_176 VGND )
( sky130_fd_sc_hd__buf_8_177 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_176 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_68 VNB )
( sky130_ef_sc_hd__decap_12_68 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_179 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_297 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_178 VNB )
( sky130_fd_sc_hd__buf_8_178 VGND )
( sky130_fd_sc_hd__buf_8_179 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_194 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_195 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_27 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_23 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_26 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_25 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_24 VGND )
( sky130_fd_sc_hd__buf_8_22 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_88 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_23 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_22 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_273 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_325 VGND )
( sky130_ef_sc_hd__decap_12_88 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_19 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_17 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_18 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_16 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_90 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_17 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_16 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_270 VGND )
( sky130_ef_sc_hd__decap_12_90 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_23 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_21 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_22 VGND )
( sky130_fd_sc_hd__buf_8_20 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_89 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_21 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_20 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_271 VGND )
( sky130_ef_sc_hd__decap_12_89 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_21 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_19 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_20 VGND )
( sky130_fd_sc_hd__buf_8_18 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_92 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_19 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_18 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_268 VGND )
( sky130_ef_sc_hd__decap_12_92 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_15 VGND )
( sky130_fd_sc_hd__buf_8_15 VNB )
( sky130_fd_sc_hd__buf_8_14 VNB )
( sky130_fd_sc_hd__buf_8_14 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_91 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_17 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_16 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_91 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_269 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_37 VGND )
( sky130_fd_sc_hd__buf_8_35 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_37 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_36 VNB )
( sky130_fd_sc_hd__buf_8_36 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_94 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_39 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_35 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_38 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_34 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_34 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_93 VGND )
( sky130_ef_sc_hd__decap_12_94 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_266 VGND )
( sky130_ef_sc_hd__decap_12_93 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_52 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_62 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_52 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_63 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_53 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_53 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_95 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_60 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_61 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_267 VGND )
( sky130_ef_sc_hd__decap_12_95 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_265 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_58 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_50 VGND )
( sky130_fd_sc_hd__buf_8_50 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_59 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_51 VNB )
( sky130_fd_sc_hd__buf_8_51 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_263 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_97 VGND )
( sky130_ef_sc_hd__decap_12_97 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_56 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_48 VGND )
( sky130_fd_sc_hd__buf_8_48 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_57 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_49 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_49 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_264 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_96 VGND )
( sky130_ef_sc_hd__decap_12_96 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_54 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_47 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_47 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_55 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_46 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_46 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_52 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_99 VGND )
( sky130_ef_sc_hd__decap_12_99 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_12 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_98 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_12 VNB )
( sky130_fd_sc_hd__buf_8_13 VNB )
( sky130_fd_sc_hd__buf_8_13 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_53 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_261 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_98 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_262 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_324 VGND )
( sky130_ef_sc_hd__decap_12_55 VNB )
( sky130_ef_sc_hd__decap_12_55 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_168 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_156 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_169 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_157 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_157 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_156 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_322 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_321 VGND )
( sky130_ef_sc_hd__decap_12_54 VNB )
( sky130_ef_sc_hd__decap_12_54 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_171 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_0 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_170 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_323 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_163 VGND )
( sky130_fd_sc_hd__buf_8_151 VGND )
( sky130_fd_sc_hd__buf_8_151 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_0 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_162 VGND )
Made a minor correction to the layout to remove an extra unused buffer. This does not affect ongoing top-level routing work, but is needed for LVS.
2022-10-16 16:57:14 -05:00
( sky130_ef_sc_hd__decap_12_100 VNB )
( sky130_ef_sc_hd__decap_12_100 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_165 VGND )
( sky130_fd_sc_hd__buf_8_152 VGND )
( sky130_fd_sc_hd__buf_8_153 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_164 VGND )
( sky130_fd_sc_hd__buf_8_153 VNB )
( sky130_fd_sc_hd__buf_8_152 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_319 VGND )
( sky130_ef_sc_hd__decap_12_52 VNB )
( sky130_ef_sc_hd__decap_12_52 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_167 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_155 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_166 VGND )
( sky130_fd_sc_hd__buf_8_154 VGND )
( sky130_fd_sc_hd__buf_8_155 VNB )
( sky130_fd_sc_hd__buf_8_154 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_320 VGND )
( sky130_ef_sc_hd__decap_12_53 VNB )
( sky130_ef_sc_hd__decap_12_53 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_144 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_157 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_156 VGND )
( sky130_fd_sc_hd__buf_8_145 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_145 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_144 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_318 VGND )
( sky130_ef_sc_hd__decap_12_51 VNB )
( sky130_ef_sc_hd__decap_12_51 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_159 VGND )
( sky130_fd_sc_hd__buf_8_147 VGND )
( sky130_fd_sc_hd__buf_8_146 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_158 VGND )
( sky130_fd_sc_hd__buf_8_147 VNB )
( sky130_fd_sc_hd__buf_8_146 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_317 VGND )
( sky130_ef_sc_hd__decap_12_50 VNB )
( sky130_ef_sc_hd__decap_12_50 VGND )
( sky130_ef_sc_hd__decap_12_48 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_149 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_48 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_161 VGND )
( sky130_fd_sc_hd__buf_8_141 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_148 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_160 VGND )
( sky130_fd_sc_hd__buf_8_149 VNB )
( sky130_fd_sc_hd__buf_8_148 VNB )
( sky130_fd_sc_hd__buf_8_141 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_140 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_140 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_315 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_316 VGND )
( sky130_ef_sc_hd__decap_12_49 VNB )
( sky130_ef_sc_hd__decap_12_49 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_153 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_143 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_152 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_155 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_142 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_154 VGND )
( sky130_fd_sc_hd__buf_8_143 VNB )
( sky130_fd_sc_hd__buf_8_142 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_314 VGND )
( sky130_ef_sc_hd__decap_12_47 VNB )
( sky130_ef_sc_hd__decap_12_47 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_147 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_134 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_146 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_135 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_135 VNB )
( sky130_fd_sc_hd__buf_8_134 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_313 VGND )
( sky130_ef_sc_hd__decap_12_45 VNB )
( sky130_ef_sc_hd__decap_12_45 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_149 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_136 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_148 VGND )
( sky130_fd_sc_hd__buf_8_137 VGND )
( sky130_fd_sc_hd__buf_8_137 VNB )
( sky130_fd_sc_hd__buf_8_136 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_311 VGND )
( sky130_ef_sc_hd__decap_12_46 VNB )
( sky130_ef_sc_hd__decap_12_46 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_151 VGND )
( sky130_fd_sc_hd__buf_8_139 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_150 VGND )
( sky130_fd_sc_hd__buf_8_138 VGND )
( sky130_fd_sc_hd__buf_8_139 VNB )
( sky130_fd_sc_hd__buf_8_138 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_312 VGND )
( sky130_ef_sc_hd__decap_12_44 VNB )
( sky130_ef_sc_hd__decap_12_44 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_145 VGND )
( sky130_fd_sc_hd__buf_8_132 VGND )
( sky130_fd_sc_hd__buf_8_133 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_144 VGND )
( sky130_fd_sc_hd__buf_8_133 VNB )
( sky130_fd_sc_hd__buf_8_132 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_310 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_56 VNB )
( sky130_ef_sc_hd__decap_12_56 VGND )
( sky130_ef_sc_hd__decap_12_57 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_130 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_57 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_143 VGND )
( sky130_fd_sc_hd__buf_8_128 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_131 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_142 VGND )
( sky130_fd_sc_hd__buf_8_131 VNB )
( sky130_fd_sc_hd__buf_8_130 VNB )
( sky130_fd_sc_hd__buf_8_129 VNB )
( sky130_fd_sc_hd__buf_8_129 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_128 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_141 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_309 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_140 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_237 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_235 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_20 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_127 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_20 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_236 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_19 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_126 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_19 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_233 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_17 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_123 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_17 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_234 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_18 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_120 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_18 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_232 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_16 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_118 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_16 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_231 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_15 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_117 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_15 VGND )
( sky130_ef_sc_hd__decap_12_14 VNB )
( sky130_ef_sc_hd__decap_12_14 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_230 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_115 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_228 VGND )
( sky130_ef_sc_hd__decap_12_12 VNB )
( sky130_ef_sc_hd__decap_12_12 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_229 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_113 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_13 VNB )
( sky130_ef_sc_hd__decap_12_13 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_227 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_111 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_11 VNB )
( sky130_ef_sc_hd__decap_12_11 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_221 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_108 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_5 VNB )
( sky130_ef_sc_hd__decap_12_5 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_106 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_226 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_10 VNB )
( sky130_ef_sc_hd__decap_12_10 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_225 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_105 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_9 VNB )
( sky130_ef_sc_hd__decap_12_9 VGND )
( sky130_ef_sc_hd__decap_12_8 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_104 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_8 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_224 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_103 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_223 VGND )
( sky130_ef_sc_hd__decap_12_7 VNB )
( sky130_ef_sc_hd__decap_12_7 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_222 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_99 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_6 VNB )
( sky130_ef_sc_hd__decap_12_6 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_2 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_98 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_0 VNB )
( sky130_ef_sc_hd__decap_12_0 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_220 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_94 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_4 VNB )
( sky130_ef_sc_hd__decap_12_4 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_219 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_92 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_3 VNB )
( sky130_ef_sc_hd__decap_12_3 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_218 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_91 VGND )
( sky130_ef_sc_hd__decap_12_2 VNB )
( sky130_ef_sc_hd__decap_12_2 VGND )
( sky130_ef_sc_hd__decap_12_22 VNB )
( sky130_ef_sc_hd__decap_12_22 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_239 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_88 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_86 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_326 VGND )
( sky130_ef_sc_hd__decap_12_43 VNB )
( sky130_ef_sc_hd__decap_12_43 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_260 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_9 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_41 VNB )
( sky130_ef_sc_hd__decap_12_41 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_7 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_258 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_259 VGND )
( sky130_ef_sc_hd__decap_12_42 VNB )
( sky130_ef_sc_hd__decap_12_42 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_255 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_5 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_38 VNB )
( sky130_ef_sc_hd__decap_12_38 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_257 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_84 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_40 VNB )
( sky130_ef_sc_hd__decap_12_40 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_256 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_3 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_39 VNB )
( sky130_ef_sc_hd__decap_12_39 VGND )
( sky130_ef_sc_hd__decap_12_37 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_55 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_37 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_254 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_57 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_252 VGND )
( sky130_ef_sc_hd__decap_12_35 VNB )
( sky130_ef_sc_hd__decap_12_35 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_253 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_59 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_36 VNB )
( sky130_ef_sc_hd__decap_12_36 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_251 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_61 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_33 VNB )
( sky130_ef_sc_hd__decap_12_33 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_63 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_250 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_34 VNB )
( sky130_ef_sc_hd__decap_12_34 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_248 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_65 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_31 VNB )
( sky130_ef_sc_hd__decap_12_31 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_249 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_66 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_32 VNB )
( sky130_ef_sc_hd__decap_12_32 VGND )
( sky130_ef_sc_hd__decap_12_30 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_69 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_30 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_247 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_71 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_245 VGND )
( sky130_ef_sc_hd__decap_12_28 VNB )
( sky130_ef_sc_hd__decap_12_28 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_246 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_73 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_29 VNB )
( sky130_ef_sc_hd__decap_12_29 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_244 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_75 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_27 VNB )
( sky130_ef_sc_hd__decap_12_27 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_243 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_77 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_25 VNB )
( sky130_ef_sc_hd__decap_12_25 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_242 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_78 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_26 VNB )
( sky130_ef_sc_hd__decap_12_26 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_240 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_81 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_23 VNB )
( sky130_ef_sc_hd__decap_12_23 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_241 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_83 VGND )
( sky130_ef_sc_hd__decap_12_24 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_1 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_24 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_139 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_136 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_138 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_135 VGND )
( sky130_fd_sc_hd__buf_8_125 VGND )
( sky130_fd_sc_hd__buf_8_127 VNB )
( sky130_fd_sc_hd__buf_8_125 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_137 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_134 VGND )
( sky130_fd_sc_hd__buf_8_124 VGND )
( sky130_fd_sc_hd__buf_8_126 VNB )
( sky130_fd_sc_hd__buf_8_124 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_133 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_132 VGND )
( sky130_fd_sc_hd__buf_8_122 VGND )
( sky130_fd_sc_hd__buf_8_123 VNB )
( sky130_fd_sc_hd__buf_8_122 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_131 VGND )
( sky130_fd_sc_hd__buf_8_121 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_130 VGND )
( sky130_fd_sc_hd__buf_8_121 VNB )
( sky130_fd_sc_hd__buf_8_120 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_129 VGND )
( sky130_fd_sc_hd__buf_8_119 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_128 VGND )
( sky130_fd_sc_hd__buf_8_119 VNB )
( sky130_fd_sc_hd__buf_8_118 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_127 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_116 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_126 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_117 VNB )
( sky130_fd_sc_hd__buf_8_116 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_115 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_114 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_114 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_125 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_124 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_123 VGND )
( sky130_fd_sc_hd__buf_8_112 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_122 VGND )
( sky130_fd_sc_hd__buf_8_113 VNB )
( sky130_fd_sc_hd__buf_8_112 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_121 VGND )
( sky130_fd_sc_hd__buf_8_110 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_120 VGND )
( sky130_fd_sc_hd__buf_8_111 VNB )
( sky130_fd_sc_hd__buf_8_110 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_119 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_118 VGND )
( sky130_fd_sc_hd__buf_8_109 VGND )
( sky130_fd_sc_hd__buf_8_109 VNB )
( sky130_fd_sc_hd__buf_8_108 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_117 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_116 VGND )
( sky130_fd_sc_hd__buf_8_107 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_107 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_106 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_115 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_113 VGND )
( sky130_fd_sc_hd__buf_8_102 VGND )
( sky130_fd_sc_hd__buf_8_105 VNB )
( sky130_fd_sc_hd__buf_8_102 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_114 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_112 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_101 VGND )
( sky130_fd_sc_hd__buf_8_104 VNB )
( sky130_fd_sc_hd__buf_8_101 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_103 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_100 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_100 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_111 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_108 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_110 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_107 VGND )
( sky130_fd_sc_hd__buf_8_97 VGND )
( sky130_fd_sc_hd__buf_8_99 VNB )
( sky130_fd_sc_hd__buf_8_97 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_109 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_106 VGND )
( sky130_fd_sc_hd__buf_8_96 VGND )
( sky130_fd_sc_hd__buf_8_98 VNB )
( sky130_fd_sc_hd__buf_8_96 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_103 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_102 VGND )
( sky130_fd_sc_hd__buf_8_95 VGND )
( sky130_fd_sc_hd__buf_8_95 VNB )
( sky130_fd_sc_hd__buf_8_94 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_105 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_104 VGND )
( sky130_fd_sc_hd__buf_8_93 VGND )
( sky130_fd_sc_hd__buf_8_93 VNB )
( sky130_fd_sc_hd__buf_8_92 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_101 VGND )
( sky130_fd_sc_hd__buf_8_90 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_100 VGND )
( sky130_fd_sc_hd__buf_8_91 VNB )
( sky130_fd_sc_hd__buf_8_90 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_99 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_98 VGND )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_89 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_89 VNB )
( sky130_fd_sc_hd__buf_8_88 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_86 VNB )
( sky130_ef_sc_hd__decap_12_1 VGND )
( sky130_ef_sc_hd__decap_12_1 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_97 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_96 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_13 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_12 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_9 VNB )
( sky130_fd_sc_hd__buf_8_8 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_8 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_11 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_10 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_7 VNB )
( sky130_fd_sc_hd__buf_8_6 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_6 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_9 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_8 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_5 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_4 VGND )
( sky130_fd_sc_hd__buf_8_4 VGND )
( sky130_fd_sc_hd__buf_8_5 VNB )
( sky130_fd_sc_hd__buf_8_4 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_95 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_85 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_94 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_85 VNB )
( sky130_fd_sc_hd__buf_8_84 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_7 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_6 VGND )
( sky130_fd_sc_hd__buf_8_2 VGND )
( sky130_fd_sc_hd__buf_8_3 VNB )
( sky130_fd_sc_hd__buf_8_2 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_65 VGND )
( sky130_fd_sc_hd__buf_8_54 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_64 VGND )
( sky130_fd_sc_hd__buf_8_55 VNB )
( sky130_fd_sc_hd__buf_8_54 VNB )
( sky130_fd_sc_hd__buf_8_57 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_56 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_56 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_67 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_66 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_69 VGND )
( sky130_fd_sc_hd__buf_8_58 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_68 VGND )
( sky130_fd_sc_hd__buf_8_59 VNB )
( sky130_fd_sc_hd__buf_8_58 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_71 VGND )
( sky130_fd_sc_hd__buf_8_60 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_70 VGND )
( sky130_fd_sc_hd__buf_8_61 VNB )
( sky130_fd_sc_hd__buf_8_60 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_73 VGND )
( sky130_fd_sc_hd__buf_8_62 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_72 VGND )
( sky130_fd_sc_hd__buf_8_63 VNB )
( sky130_fd_sc_hd__buf_8_62 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_75 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_64 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_74 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_65 VNB )
( sky130_fd_sc_hd__buf_8_64 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_77 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_76 VGND )
( sky130_fd_sc_hd__buf_8_67 VGND )
( sky130_fd_sc_hd__buf_8_67 VNB )
( sky130_fd_sc_hd__buf_8_66 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_79 VGND )
( sky130_fd_sc_hd__buf_8_68 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_78 VGND )
( sky130_fd_sc_hd__buf_8_69 VNB )
( sky130_fd_sc_hd__buf_8_68 VNB )
( sky130_fd_sc_hd__buf_8_71 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_70 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__buf_8_70 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_81 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_80 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_83 VGND )
( sky130_fd_sc_hd__buf_8_72 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_82 VGND )
( sky130_fd_sc_hd__buf_8_73 VNB )
( sky130_fd_sc_hd__buf_8_72 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_85 VGND )
( sky130_fd_sc_hd__buf_8_74 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_84 VGND )
( sky130_fd_sc_hd__buf_8_75 VNB )
( sky130_fd_sc_hd__buf_8_74 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_87 VGND )
( sky130_fd_sc_hd__buf_8_76 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_86 VGND )
( sky130_fd_sc_hd__buf_8_77 VNB )
( sky130_fd_sc_hd__buf_8_76 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_89 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_88 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_79 VGND )
( sky130_fd_sc_hd__buf_8_79 VNB )
( sky130_fd_sc_hd__buf_8_78 VNB )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_91 VGND )
( sky130_fd_sc_hd__buf_8_80 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_90 VGND )
( sky130_fd_sc_hd__buf_8_81 VNB )
( sky130_fd_sc_hd__buf_8_80 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_93 VGND )
( sky130_fd_sc_hd__buf_8_82 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_92 VGND )
( sky130_fd_sc_hd__buf_8_83 VNB )
( sky130_fd_sc_hd__buf_8_82 VNB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_1 VNB )
( sky130_ef_sc_hd__decap_12_21 VGND )
( sky130_ef_sc_hd__decap_12_21 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_238 VGND )
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_3 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met3 TAPERRULE met3_width_1740 ( 2208245 210670 ) ( 2209810 * )
NEW met3 ( 2208245 211690 ) ( 2207980 * )
NEW met3 TAPERRULE met3_width_1865 ( 2209027.5 211990 ) ( * 216800 )
NEW met3 ( 2208245 217100 ) ( 2207980 * )
NEW met3 ( 2208245 217175 ) ( 2209810 * )
NEW met3 ( 2210065 217100 ) ( 2209810 * )
NEW met2 ( 2208160 217240 ) ( 2209885 * )
NEW met2 ( 2208160 216950 ) ( 2209885 * )
NEW met2 ( 2209022.5 217100 ) via2_1785_300_vx
NEW met2 ( 2209022.5 217100 ) via_1785_300_vh
NEW met3 ( 2210065 211690 ) ( 2209810 * )
NEW met2 ( 2208160 211815 ) ( 2209885 * )
NEW met2 ( 2208160 211525 ) ( 2209885 * )
NEW met2 ( 2209022.5 211690 ) via2_1785_300_vx
NEW met2 ( 2209022.5 211690 ) via_1785_300_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[1] ( sky130_fd_sc_hd__buf_8_8 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 664825 221250 ) ( 668315 * )
NEW met1 ( 668315 221390 ) ( 789630 * ) ( * 221450 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
via_260_260_hv ( * 221540 ) ( 789690 * )
NEW met2 ( 789570 221680 ) ( * 232275 )
NEW met2 ( 789570 221360 ) ( 789690 * )
NEW met2 ( 789570 214310 ) ( * 221220 )
NEW met2 ( 789570 214170 ) ( 790205 * )
NEW met2 ( 790205 213370 ) ( * 214030 )
NEW met1 ( 790150 213290 ) ( 790270 * )
NEW met1 ( 790150 212460 ) ( 790270 * )
NEW met1 ( 790210 212875 ) via_260_850_vh
NEW met1 ( 790205 212875 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_8/A ( sky130_fd_sc_hd__buf_8_8 A )
( sky130_fd_sc_hd__buf_8_125 X )
+ ROUTED met1 ( 793885 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 793410 212970 ) ( 794360 * )
NEW met2 ( 794070 213110 ) ( * 214030 )
NEW met2 ( 793435 214170 ) ( 794070 * )
NEW met2 ( 793435 214310 ) ( * 221240 )
NEW met2 ( 793435 221380 ) ( 793555 * )
NEW met2 ( 793495 221470 ) via_260_260_hv
NEW met2 ( 793435 221560 ) ( 793555 * )
NEW met2 ( 793435 221700 ) ( * 232275 )
NEW met1 ( 793695 221530 ) ( 2266630 * ) ( * 221590 )
via_260_260_hv ( * 221680 ) ( 2266690 * )
NEW met2 ( 2266570 221820 ) ( * 232415 )
NEW met2 ( 2266570 221500 ) ( 2266690 * )
NEW met2 ( 2266570 214240 ) ( * 221360 )
NEW met2 ( 2266570 214100 ) ( 2267205 * )
NEW met2 ( 2267205 213370 ) ( * 213960 )
NEW met1 ( 2267150 213290 ) ( 2267270 * )
NEW met1 ( 2267150 212460 ) ( 2267270 * )
NEW met1 ( 2267210 212875 ) via_260_850_vh
NEW met1 ( 2267205 212875 ) mcon_170_850
NEW met2 ( 793410 212790 ) ( 794360 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[0] ( sky130_fd_sc_hd__buf_8_7 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 663825 221810 ) ( 667285 * )
NEW met1 ( 667285 221950 ) ( 784270 * ) ( * 222010 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
via_260_260_hv ( * 222100 ) ( 784330 * )
NEW met2 ( 784210 222240 ) ( * 232275 )
NEW met2 ( 784210 221920 ) ( 784330 * )
NEW met2 ( 784210 216430 ) ( * 221780 )
NEW met1 ( 784160 216350 ) ( 784280 * )
NEW met1 ( 784160 215520 ) ( 784280 * )
NEW met1 ( 784220 215935 ) via_260_850_vh
NEW met1 ( 784225 215935 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_7/A ( sky130_fd_sc_hd__buf_8_7 A )
( sky130_fd_sc_hd__buf_8_126 X )
+ ROUTED met1 ( 788405 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 787930 216030 ) ( 788880 * )
NEW met2 ( 788425 216170 ) ( * 221800 )
NEW met2 ( 788305 221940 ) ( 788425 * )
NEW met2 ( 788365 222030 ) via_260_260_hv
NEW met2 ( 788305 222120 ) ( 788425 * )
NEW met2 ( 788425 222260 ) ( * 232275 )
NEW met1 ( 788565 222090 ) ( 2261270 * ) ( * 222150 )
via_260_260_hv ( * 222240 ) ( 2261330 * )
NEW met2 ( 2261210 222380 ) ( * 232415 )
NEW met2 ( 2261210 222060 ) ( 2261330 * )
NEW met2 ( 2261210 216430 ) ( * 221920 )
NEW met1 ( 2261160 216350 ) ( 2261280 * )
NEW met1 ( 2261160 215520 ) ( 2261280 * )
NEW met1 ( 2261220 215935 ) via_260_850_vh
NEW met1 ( 2261225 215935 ) mcon_170_850
NEW met2 ( 787930 215850 ) ( 788880 * )
NEW li1 ( 787945 215965 ) ( 788865 * ) ;
- sky130_fd_sc_hd__buf_8_6/X ( sky130_fd_sc_hd__buf_8_6 X )
( sky130_fd_sc_hd__buf_8_124 A )
+ ROUTED met1 ( 787455 212875 ) mcon_170_850
NEW met1 ( 787390 213290 ) ( 787510 * )
NEW met2 ( 787455 213370 ) ( * 222360 )
NEW met2 ( 787455 222500 ) ( 787575 * )
NEW met2 ( 787515 222590 ) via_260_260_hv
NEW met2 ( 787455 222680 ) ( 787575 * )
NEW met2 ( 787455 222820 ) ( * 232275 )
NEW met1 ( 787715 222650 ) ( 2260650 * ) ( * 222710 )
via_260_260_hv ( * 222800 ) ( 2260710 * )
NEW met2 ( 2260590 222940 ) ( * 232415 )
NEW met2 ( 2260590 222620 ) ( 2260710 * )
NEW met2 ( 2260590 213110 ) ( * 222480 )
NEW met2 ( 2260300 212970 ) ( 2261250 * )
NEW met2 ( 2260775 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2260300 212790 ) ( 2261250 * )
NEW met1 ( 787390 212460 ) ( 787510 * )
NEW met1 ( 787450 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[30] ( sky130_fd_sc_hd__buf_8_6 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 662825 222370 ) ( 666370 * )
NEW met1 ( 666370 222510 ) ( 783650 * ) ( * 222570 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
via_260_260_hv ( * 222660 ) ( 783710 * )
NEW met2 ( 783590 222800 ) ( * 232275 )
NEW met2 ( 783590 222480 ) ( 783710 * )
NEW met2 ( 783590 213110 ) ( * 222340 )
NEW met2 ( 783300 212970 ) ( 784250 * )
NEW met2 ( 783775 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 783300 212790 ) ( 784250 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[30] ( sky130_fd_sc_hd__buf_8_5 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 661685 222790 ) ( 778290 * ) ( * 222850 )
via_260_260_hv ( * 222940 ) ( 778350 * )
NEW met2 ( 778230 223080 ) ( * 232275 )
NEW met2 ( 778230 222760 ) ( 778350 * )
NEW met2 ( 778230 216430 ) ( * 222620 )
NEW met1 ( 778180 216350 ) ( 778300 * )
NEW met1 ( 778180 215520 ) ( 778300 * )
NEW met1 ( 778240 215935 ) via_260_850_vh
NEW met1 ( 778245 215935 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_5/A ( sky130_fd_sc_hd__buf_8_5 A )
( sky130_fd_sc_hd__buf_8_123 X )
+ ROUTED met1 ( 782425 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 781950 216030 ) ( 782900 * )
NEW met2 ( 782445 216170 ) ( * 222640 )
NEW met2 ( 782445 222780 ) ( 782565 * )
NEW met2 ( 782505 222870 ) via_260_260_hv
NEW met2 ( 782445 222960 ) ( 782565 * )
NEW met2 ( 782445 223100 ) ( * 232275 )
NEW met1 ( 782705 222930 ) ( 2255290 * ) ( * 222990 )
via_260_260_hv ( * 223080 ) ( 2255350 * )
NEW met2 ( 2255230 223220 ) ( * 232415 )
NEW met2 ( 2255230 222900 ) ( 2255350 * )
NEW met2 ( 2255230 216430 ) ( * 222760 )
NEW met1 ( 2255180 216350 ) ( 2255300 * )
NEW met1 ( 2255180 215520 ) ( 2255300 * )
NEW met1 ( 2255240 215935 ) via_260_850_vh
NEW met1 ( 2255245 215935 ) mcon_170_850
NEW met2 ( 781950 215850 ) ( 782900 * )
NEW li1 ( 781965 215965 ) ( 782885 * ) ;
- sky130_fd_sc_hd__buf_8_4/X ( sky130_fd_sc_hd__buf_8_4 X )
( sky130_fd_sc_hd__buf_8_122 A )
+ ROUTED met1 ( 781475 212875 ) mcon_170_850
NEW met1 ( 781410 213290 ) ( 781530 * )
NEW met2 ( 781475 213370 ) ( * 223200 )
NEW met2 ( 781475 223340 ) ( 781595 * )
NEW met2 ( 781535 223430 ) via_260_260_hv
NEW met2 ( 781475 223520 ) ( 781595 * )
NEW met2 ( 781475 223660 ) ( * 232275 )
NEW met1 ( 781735 223490 ) ( 2254670 * ) ( * 223550 )
via_260_260_hv ( * 223640 ) ( 2254730 * )
NEW met2 ( 2254610 223780 ) ( * 232415 )
NEW met2 ( 2254610 223460 ) ( 2254730 * )
NEW met2 ( 2254610 213110 ) ( * 223320 )
NEW met2 ( 2254320 212970 ) ( 2255270 * )
NEW met2 ( 2254795 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2254320 212790 ) ( 2255270 * )
NEW met1 ( 781410 212460 ) ( 781530 * )
NEW met1 ( 781470 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[29] ( sky130_fd_sc_hd__buf_8_4 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 660825 223210 ) ( 664330 * )
NEW met1 ( 664330 223350 ) ( 777670 * ) ( * 223410 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
via_260_260_hv ( * 223500 ) ( 777730 * )
NEW met2 ( 777610 223640 ) ( * 232275 )
NEW met2 ( 777610 223320 ) ( 777730 * )
NEW met2 ( 777610 213110 ) ( * 223180 )
NEW met2 ( 777320 212970 ) ( 778270 * )
NEW met2 ( 777795 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 777320 212790 ) ( 778270 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[28] ( sky130_fd_sc_hd__buf_8_3 X )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
+ ROUTED met1 ( 657685 224470 ) ( 766330 * ) ( * 224530 )
via_260_260_hv ( * 224620 ) ( 766390 * )
NEW met2 ( 766270 224760 ) ( * 232275 )
NEW met2 ( 766270 224440 ) ( 766390 * )
NEW met2 ( 766270 216430 ) ( * 224300 )
NEW met1 ( 766220 216350 ) ( 766340 * )
NEW met1 ( 766220 215520 ) ( 766340 * )
NEW met1 ( 766280 215935 ) via_260_850_vh
NEW met1 ( 766285 215935 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_3/A ( sky130_fd_sc_hd__buf_8_3 A )
( sky130_fd_sc_hd__buf_8_118 X )
+ ROUTED met1 ( 770465 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 769990 216030 ) ( 770940 * )
NEW met2 ( 770485 216170 ) ( * 224320 )
NEW met2 ( 770485 224460 ) ( 770605 * )
NEW met2 ( 770545 224550 ) via_260_260_hv
NEW met2 ( 770485 224640 ) ( 770605 * )
NEW met2 ( 770485 224780 ) ( * 232275 )
NEW met1 ( 770745 224610 ) ( 2243330 * ) ( * 224670 )
via_260_260_hv ( * 224760 ) ( 2243390 * )
NEW met2 ( 2243270 224900 ) ( * 232415 )
NEW met2 ( 2243270 224580 ) ( 2243390 * )
NEW met2 ( 2243270 216430 ) ( * 224440 )
NEW met1 ( 2243220 216350 ) ( 2243340 * )
NEW met1 ( 2243220 215520 ) ( 2243340 * )
NEW met1 ( 2243280 215935 ) via_260_850_vh
NEW met1 ( 2243285 215935 ) mcon_170_850
NEW met2 ( 769990 215850 ) ( 770940 * )
NEW li1 ( 770005 215965 ) ( 770925 * ) ;
- sky130_fd_sc_hd__buf_8_2/X ( sky130_fd_sc_hd__buf_8_2 X )
( sky130_fd_sc_hd__buf_8_119 A )
+ ROUTED met1 ( 769515 212875 ) mcon_170_850
NEW met1 ( 769450 213290 ) ( 769570 * )
NEW met2 ( 769515 213370 ) ( * 224880 )
NEW met2 ( 769515 225020 ) ( 769635 * )
NEW met2 ( 769575 225110 ) via_260_260_hv
NEW met2 ( 769515 225200 ) ( 769635 * )
NEW met2 ( 769515 225340 ) ( * 232275 )
NEW met1 ( 769775 225170 ) ( 2242710 * ) ( * 225230 )
via_260_260_hv ( * 225320 ) ( 2242770 * )
NEW met2 ( 2242650 225460 ) ( * 232415 )
NEW met2 ( 2242650 225140 ) ( 2242770 * )
NEW met2 ( 2242650 213110 ) ( * 225000 )
NEW met2 ( 2242360 212970 ) ( 2243310 * )
NEW met2 ( 2242835 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2242360 212790 ) ( 2243310 * )
NEW met1 ( 769450 212460 ) ( 769570 * )
NEW met1 ( 769510 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[27] ( sky130_fd_sc_hd__buf_8_2 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 656825 224890 ) ( 660300 * )
NEW met1 ( 660300 225030 ) ( 765710 * ) ( * 225090 )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
via_260_260_hv ( * 225180 ) ( 765770 * )
NEW met2 ( 765650 225320 ) ( * 232275 )
NEW met2 ( 765650 225000 ) ( 765770 * )
NEW met2 ( 765650 213110 ) ( * 224860 )
NEW met2 ( 765360 212970 ) ( 766310 * )
NEW met2 ( 765835 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 765360 212790 ) ( 766310 * ) ;
- sky130_fd_sc_hd__buf_8_1/X ( sky130_fd_sc_hd__buf_8_1 X )
( sky130_fd_sc_hd__buf_8_129 A )
+ ROUTED met1 ( 670605 215935 ) mcon_170_850
NEW met1 ( 670540 216350 ) ( 670660 * )
NEW met2 ( 670590 216430 ) ( * 237740 )
NEW met2 ( 670590 237880 ) ( 670710 * )
NEW met2 ( 670650 237970 ) via_260_260_hv
NEW met2 ( 670590 238060 ) ( 670710 * )
NEW met2 ( 670590 238200 ) ( * 238155 )
NEW met1 ( 226785 237910 ) ( 670450 * )
NEW met1 ( 226785 238050 ) ( * 1673705 )
NEW met1 ( 226785 1673845 ) ( 226905 * )
NEW met1 ( 226845 1673935 ) via_260_260_vh
NEW met1 ( 226785 1674025 ) ( 226905 * )
NEW met2 ( 227045 1673875 ) ( 227030 * )
NEW met2 ( 203475 1673875 ) ( 226645 * )
NEW met1 ( 203215 1674595 ) ( 203335 * )
NEW met1 ( 203215 1673525 ) ( 203335 * )
NEW met1 ( 203275 1674060 ) via_260_1090_vh
NEW met1 ( 203270 1674060 ) mcon_170_1090
NEW met1 ( 670540 215520 ) ( 670660 * )
NEW met1 ( 670600 215935 ) via_260_850_vh ;
- sky130_fd_sc_hd__buf_8_1/A ( sky130_fd_sc_hd__buf_8_1 A )
( sky130_fd_sc_hd__buf_8_86 X )
+ ROUTED met1 ( 674785 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 674310 216030 ) ( 675260 * )
NEW met2 ( 674805 216170 ) ( * 237760 )
NEW met2 ( 674805 237900 ) ( 674925 * )
NEW met2 ( 674865 237990 ) via_260_260_hv
NEW met2 ( 674805 238080 ) ( 674925 * )
NEW met2 ( 674805 238220 ) ( * 238155 )
NEW met1 ( 675065 238050 ) ( 706275 * )
NEW met1 ( 706275 235390 ) ( * 237910 )
NEW met1 ( 706275 235250 ) ( 778085 * )
NEW met1 ( 778085 235390 ) ( * 237910 )
NEW met1 ( 778085 238050 ) ( 2147650 * ) ( * 238110 )
via_260_260_hv ( * 238200 ) ( 2147710 * )
NEW met2 ( 2147590 238340 ) ( * 238295 )
NEW met2 ( 2147590 238020 ) ( 2147710 * )
NEW met2 ( 2147590 216430 ) ( * 237880 )
NEW met1 ( 2147540 216350 ) ( 2147660 * )
NEW met1 ( 2147540 215520 ) ( 2147660 * )
NEW met1 ( 2147600 215935 ) via_260_850_vh
NEW met1 ( 2147605 215935 ) mcon_170_850
NEW met2 ( 674310 215850 ) ( 675260 * )
NEW li1 ( 674325 215965 ) ( 675245 * ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- vccd ( sky130_fd_sc_hd__tapvpwrvgnd_1_217 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_215 VPWR )
( sky130_fd_sc_hd__buf_8_197 VPB )
( sky130_fd_sc_hd__buf_8_197 VPWR )
( sky130_fd_sc_hd__buf_8_193 VPWR )
( sky130_fd_sc_hd__buf_8_196 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_214 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_213 VPWR )
( sky130_fd_sc_hd__buf_8_195 VPB )
( sky130_fd_sc_hd__buf_8_195 VPWR )
( sky130_fd_sc_hd__buf_8_191 VPWR )
( sky130_fd_sc_hd__buf_8_180 VPWR )
( sky130_fd_sc_hd__buf_8_194 VPWR )
( sky130_fd_sc_hd__buf_8_194 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_216 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_280 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_211 VPWR )
( sky130_fd_sc_hd__buf_8_193 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_210 VPWR )
( sky130_fd_sc_hd__buf_8_192 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_209 VPWR )
( sky130_fd_sc_hd__buf_8_191 VPB )
( sky130_fd_sc_hd__buf_8_180 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_208 VPWR )
( sky130_fd_sc_hd__buf_8_196 VPWR )
( sky130_fd_sc_hd__buf_8_192 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_15 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_285 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_11 VPWR )
( sky130_fd_sc_hd__buf_8_10 VPWR )
( sky130_fd_sc_hd__buf_8_10 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_40 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_14 VPWR )
( sky130_fd_sc_hd__buf_8_11 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_284 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_282 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_79 VPWR )
( sky130_ef_sc_hd__decap_12_79 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_283 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_78 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_281 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_80 VPWR )
( sky130_ef_sc_hd__decap_12_80 VPB )
( sky130_ef_sc_hd__decap_12_81 VPWR )
( sky130_ef_sc_hd__decap_12_81 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_212 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_78 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_286 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_41 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_77 VPWR )
( sky130_ef_sc_hd__decap_12_77 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_47 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_46 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_290 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_43 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_42 VPWR )
( sky130_fd_sc_hd__buf_8_43 VPB )
( sky130_fd_sc_hd__buf_8_42 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_49 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_48 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_44 VPWR )
( sky130_fd_sc_hd__buf_8_38 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_44 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_38 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_287 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_50 VPWR )
( sky130_fd_sc_hd__buf_8_45 VPWR )
( sky130_fd_sc_hd__buf_8_39 VPWR )
( sky130_fd_sc_hd__buf_8_45 VPB )
( sky130_fd_sc_hd__buf_8_39 VPB )
( sky130_fd_sc_hd__buf_8_43 VPWR )
( sky130_fd_sc_hd__buf_8_42 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_289 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_74 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_51 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_76 VPWR )
( sky130_ef_sc_hd__decap_12_76 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_288 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_75 VPWR )
( sky130_ef_sc_hd__decap_12_75 VPB )
( sky130_ef_sc_hd__decap_12_74 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_295 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_198 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_199 VPWR )
( sky130_ef_sc_hd__decap_12_69 VPWR )
( sky130_ef_sc_hd__decap_12_69 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_296 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_70 VPWR )
( sky130_ef_sc_hd__decap_12_70 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_184 VPWR )
( sky130_fd_sc_hd__buf_8_184 VPB )
( sky130_fd_sc_hd__buf_8_183 VPWR )
( sky130_fd_sc_hd__buf_8_183 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_197 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_196 VPWR )
( sky130_fd_sc_hd__buf_8_182 VPWR )
( sky130_fd_sc_hd__buf_8_182 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_181 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_181 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_294 VPWR )
( sky130_ef_sc_hd__decap_12_71 VPWR )
( sky130_ef_sc_hd__decap_12_71 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_293 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_72 VPWR )
( sky130_ef_sc_hd__decap_12_72 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_292 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_73 VPWR )
( sky130_ef_sc_hd__decap_12_73 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_291 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_207 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_206 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_190 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_190 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_189 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_189 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_205 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_204 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_188 VPWR )
( sky130_fd_sc_hd__buf_8_188 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_187 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_187 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_203 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_202 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_186 VPWR )
( sky130_fd_sc_hd__buf_8_186 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_185 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_185 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_201 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_200 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_37 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_36 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_279 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_44 VPWR )
( sky130_fd_sc_hd__buf_8_33 VPWR )
( sky130_fd_sc_hd__buf_8_33 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_45 VPWR )
( sky130_fd_sc_hd__buf_8_32 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_32 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_40 VPWR )
( sky130_fd_sc_hd__buf_8_40 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_276 VPWR )
( sky130_fd_sc_hd__buf_8_41 VPWR )
( sky130_fd_sc_hd__buf_8_41 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_84 VPWR )
( sky130_ef_sc_hd__decap_12_84 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_35 VPWR )
( sky130_ef_sc_hd__decap_12_82 VPWR )
( sky130_ef_sc_hd__decap_12_82 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_34 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_33 VPWR )
( sky130_fd_sc_hd__buf_8_31 VPWR )
( sky130_fd_sc_hd__buf_8_31 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_32 VPWR )
( sky130_fd_sc_hd__buf_8_30 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_30 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_278 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_277 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_83 VPWR )
( sky130_ef_sc_hd__decap_12_83 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_31 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_29 VPWR )
( sky130_fd_sc_hd__buf_8_29 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_30 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_28 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_27 VPWR )
( sky130_fd_sc_hd__buf_8_27 VPB )
( sky130_fd_sc_hd__buf_8_26 VPWR )
( sky130_fd_sc_hd__buf_8_26 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_1 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_29 VPWR )
( sky130_fd_sc_hd__buf_8_24 VPWR )
( sky130_fd_sc_hd__buf_8_24 VPB )
( sky130_fd_sc_hd__buf_8_25 VPWR )
( sky130_fd_sc_hd__buf_8_25 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_272 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_28 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_28 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_0 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_87 VPB )
( sky130_ef_sc_hd__decap_12_85 VPWR )
( sky130_ef_sc_hd__decap_12_85 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_275 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_86 VPWR )
( sky130_ef_sc_hd__decap_12_86 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_274 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_87 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_307 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_173 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_58 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_172 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_308 VPWR )
( sky130_fd_sc_hd__buf_8_159 VPWR )
( sky130_fd_sc_hd__buf_8_158 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_58 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_305 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_60 VPWR )
( sky130_ef_sc_hd__decap_12_60 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_175 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_174 VPWR )
( sky130_fd_sc_hd__buf_8_159 VPB )
( sky130_fd_sc_hd__buf_8_158 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_177 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_176 VPWR )
( sky130_fd_sc_hd__buf_8_161 VPWR )
( sky130_fd_sc_hd__buf_8_160 VPWR )
( sky130_fd_sc_hd__buf_8_161 VPB )
( sky130_fd_sc_hd__buf_8_160 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_306 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_59 VPWR )
( sky130_ef_sc_hd__decap_12_59 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_179 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_178 VPWR )
( sky130_fd_sc_hd__buf_8_163 VPWR )
( sky130_fd_sc_hd__buf_8_162 VPWR )
( sky130_fd_sc_hd__buf_8_163 VPB )
( sky130_fd_sc_hd__buf_8_162 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_303 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_62 VPWR )
( sky130_ef_sc_hd__decap_12_62 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_181 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_180 VPWR )
( sky130_fd_sc_hd__buf_8_165 VPWR )
( sky130_fd_sc_hd__buf_8_164 VPWR )
( sky130_fd_sc_hd__buf_8_165 VPB )
( sky130_fd_sc_hd__buf_8_164 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_304 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_61 VPWR )
( sky130_ef_sc_hd__decap_12_61 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_301 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_64 VPWR )
( sky130_ef_sc_hd__decap_12_64 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_302 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_63 VPWR )
( sky130_ef_sc_hd__decap_12_63 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_300 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_66 VPWR )
( sky130_ef_sc_hd__decap_12_66 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_298 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_65 VPWR )
( sky130_ef_sc_hd__decap_12_65 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_299 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_67 VPWR )
( sky130_ef_sc_hd__decap_12_67 VPB )
( sky130_ef_sc_hd__decap_12_68 VPWR )
( sky130_ef_sc_hd__decap_12_68 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_297 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_183 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_182 VPWR )
( sky130_fd_sc_hd__buf_8_167 VPWR )
( sky130_fd_sc_hd__buf_8_166 VPWR )
( sky130_fd_sc_hd__buf_8_167 VPB )
( sky130_fd_sc_hd__buf_8_166 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_185 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_184 VPWR )
( sky130_fd_sc_hd__buf_8_169 VPWR )
( sky130_fd_sc_hd__buf_8_168 VPWR )
( sky130_fd_sc_hd__buf_8_169 VPB )
( sky130_fd_sc_hd__buf_8_168 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_187 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_186 VPWR )
( sky130_fd_sc_hd__buf_8_171 VPWR )
( sky130_fd_sc_hd__buf_8_170 VPWR )
( sky130_fd_sc_hd__buf_8_171 VPB )
( sky130_fd_sc_hd__buf_8_170 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_189 VPWR )
( sky130_fd_sc_hd__buf_8_173 VPWR )
( sky130_fd_sc_hd__buf_8_172 VPWR )
( sky130_fd_sc_hd__buf_8_173 VPB )
( sky130_fd_sc_hd__buf_8_172 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_188 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_193 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_191 VPWR )
( sky130_fd_sc_hd__buf_8_175 VPWR )
( sky130_fd_sc_hd__buf_8_174 VPWR )
( sky130_fd_sc_hd__buf_8_175 VPB )
( sky130_fd_sc_hd__buf_8_174 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_192 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_190 VPWR )
( sky130_fd_sc_hd__buf_8_177 VPWR )
( sky130_fd_sc_hd__buf_8_176 VPWR )
( sky130_fd_sc_hd__buf_8_177 VPB )
( sky130_fd_sc_hd__buf_8_176 VPB )
( sky130_fd_sc_hd__buf_8_178 VPWR )
( sky130_fd_sc_hd__buf_8_178 VPB )
( sky130_fd_sc_hd__buf_8_179 VPWR )
( sky130_fd_sc_hd__buf_8_179 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_194 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_195 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_27 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_26 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_25 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_24 VPWR )
( sky130_fd_sc_hd__buf_8_23 VPWR )
( sky130_fd_sc_hd__buf_8_22 VPWR )
( sky130_fd_sc_hd__buf_8_23 VPB )
( sky130_fd_sc_hd__buf_8_22 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_273 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_325 VPWR )
( sky130_ef_sc_hd__decap_12_88 VPWR )
( sky130_ef_sc_hd__decap_12_88 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_19 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_18 VPWR )
( sky130_fd_sc_hd__buf_8_17 VPWR )
( sky130_fd_sc_hd__buf_8_16 VPWR )
( sky130_fd_sc_hd__buf_8_17 VPB )
( sky130_fd_sc_hd__buf_8_16 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_270 VPWR )
( sky130_ef_sc_hd__decap_12_90 VPWR )
( sky130_ef_sc_hd__decap_12_90 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_23 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_22 VPWR )
( sky130_fd_sc_hd__buf_8_21 VPWR )
( sky130_fd_sc_hd__buf_8_20 VPWR )
( sky130_fd_sc_hd__buf_8_21 VPB )
( sky130_fd_sc_hd__buf_8_20 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_271 VPWR )
( sky130_ef_sc_hd__decap_12_89 VPWR )
( sky130_ef_sc_hd__decap_12_89 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_21 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_20 VPWR )
( sky130_fd_sc_hd__buf_8_19 VPWR )
( sky130_fd_sc_hd__buf_8_18 VPWR )
( sky130_fd_sc_hd__buf_8_19 VPB )
( sky130_fd_sc_hd__buf_8_18 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_268 VPWR )
( sky130_ef_sc_hd__decap_12_92 VPWR )
( sky130_ef_sc_hd__decap_12_92 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_15 VPWR )
( sky130_fd_sc_hd__buf_8_15 VPB )
( sky130_fd_sc_hd__buf_8_14 VPWR )
( sky130_fd_sc_hd__buf_8_14 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_17 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_16 VPWR )
( sky130_fd_sc_hd__buf_8_37 VPWR )
( sky130_fd_sc_hd__buf_8_37 VPB )
( sky130_fd_sc_hd__buf_8_36 VPWR )
( sky130_fd_sc_hd__buf_8_36 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_39 VPWR )
( sky130_fd_sc_hd__buf_8_35 VPWR )
( sky130_fd_sc_hd__buf_8_35 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_38 VPWR )
( sky130_fd_sc_hd__buf_8_34 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_34 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_62 VPWR )
( sky130_fd_sc_hd__buf_8_52 VPWR )
( sky130_fd_sc_hd__buf_8_52 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_63 VPWR )
( sky130_fd_sc_hd__buf_8_53 VPWR )
( sky130_fd_sc_hd__buf_8_53 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_60 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_61 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_58 VPWR )
( sky130_fd_sc_hd__buf_8_50 VPWR )
( sky130_fd_sc_hd__buf_8_50 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_59 VPWR )
( sky130_fd_sc_hd__buf_8_51 VPWR )
( sky130_fd_sc_hd__buf_8_51 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_56 VPWR )
( sky130_fd_sc_hd__buf_8_48 VPWR )
( sky130_fd_sc_hd__buf_8_48 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_57 VPWR )
( sky130_fd_sc_hd__buf_8_49 VPWR )
( sky130_fd_sc_hd__buf_8_49 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_54 VPWR )
( sky130_fd_sc_hd__buf_8_47 VPWR )
( sky130_fd_sc_hd__buf_8_47 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_55 VPWR )
( sky130_fd_sc_hd__buf_8_46 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_46 VPB )
( sky130_fd_sc_hd__buf_8_12 VPWR )
( sky130_fd_sc_hd__buf_8_12 VPB )
( sky130_fd_sc_hd__buf_8_13 VPWR )
( sky130_fd_sc_hd__buf_8_13 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_53 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_261 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_91 VPWR )
( sky130_ef_sc_hd__decap_12_91 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_269 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_94 VPWR )
( sky130_ef_sc_hd__decap_12_94 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_266 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_93 VPWR )
( sky130_ef_sc_hd__decap_12_93 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_267 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_95 VPWR )
( sky130_ef_sc_hd__decap_12_95 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_265 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_263 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_97 VPWR )
( sky130_ef_sc_hd__decap_12_97 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_264 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_96 VPWR )
( sky130_ef_sc_hd__decap_12_96 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_52 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_99 VPWR )
( sky130_ef_sc_hd__decap_12_99 VPB )
( sky130_ef_sc_hd__decap_12_98 VPWR )
( sky130_ef_sc_hd__decap_12_98 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_262 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_324 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_168 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_55 VPWR )
( sky130_ef_sc_hd__decap_12_55 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_169 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_322 VPWR )
( sky130_fd_sc_hd__buf_8_157 VPWR )
( sky130_fd_sc_hd__buf_8_156 VPWR )
( sky130_fd_sc_hd__buf_8_157 VPB )
( sky130_fd_sc_hd__buf_8_156 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_321 VPWR )
( sky130_ef_sc_hd__decap_12_54 VPWR )
( sky130_ef_sc_hd__decap_12_54 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_171 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_170 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_323 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_163 VPWR )
( sky130_fd_sc_hd__buf_8_151 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_0 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_151 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_0 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_162 VPWR )
Made a minor correction to the layout to remove an extra unused buffer. This does not affect ongoing top-level routing work, but is needed for LVS.
2022-10-16 16:57:14 -05:00
( sky130_ef_sc_hd__decap_12_100 VPWR )
( sky130_ef_sc_hd__decap_12_100 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_165 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_164 VPWR )
( sky130_fd_sc_hd__buf_8_153 VPWR )
( sky130_fd_sc_hd__buf_8_152 VPWR )
( sky130_fd_sc_hd__buf_8_153 VPB )
( sky130_fd_sc_hd__buf_8_152 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_319 VPWR )
( sky130_ef_sc_hd__decap_12_52 VPWR )
( sky130_ef_sc_hd__decap_12_52 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_167 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_166 VPWR )
( sky130_fd_sc_hd__buf_8_155 VPWR )
( sky130_fd_sc_hd__buf_8_154 VPWR )
( sky130_fd_sc_hd__buf_8_155 VPB )
( sky130_fd_sc_hd__buf_8_154 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_320 VPWR )
( sky130_ef_sc_hd__decap_12_53 VPWR )
( sky130_ef_sc_hd__decap_12_53 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_318 VPWR )
( sky130_ef_sc_hd__decap_12_51 VPWR )
( sky130_ef_sc_hd__decap_12_51 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_317 VPWR )
( sky130_ef_sc_hd__decap_12_50 VPWR )
( sky130_ef_sc_hd__decap_12_50 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_315 VPWR )
( sky130_ef_sc_hd__decap_12_48 VPWR )
( sky130_ef_sc_hd__decap_12_48 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_316 VPWR )
( sky130_ef_sc_hd__decap_12_49 VPWR )
( sky130_ef_sc_hd__decap_12_49 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_314 VPWR )
( sky130_ef_sc_hd__decap_12_47 VPWR )
( sky130_ef_sc_hd__decap_12_47 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_313 VPWR )
( sky130_ef_sc_hd__decap_12_45 VPWR )
( sky130_ef_sc_hd__decap_12_45 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_311 VPWR )
( sky130_ef_sc_hd__decap_12_46 VPWR )
( sky130_ef_sc_hd__decap_12_46 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_312 VPWR )
( sky130_ef_sc_hd__decap_12_44 VPWR )
( sky130_ef_sc_hd__decap_12_44 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_310 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_56 VPWR )
( sky130_ef_sc_hd__decap_12_56 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_141 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_57 VPWR )
( sky130_ef_sc_hd__decap_12_57 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_157 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_156 VPWR )
( sky130_fd_sc_hd__buf_8_145 VPWR )
( sky130_fd_sc_hd__buf_8_144 VPWR )
( sky130_fd_sc_hd__buf_8_145 VPB )
( sky130_fd_sc_hd__buf_8_144 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_159 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_158 VPWR )
( sky130_fd_sc_hd__buf_8_147 VPWR )
( sky130_fd_sc_hd__buf_8_146 VPWR )
( sky130_fd_sc_hd__buf_8_147 VPB )
( sky130_fd_sc_hd__buf_8_146 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_161 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_160 VPWR )
( sky130_fd_sc_hd__buf_8_149 VPWR )
( sky130_fd_sc_hd__buf_8_148 VPWR )
( sky130_fd_sc_hd__buf_8_149 VPB )
( sky130_fd_sc_hd__buf_8_148 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_153 VPWR )
( sky130_fd_sc_hd__buf_8_141 VPWR )
( sky130_fd_sc_hd__buf_8_140 VPWR )
( sky130_fd_sc_hd__buf_8_141 VPB )
( sky130_fd_sc_hd__buf_8_140 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_152 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_155 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_154 VPWR )
( sky130_fd_sc_hd__buf_8_143 VPWR )
( sky130_fd_sc_hd__buf_8_142 VPWR )
( sky130_fd_sc_hd__buf_8_143 VPB )
( sky130_fd_sc_hd__buf_8_142 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_147 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_146 VPWR )
( sky130_fd_sc_hd__buf_8_135 VPWR )
( sky130_fd_sc_hd__buf_8_134 VPWR )
( sky130_fd_sc_hd__buf_8_135 VPB )
( sky130_fd_sc_hd__buf_8_134 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_149 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_148 VPWR )
( sky130_fd_sc_hd__buf_8_137 VPWR )
( sky130_fd_sc_hd__buf_8_136 VPWR )
( sky130_fd_sc_hd__buf_8_137 VPB )
( sky130_fd_sc_hd__buf_8_136 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_151 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_150 VPWR )
( sky130_fd_sc_hd__buf_8_139 VPWR )
( sky130_fd_sc_hd__buf_8_138 VPWR )
( sky130_fd_sc_hd__buf_8_139 VPB )
( sky130_fd_sc_hd__buf_8_138 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_145 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_144 VPWR )
( sky130_fd_sc_hd__buf_8_133 VPWR )
( sky130_fd_sc_hd__buf_8_132 VPWR )
( sky130_fd_sc_hd__buf_8_133 VPB )
( sky130_fd_sc_hd__buf_8_132 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_143 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_142 VPWR )
( sky130_fd_sc_hd__buf_8_131 VPWR )
( sky130_fd_sc_hd__buf_8_130 VPWR )
( sky130_fd_sc_hd__buf_8_131 VPB )
( sky130_fd_sc_hd__buf_8_130 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_309 VPWR )
( sky130_fd_sc_hd__buf_8_129 VPWR )
( sky130_fd_sc_hd__buf_8_128 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_140 VPWR )
( sky130_fd_sc_hd__buf_8_129 VPB )
( sky130_fd_sc_hd__buf_8_128 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_237 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_235 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_20 VPWR )
( sky130_ef_sc_hd__decap_12_20 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_236 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_19 VPWR )
( sky130_ef_sc_hd__decap_12_19 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_233 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_17 VPWR )
( sky130_ef_sc_hd__decap_12_17 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_234 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_18 VPWR )
( sky130_ef_sc_hd__decap_12_18 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_232 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_16 VPWR )
( sky130_ef_sc_hd__decap_12_16 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_231 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_15 VPWR )
( sky130_ef_sc_hd__decap_12_15 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_230 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_14 VPWR )
( sky130_ef_sc_hd__decap_12_14 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_228 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_12 VPWR )
( sky130_ef_sc_hd__decap_12_12 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_229 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_13 VPWR )
( sky130_ef_sc_hd__decap_12_13 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_227 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_11 VPWR )
( sky130_ef_sc_hd__decap_12_11 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_221 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_5 VPWR )
( sky130_ef_sc_hd__decap_12_5 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_226 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_10 VPWR )
( sky130_ef_sc_hd__decap_12_10 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_225 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_9 VPWR )
( sky130_ef_sc_hd__decap_12_9 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_224 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_8 VPWR )
( sky130_ef_sc_hd__decap_12_8 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_223 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_7 VPWR )
( sky130_ef_sc_hd__decap_12_7 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_222 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_6 VPWR )
( sky130_ef_sc_hd__decap_12_6 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_2 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_0 VPWR )
( sky130_ef_sc_hd__decap_12_0 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_220 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_4 VPWR )
( sky130_ef_sc_hd__decap_12_4 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_219 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_3 VPWR )
( sky130_ef_sc_hd__decap_12_3 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_218 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_2 VPWR )
( sky130_ef_sc_hd__decap_12_2 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_239 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_22 VPWR )
( sky130_ef_sc_hd__decap_12_22 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_326 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_43 VPWR )
( sky130_ef_sc_hd__decap_12_43 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_260 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_41 VPWR )
( sky130_ef_sc_hd__decap_12_41 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_258 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_259 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_42 VPWR )
( sky130_ef_sc_hd__decap_12_42 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_255 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_38 VPWR )
( sky130_ef_sc_hd__decap_12_38 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_257 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_40 VPWR )
( sky130_ef_sc_hd__decap_12_40 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_256 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_39 VPWR )
( sky130_ef_sc_hd__decap_12_39 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_254 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_37 VPWR )
( sky130_ef_sc_hd__decap_12_37 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_252 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_35 VPWR )
( sky130_ef_sc_hd__decap_12_35 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_253 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_36 VPWR )
( sky130_ef_sc_hd__decap_12_36 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_251 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_33 VPWR )
( sky130_ef_sc_hd__decap_12_33 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_250 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_34 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_248 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_31 VPWR )
( sky130_ef_sc_hd__decap_12_31 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_249 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_32 VPWR )
( sky130_ef_sc_hd__decap_12_32 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_247 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_30 VPWR )
( sky130_ef_sc_hd__decap_12_30 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_245 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_28 VPWR )
( sky130_ef_sc_hd__decap_12_28 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_246 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_29 VPWR )
( sky130_ef_sc_hd__decap_12_29 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_244 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_27 VPWR )
( sky130_ef_sc_hd__decap_12_27 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_243 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_25 VPWR )
( sky130_ef_sc_hd__decap_12_25 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_242 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_26 VPWR )
( sky130_ef_sc_hd__decap_12_26 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_240 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_23 VPWR )
( sky130_ef_sc_hd__decap_12_23 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_241 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_24 VPWR )
( sky130_ef_sc_hd__decap_12_24 VPB )
( sky130_ef_sc_hd__decap_12_34 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_139 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_136 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_138 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_135 VPWR )
( sky130_fd_sc_hd__buf_8_127 VPWR )
( sky130_fd_sc_hd__buf_8_125 VPWR )
( sky130_fd_sc_hd__buf_8_127 VPB )
( sky130_fd_sc_hd__buf_8_125 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_137 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_134 VPWR )
( sky130_fd_sc_hd__buf_8_126 VPWR )
( sky130_fd_sc_hd__buf_8_124 VPWR )
( sky130_fd_sc_hd__buf_8_126 VPB )
( sky130_fd_sc_hd__buf_8_124 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_133 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_132 VPWR )
( sky130_fd_sc_hd__buf_8_123 VPWR )
( sky130_fd_sc_hd__buf_8_122 VPWR )
( sky130_fd_sc_hd__buf_8_123 VPB )
( sky130_fd_sc_hd__buf_8_122 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_131 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_130 VPWR )
( sky130_fd_sc_hd__buf_8_121 VPWR )
( sky130_fd_sc_hd__buf_8_120 VPWR )
( sky130_fd_sc_hd__buf_8_121 VPB )
( sky130_fd_sc_hd__buf_8_120 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_129 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_128 VPWR )
( sky130_fd_sc_hd__buf_8_119 VPWR )
( sky130_fd_sc_hd__buf_8_118 VPWR )
( sky130_fd_sc_hd__buf_8_119 VPB )
( sky130_fd_sc_hd__buf_8_118 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_127 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_126 VPWR )
( sky130_fd_sc_hd__buf_8_117 VPWR )
( sky130_fd_sc_hd__buf_8_116 VPWR )
( sky130_fd_sc_hd__buf_8_117 VPB )
( sky130_fd_sc_hd__buf_8_116 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_125 VPWR )
( sky130_fd_sc_hd__buf_8_115 VPWR )
( sky130_fd_sc_hd__buf_8_114 VPWR )
( sky130_fd_sc_hd__buf_8_115 VPB )
( sky130_fd_sc_hd__buf_8_114 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_124 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_123 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_122 VPWR )
( sky130_fd_sc_hd__buf_8_113 VPWR )
( sky130_fd_sc_hd__buf_8_112 VPWR )
( sky130_fd_sc_hd__buf_8_113 VPB )
( sky130_fd_sc_hd__buf_8_112 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_121 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_120 VPWR )
( sky130_fd_sc_hd__buf_8_111 VPWR )
( sky130_fd_sc_hd__buf_8_110 VPWR )
( sky130_fd_sc_hd__buf_8_111 VPB )
( sky130_fd_sc_hd__buf_8_110 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_119 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_118 VPWR )
( sky130_fd_sc_hd__buf_8_109 VPWR )
( sky130_fd_sc_hd__buf_8_108 VPWR )
( sky130_fd_sc_hd__buf_8_109 VPB )
( sky130_fd_sc_hd__buf_8_108 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_117 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_116 VPWR )
( sky130_fd_sc_hd__buf_8_107 VPWR )
( sky130_fd_sc_hd__buf_8_106 VPWR )
( sky130_fd_sc_hd__buf_8_107 VPB )
( sky130_fd_sc_hd__buf_8_106 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_115 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_113 VPWR )
( sky130_fd_sc_hd__buf_8_105 VPWR )
( sky130_fd_sc_hd__buf_8_102 VPWR )
( sky130_fd_sc_hd__buf_8_105 VPB )
( sky130_fd_sc_hd__buf_8_102 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_114 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_112 VPWR )
( sky130_fd_sc_hd__buf_8_104 VPWR )
( sky130_fd_sc_hd__buf_8_101 VPWR )
( sky130_fd_sc_hd__buf_8_104 VPB )
( sky130_fd_sc_hd__buf_8_101 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_111 VPWR )
( sky130_fd_sc_hd__buf_8_103 VPWR )
( sky130_fd_sc_hd__buf_8_100 VPWR )
( sky130_fd_sc_hd__buf_8_103 VPB )
( sky130_fd_sc_hd__buf_8_100 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_108 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_110 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_107 VPWR )
( sky130_fd_sc_hd__buf_8_99 VPWR )
( sky130_fd_sc_hd__buf_8_97 VPWR )
( sky130_fd_sc_hd__buf_8_99 VPB )
( sky130_fd_sc_hd__buf_8_97 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_109 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_106 VPWR )
( sky130_fd_sc_hd__buf_8_98 VPWR )
( sky130_fd_sc_hd__buf_8_96 VPWR )
( sky130_fd_sc_hd__buf_8_98 VPB )
( sky130_fd_sc_hd__buf_8_96 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_103 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_102 VPWR )
( sky130_fd_sc_hd__buf_8_95 VPWR )
( sky130_fd_sc_hd__buf_8_94 VPWR )
( sky130_fd_sc_hd__buf_8_95 VPB )
( sky130_fd_sc_hd__buf_8_94 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_105 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_104 VPWR )
( sky130_fd_sc_hd__buf_8_93 VPWR )
( sky130_fd_sc_hd__buf_8_92 VPWR )
( sky130_fd_sc_hd__buf_8_93 VPB )
( sky130_fd_sc_hd__buf_8_92 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_101 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_100 VPWR )
( sky130_fd_sc_hd__buf_8_91 VPWR )
( sky130_fd_sc_hd__buf_8_90 VPWR )
( sky130_fd_sc_hd__buf_8_91 VPB )
( sky130_fd_sc_hd__buf_8_90 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_99 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_98 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_89 VPWR )
( sky130_fd_sc_hd__buf_8_88 VPWR )
( sky130_fd_sc_hd__buf_8_89 VPB )
( sky130_fd_sc_hd__buf_8_88 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_97 VPWR )
( sky130_fd_sc_hd__buf_8_86 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_1 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_96 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_86 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_1 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_13 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_12 VPWR )
( sky130_fd_sc_hd__buf_8_9 VPWR )
( sky130_fd_sc_hd__buf_8_9 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_8 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_8 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_11 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_10 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_7 VPWR )
( sky130_fd_sc_hd__buf_8_7 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__buf_8_6 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_6 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_9 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_8 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_5 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_4 VPWR )
( sky130_fd_sc_hd__buf_8_5 VPWR )
( sky130_fd_sc_hd__buf_8_4 VPWR )
( sky130_fd_sc_hd__buf_8_5 VPB )
( sky130_fd_sc_hd__buf_8_4 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_95 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_94 VPWR )
( sky130_fd_sc_hd__buf_8_85 VPWR )
( sky130_fd_sc_hd__buf_8_84 VPWR )
( sky130_fd_sc_hd__buf_8_85 VPB )
( sky130_fd_sc_hd__buf_8_84 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_7 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_6 VPWR )
( sky130_fd_sc_hd__buf_8_3 VPWR )
( sky130_fd_sc_hd__buf_8_2 VPWR )
( sky130_fd_sc_hd__buf_8_3 VPB )
( sky130_fd_sc_hd__buf_8_2 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_65 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_64 VPWR )
( sky130_fd_sc_hd__buf_8_55 VPWR )
( sky130_fd_sc_hd__buf_8_54 VPWR )
( sky130_fd_sc_hd__buf_8_55 VPB )
( sky130_fd_sc_hd__buf_8_54 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_67 VPWR )
( sky130_fd_sc_hd__buf_8_57 VPWR )
( sky130_fd_sc_hd__buf_8_56 VPWR )
( sky130_fd_sc_hd__buf_8_57 VPB )
( sky130_fd_sc_hd__buf_8_56 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_66 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_69 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_68 VPWR )
( sky130_fd_sc_hd__buf_8_59 VPWR )
( sky130_fd_sc_hd__buf_8_58 VPWR )
( sky130_fd_sc_hd__buf_8_59 VPB )
( sky130_fd_sc_hd__buf_8_58 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_71 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_70 VPWR )
( sky130_fd_sc_hd__buf_8_61 VPWR )
( sky130_fd_sc_hd__buf_8_60 VPWR )
( sky130_fd_sc_hd__buf_8_61 VPB )
( sky130_fd_sc_hd__buf_8_60 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_73 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_72 VPWR )
( sky130_fd_sc_hd__buf_8_63 VPWR )
( sky130_fd_sc_hd__buf_8_62 VPWR )
( sky130_fd_sc_hd__buf_8_63 VPB )
( sky130_fd_sc_hd__buf_8_62 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_75 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_74 VPWR )
( sky130_fd_sc_hd__buf_8_65 VPWR )
( sky130_fd_sc_hd__buf_8_64 VPWR )
( sky130_fd_sc_hd__buf_8_1 VPB )
( sky130_fd_sc_hd__buf_8_65 VPB )
( sky130_fd_sc_hd__buf_8_64 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_77 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_76 VPWR )
( sky130_fd_sc_hd__buf_8_67 VPWR )
( sky130_fd_sc_hd__buf_8_66 VPWR )
( sky130_fd_sc_hd__buf_8_67 VPB )
( sky130_fd_sc_hd__buf_8_66 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_79 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_78 VPWR )
( sky130_fd_sc_hd__buf_8_69 VPWR )
( sky130_fd_sc_hd__buf_8_68 VPWR )
( sky130_fd_sc_hd__buf_8_69 VPB )
( sky130_fd_sc_hd__buf_8_68 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_81 VPWR )
( sky130_fd_sc_hd__buf_8_71 VPWR )
( sky130_fd_sc_hd__buf_8_70 VPWR )
( sky130_fd_sc_hd__buf_8_71 VPB )
( sky130_fd_sc_hd__buf_8_70 VPB )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_80 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_83 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_82 VPWR )
( sky130_fd_sc_hd__buf_8_73 VPWR )
( sky130_fd_sc_hd__buf_8_72 VPWR )
( sky130_fd_sc_hd__buf_8_73 VPB )
( sky130_fd_sc_hd__buf_8_72 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_85 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_84 VPWR )
( sky130_fd_sc_hd__buf_8_75 VPWR )
( sky130_fd_sc_hd__buf_8_74 VPWR )
( sky130_fd_sc_hd__buf_8_75 VPB )
( sky130_fd_sc_hd__buf_8_74 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_87 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_86 VPWR )
( sky130_fd_sc_hd__buf_8_77 VPWR )
( sky130_fd_sc_hd__buf_8_76 VPWR )
( sky130_fd_sc_hd__buf_8_77 VPB )
( sky130_fd_sc_hd__buf_8_76 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_89 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_88 VPWR )
( sky130_fd_sc_hd__buf_8_79 VPWR )
( sky130_fd_sc_hd__buf_8_78 VPWR )
( sky130_fd_sc_hd__buf_8_79 VPB )
( sky130_fd_sc_hd__buf_8_78 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_91 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_90 VPWR )
( sky130_fd_sc_hd__buf_8_81 VPWR )
( sky130_fd_sc_hd__buf_8_80 VPWR )
( sky130_fd_sc_hd__buf_8_81 VPB )
( sky130_fd_sc_hd__buf_8_80 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_93 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_92 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_83 VPWR )
( sky130_fd_sc_hd__buf_8_82 VPWR )
( sky130_fd_sc_hd__buf_8_83 VPB )
( sky130_fd_sc_hd__buf_8_82 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_238 VPWR )
( sky130_fd_sc_hd__buf_8_1 VPWR )
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
( sky130_ef_sc_hd__decap_12_21 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_3 VPWR )
( sky130_ef_sc_hd__decap_12_21 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met3 TAPERRULE met3_width_1850 ( 2203045 209950 ) ( * 214095 )
NEW met3 ( 2202270 214395 ) ( 2202000 * )
NEW met3 TAPERRULE met3_width_1850 ( 2203045 214695 ) ( * 219535 )
NEW met3 ( 2202270 219835 ) ( 2202000 * )
NEW met3 ( 2202270 219905 ) ( 2203820 * )
NEW met3 ( 2204085 219835 ) ( 2203820 * )
NEW met2 ( 2202180 219985 ) ( 2203905 * )
NEW met2 ( 2202180 219695 ) ( 2203905 * )
NEW met2 ( 2203042.5 219835 ) via2_1785_300_vx
NEW met2 ( 2203042.5 219835 ) via_1785_300_vh
NEW met3 ( 2204085 214395 ) ( 2203820 * )
NEW met2 ( 2202180 214545 ) ( 2203905 * )
NEW met2 ( 2202180 214255 ) ( 2203905 * )
NEW met2 ( 2203042.5 214395 ) via2_1785_300_vx
NEW met2 ( 2203042.5 214395 ) via_1785_300_vh ;
Some additional corrections to the gpio_signal_buffering cells. Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
2022-10-16 08:50:20 -05:00
- sky130_fd_sc_hd__buf_8_0/A ( sky130_fd_sc_hd__buf_8_0 A )
( sky130_fd_sc_hd__buf_8_161 X )
+ ROUTED met1 ( 206330 1756430 ) mcon_170_1090
NEW met1 ( 206275 1756965 ) ( 206395 * )
NEW met2 ( 206535 1756450 ) ( 211825 * )
NEW met1 ( 211965 1756480 ) ( 212085 * )
NEW met1 ( 212085 1756620 ) ( * 3039970 )
NEW met1 ( 212085 3040110 ) ( 212205 * )
NEW met1 ( 212145 3040200 ) via_260_260_vh
NEW met1 ( 212085 3040290 ) ( 212205 * )
NEW met2 ( 212345 3040140 ) ( 221530 * )
NEW met2 ( 206715 3040140 ) ( 211945 * )
NEW met2 ( 206220 3040150 ) via_850_260_hv mcon_850_170
NEW met2 ( 205865 3040240 ) ( 206575 * )
NEW met2 ( 205865 3040060 ) ( 206575 * )
NEW met2 ( 212025 1756390 ) via_260_260_vh ( * 1756300 )
( 212085 * )
NEW met2 ( 212225 1756450 ) ( 223670 * )
NEW met1 ( 206275 1755895 ) ( 206395 * )
NEW met1 ( 206335 1756430 ) via_260_1090_vh ;
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
END NETS
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
BLOCKAGES 1 ;
- LAYER met2
RECT 3365990 2262740 3375745 2262880
;
END BLOCKAGES
Added layout for the gpio_signal_buffering module, including GDS, LEF, DEF, and magic views.
2022-10-13 20:59:10 -05:00
END DESIGN