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caravel/signoff/digital_pll/openlane-signoff/22-irdrop.log

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reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/tmp/merged.nom.lef
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/tmp/merged.nom.lef at line 930.
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/results/routing/digital_pll.def
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
[INFO ODB-0128] Design: digital_pll
[INFO ODB-0130] Created 39 pins.
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
[INFO ODB-0131] Created 586 components and 3453 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2244 connections.
[INFO ODB-0133] Created 366 nets and 1208 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/results/routing/digital_pll.def
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
[INFO]: Setting RC values...
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
[INFO PSM-0002] Output voltage file is specified as: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_17_10_45/reports/signoff/22-irdrop.rpt.
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net VPWR is not explicitly set.
[WARNING PSM-0022] Using voltage 1.800V for VDD network.
[WARNING PSM-0063] Specified bump pitches of 140.000 and 140.000 are less than core width of 63.940 or core height of 62.560. Changing bump location to the center of the die at (37.490, 36.720).
[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[WARNING PSM-0030] VSRC location at (37.490um, 36.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (21.840um, 21.850um).
[INFO PSM-0031] Number of PDN nodes on net VPWR = 268.
[INFO PSM-0064] Number of voltage sources = 1.
[INFO PSM-0040] All PDN stripes on net VPWR are connected.
########## IR report #################
Worstcase voltage: 1.80e+00 V
reharden!: digital_pll ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched
2022-10-17 12:56:01 -05:00
Average IR drop : 8.05e-10 V
Worstcase IR drop: 1.14e-09 V
reharden: digital_pll ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables
2022-10-13 08:21:08 -05:00
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