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caravel/xschem/simple_por_tb.sch

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Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
v {xschem version=2.9.9 file_version=1.2 }
G {}
K {}
V {}
S {}
E {}
T {Testbench for simple POR} -350 -240 0 0 0.6 0.6 {}
N -280 60 -10 60 { lab=GND}
N -540 0 -540 60 { lab=GND}
N -330 0 -330 60 { lab=GND}
N -330 -100 -330 -60 { lab=vdd3v3}
N -330 -110 -330 -100 { lab=vdd3v3}
N -210 -110 -40 -110 { lab=vdd3v3}
N -40 -110 -40 -100 { lab=vdd3v3}
N -540 -130 -540 -60 { lab=vdd1v8}
N -280 -130 20 -130 { lab=vdd1v8}
N 20 -130 20 -100 { lab=vdd1v8}
N 140 -50 180 -50 { lab=porb_h}
N 140 -20 180 -20 { lab=porb_l}
N 140 10 180 10 { lab=por_l}
N -340 -110 -330 -110 { lab=vdd3v3}
N -500 -130 -490 -130 { lab=vdd1v8}
N -540 -130 -500 -130 { lab=vdd1v8}
N -560 -130 -540 -130 { lab=vdd1v8}
N -540 60 -490 60 { lab=GND}
N -490 -130 -280 -130 { lab=vdd1v8}
N -490 60 -330 60 { lab=GND}
N -330 60 -280 60 { lab=GND}
N -330 -110 -210 -110 { lab=vdd3v3}
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
N -10 60 20 60 {}
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
C {simple_por.sym} -10 -20 0 0 {name=x1}
C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND}
C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l}
C {devices/code.sym} -470 140 0 0 {name=TT_MODELS only_toplevel=false
format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt
.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
C {devices/code_shown.sym} -320 160 0 0 {name=s2 only_toplevel=false value=".control
tran 1u 20m
plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
.endc"}