mirror of https://github.com/efabless/caravel.git
107 lines
2.8 KiB
YAML
107 lines
2.8 KiB
YAML
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- status: 0 - openlane design prep
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runtime_s: 1.78
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runtime_ts: 0h0m1s782ms
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- status: 1 - synthesis - yosys
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runtime_s: 1.25
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runtime_ts: 0h0m1s250ms
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- status: 2 - sta - openroad
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runtime_s: 0.44
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runtime_ts: 0h0m0s442ms
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- status: 3 - floorplan initialization - openroad
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runtime_s: 0.84
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runtime_ts: 0h0m0s838ms
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- status: 4 - io_place - openlane
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runtime_s: 0.34
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runtime_ts: 0h0m0s337ms
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- status: 5 - tap/decap insertion - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s453ms
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- status: 6 - pdn generation - openroad
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runtime_s: 0.47
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runtime_ts: 0h0m0s471ms
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- status: 7 - global placement - openroad
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runtime_s: 0.62
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runtime_ts: 0h0m0s616ms
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- status: 8 - detailed placement - openroad
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runtime_s: 0.48
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runtime_ts: 0h0m0s476ms
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- status: 10 - detailed placement - openroad
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runtime_s: 0.48
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runtime_ts: 0h0m0s479ms
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- status: 10 - diode insertion - openlane
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runtime_s: 0.58
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runtime_ts: 0h0m0s580ms
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- status: 11 - fill insertion - openroad
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runtime_s: 0.49
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runtime_ts: 0h0m0s487ms
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- status: 13 - write verilog - openroad
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runtime_s: 0.41
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runtime_ts: 0h0m0s408ms
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- status: 13 - global routing - openroad
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runtime_s: 0.51
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runtime_ts: 0h0m0s506ms
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- status: 14 - detailed_routing - openroad
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runtime_s: 2.55
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runtime_ts: 0h0m2s548ms
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- status: 15 - wire lengths - openlane
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runtime_s: 0.26
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runtime_ts: 0h0m0s261ms
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- status: 16 - parasitics extraction - openroad
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runtime_s: 0.48
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runtime_ts: 0h0m0s484ms
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- status: 17 - sta - openroad
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runtime_s: 1.67
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runtime_ts: 0h0m1s665ms
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- status: 18 - parasitics extraction - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s453ms
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- status: 19 - sta - openroad
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runtime_s: 1.65
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runtime_ts: 0h0m1s653ms
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- status: 20 - parasitics extraction - openroad
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runtime_s: 0.46
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runtime_ts: 0h0m0s459ms
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- status: 21 - sta - openroad
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runtime_s: 1.64
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runtime_ts: 0h0m1s639ms
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- status: 22 - sta - openroad
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runtime_s: 0.41
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runtime_ts: 0h0m0s410ms
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- status: 23 - ir drop report - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s447ms
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- status: 24 - gdsii - magic
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runtime_s: 1.41
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runtime_ts: 0h0m1s405ms
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- status: 25 - gdsii - klayout
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runtime_s: 0.45
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runtime_ts: 0h0m0s445ms
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- status: 26 - xor - klayout
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runtime_s: 0.48
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runtime_ts: 0h0m0s483ms
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- status: 27 - gds.spice extraction - magic
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runtime_s: 0.69
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runtime_ts: 0h0m0s694ms
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- status: 29 - write verilog - openroad
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runtime_s: 0.41
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runtime_ts: 0h0m0s407ms
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- status: 29 - write powered verilog - openlane
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runtime_s: 0.52
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runtime_ts: 0h0m0s521ms
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- status: 30 - lvs - netgen
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runtime_s: 0.31
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runtime_ts: 0h0m0s314ms
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- status: 31 - drc - magic
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runtime_s: 1.24
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runtime_ts: 0h0m1s241ms
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- status: 32 - antenna check - openroad
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runtime_s: 0.45
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runtime_ts: 0h0m0s452ms
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---
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- status: routed
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runtime_s: 15.0
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runtime_ts: 0h0m15s0ms
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- status: flow completed
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runtime_s: 31.0
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runtime_ts: 0h0m31s0ms
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