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caravel/def/gpio_signal_buffering_alt.def

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Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
VERSION 5.7 ;
NAMESCASESENSITIVE ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "()" ;
DESIGN gpio_signal_buffering_alt ;
TECHNOLOGY sky130A ;
UNITS DISTANCE MICRONS 1000 ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
DIEAREA ( 0 0 ) ( 3588000 5188000 ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
VIAS 18 ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- via_1785_300_vh
+ RECT met1 ( -892.5 -180 ) ( 892.5 180 )
+ RECT met2 ( -922.5 -150 ) ( 922.5 150 )
+ RECT via ( -715 -75 ) ( -565 75 )
+ RECT via ( -395 -75 ) ( -245 75 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( 245 -75 ) ( 395 75 )
+ RECT via ( 565 -75 ) ( 715 75 ) ;
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
- via_260_260_hv
+ RECT met1 ( -160 -130 ) ( 160 130 )
+ RECT met2 ( -130 -160 ) ( 130 160 )
+ RECT via ( -75 -75 ) ( 75 75 ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- via_260_660_vh
+ RECT met1 ( -130 -360 ) ( 130 360 )
+ RECT met2 ( -160 -330 ) ( 160 330 )
+ RECT via ( -75 -235 ) ( 75 -85 )
+ RECT via ( -75 85 ) ( 75 235 ) ;
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
- via_1090_260_hv
+ RECT met1 ( -575 -130 ) ( 575 130 )
+ RECT met2 ( -545 -160 ) ( 545 160 )
+ RECT via ( -395 -75 ) ( -245 75 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( 245 -75 ) ( 395 75 ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- via_300_1785_hh
+ RECT met1 ( -180 -892.5 ) ( 180 892.5 )
+ RECT met2 ( -180 -892.5 ) ( 180 892.5 )
+ RECT via ( -75 -715 ) ( 75 -565 )
+ RECT via ( -75 -395 ) ( 75 -245 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( -75 245 ) ( 75 395 )
+ RECT via ( -75 565 ) ( 75 715 ) ;
- via_260_260_vh
+ RECT met1 ( -130 -160 ) ( 130 160 )
+ RECT met2 ( -160 -130 ) ( 160 130 )
+ RECT via ( -75 -75 ) ( 75 75 ) ;
- via2_1785_300_vx
+ RECT met2 ( -892.5 -195 ) ( 892.5 195 )
+ RECT met3 ( -917.5 -175 ) ( 917.5 175 )
+ RECT via2 ( -700 -100 ) ( -500 100 )
+ RECT via2 ( -300 -100 ) ( -100 100 )
+ RECT via2 ( 100 -100 ) ( 300 100 )
+ RECT via2 ( 500 -100 ) ( 700 100 ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- via_260_290_vh
+ RECT met1 ( -130 -175 ) ( 130 175 )
+ RECT met2 ( -160 -145 ) ( 160 145 )
+ RECT via ( -75 -75 ) ( 75 75 ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- mcon_170_1090
+ RECT li1 ( -85 -545 ) ( 85 545 )
+ RECT met1 ( -115 -575 ) ( 115 575 )
+ RECT mcon ( -85 -445 ) ( 85 -275 )
+ RECT mcon ( -85 -85 ) ( 85 85 )
+ RECT mcon ( -85 275 ) ( 85 445 ) ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- via_1785_300_hh
+ RECT met1 ( -922.5 -150 ) ( 922.5 150 )
+ RECT met2 ( -922.5 -150 ) ( 922.5 150 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ RECT via ( -715 -75 ) ( -565 75 )
+ RECT via ( -395 -75 ) ( -245 75 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( 245 -75 ) ( 395 75 )
+ RECT via ( 565 -75 ) ( 715 75 ) ;
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
- via_260_1090_vh
+ RECT met1 ( -130 -575 ) ( 130 575 )
+ RECT met2 ( -160 -545 ) ( 160 545 )
+ RECT via ( -75 -395 ) ( 75 -245 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( -75 245 ) ( 75 395 ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- mcon_1090_170
+ RECT li1 ( -545 -85 ) ( 545 85 )
+ RECT met1 ( -575 -115 ) ( 575 115 )
+ RECT mcon ( -445 -85 ) ( -275 85 )
+ RECT mcon ( -85 -85 ) ( 85 85 )
+ RECT mcon ( 275 -85 ) ( 445 85 ) ;
- via2_300_1785_hx
+ RECT met2 ( -195 -892.5 ) ( 195 892.5 )
+ RECT met3 ( -175 -917.5 ) ( 175 917.5 )
+ RECT via2 ( -100 -700 ) ( 100 -500 )
+ RECT via2 ( -100 -300 ) ( 100 -100 )
+ RECT via2 ( -100 100 ) ( 100 300 )
+ RECT via2 ( -100 500 ) ( 100 700 ) ;
- via_850_260_hv
+ RECT met1 ( -455 -130 ) ( 455 130 )
+ RECT met2 ( -425 -160 ) ( 425 160 )
+ RECT via ( -235 -75 ) ( -85 75 )
+ RECT via ( 85 -75 ) ( 235 75 ) ;
- via_260_850_vh
+ RECT met1 ( -130 -455 ) ( 130 455 )
+ RECT met2 ( -160 -425 ) ( 160 425 )
+ RECT via ( -75 -235 ) ( 75 -85 )
+ RECT via ( -75 85 ) ( 75 235 ) ;
- mcon_170_850
+ RECT li1 ( -85 -425 ) ( 85 425 )
+ RECT met1 ( -115 -455 ) ( 115 455 )
+ RECT mcon ( -85 -265 ) ( 85 -95 )
+ RECT mcon ( -85 95 ) ( 85 265 ) ;
- via_300_1785_vh
+ RECT met1 ( -150 -922.5 ) ( 150 922.5 )
+ RECT met2 ( -180 -892.5 ) ( 180 892.5 )
+ RECT via ( -75 -715 ) ( 75 -565 )
+ RECT via ( -75 -395 ) ( 75 -245 )
+ RECT via ( -75 -75 ) ( 75 75 )
+ RECT via ( -75 245 ) ( 75 395 )
+ RECT via ( -75 565 ) ( 75 715 ) ;
- mcon_850_170
+ RECT li1 ( -425 -85 ) ( 425 85 )
+ RECT met1 ( -455 -115 ) ( 455 115 )
+ RECT mcon ( -265 -85 ) ( -95 85 )
+ RECT mcon ( 95 -85 ) ( 265 85 ) ;
END VIAS
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
COMPONENTS 348 ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_21 sky130_ef_sc_hd__decap_12
+ PLACED ( 669460 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_1 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 669460 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_3 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 669000 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_238 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 669000 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_82 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 675440 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_83 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 675440 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_92 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 674980 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_93 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 674980 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_80 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 681420 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_81 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 681420 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_90 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 680960 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_91 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 680960 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_78 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 687400 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_79 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 687400 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_88 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 686940 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_89 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 686940 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_24 sky130_ef_sc_hd__decap_12
+ PLACED ( 669460 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_241 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 669000 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_23 sky130_ef_sc_hd__decap_12
+ PLACED ( 675440 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_240 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 674980 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_26 sky130_ef_sc_hd__decap_12
+ PLACED ( 681420 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_242 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 680960 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_25 sky130_ef_sc_hd__decap_12
+ PLACED ( 687400 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_243 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 686940 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_27 sky130_ef_sc_hd__decap_12
+ PLACED ( 693380 217125 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_76 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 693380 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_77 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 693380 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_86 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 692920 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_87 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 692920 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_244 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 692920 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_29 sky130_ef_sc_hd__decap_12
+ PLACED ( 699360 217125 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_74 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 699360 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_75 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 699360 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_84 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 698900 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_85 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 698900 211685 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_246 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 698900 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_28 sky130_ef_sc_hd__decap_12
+ PLACED ( 705340 217125 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_72 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 705340 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_73 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 705340 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_82 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 704880 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_83 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 704880 211685 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_245 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 704880 217125 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_70 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 711320 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_71 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 711320 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_80 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 710860 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_81 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 710860 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_68 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 717300 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_69 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 717300 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_78 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 716840 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_79 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 716840 211685 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_31 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 723280 214405 ) FS ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_67 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 723280 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_76 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 722820 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_77 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 722820 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_74 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 728800 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_75 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 728800 211685 ) FN ;
- sky130_ef_sc_hd__decap_12_30 sky130_ef_sc_hd__decap_12
+ PLACED ( 711320 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_247 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 710860 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_32 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 717300 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_249 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 716840 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_33 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 723280 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_248 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 722820 217125 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_250 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 728800 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_256 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 758700 217125 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_65 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 758700 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_64 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 758700 214405 ) S ;
- sky130_ef_sc_hd__decap_12_34 sky130_ef_sc_hd__decap_12
+ PLACED ( 759160 217125 ) N ;
- sky130_ef_sc_hd__decap_12_39 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 759160 211685 ) N ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__buf_8_55 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 759160 214405 ) S ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_6 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 764680 211685 ) FN ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_7 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 764680 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_257 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 764680 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_40 sky130_ef_sc_hd__decap_12
+ PLACED ( 765140 217125 ) N ;
- sky130_fd_sc_hd__buf_8_2 sky130_fd_sc_hd__buf_8
+ PLACED ( 765140 211685 ) N ;
- sky130_fd_sc_hd__buf_8_3 sky130_fd_sc_hd__buf_8
+ PLACED ( 765140 214405 ) S ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_94 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 770660 214405 ) S ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_95 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 770660 211685 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_255 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 770660 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_38 sky130_ef_sc_hd__decap_12
+ PLACED ( 771120 217125 ) N ;
- sky130_fd_sc_hd__buf_8_84 sky130_fd_sc_hd__buf_8
+ PLACED ( 771120 214405 ) S ;
- sky130_fd_sc_hd__buf_8_85 sky130_fd_sc_hd__buf_8
+ PLACED ( 771120 211685 ) N ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_4 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 776640 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_5 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 776640 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_259 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 776640 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_42 sky130_ef_sc_hd__decap_12
+ PLACED ( 777100 217125 ) N ;
- sky130_fd_sc_hd__buf_8_4 sky130_fd_sc_hd__buf_8
+ PLACED ( 777100 211685 ) N ;
- sky130_fd_sc_hd__buf_8_5 sky130_fd_sc_hd__buf_8
+ PLACED ( 777100 214405 ) S ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_8 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 782620 211685 ) FN ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_9 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 782620 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_258 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 782620 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_41 sky130_ef_sc_hd__decap_12
+ PLACED ( 783080 217125 ) N ;
- sky130_fd_sc_hd__buf_8_6 sky130_fd_sc_hd__buf_8
+ PLACED ( 783080 211685 ) N ;
- sky130_fd_sc_hd__buf_8_7 sky130_fd_sc_hd__buf_8
+ PLACED ( 783080 214405 ) S ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_326 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 794580 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_260 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 788600 217125 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_13 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 794580 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_12 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 794580 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_11 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 788600 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_10 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 788600 211685 ) FN ;
- sky130_fd_sc_hd__buf_8_9 sky130_fd_sc_hd__buf_8
+ PLACED ( 789060 214405 ) S ;
- sky130_fd_sc_hd__buf_8_8 sky130_fd_sc_hd__buf_8
+ PLACED ( 789060 211685 ) FN ;
- sky130_ef_sc_hd__decap_12_43 sky130_ef_sc_hd__decap_12
+ PLACED ( 789060 217125 ) N ;
- sky130_ef_sc_hd__decap_12_22 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2146460 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_86 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2146460 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_96 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2146000 211685 ) FN ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_97 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2146000 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_88 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2152440 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_89 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2152440 211685 ) N ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_98 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2151980 211685 ) FN ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_99 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2151980 214405 ) S ;
- sky130_fd_sc_hd__buf_8_90 sky130_fd_sc_hd__buf_8
+ PLACED ( 2158420 211685 ) N ;
- sky130_fd_sc_hd__buf_8_91 sky130_fd_sc_hd__buf_8
+ PLACED ( 2158420 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_100 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2157960 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_101 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2157960 211685 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_1 sky130_ef_sc_hd__decap_12
+ PLACED ( 2146460 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_239 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2146000 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_2 sky130_ef_sc_hd__decap_12
+ PLACED ( 2152440 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_218 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2151980 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_3 sky130_ef_sc_hd__decap_12
+ PLACED ( 2158420 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_219 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2157960 217125 ) FN ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_92 sky130_fd_sc_hd__buf_8
+ PLACED ( 2164400 214405 ) S ;
- sky130_fd_sc_hd__buf_8_93 sky130_fd_sc_hd__buf_8
+ PLACED ( 2164400 211685 ) N ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_104 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2163940 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_105 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2163940 214405 ) S ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__buf_8_94 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2170380 214405 ) S ;
- sky130_fd_sc_hd__buf_8_95 sky130_fd_sc_hd__buf_8
+ PLACED ( 2170380 211685 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_102 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2169920 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_103 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2169920 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_106 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2175900 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_109 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2175900 214405 ) S ;
- sky130_ef_sc_hd__decap_12_4 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2164400 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_220 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2163940 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_0 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2170380 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_2 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2169920 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_222 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2175900 217125 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_96 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2176360 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_98 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2176360 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_107 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2181880 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_110 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2181880 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__buf_8_97 sky130_fd_sc_hd__buf_8
+ PLACED ( 2182340 211685 ) N ;
- sky130_fd_sc_hd__buf_8_99 sky130_fd_sc_hd__buf_8
+ PLACED ( 2182340 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_108 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2187860 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_111 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2187860 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__buf_8_100 sky130_fd_sc_hd__buf_8
+ PLACED ( 2188320 211685 ) N ;
- sky130_fd_sc_hd__buf_8_103 sky130_fd_sc_hd__buf_8
+ PLACED ( 2188320 214405 ) S ;
- sky130_ef_sc_hd__decap_12_6 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2176360 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_223 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2181880 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_7 sky130_ef_sc_hd__decap_12
+ PLACED ( 2182340 217125 ) N ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_224 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2187860 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_8 sky130_ef_sc_hd__decap_12
+ PLACED ( 2188320 217125 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_101 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2194300 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_104 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2194300 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_112 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2193840 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_114 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2193840 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_10 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2200280 214405 ) FS ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_102 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2200280 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_113 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2199820 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_115 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2199820 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_116 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2205800 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_117 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2205800 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_9 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2194300 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_225 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2193840 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_11 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2200280 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_226 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2199820 217125 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_221 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2205800 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_15 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2236160 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_117 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2236160 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_126 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2235700 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_127 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2235700 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_118 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2242140 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_119 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2242140 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_128 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2241680 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_129 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2241680 211685 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_5 sky130_ef_sc_hd__decap_12
+ PLACED ( 2236160 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_231 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2235700 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_16 sky130_ef_sc_hd__decap_12
+ PLACED ( 2242140 217125 ) N ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_232 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2241680 217125 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_120 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2248120 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_121 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2248120 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_130 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2247660 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_131 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2247660 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_122 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2254100 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_123 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2254100 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_132 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2253640 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_133 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2253640 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_124 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2260080 211685 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_126 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2260080 214405 ) S ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_134 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2259620 211685 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_137 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2259620 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_18 sky130_ef_sc_hd__decap_12
+ PLACED ( 2248120 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_234 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2247660 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_17 sky130_ef_sc_hd__decap_12
+ PLACED ( 2254100 217125 ) N ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_233 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2253640 217125 ) FN ;
- sky130_ef_sc_hd__decap_12_19 sky130_ef_sc_hd__decap_12
+ PLACED ( 2260080 217125 ) N ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_236 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2259620 217125 ) FN ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_237 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2271580 217125 ) FN ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_235 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2265600 217125 ) FN ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_139 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 2271580 214405 ) S ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_138 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2265600 214405 ) S ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_136 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2271580 211685 ) FN ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_135 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 2265600 211685 ) FN ;
- sky130_fd_sc_hd__buf_8_127 sky130_fd_sc_hd__buf_8
+ PLACED ( 2266060 214405 ) S ;
- sky130_fd_sc_hd__buf_8_125 sky130_fd_sc_hd__buf_8
+ PLACED ( 2266060 211685 ) FN ;
- sky130_ef_sc_hd__decap_12_20 sky130_ef_sc_hd__decap_12
+ PLACED ( 2266060 217125 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_128 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1673365 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_129 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1673365 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_140 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1672905 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_309 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1672905 ) E ;
- sky130_ef_sc_hd__decap_12_14 sky130_ef_sc_hd__decap_12
+ PLACED ( 207520 1673365 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_141 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1672905 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_130 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1679345 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_131 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1679345 ) FW ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_142 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1678885 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_143 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1678885 ) E ;
- sky130_ef_sc_hd__decap_12_12 sky130_ef_sc_hd__decap_12
+ PLACED ( 207520 1679345 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_310 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1678885 ) E ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__buf_8_132 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1685325 ) FE ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__buf_8_133 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1685325 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_144 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1684865 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_145 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1684865 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_44 sky130_ef_sc_hd__decap_12
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1685325 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_312 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1684865 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_138 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1691305 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_139 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1691305 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_150 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1690845 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_151 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1690845 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_46 sky130_ef_sc_hd__decap_12
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1691305 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_311 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1690845 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_136 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1697285 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_137 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1697285 ) FW ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_148 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1696825 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_149 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1696825 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_45 sky130_ef_sc_hd__decap_12
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1697285 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_313 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1696825 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_134 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1703265 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_135 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1703265 ) FW ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_146 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1702805 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_147 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1702805 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_47 sky130_ef_sc_hd__decap_12
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1703265 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_314 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1702805 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_142 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1709245 ) FW ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_143 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1709245 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_154 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1708785 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_155 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1708785 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_49 sky130_ef_sc_hd__decap_12
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1709245 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_316 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1708785 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_140 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1715225 ) FW ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_141 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1715225 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_152 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204800 1714765 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_153 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1714765 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_48 sky130_ef_sc_hd__decap_12
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1715225 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_315 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1714765 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_318 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 207520 1726725 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_317 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207520 1720745 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_161 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 202080 1720745 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_160 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 204800 1720745 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_159 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 202080 1726725 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_158 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 204800 1726725 ) FE ;
- sky130_fd_sc_hd__buf_8_149 sky130_fd_sc_hd__buf_8
+ PLACED ( 204800 1721205 ) FE ;
- sky130_fd_sc_hd__buf_8_148 sky130_fd_sc_hd__buf_8
+ PLACED ( 202080 1721205 ) FW ;
- sky130_ef_sc_hd__decap_12_50 sky130_ef_sc_hd__decap_12
+ PLACED ( 207520 1721205 ) E ;
- sky130_ef_sc_hd__decap_12_58 sky130_ef_sc_hd__decap_12
+ PLACED ( 3377865 2196520 ) FE ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__buf_8_13 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2196520 ) E ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_53 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2196060 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_262 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2196060 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_12 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2196520 ) W ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_261 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 2196060 ) FE ;
- sky130_ef_sc_hd__decap_12_59 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2202500 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_46 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2202500 ) E ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_52 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2202040 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_55 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2202040 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_47 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2202500 ) W ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_54 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2202040 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_56 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2208480 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__buf_8_49 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2208480 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_57 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2208020 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_264 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2208020 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_48 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2208480 ) W ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_56 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2208020 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_57 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2214460 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__buf_8_51 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2214460 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_59 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2214000 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_263 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2214000 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_50 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2214460 ) W ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_58 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2214000 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_55 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2220440 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__buf_8_53 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2220440 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_61 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2219980 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_265 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2219980 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_52 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2220440 ) W ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_60 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2219980 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_ef_sc_hd__decap_12_53 sky130_ef_sc_hd__decap_12
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3377865 2226420 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_34 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 2226420 ) E ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_63 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2225960 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_267 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2225960 ) FE ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__buf_8_35 sky130_fd_sc_hd__buf_8
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2226420 ) W ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_62 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2225960 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_269 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2237920 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_266 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 2231940 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_39 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 2231940 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_38 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2231940 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_17 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3383305 2237920 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_16 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 2237920 ) E ;
- sky130_fd_sc_hd__buf_8_37 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 2232400 ) W ;
- sky130_fd_sc_hd__buf_8_36 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 2232400 ) E ;
- sky130_ef_sc_hd__decap_12_54 sky130_ef_sc_hd__decap_12
+ PLACED ( 3377865 2232400 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_194 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 201970 2984730 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_195 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 204690 2984730 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_297 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 207410 2984730 ) E ;
- sky130_ef_sc_hd__decap_12_52 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 2985190 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_178 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 201970 2985190 ) FW ;
- sky130_fd_sc_hd__buf_8_179 sky130_fd_sc_hd__buf_8
+ PLACED ( 204690 2985190 ) FE ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_190 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 201970 2990710 ) E ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_192 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204690 2990710 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_299 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207410 2990710 ) E ;
- sky130_ef_sc_hd__decap_12_51 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 2991170 ) E ;
- sky130_fd_sc_hd__buf_8_176 sky130_fd_sc_hd__buf_8
+ PLACED ( 201970 2991170 ) FW ;
- sky130_fd_sc_hd__buf_8_177 sky130_fd_sc_hd__buf_8
+ PLACED ( 204690 2991170 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_191 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 201970 2996690 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_193 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204690 2996690 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_298 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207410 2996690 ) E ;
- sky130_ef_sc_hd__decap_12_35 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 2997150 ) E ;
- sky130_fd_sc_hd__buf_8_174 sky130_fd_sc_hd__buf_8
+ PLACED ( 201970 2997150 ) FW ;
- sky130_fd_sc_hd__buf_8_175 sky130_fd_sc_hd__buf_8
+ PLACED ( 204690 2997150 ) FE ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_188 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 201970 3002670 ) E ;
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_189 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204690 3002670 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_300 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207410 3002670 ) E ;
- sky130_ef_sc_hd__decap_12_37 sky130_ef_sc_hd__decap_12
+ PLACED ( 207410 3003130 ) E ;
- sky130_fd_sc_hd__buf_8_172 sky130_fd_sc_hd__buf_8
+ PLACED ( 204690 3003130 ) FE ;
- sky130_fd_sc_hd__buf_8_173 sky130_fd_sc_hd__buf_8
+ PLACED ( 201970 3003130 ) FW ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_36 sky130_ef_sc_hd__decap_12
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207410 3009110 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_170 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 201970 3009110 ) FW ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_171 sky130_fd_sc_hd__buf_8
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204690 3009110 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_186 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 204690 3008650 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_187 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 201970 3008650 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_302 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207410 3008650 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_301 sky130_fd_sc_hd__tapvpwrvgnd_1
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ PLACED ( 207410 3014630 ) E ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_185 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 204690 3014630 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_184 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 201970 3014630 ) E ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_ef_sc_hd__decap_12_13 sky130_ef_sc_hd__decap_12
+ PLACED ( 3377865 3602520 ) FE ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__buf_8_24 sky130_fd_sc_hd__buf_8
+ PLACED ( 3383305 3602520 ) W ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__buf_8_25 sky130_fd_sc_hd__buf_8
+ PLACED ( 3380585 3602520 ) E ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_1 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 3608040 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_28 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3380585 3602060 ) E ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_29 sky130_fd_sc_hd__tapvpwrvgnd_1
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PLACED ( 3380585 3608040 ) E ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_272 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3383305 3602060 ) FE ;
- sky130_fd_sc_hd__tapvpwrvgnd_1_274 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3602060 ) FE ;
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
- sky130_fd_sc_hd__tapvpwrvgnd_1_275 sky130_fd_sc_hd__tapvpwrvgnd_1
+ PLACED ( 3377865 3608040 ) FE ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
END COMPONENTS
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
PINS 98 ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387535 2235397.5 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387545 2241392.5 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387530 3617392.5 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 3387575 3623377.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[4] + NET mgmt_io_in_unbuf[4]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368750 2278557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[6] + NET mgmt_io_in_unbuf[6]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370850 3640887.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[5] + NET mgmt_io_in_unbuf[5]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3369870 2280557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[0] + NET mgmt_io_in_unbuf[0]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364270 2270557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[1] + NET mgmt_io_in_unbuf[1]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3365390 2272557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[2] + NET mgmt_io_in_unbuf[2]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3366510 2274557.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[3] + NET mgmt_io_in_unbuf[3]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367630 2276557.5 ) N ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 737925 210220 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 731895 210220 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 2208985 210125 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -765 -235 ) ( 765 235 ) + PLACED ( 2203020 210155 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[2] + NET mgmt_io_oeb_buf[2]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 666242.5 220830 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[16] + NET mgmt_io_in_unbuf[16]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 657242.5 225030 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[17] + NET mgmt_io_in_unbuf[17]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 659242.5 224190 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[18] + NET mgmt_io_in_unbuf[18]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 661242.5 223350 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[19] + NET mgmt_io_in_unbuf[19]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 663242.5 222510 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[0] + NET mgmt_io_oeb_buf[0]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 664242.5 221950 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[1] + NET mgmt_io_oeb_buf[1]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 665242.5 221390 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200595 1735667.5 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200605 1729702.5 ) N ;
- vssd + NET vssd
+ DIRECTION INPUT
+ USE GROUND
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200490 3023947.5 ) N ;
- vccd + NET vccd
+ DIRECTION INPUT
+ USE POWER
+ PORT
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200490 3017942.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[15] + NET mgmt_io_in_unbuf[15]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 226645 1766915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[14] + NET mgmt_io_in_unbuf[14]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 225525 1768915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[13] + NET mgmt_io_in_unbuf[13]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 224405 1770915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[12] + NET mgmt_io_in_unbuf[12]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 223285 1772915 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[4] + NET mgmt_io_in_buf[4]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368890 1176967.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[6] + NET mgmt_io_in_buf[6]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3371130 1172967.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[5] + NET mgmt_io_in_buf[5]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370010 1174967.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[0] + NET mgmt_io_in_buf[0]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364410 1184967.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[1] + NET mgmt_io_in_buf[1]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3365530 1182967.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[2] + NET mgmt_io_in_buf[2]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3366650 1180967.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[3] + NET mgmt_io_in_buf[3]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367770 1178967.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[15] + NET mgmt_io_out_unbuf[15]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3354750 1115957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[14] + NET mgmt_io_out_unbuf[14]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3355870 1117957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[13] + NET mgmt_io_out_unbuf[13]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3356990 1119957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[12] + NET mgmt_io_out_unbuf[12]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3358110 1121957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[11] + NET mgmt_io_out_unbuf[11]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3359230 1123957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[10] + NET mgmt_io_out_unbuf[10]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ USE SIGNAL
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3360350 1125957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[9] + NET mgmt_io_out_unbuf[9]
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ DIRECTION INPUT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ USE SIGNAL
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3361470 1127957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[8] + NET mgmt_io_out_unbuf[8]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3362590 1129957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[7] + NET mgmt_io_out_unbuf[7]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3363710 1131957.5 ) N ;
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
- mgmt_io_in_buf[15] + NET mgmt_io_in_buf[15]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3355310 1116957.5 ) N ;
- mgmt_io_in_buf[14] + NET mgmt_io_in_buf[14]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3356430 1118957.5 ) N ;
- mgmt_io_in_buf[13] + NET mgmt_io_in_buf[13]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3357550 1120957.5 ) N ;
- mgmt_io_in_buf[12] + NET mgmt_io_in_buf[12]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3358670 1122957.5 ) N ;
- mgmt_io_in_buf[11] + NET mgmt_io_in_buf[11]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3359790 1124957.5 ) N ;
- mgmt_io_in_buf[10] + NET mgmt_io_in_buf[10]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3360910 1126957.5 ) N ;
- mgmt_io_in_buf[9] + NET mgmt_io_in_buf[9]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3362030 1128957.5 ) N ;
- mgmt_io_in_buf[8] + NET mgmt_io_in_buf[8]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3363150 1130957.5 ) N ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[7] + NET mgmt_io_in_buf[7]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -707.5 ) ( 70 707.5 ) + PLACED ( 3364270 1132957.5 ) N ;
- mgmt_io_out_unbuf[0] + NET mgmt_io_out_unbuf[0]
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3363850 1185967.5 ) N ;
- mgmt_io_out_unbuf[1] + NET mgmt_io_out_unbuf[1]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364970 1183967.5 ) N ;
- mgmt_io_out_unbuf[2] + NET mgmt_io_out_unbuf[2]
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ DIRECTION INPUT
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ USE SIGNAL
+ PORT
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3366090 1181967.5 ) N ;
- mgmt_io_out_unbuf[3] + NET mgmt_io_out_unbuf[3]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367210 1179967.5 ) N ;
- mgmt_io_out_unbuf[4] + NET mgmt_io_out_unbuf[4]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368330 1177967.5 ) N ;
- mgmt_io_out_unbuf[5] + NET mgmt_io_out_unbuf[5]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3369450 1175967.5 ) N ;
- mgmt_io_out_unbuf[6] + NET mgmt_io_out_unbuf[6]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370570 1173967.5 ) N ;
- mgmt_io_out_buf[0] + NET mgmt_io_out_buf[0]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3363710 2269557.5 ) N ;
- mgmt_io_out_buf[1] + NET mgmt_io_out_buf[1]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3364830 2271557.5 ) N ;
- mgmt_io_out_buf[2] + NET mgmt_io_out_buf[2]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3365950 2273557.5 ) N ;
- mgmt_io_out_buf[3] + NET mgmt_io_out_buf[3]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3367070 2275557.5 ) N ;
- mgmt_io_out_buf[4] + NET mgmt_io_out_buf[4]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3368190 2277557.5 ) N ;
- mgmt_io_out_buf[5] + NET mgmt_io_out_buf[5]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3369310 2279557.5 ) N ;
- mgmt_io_out_buf[6] + NET mgmt_io_out_buf[6]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370290 3639887.5 ) N ;
- mgmt_io_out_buf[12] + NET mgmt_io_out_buf[12]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 223845 1771915 ) N ;
- mgmt_io_out_buf[13] + NET mgmt_io_out_buf[13]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 224965 1769915 ) N ;
- mgmt_io_out_buf[14] + NET mgmt_io_out_buf[14]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 226085 1767915 ) N ;
- mgmt_io_out_buf[15] + NET mgmt_io_out_buf[15]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 227205 1765915 ) N ;
- mgmt_io_out_buf[16] + NET mgmt_io_out_buf[16]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 656382.5 225450 ) N ;
- mgmt_io_out_buf[17] + NET mgmt_io_out_buf[17]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 658382.5 224610 ) N ;
- mgmt_io_out_buf[18] + NET mgmt_io_out_buf[18]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 660382.5 223770 ) N ;
- mgmt_io_out_buf[19] + NET mgmt_io_out_buf[19]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 662382.5 222930 ) N ;
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
- mgmt_io_out_buf[11] + NET mgmt_io_out_buf[11]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222865 3053127.5 ) N ;
- mgmt_io_out_buf[10] + NET mgmt_io_out_buf[10]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 221745 3055127.5 ) N ;
- mgmt_io_in_unbuf[10] + NET mgmt_io_in_unbuf[10]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 221185 3056127.5 ) N ;
- mgmt_io_in_unbuf[11] + NET mgmt_io_in_unbuf[11]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222305 3054127.5 ) N ;
- mgmt_io_out_buf[9] + NET mgmt_io_out_buf[9]
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220625 3057322.5 ) N ;
- mgmt_io_in_unbuf[9] + NET mgmt_io_in_unbuf[9]
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220065 3058322.5 ) N ;
- mgmt_io_out_buf[8] + NET mgmt_io_out_buf[8]
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 219505 3059322.5 ) N ;
- mgmt_io_in_unbuf[8] + NET mgmt_io_in_unbuf[8]
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218945 3060322.5 ) N ;
- mgmt_io_out_buf[7] + NET mgmt_io_out_buf[7]
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218385 3061187.5 ) N ;
- mgmt_io_in_unbuf[7] + NET mgmt_io_in_unbuf[7]
+ PORT
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 217825 3062187.5 ) N ;
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
- mgmt_io_in_buf[16] + NET mgmt_io_in_buf[16]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3370710 1146842.5 ) N ;
- mgmt_io_in_buf[17] + NET mgmt_io_in_buf[17]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3371830 1148842.5 ) N ;
- mgmt_io_in_buf[18] + NET mgmt_io_in_buf[18]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3372950 1150842.5 ) N ;
- mgmt_io_in_buf[19] + NET mgmt_io_in_buf[19]
+ DIRECTION OUTPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3374070 1152842.5 ) N ;
- mgmt_io_oeb_unbuf[0] + NET mgmt_io_oeb_unbuf[0]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3374910 1153842.5 ) N ;
- mgmt_io_oeb_unbuf[2] + NET mgmt_io_oeb_unbuf[2]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3376590 1155842.5 ) N ;
- mgmt_io_oeb_unbuf[1] + NET mgmt_io_oeb_unbuf[1]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3375750 1154842.5 ) N ;
- mgmt_io_out_unbuf[18] + NET mgmt_io_out_unbuf[18]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3372390 1149842.5 ) N ;
- mgmt_io_out_unbuf[17] + NET mgmt_io_out_unbuf[17]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3371270 1147842.5 ) N ;
- mgmt_io_out_unbuf[16] + NET mgmt_io_out_unbuf[16]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3370150 1145842.5 ) N ;
- mgmt_io_out_unbuf[19] + NET mgmt_io_out_unbuf[19]
+ DIRECTION INPUT
+ USE SIGNAL
+ PORT
+ LAYER met1 ( -70 -592.5 ) ( 70 592.5 ) + PLACED ( 3373510 1151842.5 ) N ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
END PINS
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NONDEFAULTRULES 4 ;
- met3_width_1865
+ LAYER met3 WIDTH 1865 ;
- met1_width_300
+ LAYER met1 WIDTH 300 ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- met3_width_1740
+ LAYER met3 WIDTH 1740 ;
- met3_width_1850
+ LAYER met3 WIDTH 1850 ;
END NONDEFAULTRULES
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
NETS 147 ;
- mgmt_io_in_buf[16] ( sky130_fd_sc_hd__buf_8_119 X )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3370710 216450 ) ( * 1147370 )
NEW met1 ( 2531410 216310 ) ( 3370710 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2531410 214370 ) ( * 216170 )
NEW met1 ( 2422010 214230 ) ( 2531410 * )
NEW met1 ( 2422010 214370 ) ( * 225170 )
NEW met1 ( 2246775 225310 ) ( 2422010 * )
NEW met1 ( 2246575 225250 ) via_260_260_hv ( * 225340 )
( 2246635 * )
NEW met2 ( 2246515 225480 ) ( * 232415 )
NEW met2 ( 2246515 225160 ) ( 2246635 * )
NEW met2 ( 2246515 213370 ) ( * 225020 )
NEW met1 ( 2246450 213290 ) ( 2246570 * )
NEW met1 ( 2246450 212460 ) ( 2246570 * )
NEW met1 ( 2246510 212875 ) via_260_850_vh
NEW met1 ( 2246515 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[17] ( sky130_fd_sc_hd__buf_8_118 A )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3371270 1145075 ) ( * 1148380 )
NEW met1 ( 3371270 1144935 ) ( 3371550 * )
NEW met1 ( 3371550 215890 ) ( * 1144795 )
NEW met1 ( 2532250 215750 ) ( 3371550 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2532250 214090 ) ( * 215610 )
NEW met1 ( 2421170 213950 ) ( 2532250 * )
NEW met1 ( 2421170 214090 ) ( * 224610 )
NEW met1 ( 2247745 224750 ) ( 2421170 * )
NEW met1 ( 2247545 224690 ) via_260_260_hv ( * 224780 )
( 2247605 * )
NEW met2 ( 2247485 224920 ) ( * 232415 )
NEW met2 ( 2247485 224600 ) ( 2247605 * )
NEW met2 ( 2247485 216170 ) ( * 224460 )
NEW met2 ( 2246990 216030 ) ( 2247940 * )
NEW met2 ( 2247465 215940 ) via_1090_260_hv
NEW li1 ( 2247005 215965 ) ( 2247925 * )
NEW li1 ( 2247465 215935 ) mcon_1090_170
NEW met2 ( 2246990 215850 ) ( 2247940 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[15] ( sky130_fd_sc_hd__buf_8_129 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 227205 1763595 ) ( * 1766580 )
NEW met1 ( 226925 1763455 ) ( 227205 * )
NEW met1 ( 226925 1678030 ) ( * 1763315 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 226805 1677890 ) ( 226925 * )
NEW met1 ( 226865 1677800 ) via_260_260_vh ( * 1677740 )
( 227030 * )
NEW met2 ( 203765 1677740 ) ( 226665 * )
NEW met2 ( 203270 1677735 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1677825 ) ( 203625 * )
NEW met2 ( 202915 1677645 ) ( 203625 * )
NEW met1 ( 226805 1677710 ) ( 226925 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[2] ( sky130_fd_sc_hd__buf_8_49 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3366650 1180320 ) ( * 2209440 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3366530 2209580 ) ( 3366650 * )
NEW met1 ( 3366590 2209670 ) via_260_260_vh
NEW met1 ( 3366530 2209760 ) ( 3366650 * )
NEW met2 ( 3366790 2209610 ) ( 3381775 * ) ( * 2209620 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2209710 ) ( 3382130 * )
NEW met2 ( 3381420 2209530 ) ( 3382130 * )
NEW met2 ( 3366060 2209610 ) ( 3366390 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[2] ( sky130_fd_sc_hd__buf_8_49 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3366510 2214115 ) ( * 2275205 )
NEW met1 ( 3366510 2213975 ) ( 3366630 * )
NEW met1 ( 3366570 2213885 ) via_260_260_vh ( * 2213825 )
( 3381570 * )
NEW met1 ( 3381710 2214340 ) ( 3381830 * )
NEW met1 ( 3381710 2213270 ) ( 3381830 * )
NEW met1 ( 3381770 2213805 ) via_260_1090_vh
NEW met1 ( 3381775 2213805 ) mcon_170_1090
NEW met2 ( 3366060 2213825 ) ( 3366370 * )
NEW met1 ( 3366510 2213795 ) ( 3366630 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[16] ( sky130_fd_sc_hd__buf_8_117 A )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3370150 1143110 ) ( * 1146370 )
NEW met1 ( 3370150 1142970 ) ( 3370430 * )
NEW met1 ( 3370430 216730 ) ( * 1142830 )
NEW met1 ( 2531130 216590 ) ( 3370430 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2531130 214650 ) ( * 216450 )
NEW met1 ( 2422290 214510 ) ( 2531130 * )
NEW met1 ( 2422290 214650 ) ( * 225450 )
NEW met1 ( 2241765 225590 ) ( 2422290 * )
NEW met1 ( 2241565 225530 ) via_260_260_hv ( * 225620 )
( 2241625 * )
NEW met2 ( 2241505 225760 ) ( * 232415 )
NEW met2 ( 2241505 225440 ) ( 2241625 * )
NEW met2 ( 2241505 216170 ) ( * 225300 )
NEW met2 ( 2241010 216030 ) ( 2241960 * )
NEW met2 ( 2241485 215940 ) via_1090_260_hv
NEW li1 ( 2241025 215965 ) ( 2241945 * )
NEW li1 ( 2241485 215935 ) mcon_1090_170
NEW met2 ( 2241010 215850 ) ( 2241960 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[15] ( sky130_fd_sc_hd__buf_8_128 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 226645 1679000 ) ( * 1767580 )
NEW met1 ( 226525 1678860 ) ( 226645 * )
NEW met1 ( 226585 1678770 ) via_260_260_vh ( * 1678710 )
( 227030 * )
NEW met2 ( 206535 1678710 ) ( 226385 * )
NEW met1 ( 206275 1679225 ) ( 206395 * )
NEW met1 ( 206275 1678155 ) ( 206395 * )
NEW met1 ( 206335 1678690 ) via_260_1090_vh
NEW met1 ( 206330 1678690 ) mcon_170_1090
NEW met1 ( 226525 1678680 ) ( 226645 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[12] ( sky130_fd_sc_hd__buf_8_139 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 223285 1696940 ) ( * 1773580 )
NEW met1 ( 223165 1696800 ) ( 223285 * )
NEW met1 ( 223225 1696710 ) via_260_260_vh ( * 1696650 )
( 223770 * )
NEW met2 ( 206535 1696650 ) ( 223025 * )
NEW met1 ( 206275 1697165 ) ( 206395 * )
NEW met1 ( 206275 1696095 ) ( 206395 * )
NEW met1 ( 206335 1696630 ) via_260_1090_vh
NEW met1 ( 206330 1696630 ) mcon_170_1090
NEW met1 ( 223165 1696620 ) ( 223285 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[2] ( sky130_fd_sc_hd__buf_8_48 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3365950 2271735 ) ( * 2274205 )
NEW met1 ( 3365950 2271595 ) ( 3366230 * )
NEW met1 ( 3366230 2213145 ) ( * 2271455 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3366230 2213005 ) ( 3366350 * )
NEW met1 ( 3366290 2212915 ) via_260_260_vh ( * 2212855 )
( 3384835 * ) ( * 2212850 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2212940 ) ( 3385190 * )
NEW met2 ( 3384480 2212760 ) ( 3385190 * )
NEW met2 ( 3366060 2212855 ) ( 3366090 * )
NEW met1 ( 3366230 2212825 ) ( 3366350 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[2] ( sky130_fd_sc_hd__buf_8_48 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3366090 1181320 ) ( * 1184275 )
NEW met1 ( 3366090 1184415 ) ( 3366370 * )
NEW met1 ( 3366370 1184555 ) ( * 2208820 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3366250 2208960 ) ( 3366370 * )
NEW met1 ( 3366310 2209050 ) via_260_260_vh
NEW met1 ( 3366250 2209140 ) ( 3366370 * )
NEW met2 ( 3366510 2208990 ) ( 3384630 * )
NEW met1 ( 3384770 2209710 ) ( 3384890 * )
NEW met1 ( 3384770 2208640 ) ( 3384890 * )
NEW met1 ( 3384830 2209175 ) via_260_1090_vh
NEW met1 ( 3384835 2209175 ) mcon_170_1090
NEW met2 ( 3366060 2208990 ) ( 3366110 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_37/X ( sky130_fd_sc_hd__buf_8_37 X )
( sky130_fd_sc_hd__buf_8_24 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3384835 2236775 ) mcon_850_170 via_850_260_hv
NEW met2 ( 3384480 2236860 ) ( 3385190 * )
NEW met2 ( 3384480 2236680 ) ( 3385190 * )
NEW met2 ( 3370970 2236775 ) ( 3384340 * )
NEW met1 ( 3370710 2236925 ) ( 3370830 * )
NEW met1 ( 3370710 2237065 ) ( * 3602860 )
NEW met1 ( 3370590 3603000 ) ( 3370710 * )
NEW met1 ( 3370650 3603090 ) via_260_260_vh
NEW met1 ( 3370590 3603180 ) ( 3370710 * )
NEW met1 ( 3370710 3603320 ) ( * 3603205 )
NEW met2 ( 3370850 3603030 ) ( 3384630 * )
NEW met1 ( 3384770 3603750 ) ( 3384890 * )
NEW met1 ( 3384770 3602680 ) ( 3384890 * )
NEW met1 ( 3384830 3603215 ) via_260_1090_vh
NEW met1 ( 3384835 3603215 ) mcon_170_1090
NEW met2 ( 3370400 3603030 ) ( 3370450 * )
NEW met2 ( 3370770 2236835 ) via_260_260_vh
NEW met2 ( 3366060 2236775 ) ( 3370570 * )
NEW met1 ( 3370710 2236745 ) ( 3370830 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[6] ( sky130_fd_sc_hd__buf_8_37 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3370570 1173320 ) ( * 1176280 )
NEW met1 ( 3370570 1176420 ) ( 3370850 * )
NEW met1 ( 3370850 1176560 ) ( * 2232740 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3370730 2232880 ) ( 3370850 * )
NEW met1 ( 3370790 2232970 ) via_260_260_vh
NEW met1 ( 3370730 2233060 ) ( 3370850 * )
NEW met2 ( 3370990 2232910 ) ( 3384630 * )
NEW met1 ( 3384770 2233630 ) ( 3384890 * )
NEW met1 ( 3384770 2232560 ) ( 3384890 * )
NEW met1 ( 3384830 2233095 ) via_260_1090_vh
NEW met1 ( 3384835 2233095 ) mcon_170_1090
NEW met2 ( 3366060 2232910 ) ( 3370590 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_unbuf[2] ( sky130_fd_sc_hd__buf_8_127 A )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3376590 212315 ) ( * 1156380 )
NEW met1 ( 2537290 212175 ) ( 3376590 * )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 2537290 211850 ) ( * 212035 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2416130 211710 ) ( 2537290 * )
NEW met1 ( 2416130 211850 ) ( * 220970 )
NEW met1 ( 2271665 221110 ) ( 2416130 * )
NEW met1 ( 2271465 221050 ) via_260_260_hv ( * 221140 )
( 2271525 * )
NEW met2 ( 2271405 221280 ) ( * 232415 )
NEW met2 ( 2271405 220960 ) ( 2271525 * )
NEW met2 ( 2271405 216170 ) ( * 220820 )
NEW met2 ( 2270910 216030 ) ( 2271860 * )
NEW met2 ( 2271385 215940 ) via_1090_260_hv
NEW li1 ( 2270925 215965 ) ( 2271845 * )
NEW li1 ( 2271385 215935 ) mcon_1090_170
NEW met2 ( 2270910 215850 ) ( 2271860 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[12] ( sky130_fd_sc_hd__buf_8_138 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 223845 1769585 ) ( * 1772580 )
NEW met1 ( 223565 1769445 ) ( 223845 * )
NEW met1 ( 223565 1695970 ) ( * 1769305 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 223445 1695830 ) ( 223565 * )
NEW met1 ( 223505 1695740 ) via_260_260_vh ( * 1695680 )
( 223770 * )
NEW met2 ( 203765 1695680 ) ( 223305 * )
NEW met2 ( 203270 1695675 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1695765 ) ( 203625 * )
NEW met2 ( 202915 1695585 ) ( 203625 * )
NEW met1 ( 223445 1695650 ) ( 223565 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_171/X ( sky130_fd_sc_hd__buf_8_171 X )
( sky130_fd_sc_hd__buf_8_149 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 206220 3010255 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3010340 ) ( 206575 * )
NEW met2 ( 206715 3010240 ) ( 217545 * )
NEW met1 ( 217685 3010390 ) ( 217805 * )
NEW met1 ( 217745 3010300 ) via_260_260_vh
NEW met1 ( 217685 3010210 ) ( 217805 * )
NEW met1 ( 217685 1726840 ) ( * 3010070 )
NEW met1 ( 217565 1726700 ) ( 217685 * )
NEW met1 ( 217625 1726610 ) via_260_260_vh ( * 1726550 )
( 223670 * )
NEW met2 ( 206535 1726550 ) ( 217425 * )
NEW met1 ( 206275 1727065 ) ( 206395 * )
NEW met1 ( 206275 1725995 ) ( 206395 * )
NEW met1 ( 206335 1726530 ) via_260_1090_vh
NEW met1 ( 206330 1726530 ) mcon_170_1090
NEW met1 ( 217565 1726520 ) ( 217685 * )
NEW met2 ( 217945 3010240 ) ( 221530 * )
NEW met2 ( 205865 3010160 ) ( 206575 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_69/X ( sky130_fd_sc_hd__buf_8_69 X )
( sky130_fd_sc_hd__buf_8_148 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 718445 215935 ) mcon_170_850
NEW met1 ( 718380 216350 ) ( 718500 * )
NEW met2 ( 718430 216430 ) ( * 230460 )
NEW met2 ( 718430 230600 ) ( 718550 * )
NEW met2 ( 718490 230690 ) via_260_260_hv
NEW met2 ( 718430 230780 ) ( 718550 * )
NEW met2 ( 718430 230920 ) ( * 232275 )
NEW met1 ( 701365 230630 ) ( 718290 * )
NEW met1 ( 701365 230770 ) ( * 231050 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 217825 231190 ) ( 701365 * )
NEW met1 ( 217825 231330 ) ( * 1721545 )
NEW met1 ( 217825 1721685 ) ( 217945 * )
NEW met1 ( 217885 1721775 ) via_260_260_vh
NEW met1 ( 217825 1721865 ) ( 217945 * )
NEW met2 ( 218085 1721715 ) ( 223670 * )
NEW met2 ( 203475 1721715 ) ( 217685 * )
NEW met1 ( 203215 1722435 ) ( 203335 * )
NEW met1 ( 203215 1721365 ) ( 203335 * )
NEW met1 ( 203275 1721900 ) via_260_1090_vh
NEW met1 ( 203270 1721900 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 718380 215520 ) ( 718500 * )
NEW met1 ( 718440 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_69/A ( sky130_fd_sc_hd__buf_8_69 A )
( sky130_fd_sc_hd__buf_8_104 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 722625 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 722150 216030 ) ( 723100 * )
NEW met2 ( 722645 216170 ) ( * 230480 )
NEW met2 ( 722645 230620 ) ( 722765 * )
NEW met2 ( 722705 230710 ) via_260_260_hv
NEW met2 ( 722645 230800 ) ( 722765 * )
NEW met2 ( 722645 230940 ) ( * 232275 )
NEW met1 ( 722905 230770 ) ( 784805 * )
NEW met1 ( 784805 230910 ) ( * 231190 )
NEW met1 ( 784805 231330 ) ( 2195490 * ) ( * 231390 )
via_260_260_hv ( * 231480 ) ( 2195550 * )
NEW met2 ( 2195430 231620 ) ( * 232415 )
NEW met2 ( 2195430 231300 ) ( 2195550 * )
NEW met2 ( 2195430 216430 ) ( * 231160 )
NEW met1 ( 2195380 216350 ) ( 2195500 * )
NEW met1 ( 2195380 215520 ) ( 2195500 * )
NEW met1 ( 2195440 215935 ) via_260_850_vh
NEW met1 ( 2195445 215935 ) mcon_170_850
NEW met2 ( 722150 215850 ) ( 723100 * )
NEW li1 ( 722165 215965 ) ( 723085 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[1] ( sky130_fd_sc_hd__buf_8_47 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3364830 2269730 ) ( * 2272205 )
NEW met1 ( 3364830 2269590 ) ( 3365110 * )
NEW met1 ( 3365110 2207165 ) ( * 2269450 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3365110 2207025 ) ( 3365230 * )
NEW met1 ( 3365170 2206935 ) via_260_260_vh ( * 2206875 )
( 3384835 * ) ( * 2206870 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2206960 ) ( 3385190 * )
NEW met2 ( 3384480 2206780 ) ( 3385190 * )
NEW met2 ( 3364935 2206875 ) ( 3364970 * )
NEW met1 ( 3365110 2206845 ) ( 3365230 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[1] ( sky130_fd_sc_hd__buf_8_47 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3364970 1183320 ) ( * 1186290 )
NEW met1 ( 3364970 1186430 ) ( 3365250 * )
NEW met1 ( 3365250 1186570 ) ( * 2202840 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3365130 2202980 ) ( 3365250 * )
NEW met1 ( 3365190 2203070 ) via_260_260_vh
NEW met1 ( 3365130 2203160 ) ( 3365250 * )
NEW met2 ( 3365390 2203010 ) ( 3384630 * )
NEW met1 ( 3384770 2203730 ) ( 3384890 * )
NEW met1 ( 3384770 2202660 ) ( 3384890 * )
NEW met1 ( 3384830 2203195 ) via_260_1090_vh
NEW met1 ( 3384835 2203195 ) mcon_170_1090
NEW met2 ( 3364970 2203010 ) ( 3364990 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[6] ( sky130_fd_sc_hd__buf_8_36 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3371130 1172320 ) ( * 2233360 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3371010 2233500 ) ( 3371130 * )
NEW met1 ( 3371070 2233590 ) via_260_260_vh
NEW met1 ( 3371010 2233680 ) ( 3371130 * )
NEW met2 ( 3371270 2233530 ) ( 3381775 * ) ( * 2233540 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2233630 ) ( 3382130 * )
NEW met2 ( 3381420 2233450 ) ( 3382130 * )
NEW met2 ( 3366060 2233530 ) ( 3370870 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_36/A ( sky130_fd_sc_hd__buf_8_36 A )
( sky130_fd_sc_hd__buf_8_25 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3381775 2237725 ) mcon_170_1090
NEW met1 ( 3381710 2238260 ) ( 3381830 * )
NEW met2 ( 3371250 2237745 ) ( 3381570 * )
NEW met1 ( 3370990 2237895 ) ( 3371110 * )
NEW met1 ( 3370990 2238035 ) ( * 3603480 )
NEW met1 ( 3370870 3603620 ) ( 3370990 * )
NEW met1 ( 3370930 3603710 ) via_260_260_vh
NEW met1 ( 3370870 3603800 ) ( 3370990 * )
NEW met2 ( 3371130 3603650 ) ( 3381775 * ) ( * 3603660 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 3603750 ) ( 3382130 * )
NEW met2 ( 3381420 3603570 ) ( 3382130 * )
NEW met2 ( 3370400 3603650 ) ( 3370730 * )
NEW met2 ( 3371050 2237805 ) via_260_260_vh
NEW met2 ( 3366060 2237745 ) ( 3370850 * )
NEW met1 ( 3370990 2237715 ) ( 3371110 * )
NEW met1 ( 3381710 2237190 ) ( 3381830 * )
NEW met1 ( 3381770 2237725 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[6] ( sky130_fd_sc_hd__buf_8_25 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3370850 3608155 ) ( * 3641535 )
NEW met1 ( 3370850 3608015 ) ( 3370970 * )
NEW met1 ( 3370910 3607925 ) via_260_260_vh ( * 3607865 )
( 3381570 * )
NEW met1 ( 3381710 3608380 ) ( 3381830 * )
NEW met1 ( 3381710 3607310 ) ( 3381830 * )
NEW met1 ( 3381770 3607845 ) via_260_1090_vh
NEW met1 ( 3381775 3607845 ) mcon_170_1090
NEW met2 ( 3370400 3607865 ) ( 3370710 * )
NEW met1 ( 3370850 3607835 ) ( 3370970 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[7] ( sky130_fd_sc_hd__buf_8_104 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3363710 222610 ) ( * 1132620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2523290 222470 ) ( 3363710 * )
NEW met1 ( 2523290 218570 ) ( * 222330 )
NEW met1 ( 2430130 218430 ) ( 2523290 * )
NEW met1 ( 2430130 218570 ) ( * 231330 )
NEW met1 ( 2199905 231470 ) ( 2430130 * )
NEW met1 ( 2199705 231410 ) via_260_260_hv ( * 231500 )
( 2199765 * )
NEW met2 ( 2199645 231640 ) ( * 232415 )
NEW met2 ( 2199645 231320 ) ( 2199765 * )
NEW met2 ( 2199645 216170 ) ( * 231180 )
NEW met2 ( 2199150 216030 ) ( 2200100 * )
NEW met2 ( 2199625 215940 ) via_1090_260_hv
NEW li1 ( 2199165 215965 ) ( 2200085 * )
NEW li1 ( 2199625 215935 ) mcon_1090_170
NEW met2 ( 2199150 215850 ) ( 2200100 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_unbuf[0] ( sky130_fd_sc_hd__buf_8_126 A )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3374910 213370 ) ( * 1154370 )
NEW met1 ( 2535610 213230 ) ( 3374910 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2535610 212410 ) ( * 213090 )
NEW met1 ( 2417810 212270 ) ( 2535610 * )
NEW met1 ( 2417810 212410 ) ( * 222090 )
NEW met1 ( 2265565 222230 ) ( 2417810 * )
NEW met1 ( 2265365 222170 ) via_260_260_hv ( * 222260 )
( 2265425 * )
NEW met2 ( 2265425 222400 ) ( * 232415 )
NEW met2 ( 2265305 222080 ) ( 2265425 * )
NEW met2 ( 2265425 216170 ) ( * 221940 )
NEW met2 ( 2264930 216030 ) ( 2265880 * )
NEW met2 ( 2265405 215940 ) via_1090_260_hv
NEW li1 ( 2264945 215965 ) ( 2265865 * )
NEW li1 ( 2265405 215935 ) mcon_1090_170
NEW met2 ( 2264930 215850 ) ( 2265880 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_178/A ( sky130_fd_sc_hd__buf_8_178 A )
( sky130_fd_sc_hd__buf_8_137 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 203160 2985885 ) mcon_170_1090
NEW met1 ( 203105 2986420 ) ( 203225 * )
NEW met2 ( 203365 2985700 ) ( 222305 * )
NEW met1 ( 222445 2985850 ) ( 222565 * )
NEW met1 ( 222505 2985760 ) via_260_260_vh
NEW met1 ( 222445 2985670 ) ( 222565 * )
NEW met1 ( 222445 1701950 ) ( * 2985530 )
NEW met1 ( 222325 1701810 ) ( 222445 * )
NEW met1 ( 222385 1701720 ) via_260_260_vh ( * 1701660 )
( 223670 * )
NEW met2 ( 203765 1701660 ) ( 222185 * )
NEW met2 ( 203270 1701655 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1701745 ) ( 203625 * )
NEW met2 ( 202915 1701565 ) ( 203625 * )
NEW met1 ( 222325 1701630 ) ( 222445 * )
NEW met2 ( 222705 2985700 ) ( 222650 * )
NEW met1 ( 203105 2985350 ) ( 203225 * )
NEW met1 ( 203165 2985885 ) via_260_1090_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_170/A ( sky130_fd_sc_hd__buf_8_170 A )
( sky130_fd_sc_hd__buf_8_148 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 203160 3009805 ) mcon_170_1090
NEW met1 ( 203105 3010340 ) ( 203225 * )
NEW met2 ( 203365 3009620 ) ( 217825 * )
NEW met1 ( 217965 3009770 ) ( 218085 * )
NEW met1 ( 218025 3009680 ) via_260_260_vh
NEW met1 ( 217965 3009590 ) ( 218085 * )
NEW met1 ( 217965 1725870 ) ( * 3009450 )
NEW met1 ( 217845 1725730 ) ( 217965 * )
NEW met1 ( 217905 1725640 ) via_260_260_vh ( * 1725580 )
( 223670 * )
NEW met2 ( 203765 1725580 ) ( 217705 * )
NEW met2 ( 203270 1725575 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1725665 ) ( 203625 * )
NEW met2 ( 202915 1725485 ) ( 203625 * )
NEW met1 ( 217845 1725550 ) ( 217965 * )
NEW met2 ( 218225 3009620 ) ( 221530 * )
NEW met1 ( 203105 3009270 ) ( 203225 * )
NEW met1 ( 203165 3009805 ) via_260_1090_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_68/X ( sky130_fd_sc_hd__buf_8_68 X )
( sky130_fd_sc_hd__buf_8_101 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 721675 212875 ) mcon_170_850
NEW met1 ( 721610 213290 ) ( 721730 * )
NEW met2 ( 721675 213370 ) ( * 230760 )
NEW met2 ( 721675 230900 ) ( 721795 * )
NEW met2 ( 721735 230990 ) via_260_260_hv
NEW met2 ( 721675 231080 ) ( 721795 * )
NEW met2 ( 721675 231220 ) ( * 232275 )
NEW met1 ( 721935 231050 ) ( 784245 * )
NEW met1 ( 784245 231190 ) ( * 231750 )
NEW met1 ( 784245 231890 ) ( 2194870 * ) ( * 231950 )
via_260_260_hv ( * 232040 ) ( 2194930 * )
NEW met2 ( 2194810 232180 ) ( * 232415 )
NEW met2 ( 2194810 231860 ) ( 2194930 * )
NEW met2 ( 2194810 213110 ) ( * 231720 )
NEW met2 ( 2194520 212970 ) ( 2195470 * )
NEW met2 ( 2194995 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2194520 212790 ) ( 2195470 * )
NEW met1 ( 721610 212460 ) ( 721730 * )
NEW met1 ( 721670 212875 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_68/A ( sky130_fd_sc_hd__buf_8_68 A )
( sky130_fd_sc_hd__buf_8_141 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 717995 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 717520 212970 ) ( 718470 * )
NEW met2 ( 717810 213110 ) ( * 230740 )
NEW met2 ( 717810 230880 ) ( 717930 * )
NEW met2 ( 717870 230970 ) via_260_260_hv
NEW met2 ( 717810 231060 ) ( 717930 * )
NEW met2 ( 717810 231200 ) ( * 232275 )
NEW met1 ( 701665 230910 ) ( 717670 * )
NEW met1 ( 701665 231050 ) ( * 231610 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 218665 231750 ) ( 701665 * )
NEW met1 ( 218665 231890 ) ( * 1716185 )
NEW met1 ( 218665 1716325 ) ( 218785 * )
NEW met1 ( 218725 1716415 ) via_260_260_vh
NEW met1 ( 218665 1716505 ) ( 218785 * )
NEW met2 ( 218925 1716355 ) ( 223670 * )
NEW met2 ( 206825 1716355 ) ( 218525 * )
NEW met2 ( 206330 1716365 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1716455 ) ( 206685 * )
NEW met2 ( 205975 1716275 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 717520 212790 ) ( 718470 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_93/A ( sky130_fd_sc_hd__buf_8_93 A )
( sky130_fd_sc_hd__buf_8_79 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2165095 212875 ) mcon_1090_170
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2164620 212970 ) ( 2165570 * )
NEW met2 ( 2164910 213110 ) ( * 235920 )
NEW met2 ( 2164910 236060 ) ( 2165030 * )
NEW met2 ( 2164970 236150 ) via_260_260_hv
NEW met2 ( 2164910 236240 ) ( 2165030 * )
NEW met2 ( 2164910 236380 ) ( * 236325 )
NEW met1 ( 780045 236090 ) ( 2164770 * )
NEW met1 ( 780045 233990 ) ( * 235950 )
NEW met1 ( 704315 233850 ) ( 780045 * )
NEW met1 ( 704315 233990 ) ( * 235950 )
NEW met1 ( 692035 236090 ) ( 704315 * )
NEW met1 ( 691835 236030 ) via_260_260_hv ( * 236120 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 691895 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 691775 236260 ) ( * 236190 )
NEW met2 ( 691775 235940 ) ( 691895 * )
NEW met2 ( 691775 213370 ) ( * 235800 )
NEW met1 ( 691710 213290 ) ( 691830 * )
NEW met1 ( 691710 212460 ) ( 691830 * )
NEW met1 ( 691770 212875 ) via_260_850_vh
NEW met1 ( 691775 212875 ) mcon_170_850
NEW met2 ( 2164620 212790 ) ( 2165570 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_79/A ( sky130_fd_sc_hd__buf_8_79 A )
( sky130_fd_sc_hd__buf_8_132 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 688095 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 687620 212970 ) ( 688570 * )
NEW met2 ( 687910 213110 ) ( * 235780 )
NEW met2 ( 687910 235920 ) ( 688030 * )
NEW met2 ( 687970 236010 ) via_260_260_hv
NEW met2 ( 687910 236100 ) ( 688030 * )
NEW met2 ( 687910 236240 ) ( * 236165 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 224265 235950 ) ( 687770 * )
NEW met1 ( 224265 236090 ) ( * 1686285 )
NEW met1 ( 224265 1686425 ) ( 224385 * )
NEW met1 ( 224325 1686515 ) via_260_260_vh
NEW met1 ( 224265 1686605 ) ( 224385 * )
NEW met2 ( 224525 1686455 ) ( 224735 * )
NEW met2 ( 206825 1686455 ) ( 224125 * )
NEW met2 ( 206330 1686465 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1686555 ) ( 206685 * )
NEW met2 ( 205975 1686375 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 687620 212790 ) ( 688570 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[1] ( sky130_fd_sc_hd__buf_8_46 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3365530 1182320 ) ( * 2203460 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3365410 2203600 ) ( 3365530 * )
NEW met1 ( 3365470 2203690 ) via_260_260_vh
NEW met1 ( 3365410 2203780 ) ( 3365530 * )
NEW met2 ( 3365670 2203630 ) ( 3381775 * ) ( * 2203640 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2203730 ) ( 3382130 * )
NEW met2 ( 3381420 2203550 ) ( 3382130 * )
NEW met2 ( 3364970 2203630 ) ( 3365270 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[1] ( sky130_fd_sc_hd__buf_8_46 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3365390 2208135 ) ( * 2273205 )
NEW met1 ( 3365390 2207995 ) ( 3365510 * )
NEW met1 ( 3365450 2207905 ) via_260_260_vh ( * 2207845 )
( 3381570 * )
NEW met1 ( 3381710 2208360 ) ( 3381830 * )
NEW met1 ( 3381710 2207290 ) ( 3381830 * )
NEW met1 ( 3381770 2207825 ) via_260_1090_vh
NEW met1 ( 3381775 2207825 ) mcon_170_1090
NEW met2 ( 3364935 2207845 ) ( 3365250 * )
NEW met1 ( 3365390 2207815 ) ( 3365510 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[5] ( sky130_fd_sc_hd__buf_8_35 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3369310 2277735 ) ( * 2280205 )
NEW met1 ( 3369310 2277595 ) ( 3369590 * )
NEW met1 ( 3369590 2231085 ) ( * 2277455 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3369590 2230945 ) ( 3369710 * )
NEW met1 ( 3369650 2230855 ) via_260_260_vh ( * 2230795 )
( 3384835 * ) ( * 2230790 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2230880 ) ( 3385190 * )
NEW met2 ( 3384480 2230700 ) ( 3385190 * )
NEW met2 ( 3366060 2230795 ) ( 3369450 * )
NEW met1 ( 3369590 2230765 ) ( 3369710 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[5] ( sky130_fd_sc_hd__buf_8_35 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3369450 1175320 ) ( * 1178290 )
NEW met1 ( 3369450 1178430 ) ( 3369730 * )
NEW met1 ( 3369730 1178570 ) ( * 2226760 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3369610 2226900 ) ( 3369730 * )
NEW met1 ( 3369670 2226990 ) via_260_260_vh
NEW met1 ( 3369610 2227080 ) ( 3369730 * )
NEW met2 ( 3369870 2226930 ) ( 3384630 * )
NEW met1 ( 3384770 2227650 ) ( 3384890 * )
NEW met1 ( 3384770 2226580 ) ( 3384890 * )
NEW met1 ( 3384830 2227115 ) via_260_1090_vh
NEW met1 ( 3384835 2227115 ) mcon_170_1090
NEW met2 ( 3366060 2226930 ) ( 3369470 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[8] ( sky130_fd_sc_hd__buf_8_103 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3362590 223450 ) ( * 1130620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2522170 223310 ) ( 3362590 * )
NEW met1 ( 2522170 219130 ) ( * 223170 )
NEW met1 ( 2431250 218990 ) ( 2522170 * )
NEW met1 ( 2431250 219130 ) ( * 232170 )
NEW met1 ( 2193805 232310 ) ( 2431250 * )
NEW met1 ( 2193605 232250 ) via_260_260_hv ( * 232340 )
( 2193665 * )
NEW met2 ( 2193665 232480 ) ( * 232415 )
NEW met2 ( 2193545 232160 ) ( 2193665 * )
NEW met2 ( 2193665 216170 ) ( * 232020 )
NEW met2 ( 2193170 216030 ) ( 2194120 * )
NEW met2 ( 2193645 215940 ) via_1090_260_hv
NEW li1 ( 2193185 215965 ) ( 2194105 * )
NEW li1 ( 2193645 215935 ) mcon_1090_170
NEW met2 ( 2193170 215850 ) ( 2194120 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_unbuf[1] ( sky130_fd_sc_hd__buf_8_125 A )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3375750 212810 ) ( * 1155380 )
NEW met1 ( 2536450 212670 ) ( 3375750 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2536450 212130 ) ( * 212530 )
NEW met1 ( 2416970 211990 ) ( 2536450 * )
NEW met1 ( 2416970 212130 ) ( * 221530 )
NEW met1 ( 2270695 221670 ) ( 2416970 * )
NEW met1 ( 2270495 221610 ) via_260_260_hv ( * 221700 )
( 2270555 * )
NEW met2 ( 2270435 221840 ) ( * 232415 )
NEW met2 ( 2270435 221520 ) ( 2270555 * )
NEW met2 ( 2270435 214240 ) ( * 221380 )
NEW met2 ( 2270435 214100 ) ( 2271070 * )
NEW met2 ( 2271070 213110 ) ( * 213960 )
NEW met2 ( 2270410 212970 ) ( 2271360 * )
NEW met2 ( 2270885 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2270410 212790 ) ( 2271360 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_179/X ( sky130_fd_sc_hd__buf_8_179 X )
( sky130_fd_sc_hd__buf_8_136 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 206220 2986335 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 2986420 ) ( 206575 * )
NEW met2 ( 206715 2986320 ) ( 222025 * )
NEW met1 ( 222165 2986470 ) ( 222285 * )
NEW met1 ( 222225 2986380 ) via_260_260_vh
NEW met1 ( 222165 2986290 ) ( 222285 * )
NEW met1 ( 222165 1702920 ) ( * 2986150 )
NEW met1 ( 222045 1702780 ) ( 222165 * )
NEW met1 ( 222105 1702690 ) via_260_260_vh ( * 1702630 )
( 223670 * )
NEW met2 ( 206535 1702630 ) ( 221905 * )
NEW met1 ( 206275 1703145 ) ( 206395 * )
NEW met1 ( 206275 1702075 ) ( 206395 * )
NEW met1 ( 206335 1702610 ) via_260_1090_vh
NEW met1 ( 206330 1702610 ) mcon_170_1090
NEW met1 ( 222045 1702600 ) ( 222165 * )
NEW met2 ( 222425 2986320 ) ( 222650 * )
NEW met2 ( 205865 2986240 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[0] ( sky130_fd_sc_hd__buf_8_13 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3364410 1184320 ) ( * 2197480 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3364290 2197620 ) ( 3364410 * )
NEW met1 ( 3364350 2197710 ) via_260_260_vh
NEW met1 ( 3364290 2197800 ) ( 3364410 * )
NEW met2 ( 3364550 2197650 ) ( 3381775 * ) ( * 2197660 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2197750 ) ( 3382130 * )
NEW met2 ( 3381420 2197570 ) ( 3382130 * )
NEW met2 ( 3363820 2197650 ) ( 3364150 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[0] ( sky130_fd_sc_hd__buf_8_13 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3364270 2202155 ) ( * 2271205 )
NEW met1 ( 3364270 2202015 ) ( 3364390 * )
NEW met1 ( 3364330 2201925 ) via_260_260_vh ( * 2201865 )
( 3381570 * )
NEW met1 ( 3381710 2202380 ) ( 3381830 * )
NEW met1 ( 3381710 2201310 ) ( 3381830 * )
NEW met1 ( 3381770 2201845 ) via_260_1090_vh
NEW met1 ( 3381775 2201845 ) mcon_170_1090
NEW met2 ( 3363820 2201865 ) ( 3364130 * )
NEW met1 ( 3364270 2201835 ) ( 3364390 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[6] ( sky130_fd_sc_hd__buf_8_24 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3370290 3638605 ) ( * 3640535 )
NEW met1 ( 3370290 3638465 ) ( 3370570 * )
NEW met1 ( 3370570 3607185 ) ( * 3638325 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3370570 3607045 ) ( 3370690 * )
NEW met1 ( 3370630 3606955 ) via_260_260_vh ( * 3606895 )
( 3384835 * ) ( * 3606890 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 3606980 ) ( 3385190 * )
NEW met2 ( 3384480 3606800 ) ( 3385190 * )
NEW met2 ( 3370400 3606895 ) ( 3370430 * )
NEW met1 ( 3370570 3606865 ) ( 3370690 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_67/X ( sky130_fd_sc_hd__buf_8_67 X )
( sky130_fd_sc_hd__buf_8_102 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 727655 212875 ) mcon_170_850
NEW met1 ( 727590 213290 ) ( 727710 * )
NEW met2 ( 727655 213370 ) ( * 230200 )
NEW met2 ( 727655 230340 ) ( 727775 * )
NEW met2 ( 727715 230430 ) via_260_260_hv
NEW met2 ( 727655 230520 ) ( 727775 * )
NEW met2 ( 727655 230660 ) ( * 232275 )
NEW met1 ( 727915 230490 ) ( 785085 * )
NEW met1 ( 785085 230630 ) ( * 230910 )
NEW met1 ( 785085 231050 ) ( 2200850 * ) ( * 231110 )
via_260_260_hv ( * 231200 ) ( 2200910 * )
NEW met2 ( 2200790 231340 ) ( * 232415 )
NEW met2 ( 2200790 231020 ) ( 2200910 * )
NEW met2 ( 2200790 213110 ) ( * 230880 )
NEW met2 ( 2200500 212970 ) ( 2201450 * )
NEW met2 ( 2200975 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2200500 212790 ) ( 2201450 * )
NEW met1 ( 727590 212460 ) ( 727710 * )
NEW met1 ( 727650 212875 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_67/A ( sky130_fd_sc_hd__buf_8_67 A )
( sky130_fd_sc_hd__buf_8_149 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 723975 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 723500 212970 ) ( 724450 * )
NEW met2 ( 723790 213110 ) ( * 230180 )
NEW met2 ( 723790 230320 ) ( 723910 * )
NEW met2 ( 723850 230410 ) via_260_260_hv
NEW met2 ( 723790 230500 ) ( 723910 * )
NEW met2 ( 723790 230640 ) ( * 232275 )
NEW met1 ( 701085 230350 ) ( 723650 * )
NEW met1 ( 701085 230490 ) ( * 230770 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 217545 230910 ) ( 701085 * )
NEW met1 ( 217545 231050 ) ( * 1722165 )
NEW met1 ( 217545 1722305 ) ( 217665 * )
NEW met1 ( 217605 1722395 ) via_260_260_vh
NEW met1 ( 217545 1722485 ) ( 217665 * )
NEW met2 ( 217805 1722335 ) ( 223670 * )
NEW met2 ( 206825 1722335 ) ( 217405 * )
NEW met2 ( 206330 1722345 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1722435 ) ( 206685 * )
NEW met2 ( 205975 1722255 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 723500 212790 ) ( 724450 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_78/X ( sky130_fd_sc_hd__buf_8_78 X )
( sky130_fd_sc_hd__buf_8_138 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 688545 215935 ) mcon_170_850
NEW met1 ( 688480 216350 ) ( 688600 * )
NEW met2 ( 688530 216430 ) ( * 235220 )
NEW met2 ( 688530 235360 ) ( 688650 * )
NEW met2 ( 688590 235450 ) via_260_260_hv
NEW met2 ( 688530 235540 ) ( 688650 * )
NEW met2 ( 688530 235680 ) ( * 235745 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 223425 235390 ) ( 688390 * )
NEW met1 ( 223425 235530 ) ( * 1691645 )
NEW met1 ( 223425 1691785 ) ( 223545 * )
NEW met1 ( 223485 1691875 ) via_260_260_vh
NEW met1 ( 223425 1691965 ) ( 223545 * )
NEW met2 ( 223685 1691815 ) ( 223675 * )
NEW met2 ( 203475 1691815 ) ( 223285 * )
NEW met1 ( 203215 1692535 ) ( 203335 * )
NEW met1 ( 203215 1691465 ) ( 203335 * )
NEW met1 ( 203275 1692000 ) via_260_1090_vh
NEW met1 ( 203270 1692000 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 688480 215520 ) ( 688600 * )
NEW met1 ( 688540 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_92/X ( sky130_fd_sc_hd__buf_8_92 X )
( sky130_fd_sc_hd__buf_8_78 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2165545 215935 ) mcon_170_850
NEW met1 ( 2165480 216350 ) ( 2165600 * )
NEW met2 ( 2165530 216430 ) ( * 235360 )
NEW met2 ( 2165530 235500 ) ( 2165650 * )
NEW met2 ( 2165590 235590 ) via_260_260_hv
NEW met2 ( 2165530 235680 ) ( 2165650 * )
NEW met2 ( 2165530 235820 ) ( * 235745 )
NEW met1 ( 780605 235530 ) ( 2165390 * )
NEW met1 ( 780605 233710 ) ( * 235390 )
NEW met1 ( 703755 233570 ) ( 780605 * )
NEW met1 ( 703755 233710 ) ( * 235390 )
NEW met1 ( 693005 235530 ) ( 703755 * )
NEW met1 ( 692805 235470 ) via_260_260_hv ( * 235560 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 692865 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 692745 235700 ) ( * 235625 )
NEW met2 ( 692745 235380 ) ( 692865 * )
NEW met2 ( 692745 216170 ) ( * 235240 )
NEW met2 ( 692250 216030 ) ( 693200 * )
NEW met2 ( 692725 215940 ) via_1090_260_hv
NEW li1 ( 692265 215965 ) ( 693185 * )
NEW li1 ( 692725 215935 ) mcon_1090_170
NEW met2 ( 692250 215850 ) ( 693200 * )
NEW met1 ( 2165480 215520 ) ( 2165600 * )
NEW met1 ( 2165540 215935 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[15] ( sky130_fd_sc_hd__buf_8_89 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3355310 1114350 ) ( * 1117660 )
NEW met1 ( 3355030 1114210 ) ( 3355310 * )
NEW met1 ( 3355030 229050 ) ( * 1114070 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2514610 228910 ) ( 3355030 * )
NEW met1 ( 2514610 222770 ) ( * 228770 )
NEW met1 ( 2438810 222630 ) ( 2514610 * )
NEW met1 ( 2438810 222770 ) ( * 237770 )
NEW met1 ( 2157075 237910 ) ( 2438810 * )
NEW met1 ( 2156875 237850 ) via_260_260_hv ( * 237940 )
( 2156935 * )
NEW met2 ( 2156815 238080 ) ( * 238015 )
NEW met2 ( 2156815 237760 ) ( 2156935 * )
NEW met2 ( 2156815 213370 ) ( * 237620 )
NEW met1 ( 2156750 213290 ) ( 2156870 * )
NEW met1 ( 2156750 212460 ) ( 2156870 * )
NEW met1 ( 2156810 212875 ) via_260_850_vh
NEW met1 ( 2156815 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[0] ( sky130_fd_sc_hd__buf_8_12 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3363710 2267705 ) ( * 2270205 )
NEW met1 ( 3363710 2267565 ) ( 3363990 * )
NEW met1 ( 3363990 2201185 ) ( * 2267425 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3363990 2201045 ) ( 3364110 * )
NEW met1 ( 3364050 2200955 ) via_260_260_vh ( * 2200895 )
( 3384835 * ) ( * 2200890 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2200980 ) ( 3385190 * )
NEW met2 ( 3384480 2200800 ) ( 3385190 * )
NEW met2 ( 3363820 2200895 ) ( 3363850 * )
NEW met1 ( 3363990 2200865 ) ( 3364110 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[0] ( sky130_fd_sc_hd__buf_8_12 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3363850 1185320 ) ( * 1188015 )
NEW met1 ( 3363850 1188155 ) ( 3364130 * )
NEW met1 ( 3364130 1188295 ) ( * 2196860 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3364010 2197000 ) ( 3364130 * )
NEW met1 ( 3364070 2197090 ) via_260_260_vh
NEW met1 ( 3364010 2197180 ) ( 3364130 * )
NEW met2 ( 3364270 2197030 ) ( 3384630 * )
NEW met1 ( 3384770 2197750 ) ( 3384890 * )
NEW met1 ( 3384770 2196680 ) ( 3384890 * )
NEW met1 ( 3384830 2197215 ) via_260_1090_vh
NEW met1 ( 3384835 2197215 ) mcon_170_1090
NEW met2 ( 3363820 2197030 ) ( 3363870 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[5] ( sky130_fd_sc_hd__buf_8_34 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3370010 1174320 ) ( * 2227380 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3369890 2227520 ) ( 3370010 * )
NEW met1 ( 3369950 2227610 ) via_260_260_vh
NEW met1 ( 3369890 2227700 ) ( 3370010 * )
NEW met2 ( 3370150 2227550 ) ( 3381775 * ) ( * 2227560 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2227650 ) ( 3382130 * )
NEW met2 ( 3381420 2227470 ) ( 3382130 * )
NEW met2 ( 3366060 2227550 ) ( 3369750 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[5] ( sky130_fd_sc_hd__buf_8_34 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3369870 2232055 ) ( * 2281205 )
NEW met1 ( 3369870 2231915 ) ( 3369990 * )
NEW met1 ( 3369930 2231825 ) via_260_260_vh ( * 2231765 )
( 3381570 * )
NEW met1 ( 3381710 2232280 ) ( 3381830 * )
NEW met1 ( 3381710 2231210 ) ( 3381830 * )
NEW met1 ( 3381770 2231745 ) via_260_1090_vh
NEW met1 ( 3381775 2231745 ) mcon_170_1090
NEW met2 ( 3366060 2231765 ) ( 3369730 * )
NEW met1 ( 3369870 2231735 ) ( 3369990 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[7] ( sky130_fd_sc_hd__buf_8_102 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3364270 1130215 ) ( * 1133610 )
NEW met1 ( 3363990 1130075 ) ( 3364270 * )
NEW met1 ( 3363990 222330 ) ( * 1129935 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2523570 222190 ) ( 3363990 * )
NEW met1 ( 2523570 218290 ) ( * 222050 )
NEW met1 ( 2429850 218150 ) ( 2523570 * )
NEW met1 ( 2429850 218290 ) ( * 231050 )
NEW met1 ( 2204915 231190 ) ( 2429850 * )
NEW met1 ( 2204715 231130 ) via_260_260_hv ( * 231220 )
( 2204775 * )
NEW met2 ( 2204655 231360 ) ( * 232415 )
NEW met2 ( 2204655 231040 ) ( 2204775 * )
NEW met2 ( 2204655 213370 ) ( * 230900 )
NEW met1 ( 2204590 213290 ) ( 2204710 * )
NEW met1 ( 2204590 212460 ) ( 2204710 * )
NEW met1 ( 2204650 212875 ) via_260_850_vh
NEW met1 ( 2204655 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[19] ( sky130_fd_sc_hd__buf_8_124 X )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3374070 213930 ) ( * 1153380 )
NEW met1 ( 2534770 213790 ) ( 3374070 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2534770 212690 ) ( * 213650 )
NEW met1 ( 2418650 212550 ) ( 2534770 * )
NEW met1 ( 2418650 212690 ) ( * 222650 )
NEW met1 ( 2264715 222790 ) ( 2418650 * )
NEW met1 ( 2264515 222730 ) via_260_260_hv ( * 222820 )
( 2264575 * )
NEW met2 ( 2264455 222960 ) ( * 232415 )
NEW met2 ( 2264455 222640 ) ( 2264575 * )
NEW met2 ( 2264455 213370 ) ( * 222500 )
NEW met1 ( 2264390 213290 ) ( 2264510 * )
NEW met1 ( 2264390 212460 ) ( 2264510 * )
NEW met1 ( 2264450 212875 ) via_260_850_vh
NEW met1 ( 2264455 212875 ) mcon_170_850 ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_176/A ( sky130_fd_sc_hd__buf_8_176 A )
( sky130_fd_sc_hd__buf_8_135 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 203160 2991865 ) mcon_170_1090
NEW met1 ( 203105 2992400 ) ( 203225 * )
NEW met2 ( 203365 2991680 ) ( 221185 * )
NEW met1 ( 221325 2991830 ) ( 221445 * )
NEW met1 ( 221385 2991740 ) via_260_260_vh
NEW met1 ( 221325 2991650 ) ( 221445 * )
NEW met1 ( 221325 1707930 ) ( * 2991510 )
NEW met1 ( 221205 1707790 ) ( 221325 * )
NEW met1 ( 221265 1707700 ) via_260_260_vh ( * 1707640 )
( 223670 * )
NEW met2 ( 203765 1707640 ) ( 221065 * )
NEW met2 ( 203270 1707635 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1707725 ) ( 203625 * )
NEW met2 ( 202915 1707545 ) ( 203625 * )
NEW met1 ( 221205 1707610 ) ( 221325 * )
NEW met2 ( 221585 2991680 ) ( 221605 * )
NEW met1 ( 203105 2991330 ) ( 203225 * )
NEW met1 ( 203165 2991865 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[11] ( sky130_fd_sc_hd__buf_8_179 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 222305 2990825 ) ( * 3054710 )
NEW met1 ( 222185 2990685 ) ( 222305 * )
NEW met1 ( 222245 2990595 ) via_260_260_vh ( * 2990535 )
( 222650 * )
NEW met2 ( 206425 2990535 ) ( 222045 * )
NEW met1 ( 206165 2991050 ) ( 206285 * )
NEW met1 ( 206165 2989980 ) ( 206285 * )
NEW met1 ( 206225 2990515 ) via_260_1090_vh
NEW met1 ( 206220 2990515 ) mcon_170_1090
NEW met1 ( 222185 2990505 ) ( 222305 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[16] ( sky130_fd_sc_hd__buf_8_55 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 655825 225450 ) ( 659530 * )
NEW met1 ( 659530 225310 ) ( 760350 * ) ( * 225370 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv ( * 225460 ) ( 760410 * )
NEW met2 ( 760290 225600 ) ( * 232275 )
NEW met2 ( 760290 225280 ) ( 760410 * )
NEW met2 ( 760290 216430 ) ( * 225140 )
NEW met1 ( 760240 216350 ) ( 760360 * )
NEW met1 ( 760240 215520 ) ( 760360 * )
NEW met1 ( 760300 215935 ) via_260_850_vh
NEW met1 ( 760305 215935 ) mcon_170_850 ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_55/A ( sky130_fd_sc_hd__buf_8_55 A )
( sky130_fd_sc_hd__buf_8_117 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 764485 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 764010 216030 ) ( 764960 * )
NEW met2 ( 764505 216170 ) ( * 225160 )
NEW met2 ( 764505 225300 ) ( 764625 * )
NEW met2 ( 764565 225390 ) via_260_260_hv
NEW met2 ( 764505 225480 ) ( 764625 * )
NEW met2 ( 764505 225620 ) ( * 232275 )
NEW met1 ( 764765 225450 ) ( 2237350 * ) ( * 225510 )
via_260_260_hv ( * 225600 ) ( 2237410 * )
NEW met2 ( 2237290 225740 ) ( * 232415 )
NEW met2 ( 2237290 225420 ) ( 2237410 * )
NEW met2 ( 2237290 216430 ) ( * 225280 )
NEW met1 ( 2237240 216350 ) ( 2237360 * )
NEW met1 ( 2237240 215520 ) ( 2237360 * )
NEW met1 ( 2237300 215935 ) via_260_850_vh
NEW met1 ( 2237305 215935 ) mcon_170_850
NEW met2 ( 764010 215850 ) ( 764960 * )
NEW li1 ( 764025 215965 ) ( 764945 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_77/X ( sky130_fd_sc_hd__buf_8_77 X )
( sky130_fd_sc_hd__buf_8_137 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 694525 215935 ) mcon_170_850
NEW met1 ( 694460 216350 ) ( 694580 * )
NEW met2 ( 694510 216430 ) ( * 234380 )
NEW met2 ( 694510 234520 ) ( 694630 * )
NEW met2 ( 694570 234610 ) via_260_260_hv
NEW met2 ( 694510 234700 ) ( 694630 * )
NEW met2 ( 694510 234840 ) ( * 234800 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 222305 234550 ) ( 694370 * )
NEW met1 ( 222305 234690 ) ( * 1697625 )
NEW met1 ( 222305 1697765 ) ( 222425 * )
NEW met1 ( 222365 1697855 ) via_260_260_vh
NEW met1 ( 222305 1697945 ) ( 222425 * )
NEW met2 ( 222565 1697795 ) ( 223670 * )
NEW met2 ( 203475 1697795 ) ( 222165 * )
NEW met1 ( 203215 1698515 ) ( 203335 * )
NEW met1 ( 203215 1697445 ) ( 203335 * )
NEW met1 ( 203275 1697980 ) via_260_1090_vh
NEW met1 ( 203270 1697980 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 694460 215520 ) ( 694580 * )
NEW met1 ( 694520 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_94/X ( sky130_fd_sc_hd__buf_8_94 X )
( sky130_fd_sc_hd__buf_8_77 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2171525 215935 ) mcon_170_850
NEW met1 ( 2171460 216350 ) ( 2171580 * )
NEW met2 ( 2171510 216430 ) ( * 234520 )
NEW met2 ( 2171510 234660 ) ( 2171630 * )
NEW met2 ( 2171570 234750 ) via_260_260_hv
NEW met2 ( 2171510 234840 ) ( 2171630 * )
NEW met2 ( 2171510 234980 ) ( * 234920 )
NEW met1 ( 781445 234690 ) ( 2171370 * )
NEW met1 ( 781445 233150 ) ( * 234550 )
NEW met1 ( 703185 233010 ) ( 781445 * )
NEW met1 ( 703185 233150 ) ( * 234550 )
NEW met1 ( 698985 234690 ) ( 703185 * )
NEW met1 ( 698785 234630 ) via_260_260_hv ( * 234720 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 698845 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 698725 234860 ) ( * 234835 )
NEW met2 ( 698725 234540 ) ( 698845 * )
NEW met2 ( 698725 216170 ) ( * 234400 )
NEW met2 ( 698230 216030 ) ( 699180 * )
NEW met2 ( 698705 215940 ) via_1090_260_hv
NEW li1 ( 698245 215965 ) ( 699165 * )
NEW li1 ( 698705 215935 ) mcon_1090_170
NEW met2 ( 698230 215850 ) ( 699180 * )
NEW met1 ( 2171460 215520 ) ( 2171580 * )
NEW met1 ( 2171520 215935 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[14] ( sky130_fd_sc_hd__buf_8_88 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3355870 228490 ) ( * 1118630 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2515450 228350 ) ( 3355870 * )
NEW met1 ( 2515450 222490 ) ( * 228210 )
NEW met1 ( 2437970 222350 ) ( 2515450 * )
NEW met1 ( 2437970 222490 ) ( * 237210 )
NEW met1 ( 2158045 237350 ) ( 2437970 * )
NEW met1 ( 2157845 237290 ) via_260_260_hv ( * 237380 )
( 2157905 * )
NEW met2 ( 2157785 237520 ) ( * 237505 )
NEW met2 ( 2157785 237200 ) ( 2157905 * )
NEW met2 ( 2157785 216170 ) ( * 237060 )
NEW met2 ( 2157290 216030 ) ( 2158240 * )
NEW met2 ( 2157765 215940 ) via_1090_260_hv
NEW li1 ( 2157305 215965 ) ( 2158225 * )
NEW li1 ( 2157765 215935 ) mcon_1090_170
NEW met2 ( 2157290 215850 ) ( 2158240 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[9] ( sky130_fd_sc_hd__buf_8_99 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3361470 224290 ) ( * 1128620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2521050 224150 ) ( 3361470 * )
NEW met1 ( 2521050 219690 ) ( * 224010 )
NEW met1 ( 2432370 219550 ) ( 2521050 * )
NEW met1 ( 2432370 219690 ) ( * 233010 )
NEW met1 ( 2187945 233150 ) ( 2432370 * )
NEW met1 ( 2187745 233090 ) via_260_260_hv ( * 233180 )
( 2187805 * )
NEW met2 ( 2187685 233320 ) ( * 233295 )
NEW met2 ( 2187685 233000 ) ( 2187805 * )
NEW met2 ( 2187685 216170 ) ( * 232860 )
NEW met2 ( 2187190 216030 ) ( 2188140 * )
NEW met2 ( 2187665 215940 ) via_1090_260_hv
NEW li1 ( 2187205 215965 ) ( 2188125 * )
NEW li1 ( 2187665 215935 ) mcon_1090_170
NEW met2 ( 2187190 215850 ) ( 2188140 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[8] ( sky130_fd_sc_hd__buf_8_101 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3363150 1128340 ) ( * 1131610 )
NEW met1 ( 3362870 1128200 ) ( 3363150 * )
NEW met1 ( 3362870 223170 ) ( * 1128060 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2522450 223030 ) ( 3362870 * )
NEW met1 ( 2522450 218850 ) ( * 222890 )
NEW met1 ( 2430970 218710 ) ( 2522450 * )
NEW met1 ( 2430970 218850 ) ( * 231890 )
NEW met1 ( 2198935 232030 ) ( 2430970 * )
NEW met1 ( 2198735 231970 ) via_260_260_hv ( * 232060 )
( 2198795 * )
NEW met2 ( 2198675 232200 ) ( * 232415 )
NEW met2 ( 2198675 231880 ) ( 2198795 * )
NEW met2 ( 2198675 213370 ) ( * 231740 )
NEW met1 ( 2198610 213290 ) ( 2198730 * )
NEW met1 ( 2198610 212460 ) ( 2198730 * )
NEW met1 ( 2198670 212875 ) via_260_850_vh
NEW met1 ( 2198675 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[19] ( sky130_fd_sc_hd__buf_8_123 A )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3373510 1149050 ) ( * 1152380 )
NEW met1 ( 3373510 1148910 ) ( 3373790 * )
NEW met1 ( 3373790 214210 ) ( * 1148770 )
NEW met1 ( 2534490 214070 ) ( 3373790 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2534490 212970 ) ( * 213930 )
NEW met1 ( 2418930 212830 ) ( 2534490 * )
NEW met1 ( 2418930 212970 ) ( * 222930 )
NEW met1 ( 2259705 223070 ) ( 2418930 * )
NEW met1 ( 2259505 223010 ) via_260_260_hv ( * 223100 )
( 2259565 * )
NEW met2 ( 2259445 223240 ) ( * 232415 )
NEW met2 ( 2259445 222920 ) ( 2259565 * )
NEW met2 ( 2259445 216170 ) ( * 222780 )
NEW met2 ( 2258950 216030 ) ( 2259900 * )
NEW met2 ( 2259425 215940 ) via_1090_260_hv
NEW li1 ( 2258965 215965 ) ( 2259885 * )
NEW li1 ( 2259425 215935 ) mcon_1090_170
NEW met2 ( 2258950 215850 ) ( 2259900 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_177/X ( sky130_fd_sc_hd__buf_8_177 X )
( sky130_fd_sc_hd__buf_8_134 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 206220 2992315 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 2992400 ) ( 206575 * )
NEW met2 ( 206715 2992300 ) ( 220905 * )
NEW met1 ( 221045 2992450 ) ( 221165 * )
NEW met1 ( 221105 2992360 ) via_260_260_vh
NEW met1 ( 221045 2992270 ) ( 221165 * )
NEW met1 ( 221045 1708900 ) ( * 2992130 )
NEW met1 ( 220925 1708760 ) ( 221045 * )
NEW met1 ( 220985 1708670 ) via_260_260_vh ( * 1708610 )
( 223670 * )
NEW met2 ( 206535 1708610 ) ( 220785 * )
NEW met1 ( 206275 1709125 ) ( 206395 * )
NEW met1 ( 206275 1708055 ) ( 206395 * )
NEW met1 ( 206335 1708590 ) via_260_1090_vh
NEW met1 ( 206330 1708590 ) mcon_170_1090
NEW met1 ( 220925 1708580 ) ( 221045 * )
NEW met2 ( 221305 2992300 ) ( 221605 * )
NEW met2 ( 205865 2992220 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[11] ( sky130_fd_sc_hd__buf_8_178 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 222865 3051180 ) ( * 3053710 )
NEW met1 ( 222585 3051040 ) ( 222865 * )
NEW met1 ( 222585 2989855 ) ( * 3050900 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 222465 2989715 ) ( 222585 * )
NEW met1 ( 222525 2989625 ) via_260_260_vh ( * 2989565 )
( 222650 * )
NEW met2 ( 203655 2989565 ) ( 222325 * )
NEW met2 ( 203160 2989560 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 2989650 ) ( 203515 * )
NEW met2 ( 202805 2989470 ) ( 203515 * )
NEW met1 ( 222465 2989535 ) ( 222585 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_95/A ( sky130_fd_sc_hd__buf_8_95 A )
( sky130_fd_sc_hd__buf_8_76 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2171075 212875 ) mcon_1090_170
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2170600 212970 ) ( 2171550 * )
NEW met2 ( 2170890 213110 ) ( * 235080 )
NEW met2 ( 2170890 235220 ) ( 2171010 * )
NEW met2 ( 2170950 235310 ) via_260_260_hv
NEW met2 ( 2170890 235400 ) ( 2171010 * )
NEW met2 ( 2170890 235540 ) ( * 235470 )
NEW met1 ( 780885 235250 ) ( 2170750 * )
NEW met1 ( 780885 233430 ) ( * 235110 )
NEW met1 ( 703475 233290 ) ( 780885 * )
NEW met1 ( 703475 233430 ) ( * 235110 )
NEW met1 ( 698015 235250 ) ( 703475 * )
NEW met1 ( 697815 235190 ) via_260_260_hv ( * 235280 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 697875 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 697755 235420 ) ( * 235400 )
NEW met2 ( 697755 235100 ) ( 697875 * )
NEW met2 ( 697755 213370 ) ( * 234960 )
NEW met1 ( 697690 213290 ) ( 697810 * )
NEW met1 ( 697690 212460 ) ( 697810 * )
NEW met1 ( 697750 212875 ) via_260_850_vh
NEW met1 ( 697755 212875 ) mcon_170_850
NEW met2 ( 2170600 212790 ) ( 2171550 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_76/A ( sky130_fd_sc_hd__buf_8_76 A )
( sky130_fd_sc_hd__buf_8_139 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 694075 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 693600 212970 ) ( 694550 * )
NEW met2 ( 693890 213110 ) ( * 234940 )
NEW met2 ( 693890 235080 ) ( 694010 * )
NEW met2 ( 693950 235170 ) via_260_260_hv
NEW met2 ( 693890 235260 ) ( 694010 * )
NEW met2 ( 693890 235400 ) ( * 235380 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 223145 235110 ) ( 693750 * )
NEW met1 ( 223145 235250 ) ( * 1692265 )
NEW met1 ( 223145 1692405 ) ( 223265 * )
NEW met1 ( 223205 1692495 ) via_260_260_vh
NEW met1 ( 223145 1692585 ) ( 223265 * )
NEW met2 ( 223405 1692435 ) ( 223675 * )
NEW met2 ( 206825 1692435 ) ( 223005 * )
NEW met2 ( 206330 1692445 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1692535 ) ( 206685 * )
NEW met2 ( 205975 1692355 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 693600 212790 ) ( 694550 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[10] ( sky130_fd_sc_hd__buf_8_98 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3360350 225130 ) ( * 1126630 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2519930 224990 ) ( 3360350 * )
NEW met1 ( 2519930 220250 ) ( * 224850 )
NEW met1 ( 2433490 220110 ) ( 2519930 * )
NEW met1 ( 2433490 220250 ) ( * 233850 )
NEW met1 ( 2181845 233990 ) ( 2433490 * )
NEW met1 ( 2181645 233930 ) via_260_260_hv ( * 234020 )
( 2181705 * )
NEW met2 ( 2181705 234160 ) ( * 234130 )
NEW met2 ( 2181585 233840 ) ( 2181705 * )
NEW met2 ( 2181705 216170 ) ( * 233700 )
NEW met2 ( 2181210 216030 ) ( 2182160 * )
NEW met2 ( 2181685 215940 ) via_1090_260_hv
NEW li1 ( 2181225 215965 ) ( 2182145 * )
NEW li1 ( 2181685 215935 ) mcon_1090_170
NEW met2 ( 2181210 215850 ) ( 2182160 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[9] ( sky130_fd_sc_hd__buf_8_100 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3362030 1126345 ) ( * 1129640 )
NEW met1 ( 3361750 1126205 ) ( 3362030 * )
NEW met1 ( 3361750 224010 ) ( * 1126065 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2521330 223870 ) ( 3361750 * )
NEW met1 ( 2521330 219410 ) ( * 223730 )
NEW met1 ( 2432090 219270 ) ( 2521330 * )
NEW met1 ( 2432090 219410 ) ( * 232730 )
NEW met1 ( 2192955 232870 ) ( 2432090 * )
NEW met1 ( 2192755 232810 ) via_260_260_hv ( * 232900 )
( 2192815 * )
NEW met2 ( 2192695 233040 ) ( * 232940 )
NEW met2 ( 2192695 232720 ) ( 2192815 * )
NEW met2 ( 2192695 213370 ) ( * 232580 )
NEW met1 ( 2192630 213290 ) ( 2192750 * )
NEW met1 ( 2192630 212460 ) ( 2192750 * )
NEW met1 ( 2192690 212875 ) via_260_850_vh
NEW met1 ( 2192695 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[18] ( sky130_fd_sc_hd__buf_8_122 X )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3372950 214770 ) ( * 1151380 )
NEW met1 ( 2533650 214630 ) ( 3372950 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2533650 213250 ) ( * 214490 )
NEW met1 ( 2419765 213110 ) ( 2533650 * )
NEW met1 ( 2419765 213250 ) ( * 223490 )
NEW met1 ( 2258735 223630 ) ( 2419770 * )
NEW met1 ( 2258535 223570 ) via_260_260_hv ( * 223660 )
( 2258595 * )
NEW met2 ( 2258475 223800 ) ( * 232415 )
NEW met2 ( 2258475 223480 ) ( 2258595 * )
NEW met2 ( 2258475 213370 ) ( * 223340 )
NEW met1 ( 2258410 213290 ) ( 2258530 * )
NEW met1 ( 2258410 212460 ) ( 2258530 * )
NEW met1 ( 2258470 212875 ) via_260_850_vh
NEW met1 ( 2258475 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[13] ( sky130_fd_sc_hd__buf_8_133 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 224965 1767600 ) ( * 1770580 )
NEW met1 ( 224685 1767460 ) ( 224965 * )
NEW met1 ( 224685 1689990 ) ( * 1767320 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 224565 1689850 ) ( 224685 * )
NEW met1 ( 224625 1689760 ) via_260_260_vh ( * 1689700 )
( 224840 * )
NEW met2 ( 203765 1689700 ) ( 224425 * )
NEW met2 ( 203270 1689695 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1689785 ) ( 203625 * )
NEW met2 ( 202915 1689605 ) ( 203625 * )
NEW met1 ( 224565 1689670 ) ( 224685 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[10] ( sky130_fd_sc_hd__buf_8_177 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 221185 2996805 ) ( * 3056710 )
NEW met1 ( 221065 2996665 ) ( 221185 * )
NEW met1 ( 221125 2996575 ) via_260_260_vh ( * 2996515 )
( 221535 * )
NEW met2 ( 206425 2996515 ) ( 220925 * )
NEW met1 ( 206165 2997030 ) ( 206285 * )
NEW met1 ( 206165 2995960 ) ( 206285 * )
NEW met1 ( 206225 2996495 ) via_260_1090_vh
NEW met1 ( 206220 2996495 ) mcon_170_1090
NEW met1 ( 221065 2996485 ) ( 221185 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_75/X ( sky130_fd_sc_hd__buf_8_75 X )
( sky130_fd_sc_hd__buf_8_135 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 700505 215935 ) mcon_170_850
NEW met1 ( 700440 216350 ) ( 700560 * )
NEW met2 ( 700490 216430 ) ( * 233540 )
NEW met2 ( 700490 233680 ) ( 700610 * )
NEW met2 ( 700550 233770 ) via_260_260_hv
NEW met2 ( 700490 233860 ) ( 700610 * )
NEW met2 ( 700490 234000 ) ( * 233990 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 221185 233710 ) ( 700350 * )
NEW met1 ( 221185 233850 ) ( * 1703605 )
NEW met1 ( 221185 1703745 ) ( 221305 * )
NEW met1 ( 221245 1703835 ) via_260_260_vh
NEW met1 ( 221185 1703925 ) ( 221305 * )
NEW met2 ( 221445 1703775 ) ( 223670 * )
NEW met2 ( 203475 1703775 ) ( 221045 * )
NEW met1 ( 203215 1704495 ) ( 203335 * )
NEW met1 ( 203215 1703425 ) ( 203335 * )
NEW met1 ( 203275 1703960 ) via_260_1090_vh
NEW met1 ( 203270 1703960 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 700440 215520 ) ( 700560 * )
NEW met1 ( 700500 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_98/X ( sky130_fd_sc_hd__buf_8_98 X )
( sky130_fd_sc_hd__buf_8_75 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2177505 215935 ) mcon_170_850
NEW met1 ( 2177440 216350 ) ( 2177560 * )
NEW met2 ( 2177490 216430 ) ( * 233680 )
NEW met2 ( 2177490 233820 ) ( 2177610 * )
NEW met2 ( 2177550 233910 ) via_260_260_hv
NEW met2 ( 2177490 234000 ) ( 2177610 * )
NEW met2 ( 2177490 234140 ) ( * 234110 )
NEW met1 ( 782285 233850 ) ( 2177350 * )
NEW met1 ( 782285 232590 ) ( * 233710 )
NEW met1 ( 704845 232450 ) ( 782285 * )
NEW met1 ( 704645 232390 ) via_260_260_hv ( * 232480 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 704705 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 704705 232620 ) ( * 232610 )
NEW met2 ( 704585 232300 ) ( 704705 * )
NEW met2 ( 704705 216170 ) ( * 232160 )
NEW met2 ( 704210 216030 ) ( 705160 * )
NEW met2 ( 704685 215940 ) via_1090_260_hv
NEW li1 ( 704225 215965 ) ( 705145 * )
NEW li1 ( 704685 215935 ) mcon_1090_170
NEW met2 ( 704210 215850 ) ( 705160 * )
NEW met1 ( 2177440 215520 ) ( 2177560 * )
NEW met1 ( 2177500 215935 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[15] ( sky130_fd_sc_hd__buf_8_86 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3354750 229330 ) ( * 1116680 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2514330 229190 ) ( 3354750 * )
NEW met1 ( 2514330 223050 ) ( * 229050 )
NEW met1 ( 2439090 222910 ) ( 2514330 * )
NEW met1 ( 2439090 223050 ) ( * 238050 )
NEW met1 ( 2152065 238190 ) ( 2439090 * )
NEW met1 ( 2151865 238130 ) via_260_260_hv ( * 238220 )
( 2151925 * )
NEW met2 ( 2151805 238360 ) ( * 238295 )
NEW met2 ( 2151805 238040 ) ( 2151925 * )
NEW met2 ( 2151805 216170 ) ( * 237900 )
NEW met2 ( 2151310 216030 ) ( 2152260 * )
NEW met2 ( 2151785 215940 ) via_1090_260_hv
NEW li1 ( 2151325 215965 ) ( 2152245 * )
NEW li1 ( 2151785 215935 ) mcon_1090_170
NEW met2 ( 2151310 215850 ) ( 2152260 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[10] ( sky130_fd_sc_hd__buf_8_97 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3360910 1124235 ) ( * 1127610 )
NEW met1 ( 3360630 1124095 ) ( 3360910 * )
NEW met1 ( 3360630 224850 ) ( * 1123955 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2520210 224710 ) ( 3360630 * )
NEW met1 ( 2520210 219970 ) ( * 224570 )
NEW met1 ( 2433210 219830 ) ( 2520210 * )
NEW met1 ( 2433210 219970 ) ( * 233570 )
NEW met1 ( 2186975 233710 ) ( 2433210 * )
NEW met1 ( 2186775 233650 ) via_260_260_hv ( * 233740 )
( 2186835 * )
NEW met2 ( 2186715 233880 ) ( * 233800 )
NEW met2 ( 2186715 233560 ) ( 2186835 * )
NEW met2 ( 2186715 213370 ) ( * 233420 )
NEW met1 ( 2186650 213290 ) ( 2186770 * )
NEW met1 ( 2186650 212460 ) ( 2186770 * )
NEW met1 ( 2186710 212875 ) via_260_850_vh
NEW met1 ( 2186715 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[17] ( sky130_fd_sc_hd__buf_8_121 X )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3371830 215610 ) ( * 1149370 )
NEW met1 ( 2532530 215470 ) ( 3371830 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2532530 213810 ) ( * 215330 )
NEW met1 ( 2420890 213670 ) ( 2532530 * )
NEW met1 ( 2420890 213810 ) ( * 224330 )
NEW met1 ( 2252755 224470 ) ( 2420890 * )
NEW met1 ( 2252555 224410 ) via_260_260_hv ( * 224500 )
( 2252615 * )
NEW met2 ( 2252495 224640 ) ( * 232415 )
NEW met2 ( 2252495 224320 ) ( 2252615 * )
NEW met2 ( 2252495 213370 ) ( * 224180 )
NEW met1 ( 2252430 213290 ) ( 2252550 * )
NEW met1 ( 2252430 212460 ) ( 2252550 * )
NEW met1 ( 2252490 212875 ) via_260_850_vh
NEW met1 ( 2252495 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[13] ( sky130_fd_sc_hd__buf_8_132 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 224405 1690960 ) ( * 1771580 )
NEW met1 ( 224285 1690820 ) ( 224405 * )
NEW met1 ( 224345 1690730 ) via_260_260_vh ( * 1690670 )
( 224840 * )
NEW met2 ( 206535 1690670 ) ( 224145 * )
NEW met1 ( 206275 1691185 ) ( 206395 * )
NEW met1 ( 206275 1690115 ) ( 206395 * )
NEW met1 ( 206335 1690650 ) via_260_1090_vh
NEW met1 ( 206330 1690650 ) mcon_170_1090
NEW met1 ( 224285 1690640 ) ( 224405 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_175/X ( sky130_fd_sc_hd__buf_8_175 X )
( sky130_fd_sc_hd__buf_8_143 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 206220 2998295 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 2998380 ) ( 206575 * )
NEW met2 ( 206715 2998280 ) ( 219785 * )
NEW met1 ( 219925 2998430 ) ( 220045 * )
NEW met1 ( 219985 2998340 ) via_260_260_vh
NEW met1 ( 219925 2998250 ) ( 220045 * )
NEW met1 ( 219925 1714880 ) ( * 2998110 )
NEW met1 ( 219805 1714740 ) ( 219925 * )
NEW met1 ( 219865 1714650 ) via_260_260_vh ( * 1714590 )
( 223670 * )
NEW met2 ( 206535 1714590 ) ( 219665 * )
NEW met1 ( 206275 1715105 ) ( 206395 * )
NEW met1 ( 206275 1714035 ) ( 206395 * )
NEW met1 ( 206335 1714570 ) via_260_1090_vh
NEW met1 ( 206330 1714570 ) mcon_170_1090
NEW met1 ( 219805 1714560 ) ( 219925 * )
NEW met2 ( 220185 2998280 ) ( 221530 * )
NEW met2 ( 205865 2998200 ) ( 206575 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[4] ( sky130_fd_sc_hd__buf_8_53 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3368890 1176320 ) ( * 2221400 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3368770 2221540 ) ( 3368890 * )
NEW met1 ( 3368830 2221630 ) via_260_260_vh
NEW met1 ( 3368770 2221720 ) ( 3368890 * )
NEW met2 ( 3369030 2221570 ) ( 3381775 * ) ( * 2221580 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2221670 ) ( 3382130 * )
NEW met2 ( 3381420 2221490 ) ( 3382130 * )
NEW met2 ( 3366060 2221570 ) ( 3368630 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[4] ( sky130_fd_sc_hd__buf_8_53 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3368750 2226075 ) ( * 2279205 )
NEW met1 ( 3368750 2225935 ) ( 3368870 * )
NEW met1 ( 3368810 2225845 ) via_260_260_vh ( * 2225785 )
( 3381570 * )
NEW met1 ( 3381710 2226300 ) ( 3381830 * )
NEW met1 ( 3381710 2225230 ) ( 3381830 * )
NEW met1 ( 3381770 2225765 ) via_260_1090_vh
NEW met1 ( 3381775 2225765 ) mcon_170_1090
NEW met2 ( 3366060 2225785 ) ( 3368610 * )
NEW met1 ( 3368750 2225755 ) ( 3368870 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[10] ( sky130_fd_sc_hd__buf_8_176 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 221745 3053245 ) ( * 3055710 )
NEW met1 ( 221465 3053105 ) ( 221745 * )
NEW met1 ( 221465 2995835 ) ( * 3052965 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 221345 2995695 ) ( 221465 * )
NEW met1 ( 221405 2995605 ) via_260_260_vh ( * 2995545 )
( 221535 * )
NEW met2 ( 203655 2995545 ) ( 221205 * )
NEW met2 ( 203160 2995540 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 2995630 ) ( 203515 * )
NEW met2 ( 202805 2995450 ) ( 203515 * )
NEW met1 ( 221345 2995515 ) ( 221465 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_85/X ( sky130_fd_sc_hd__buf_8_85 X )
( sky130_fd_sc_hd__buf_8_121 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 775495 212875 ) mcon_170_850
NEW met1 ( 775430 213290 ) ( 775550 * )
NEW met2 ( 775495 213370 ) ( * 224040 )
NEW met2 ( 775495 224180 ) ( 775615 * )
NEW met2 ( 775555 224270 ) via_260_260_hv
NEW met2 ( 775495 224360 ) ( 775615 * )
NEW met2 ( 775495 224500 ) ( * 232275 )
NEW met1 ( 775755 224330 ) ( 2248690 * ) ( * 224390 )
via_260_260_hv ( * 224480 ) ( 2248750 * )
NEW met2 ( 2248630 224620 ) ( * 232415 )
NEW met2 ( 2248630 224300 ) ( 2248750 * )
NEW met2 ( 2248630 213110 ) ( * 224160 )
NEW met2 ( 2248340 212970 ) ( 2249290 * )
NEW met2 ( 2248815 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2248340 212790 ) ( 2249290 * )
NEW met1 ( 775430 212460 ) ( 775550 * )
NEW met1 ( 775490 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[17] ( sky130_fd_sc_hd__buf_8_85 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 658685 224190 ) ( 771690 * ) ( * 224250 )
via_260_260_hv ( * 224340 ) ( 771750 * )
NEW met2 ( 771630 224480 ) ( * 232275 )
NEW met2 ( 771630 224160 ) ( 771750 * )
NEW met2 ( 771630 213110 ) ( * 224020 )
NEW met2 ( 771340 212970 ) ( 772290 * )
NEW met2 ( 771815 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 771340 212790 ) ( 772290 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_96/A ( sky130_fd_sc_hd__buf_8_96 A )
( sky130_fd_sc_hd__buf_8_74 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2177055 212875 ) mcon_1090_170
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2176580 212970 ) ( 2177530 * )
NEW met2 ( 2176870 213110 ) ( * 234240 )
NEW met2 ( 2176870 234380 ) ( 2176990 * )
NEW met2 ( 2176930 234470 ) via_260_260_hv
NEW met2 ( 2176870 234560 ) ( 2176990 * )
NEW met2 ( 2176870 234700 ) ( * 234605 )
NEW met1 ( 781725 234410 ) ( 2176730 * )
NEW met1 ( 781725 232870 ) ( * 234270 )
NEW met1 ( 703995 232730 ) ( 781725 * )
NEW met1 ( 703795 232670 ) via_260_260_hv ( * 232760 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 703855 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 703735 232900 ) ( * 232820 )
NEW met2 ( 703735 232580 ) ( 703855 * )
NEW met2 ( 703735 213370 ) ( * 232440 )
NEW met1 ( 703670 213290 ) ( 703790 * )
NEW met1 ( 703670 212460 ) ( 703790 * )
NEW met1 ( 703730 212875 ) via_260_850_vh
NEW met1 ( 703735 212875 ) mcon_170_850
NEW met2 ( 2176580 212790 ) ( 2177530 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_74/A ( sky130_fd_sc_hd__buf_8_74 A )
( sky130_fd_sc_hd__buf_8_136 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 700055 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 699580 212970 ) ( 700530 * )
NEW met2 ( 699870 213110 ) ( * 234100 )
NEW met2 ( 699870 234240 ) ( 699990 * )
NEW met2 ( 699930 234330 ) via_260_260_hv
NEW met2 ( 699870 234420 ) ( 699990 * )
NEW met2 ( 699870 234560 ) ( * 234445 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 222025 234270 ) ( 699730 * )
NEW met1 ( 222025 234410 ) ( * 1698245 )
NEW met1 ( 222025 1698385 ) ( 222145 * )
NEW met1 ( 222085 1698475 ) via_260_260_vh
NEW met1 ( 222025 1698565 ) ( 222145 * )
NEW met2 ( 222285 1698415 ) ( 223670 * )
NEW met2 ( 206825 1698415 ) ( 221885 * )
NEW met2 ( 206330 1698425 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1698515 ) ( 206685 * )
NEW met2 ( 205975 1698335 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 699580 212790 ) ( 700530 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[11] ( sky130_fd_sc_hd__buf_8_96 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3359790 1122285 ) ( * 1125630 )
NEW met1 ( 3359510 1122145 ) ( 3359790 * )
NEW met1 ( 3359510 225690 ) ( * 1122005 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2519090 225550 ) ( 3359510 * )
NEW met1 ( 2519090 220530 ) ( * 225410 )
NEW met1 ( 2434330 220390 ) ( 2519090 * )
NEW met1 ( 2434330 220530 ) ( * 234410 )
NEW met1 ( 2180995 234550 ) ( 2434330 * )
NEW met1 ( 2180795 234490 ) via_260_260_hv ( * 234580 )
( 2180855 * )
NEW met2 ( 2180735 234720 ) ( * 234635 )
NEW met2 ( 2180735 234400 ) ( 2180855 * )
NEW met2 ( 2180735 213370 ) ( * 234260 )
NEW met1 ( 2180670 213290 ) ( 2180790 * )
NEW met1 ( 2180670 212460 ) ( 2180790 * )
NEW met1 ( 2180730 212875 ) via_260_850_vh
NEW met1 ( 2180735 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[4] ( sky130_fd_sc_hd__buf_8_52 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3368190 2275725 ) ( * 2278205 )
NEW met1 ( 3368190 2275585 ) ( 3368470 * )
NEW met1 ( 3368470 2225105 ) ( * 2275445 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3368470 2224965 ) ( 3368590 * )
NEW met1 ( 3368530 2224875 ) via_260_260_vh ( * 2224815 )
( 3384835 * ) ( * 2224810 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2224900 ) ( 3385190 * )
NEW met2 ( 3384480 2224720 ) ( 3385190 * )
NEW met2 ( 3366060 2224815 ) ( 3368330 * )
NEW met1 ( 3368470 2224785 ) ( 3368590 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[4] ( sky130_fd_sc_hd__buf_8_52 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3368330 1177320 ) ( * 1180260 )
NEW met1 ( 3368330 1180400 ) ( 3368610 * )
NEW met1 ( 3368610 1180540 ) ( * 2220780 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3368490 2220920 ) ( 3368610 * )
NEW met1 ( 3368550 2221010 ) via_260_260_vh
NEW met1 ( 3368490 2221100 ) ( 3368610 * )
NEW met2 ( 3368750 2220950 ) ( 3384630 * )
NEW met1 ( 3384770 2221670 ) ( 3384890 * )
NEW met1 ( 3384770 2220600 ) ( 3384890 * )
NEW met1 ( 3384830 2221135 ) via_260_1090_vh
NEW met1 ( 3384835 2221135 ) mcon_170_1090
NEW met2 ( 3366060 2220950 ) ( 3368350 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[18] ( sky130_fd_sc_hd__buf_8_120 A )
One additional small change to the signal buffer layouts to avoid a collision with the lower three right-hand side I/O cells that was discovered by LVS.
2022-10-17 14:51:43 -05:00
+ ROUTED met1 ( 3372390 1147055 ) ( * 1150370 )
NEW met1 ( 3372390 1146915 ) ( 3372670 * )
NEW met1 ( 3372670 215050 ) ( * 1146775 )
NEW met1 ( 2533370 214910 ) ( 3372670 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2533370 213530 ) ( * 214770 )
NEW met1 ( 2420050 213390 ) ( 2533370 * )
NEW met1 ( 2420050 213530 ) ( * 223770 )
NEW met1 ( 2253605 223910 ) ( 2420050 * )
NEW met1 ( 2253405 223850 ) via_260_260_hv ( * 223940 )
( 2253465 * )
NEW met2 ( 2253465 224080 ) ( * 232415 )
NEW met2 ( 2253345 223760 ) ( 2253465 * )
NEW met2 ( 2253465 216170 ) ( * 223620 )
NEW met2 ( 2252970 216030 ) ( 2253920 * )
NEW met2 ( 2253445 215940 ) via_1090_260_hv
NEW li1 ( 2252985 215965 ) ( 2253905 * )
NEW li1 ( 2253445 215935 ) mcon_1090_170
NEW met2 ( 2252970 215850 ) ( 2253920 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[14] ( sky130_fd_sc_hd__buf_8_131 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 226085 1765670 ) ( * 1768580 )
NEW met1 ( 225805 1765530 ) ( 226085 * )
NEW met1 ( 225805 1684010 ) ( * 1765390 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 225685 1683870 ) ( 225805 * )
NEW met1 ( 225745 1683780 ) via_260_260_vh ( * 1683720 )
( 225905 * )
NEW met2 ( 203765 1683720 ) ( 225545 * )
NEW met2 ( 203270 1683715 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1683805 ) ( 203625 * )
NEW met2 ( 202915 1683625 ) ( 203625 * )
NEW met1 ( 225685 1683690 ) ( 225805 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_174/A ( sky130_fd_sc_hd__buf_8_174 A )
( sky130_fd_sc_hd__buf_8_142 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 203160 2997845 ) mcon_170_1090
NEW met1 ( 203105 2998380 ) ( 203225 * )
NEW met2 ( 203365 2997660 ) ( 220065 * )
NEW met1 ( 220205 2997810 ) ( 220325 * )
NEW met1 ( 220265 2997720 ) via_260_260_vh
NEW met1 ( 220205 2997630 ) ( 220325 * )
NEW met1 ( 220205 1713910 ) ( * 2997490 )
NEW met1 ( 220085 1713770 ) ( 220205 * )
NEW met1 ( 220145 1713680 ) via_260_260_vh ( * 1713620 )
( 223670 * )
NEW met2 ( 203765 1713620 ) ( 219945 * )
NEW met2 ( 203270 1713615 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1713705 ) ( 203625 * )
NEW met2 ( 202915 1713525 ) ( 203625 * )
NEW met1 ( 220085 1713590 ) ( 220205 * )
NEW met2 ( 220465 2997660 ) ( 221530 * )
NEW met1 ( 203105 2997310 ) ( 203225 * )
NEW met1 ( 203165 2997845 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[9] ( sky130_fd_sc_hd__buf_8_175 A )
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
+ ROUTED met1 ( 220065 3002785 ) ( * 3058905 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 219945 3002645 ) ( 220065 * )
NEW met1 ( 220005 3002555 ) via_260_260_vh ( * 3002495 )
( 221530 * )
NEW met2 ( 206425 3002495 ) ( 219805 * )
NEW met1 ( 206165 3003010 ) ( 206285 * )
NEW met1 ( 206165 3001940 ) ( 206285 * )
NEW met1 ( 206225 3002475 ) via_260_1090_vh
NEW met1 ( 206220 3002475 ) mcon_170_1090
NEW met1 ( 219945 3002465 ) ( 220065 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[18] ( sky130_fd_sc_hd__buf_8_84 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 659825 223770 ) ( 663565 * )
NEW met1 ( 663565 223630 ) ( 772310 * ) ( * 223690 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
via_260_260_hv ( * 223780 ) ( 772370 * )
NEW met2 ( 772250 223920 ) ( * 232275 )
NEW met2 ( 772250 223600 ) ( 772370 * )
NEW met2 ( 772250 216430 ) ( * 223460 )
NEW met1 ( 772200 216350 ) ( 772320 * )
NEW met1 ( 772200 215520 ) ( 772320 * )
NEW met1 ( 772260 215935 ) via_260_850_vh
NEW met1 ( 772265 215935 ) mcon_170_850 ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_84/A ( sky130_fd_sc_hd__buf_8_84 A )
( sky130_fd_sc_hd__buf_8_120 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 776445 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 775970 216030 ) ( 776920 * )
NEW met2 ( 776465 216170 ) ( * 223480 )
NEW met2 ( 776345 223620 ) ( 776465 * )
NEW met2 ( 776405 223710 ) via_260_260_hv
NEW met2 ( 776345 223800 ) ( 776465 * )
NEW met2 ( 776465 223940 ) ( * 232275 )
NEW met1 ( 776605 223770 ) ( 2249310 * ) ( * 223830 )
via_260_260_hv ( * 223920 ) ( 2249370 * )
NEW met2 ( 2249250 224060 ) ( * 232415 )
NEW met2 ( 2249250 223740 ) ( 2249370 * )
NEW met2 ( 2249250 216430 ) ( * 223600 )
NEW met1 ( 2249200 216350 ) ( 2249320 * )
NEW met1 ( 2249200 215520 ) ( 2249320 * )
NEW met1 ( 2249260 215935 ) via_260_850_vh
NEW met1 ( 2249265 215935 ) mcon_170_850
NEW met2 ( 775970 215850 ) ( 776920 * )
NEW li1 ( 775985 215965 ) ( 776905 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_73/X ( sky130_fd_sc_hd__buf_8_73 X )
( sky130_fd_sc_hd__buf_8_142 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 706485 215935 ) mcon_170_850
NEW met1 ( 706420 216350 ) ( 706540 * )
NEW met2 ( 706470 216430 ) ( * 231580 )
NEW met2 ( 706470 231720 ) ( 706590 * )
NEW met2 ( 706530 231810 ) via_260_260_hv
NEW met2 ( 706470 231900 ) ( 706590 * )
NEW met2 ( 706470 232040 ) ( * 232080 )
NEW met1 ( 702560 231750 ) ( 706330 * )
NEW met1 ( 702560 231890 ) ( * 232730 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 220065 232870 ) ( 702560 * )
NEW met1 ( 220065 233010 ) ( * 1709585 )
NEW met1 ( 220065 1709725 ) ( 220185 * )
NEW met1 ( 220125 1709815 ) via_260_260_vh
NEW met1 ( 220065 1709905 ) ( 220185 * )
NEW met2 ( 220325 1709755 ) ( 223670 * )
NEW met2 ( 203475 1709755 ) ( 219925 * )
NEW met1 ( 203215 1710475 ) ( 203335 * )
NEW met1 ( 203215 1709405 ) ( 203335 * )
NEW met1 ( 203275 1709940 ) via_260_1090_vh
NEW met1 ( 203270 1709940 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 706420 215520 ) ( 706540 * )
NEW met1 ( 706480 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_99/X ( sky130_fd_sc_hd__buf_8_99 X )
( sky130_fd_sc_hd__buf_8_73 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2183485 215935 ) mcon_170_850
NEW met1 ( 2183420 216350 ) ( 2183540 * )
NEW met2 ( 2183470 216430 ) ( * 232840 )
NEW met2 ( 2183470 232980 ) ( 2183590 * )
NEW met2 ( 2183530 233070 ) via_260_260_hv
NEW met2 ( 2183470 233160 ) ( 2183590 * )
NEW met2 ( 2183470 233300 ) ( * 233240 )
NEW met1 ( 783125 233010 ) ( 2183330 * )
NEW met1 ( 783125 232030 ) ( * 232870 )
NEW met1 ( 710945 231890 ) ( 783125 * )
NEW met1 ( 710745 231830 ) via_260_260_hv ( * 231920 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 710805 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 710685 232060 ) ( * 232120 )
NEW met2 ( 710685 231740 ) ( 710805 * )
NEW met2 ( 710685 216170 ) ( * 231600 )
NEW met2 ( 710190 216030 ) ( 711140 * )
NEW met2 ( 710665 215940 ) via_1090_260_hv
NEW li1 ( 710205 215965 ) ( 711125 * )
NEW li1 ( 710665 215935 ) mcon_1090_170
NEW met2 ( 710190 215850 ) ( 711140 * )
NEW met1 ( 2183420 215520 ) ( 2183540 * )
NEW met1 ( 2183480 215935 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[12] ( sky130_fd_sc_hd__buf_8_95 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3358670 1120400 ) ( * 1123650 )
NEW met1 ( 3358390 1120260 ) ( 3358670 * )
NEW met1 ( 3358390 226530 ) ( * 1120120 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2517970 226390 ) ( 3358390 * )
NEW met1 ( 2517970 221090 ) ( * 226250 )
NEW met1 ( 2435450 220950 ) ( 2517970 * )
NEW met1 ( 2435450 221090 ) ( * 235250 )
NEW met1 ( 2175015 235390 ) ( 2435450 * )
NEW met1 ( 2174815 235330 ) via_260_260_hv ( * 235420 )
( 2174875 * )
NEW met2 ( 2174755 235560 ) ( * 235460 )
NEW met2 ( 2174755 235240 ) ( 2174875 * )
NEW met2 ( 2174755 213370 ) ( * 235100 )
NEW met1 ( 2174690 213290 ) ( 2174810 * )
NEW met1 ( 2174690 212460 ) ( 2174810 * )
NEW met1 ( 2174750 212875 ) via_260_850_vh
NEW met1 ( 2174755 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[3] ( sky130_fd_sc_hd__buf_8_51 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3367770 1178320 ) ( * 2215420 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3367650 2215560 ) ( 3367770 * )
NEW met1 ( 3367710 2215650 ) via_260_260_vh
NEW met1 ( 3367650 2215740 ) ( 3367770 * )
NEW met2 ( 3367910 2215590 ) ( 3381775 * ) ( * 2215600 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_850_260_hv mcon_850_170
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 3381420 2215690 ) ( 3382130 * )
NEW met2 ( 3381420 2215510 ) ( 3382130 * )
NEW met2 ( 3366060 2215590 ) ( 3367510 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[3] ( sky130_fd_sc_hd__buf_8_51 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 3367630 2220095 ) ( * 2277205 )
NEW met1 ( 3367630 2219955 ) ( 3367750 * )
NEW met1 ( 3367690 2219865 ) via_260_260_vh ( * 2219805 )
( 3381570 * )
NEW met1 ( 3381710 2220320 ) ( 3381830 * )
NEW met1 ( 3381710 2219250 ) ( 3381830 * )
NEW met1 ( 3381770 2219785 ) via_260_1090_vh
NEW met1 ( 3381775 2219785 ) mcon_170_1090
NEW met2 ( 3366060 2219805 ) ( 3367490 * )
NEW met1 ( 3367630 2219775 ) ( 3367750 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[9] ( sky130_fd_sc_hd__buf_8_174 X )
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
+ ROUTED met1 ( 220625 3055225 ) ( * 3057905 )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
NEW met1 ( 220345 3055085 ) ( 220625 * )
NEW met1 ( 220345 3001815 ) ( * 3054945 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 220225 3001675 ) ( 220345 * )
NEW met1 ( 220285 3001585 ) via_260_260_vh ( * 3001525 )
( 221530 * )
NEW met2 ( 203655 3001525 ) ( 220085 * )
NEW met2 ( 203160 3001520 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3001610 ) ( 203515 * )
NEW met2 ( 202805 3001430 ) ( 203515 * )
NEW met1 ( 220225 3001495 ) ( 220345 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[14] ( sky130_fd_sc_hd__buf_8_130 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 225525 1684860 ) ( * 1769580 )
NEW met1 ( 225405 1684720 ) ( 225525 * )
NEW met1 ( 225465 1684630 ) via_260_260_vh
NEW met2 ( 206535 1684690 ) ( 225265 * )
NEW met1 ( 206275 1685205 ) ( 206395 * )
NEW met1 ( 206275 1684135 ) ( 206395 * )
NEW met1 ( 206335 1684670 ) via_260_1090_vh
NEW met1 ( 206330 1684670 ) mcon_170_1090
NEW met2 ( 225665 1684690 ) ( 225905 * )
NEW met1 ( 225405 1684540 ) ( 225525 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_172/X ( sky130_fd_sc_hd__buf_8_172 X )
( sky130_fd_sc_hd__buf_8_141 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 206220 3004275 ) mcon_850_170 via_850_260_hv
NEW met2 ( 205865 3004360 ) ( 206575 * )
NEW met2 ( 206715 3004260 ) ( 218665 * )
NEW met1 ( 218805 3004410 ) ( 218925 * )
NEW met1 ( 218865 3004320 ) via_260_260_vh
NEW met1 ( 218805 3004230 ) ( 218925 * )
NEW met1 ( 218805 1720860 ) ( * 3004090 )
NEW met1 ( 218685 1720720 ) ( 218805 * )
NEW met1 ( 218745 1720630 ) via_260_260_vh ( * 1720570 )
( 223670 * )
NEW met2 ( 206535 1720570 ) ( 218545 * )
NEW met1 ( 206275 1721085 ) ( 206395 * )
NEW met1 ( 206275 1720015 ) ( 206395 * )
NEW met1 ( 206335 1720550 ) via_260_1090_vh
NEW met1 ( 206330 1720550 ) mcon_170_1090
NEW met1 ( 218685 1720540 ) ( 218805 * )
NEW met2 ( 219065 3004260 ) ( 221530 * )
NEW met2 ( 205865 3004180 ) ( 206575 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_97/A ( sky130_fd_sc_hd__buf_8_97 A )
( sky130_fd_sc_hd__buf_8_72 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2183035 212875 ) mcon_1090_170
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2182560 212970 ) ( 2183510 * )
NEW met2 ( 2182850 213110 ) ( * 233400 )
NEW met2 ( 2182850 233540 ) ( 2182970 * )
NEW met2 ( 2182910 233630 ) via_260_260_hv
NEW met2 ( 2182850 233720 ) ( 2182970 * )
NEW met2 ( 2182850 233860 ) ( * 233775 )
NEW met1 ( 782565 233570 ) ( 2182710 * )
NEW met1 ( 782565 232310 ) ( * 233430 )
NEW met1 ( 709975 232170 ) ( 782565 * )
NEW met1 ( 709775 232110 ) via_260_260_hv ( * 232200 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 709835 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 709715 232340 ) ( * 232240 )
NEW met2 ( 709715 232020 ) ( 709835 * )
NEW met2 ( 709715 213370 ) ( * 231880 )
NEW met1 ( 709650 213290 ) ( 709770 * )
NEW met1 ( 709650 212460 ) ( 709770 * )
NEW met1 ( 709710 212875 ) via_260_850_vh
NEW met1 ( 709715 212875 ) mcon_170_850
NEW met2 ( 2182560 212790 ) ( 2183510 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_72/A ( sky130_fd_sc_hd__buf_8_72 A )
( sky130_fd_sc_hd__buf_8_134 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 706035 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 705560 212970 ) ( 706510 * )
NEW met2 ( 705850 213110 ) ( * 231860 )
NEW met2 ( 705850 232000 ) ( 705970 * )
NEW met2 ( 705910 232090 ) via_260_260_hv
NEW met2 ( 705850 232180 ) ( 705970 * )
NEW met2 ( 705850 232320 ) ( * 232245 )
NEW met1 ( 702855 232030 ) ( 705710 * )
NEW met1 ( 702855 232170 ) ( * 233290 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 220905 233430 ) ( 702855 * )
NEW met1 ( 220905 233570 ) ( * 1704225 )
NEW met1 ( 220905 1704365 ) ( 221025 * )
NEW met1 ( 220965 1704455 ) via_260_260_vh
NEW met1 ( 220905 1704545 ) ( 221025 * )
NEW met2 ( 221165 1704395 ) ( 223670 * )
NEW met2 ( 206825 1704395 ) ( 220765 * )
NEW met2 ( 206330 1704405 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1704495 ) ( 206685 * )
NEW met2 ( 205975 1704315 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 705560 212790 ) ( 706510 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_83/X ( sky130_fd_sc_hd__buf_8_83 X )
( sky130_fd_sc_hd__buf_8_131 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 676585 215935 ) mcon_170_850
NEW met1 ( 676520 216350 ) ( 676640 * )
NEW met2 ( 676570 216430 ) ( * 236900 )
NEW met2 ( 676570 237040 ) ( 676690 * )
NEW met2 ( 676630 237130 ) via_260_260_hv
NEW met2 ( 676570 237220 ) ( 676690 * )
NEW met2 ( 676570 237360 ) ( * 237330 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 225665 237070 ) ( 676430 * )
NEW met1 ( 225665 237210 ) ( * 1679685 )
NEW met1 ( 225665 1679825 ) ( 225785 * )
NEW met1 ( 225725 1679915 ) via_260_260_vh
NEW met1 ( 225665 1680005 ) ( 225785 * )
NEW met2 ( 225925 1679855 ) ( 225960 * )
NEW met2 ( 203475 1679855 ) ( 225525 * )
NEW met1 ( 203215 1680575 ) ( 203335 * )
NEW met1 ( 203215 1679505 ) ( 203335 * )
NEW met1 ( 203275 1680040 ) via_260_1090_vh
NEW met1 ( 203270 1680040 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 676520 215520 ) ( 676640 * )
NEW met1 ( 676580 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_88/X ( sky130_fd_sc_hd__buf_8_88 X )
( sky130_fd_sc_hd__buf_8_83 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2153585 215935 ) mcon_170_850
NEW met1 ( 2153520 216350 ) ( 2153640 * )
NEW met2 ( 2153570 216430 ) ( * 237040 )
NEW met2 ( 2153570 237180 ) ( 2153690 * )
NEW met2 ( 2153630 237270 ) via_260_260_hv
NEW met2 ( 2153570 237360 ) ( 2153690 * )
NEW met2 ( 2153570 237500 ) ( * 237455 )
NEW met1 ( 778925 237210 ) ( 2153430 * )
NEW met1 ( 778925 234830 ) ( * 237070 )
NEW met1 ( 705435 234690 ) ( 778925 * )
NEW met1 ( 705435 234830 ) ( * 237070 )
NEW met1 ( 681045 237210 ) ( 705435 * )
NEW met1 ( 680845 237150 ) via_260_260_hv ( * 237240 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 680905 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 680785 237380 ) ( * 237330 )
NEW met2 ( 680785 237060 ) ( 680905 * )
NEW met2 ( 680785 216170 ) ( * 236920 )
NEW met2 ( 680290 216030 ) ( 681240 * )
NEW met2 ( 680765 215940 ) via_1090_260_hv
NEW li1 ( 680305 215965 ) ( 681225 * )
NEW li1 ( 680765 215935 ) mcon_1090_170
NEW met2 ( 680290 215850 ) ( 681240 * )
NEW met1 ( 2153520 215520 ) ( 2153640 * )
NEW met1 ( 2153580 215935 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[11] ( sky130_fd_sc_hd__buf_8_94 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3359230 225970 ) ( * 1124610 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2518810 225830 ) ( 3359230 * )
NEW met1 ( 2518810 220810 ) ( * 225690 )
NEW met1 ( 2434610 220670 ) ( 2518810 * )
NEW met1 ( 2434610 220810 ) ( * 234690 )
NEW met1 ( 2175985 234830 ) ( 2434610 * )
NEW met1 ( 2175785 234770 ) via_260_260_hv ( * 234860 )
( 2175845 * )
NEW met2 ( 2175725 235000 ) ( * 234940 )
NEW met2 ( 2175725 234680 ) ( 2175845 * )
NEW met2 ( 2175725 216170 ) ( * 234540 )
NEW met2 ( 2175230 216030 ) ( 2176180 * )
NEW met2 ( 2175705 215940 ) via_1090_260_hv
NEW li1 ( 2175245 215965 ) ( 2176165 * )
NEW li1 ( 2175705 215935 ) mcon_1090_170
NEW met2 ( 2175230 215850 ) ( 2176180 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[3] ( sky130_fd_sc_hd__buf_8_50 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3367070 2273965 ) ( * 2276205 )
NEW met1 ( 3367070 2273825 ) ( 3367350 * )
NEW met1 ( 3367350 2219125 ) ( * 2273685 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3367350 2218985 ) ( 3367470 * )
NEW met1 ( 3367410 2218895 ) via_260_260_vh ( * 2218835 )
( 3384835 * ) ( * 2218830 ) via_850_260_hv mcon_850_170
NEW met2 ( 3384480 2218920 ) ( 3385190 * )
NEW met2 ( 3384480 2218740 ) ( 3385190 * )
NEW met2 ( 3366060 2218835 ) ( 3367210 * )
NEW met1 ( 3367350 2218805 ) ( 3367470 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[3] ( sky130_fd_sc_hd__buf_8_50 A )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3367210 1179320 ) ( * 1182230 )
NEW met1 ( 3367210 1182370 ) ( 3367490 * )
NEW met1 ( 3367490 1182510 ) ( * 2214800 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 3367370 2214940 ) ( 3367490 * )
NEW met1 ( 3367430 2215030 ) via_260_260_vh
NEW met1 ( 3367370 2215120 ) ( 3367490 * )
NEW met2 ( 3367630 2214970 ) ( 3384630 * )
NEW met1 ( 3384770 2215690 ) ( 3384890 * )
NEW met1 ( 3384770 2214620 ) ( 3384890 * )
NEW met1 ( 3384830 2215155 ) via_260_1090_vh
NEW met1 ( 3384835 2215155 ) mcon_170_1090
NEW met2 ( 3366060 2214970 ) ( 3367230 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_173/A ( sky130_fd_sc_hd__buf_8_173 A )
( sky130_fd_sc_hd__buf_8_140 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 203160 3003825 ) mcon_170_1090
NEW met1 ( 203105 3004360 ) ( 203225 * )
NEW met2 ( 203365 3003640 ) ( 218945 * )
NEW met1 ( 219085 3003790 ) ( 219205 * )
NEW met1 ( 219145 3003700 ) via_260_260_vh
NEW met1 ( 219085 3003610 ) ( 219205 * )
NEW met1 ( 219085 1719890 ) ( * 3003470 )
NEW met1 ( 218965 1719750 ) ( 219085 * )
NEW met1 ( 219025 1719660 ) via_260_260_vh ( * 1719600 )
( 223670 * )
NEW met2 ( 203765 1719600 ) ( 218825 * )
NEW met2 ( 203270 1719595 ) via_850_260_hv mcon_850_170
NEW met2 ( 202915 1719685 ) ( 203625 * )
NEW met2 ( 202915 1719505 ) ( 203625 * )
NEW met1 ( 218965 1719570 ) ( 219085 * )
NEW met2 ( 219345 3003640 ) ( 221530 * )
NEW met1 ( 203105 3003290 ) ( 203225 * )
NEW met1 ( 203165 3003825 ) via_260_1090_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[8] ( sky130_fd_sc_hd__buf_8_173 X )
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
+ ROUTED met1 ( 219505 3057440 ) ( * 3059905 )
NEW met1 ( 219225 3057300 ) ( 219505 * )
NEW met1 ( 219225 3007795 ) ( * 3057160 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 219105 3007655 ) ( 219225 * )
NEW met1 ( 219165 3007565 ) via_260_260_vh ( * 3007505 )
( 221530 * )
NEW met2 ( 203655 3007505 ) ( 218965 * )
NEW met2 ( 203160 3007500 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3007590 ) ( 203515 * )
NEW met2 ( 202805 3007410 ) ( 203515 * )
NEW met1 ( 219105 3007475 ) ( 219225 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_71/X ( sky130_fd_sc_hd__buf_8_71 X )
( sky130_fd_sc_hd__buf_8_140 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 712465 215935 ) mcon_170_850
NEW met1 ( 712400 216350 ) ( 712520 * )
NEW met2 ( 712450 216430 ) ( * 231020 )
NEW met2 ( 712450 231160 ) ( 712570 * )
NEW met2 ( 712510 231250 ) via_260_260_hv
NEW met2 ( 712450 231340 ) ( 712570 * )
NEW met2 ( 712450 231480 ) ( * 231435 )
NEW met1 ( 701945 231190 ) ( 712310 * )
NEW met1 ( 701945 231330 ) ( * 231890 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 218945 232030 ) ( 701945 * )
NEW met1 ( 218945 232170 ) ( * 1715565 )
NEW met1 ( 218945 1715705 ) ( 219065 * )
NEW met1 ( 219005 1715795 ) via_260_260_vh
NEW met1 ( 218945 1715885 ) ( 219065 * )
NEW met2 ( 219205 1715735 ) ( 223670 * )
NEW met2 ( 202915 1715735 ) ( 218805 * )
NEW met1 ( 203215 1716455 ) ( 203335 * )
NEW met1 ( 203425 1715735 ) ( 203335 * )
NEW met1 ( 203215 1715385 ) ( 203335 * )
NEW met1 ( 203275 1715520 ) via_260_290_vh
NEW met1 ( 203215 1715735 ) ( 203115 * )
NEW met1 ( 203275 1716135 ) via_260_660_vh
NEW met1 ( 203270 1715920 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 712400 215520 ) ( 712520 * )
NEW met1 ( 712460 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_71/A ( sky130_fd_sc_hd__buf_8_71 A )
( sky130_fd_sc_hd__buf_8_103 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 716645 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 716170 216030 ) ( 717120 * )
NEW met2 ( 716665 216170 ) ( * 231040 )
NEW met2 ( 716545 231180 ) ( 716665 * )
NEW met2 ( 716605 231270 ) via_260_260_hv
NEW met2 ( 716545 231360 ) ( 716665 * )
NEW met2 ( 716665 231500 ) ( * 231455 )
NEW met1 ( 716805 231330 ) ( 783965 * )
NEW met1 ( 783965 231470 ) ( * 232030 )
NEW met1 ( 783965 232170 ) ( 2189510 * ) ( * 232230 )
via_260_260_hv ( * 232320 ) ( 2189570 * )
NEW met2 ( 2189450 232460 ) ( * 232415 )
NEW met2 ( 2189450 232140 ) ( 2189570 * )
NEW met2 ( 2189450 216430 ) ( * 232000 )
NEW met1 ( 2189400 216350 ) ( 2189520 * )
NEW met1 ( 2189400 215520 ) ( 2189520 * )
NEW met1 ( 2189460 215935 ) via_260_850_vh
NEW met1 ( 2189465 215935 ) mcon_170_850
NEW met2 ( 716170 215850 ) ( 717120 * )
NEW li1 ( 716185 215965 ) ( 717105 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_89/A ( sky130_fd_sc_hd__buf_8_89 A )
( sky130_fd_sc_hd__buf_8_82 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2153135 212875 ) mcon_1090_170
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2152660 212970 ) ( 2153610 * )
NEW met2 ( 2152950 213110 ) ( * 237600 )
NEW met2 ( 2152950 237740 ) ( 2153070 * )
NEW met2 ( 2153010 237830 ) via_260_260_hv
NEW met2 ( 2152950 237920 ) ( 2153070 * )
NEW met2 ( 2152950 238060 ) ( * 237980 )
NEW met1 ( 778365 237770 ) ( 2152810 * )
NEW met1 ( 778365 235110 ) ( * 237630 )
NEW met1 ( 705995 234970 ) ( 778365 * )
NEW met1 ( 705995 235110 ) ( * 237630 )
NEW met1 ( 680075 237770 ) ( 705995 * )
NEW met1 ( 679875 237710 ) via_260_260_hv ( * 237800 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 679935 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 679815 237940 ) ( * 237855 )
NEW met2 ( 679815 237620 ) ( 679935 * )
NEW met2 ( 679815 213370 ) ( * 237480 )
NEW met1 ( 679750 213290 ) ( 679870 * )
NEW met1 ( 679750 212460 ) ( 679870 * )
NEW met1 ( 679810 212875 ) via_260_850_vh
NEW met1 ( 679815 212875 ) mcon_170_850
NEW met2 ( 2152660 212790 ) ( 2153610 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_82/A ( sky130_fd_sc_hd__buf_8_82 A )
( sky130_fd_sc_hd__buf_8_128 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 676135 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 675660 212970 ) ( 676610 * )
NEW met2 ( 675950 213110 ) ( * 237460 )
NEW met2 ( 675950 237600 ) ( 676070 * )
NEW met2 ( 676010 237690 ) via_260_260_hv
NEW met2 ( 675950 237780 ) ( 676070 * )
NEW met2 ( 675950 237920 ) ( * 237830 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 226505 237630 ) ( 675810 * )
NEW met1 ( 226505 237770 ) ( * 1674325 )
NEW met1 ( 226505 1674465 ) ( 226625 * )
NEW met1 ( 226565 1674555 ) via_260_260_vh
NEW met1 ( 226505 1674645 ) ( 226625 * )
NEW met2 ( 226765 1674495 ) ( 227030 * )
NEW met2 ( 206825 1674495 ) ( 226365 * )
NEW met2 ( 206330 1674505 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1674595 ) ( 206685 * )
NEW met2 ( 205975 1674415 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 675660 212790 ) ( 676610 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[13] ( sky130_fd_sc_hd__buf_8_93 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3357550 1118280 ) ( * 1121670 )
NEW met1 ( 3357270 1118140 ) ( 3357550 * )
NEW met1 ( 3357270 227370 ) ( * 1118000 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2516850 227230 ) ( 3357270 * )
NEW met1 ( 2516850 221650 ) ( * 227090 )
NEW met1 ( 2436570 221510 ) ( 2516850 * )
NEW met1 ( 2436570 221650 ) ( * 236090 )
NEW met1 ( 2169035 236230 ) ( 2436570 * )
NEW met1 ( 2168835 236170 ) via_260_260_hv ( * 236260 )
( 2168895 * )
NEW met2 ( 2168775 236400 ) ( * 236330 )
NEW met2 ( 2168775 236080 ) ( 2168895 * )
NEW met2 ( 2168775 213370 ) ( * 235940 )
NEW met1 ( 2168710 213290 ) ( 2168830 * )
NEW met1 ( 2168710 212460 ) ( 2168830 * )
NEW met1 ( 2168770 212875 ) via_260_850_vh
NEW met1 ( 2168775 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[8] ( sky130_fd_sc_hd__buf_8_172 A )
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
+ ROUTED met1 ( 218945 3008765 ) ( * 3060905 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 218825 3008625 ) ( 218945 * )
NEW met1 ( 218885 3008535 ) via_260_260_vh ( * 3008475 )
( 221530 * )
NEW met2 ( 206425 3008475 ) ( 218685 * )
NEW met1 ( 206165 3008990 ) ( 206285 * )
NEW met1 ( 206165 3007920 ) ( 206285 * )
NEW met1 ( 206225 3008455 ) via_260_1090_vh
NEW met1 ( 206220 3008455 ) mcon_170_1090
NEW met1 ( 218825 3008445 ) ( 218945 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_70/X ( sky130_fd_sc_hd__buf_8_70 X )
( sky130_fd_sc_hd__buf_8_100 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 715695 212875 ) mcon_170_850
NEW met1 ( 715630 213290 ) ( 715750 * )
NEW met2 ( 715695 213370 ) ( * 231320 )
NEW met2 ( 715695 231460 ) ( 715815 * )
NEW met2 ( 715755 231550 ) via_260_260_hv
NEW met2 ( 715695 231640 ) ( 715815 * )
NEW met2 ( 715695 231780 ) ( * 231710 )
NEW met1 ( 715955 231610 ) ( 783405 * )
NEW met1 ( 783405 231750 ) ( * 232590 )
NEW met1 ( 783405 232730 ) ( 2188890 * ) ( * 232790 )
via_260_260_hv ( * 232880 ) ( 2188950 * )
NEW met2 ( 2188830 233020 ) ( * 232930 )
NEW met2 ( 2188830 232700 ) ( 2188950 * )
NEW met2 ( 2188830 213110 ) ( * 232560 )
NEW met2 ( 2188540 212970 ) ( 2189490 * )
NEW met2 ( 2189015 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2188540 212790 ) ( 2189490 * )
NEW met1 ( 715630 212460 ) ( 715750 * )
NEW met1 ( 715690 212875 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_70/A ( sky130_fd_sc_hd__buf_8_70 A )
( sky130_fd_sc_hd__buf_8_143 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 712015 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 711540 212970 ) ( 712490 * )
NEW met2 ( 711830 213110 ) ( * 231300 )
NEW met2 ( 711830 231440 ) ( 711950 * )
NEW met2 ( 711890 231530 ) via_260_260_hv
NEW met2 ( 711830 231620 ) ( 711950 * )
NEW met2 ( 711830 231760 ) ( * 231680 )
NEW met1 ( 702240 231470 ) ( 711690 * )
NEW met1 ( 702240 231610 ) ( * 232450 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 219785 232590 ) ( 702240 * )
NEW met1 ( 219785 232730 ) ( * 1710205 )
NEW met1 ( 219785 1710345 ) ( 219905 * )
NEW met1 ( 219845 1710435 ) via_260_260_vh
NEW met1 ( 219785 1710525 ) ( 219905 * )
NEW met2 ( 220045 1710375 ) ( 223670 * )
NEW met2 ( 206825 1710375 ) ( 219645 * )
NEW met2 ( 206330 1710385 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1710475 ) ( 206685 * )
NEW met2 ( 205975 1710295 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 711540 212790 ) ( 712490 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_81/X ( sky130_fd_sc_hd__buf_8_81 X )
( sky130_fd_sc_hd__buf_8_133 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 682565 215935 ) mcon_170_850
NEW met1 ( 682500 216350 ) ( 682620 * )
NEW met2 ( 682550 216430 ) ( * 236060 )
NEW met2 ( 682550 236200 ) ( 682670 * )
NEW met2 ( 682610 236290 ) via_260_260_hv
NEW met2 ( 682550 236380 ) ( 682670 * )
NEW met2 ( 682550 236520 ) ( * 236475 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 224545 236230 ) ( 682410 * )
NEW met1 ( 224545 236370 ) ( * 1685665 )
NEW met1 ( 224545 1685805 ) ( 224665 * )
NEW met1 ( 224605 1685895 ) via_260_260_vh
NEW met1 ( 224545 1685985 ) ( 224665 * )
NEW met2 ( 224805 1685835 ) ( 224735 * )
NEW met2 ( 203475 1685835 ) ( 224405 * )
NEW met1 ( 203215 1686555 ) ( 203335 * )
NEW met1 ( 203215 1685485 ) ( 203335 * )
NEW met1 ( 203275 1686020 ) via_260_1090_vh
NEW met1 ( 203270 1686020 ) mcon_170_1090
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 682500 215520 ) ( 682620 * )
NEW met1 ( 682560 215935 ) via_260_850_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_91/X ( sky130_fd_sc_hd__buf_8_91 X )
( sky130_fd_sc_hd__buf_8_81 A )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2159565 215935 ) mcon_170_850
NEW met1 ( 2159500 216350 ) ( 2159620 * )
NEW met2 ( 2159550 216430 ) ( * 236200 )
NEW met2 ( 2159550 236340 ) ( 2159670 * )
NEW met2 ( 2159610 236430 ) via_260_260_hv
NEW met2 ( 2159550 236520 ) ( 2159670 * )
NEW met2 ( 2159550 236660 ) ( * 236635 )
NEW met1 ( 779765 236370 ) ( 2159410 * )
NEW met1 ( 779765 234270 ) ( * 236230 )
NEW met1 ( 704595 234130 ) ( 779765 * )
NEW met1 ( 704595 234270 ) ( * 236230 )
NEW met1 ( 687025 236370 ) ( 704595 * )
NEW met1 ( 686825 236310 ) via_260_260_hv ( * 236400 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 686885 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 686765 236540 ) ( * 236450 )
NEW met2 ( 686765 236220 ) ( 686885 * )
NEW met2 ( 686765 216170 ) ( * 236080 )
NEW met2 ( 686270 216030 ) ( 687220 * )
NEW met2 ( 686745 215940 ) via_1090_260_hv
NEW li1 ( 686285 215965 ) ( 687205 * )
NEW li1 ( 686745 215935 ) mcon_1090_170
NEW met2 ( 686270 215850 ) ( 687220 * )
NEW met1 ( 2159500 215520 ) ( 2159620 * )
NEW met1 ( 2159560 215935 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[12] ( sky130_fd_sc_hd__buf_8_92 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3358110 226810 ) ( * 1122640 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2517690 226670 ) ( 3358110 * )
NEW met1 ( 2517690 221370 ) ( * 226530 )
NEW met1 ( 2435730 221230 ) ( 2517690 * )
NEW met1 ( 2435730 221370 ) ( * 235530 )
NEW met1 ( 2170005 235670 ) ( 2435730 * )
NEW met1 ( 2169805 235610 ) via_260_260_hv ( * 235700 )
( 2169865 * )
NEW met2 ( 2169745 235840 ) ( * 235860 )
NEW met2 ( 2169745 235520 ) ( 2169865 * )
NEW met2 ( 2169745 216170 ) ( * 235380 )
NEW met2 ( 2169250 216030 ) ( 2170200 * )
NEW met2 ( 2169725 215940 ) via_1090_260_hv
NEW li1 ( 2169265 215965 ) ( 2170185 * )
NEW li1 ( 2169725 215935 ) mcon_1090_170
NEW met2 ( 2169250 215850 ) ( 2170200 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[7] ( sky130_fd_sc_hd__buf_8_171 A )
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
+ ROUTED met1 ( 217825 3014745 ) ( * 3062770 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 217705 3014605 ) ( 217825 * )
NEW met1 ( 217765 3014515 ) via_260_260_vh ( * 3014455 )
( 221530 * )
NEW met2 ( 206425 3014455 ) ( 217565 * )
NEW met1 ( 206165 3014970 ) ( 206285 * )
NEW met1 ( 206165 3013900 ) ( 206285 * )
NEW met1 ( 206225 3014435 ) via_260_1090_vh
NEW met1 ( 206220 3014435 ) mcon_170_1090
NEW met1 ( 217705 3014425 ) ( 217825 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_90/A ( sky130_fd_sc_hd__buf_8_90 A )
( sky130_fd_sc_hd__buf_8_80 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 2159115 212875 ) mcon_1090_170
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
via_1090_260_hv
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 2158640 212970 ) ( 2159590 * )
NEW met2 ( 2158930 213110 ) ( * 236760 )
NEW met2 ( 2158930 236900 ) ( 2159050 * )
NEW met2 ( 2158990 236990 ) via_260_260_hv
NEW met2 ( 2158930 237080 ) ( 2159050 * )
NEW met2 ( 2158930 237220 ) ( * 237165 )
NEW met1 ( 779205 236930 ) ( 2158790 * )
NEW met1 ( 779205 234550 ) ( * 236790 )
NEW met1 ( 705155 234410 ) ( 779205 * )
NEW met1 ( 705155 234550 ) ( * 236790 )
NEW met1 ( 686055 236930 ) ( 705155 * )
NEW met1 ( 685855 236870 ) via_260_260_hv ( * 236960 )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( 685915 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 685795 237100 ) ( * 237015 )
NEW met2 ( 685795 236780 ) ( 685915 * )
NEW met2 ( 685795 213370 ) ( * 236640 )
NEW met1 ( 685730 213290 ) ( 685850 * )
NEW met1 ( 685730 212460 ) ( 685850 * )
NEW met1 ( 685790 212875 ) via_260_850_vh
NEW met1 ( 685795 212875 ) mcon_170_850
NEW met2 ( 2158640 212790 ) ( 2159590 * ) ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_80/A ( sky130_fd_sc_hd__buf_8_80 A )
( sky130_fd_sc_hd__buf_8_130 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 682115 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 681640 212970 ) ( 682590 * )
NEW met2 ( 681930 213110 ) ( * 236620 )
NEW met2 ( 681930 236760 ) ( 682050 * )
NEW met2 ( 681990 236850 ) via_260_260_hv
NEW met2 ( 681930 236940 ) ( 682050 * )
NEW met2 ( 681930 237080 ) ( * 236980 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 225385 236790 ) ( 681790 * )
NEW met1 ( 225385 236930 ) ( * 1680305 )
NEW met1 ( 225385 1680445 ) ( 225505 * )
NEW met1 ( 225445 1680535 ) via_260_260_vh
NEW met1 ( 225385 1680625 ) ( 225505 * )
NEW met2 ( 225645 1680475 ) ( 225960 * )
NEW met2 ( 206825 1680475 ) ( 225245 * )
NEW met2 ( 206330 1680485 ) via_850_260_hv mcon_850_170
NEW met2 ( 205975 1680575 ) ( 206685 * )
NEW met2 ( 205975 1680395 ) ( 206685 * )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met2 ( 681640 212790 ) ( 682590 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_unbuf[13] ( sky130_fd_sc_hd__buf_8_91 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 3356990 227650 ) ( * 1120620 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2516570 227510 ) ( 3356990 * )
NEW met1 ( 2516570 221930 ) ( * 227370 )
NEW met1 ( 2436850 221790 ) ( 2516570 * )
NEW met1 ( 2436850 221930 ) ( * 236370 )
NEW met1 ( 2164025 236510 ) ( 2436850 * )
NEW met1 ( 2163825 236450 ) via_260_260_hv ( * 236540 )
( 2163885 * )
NEW met2 ( 2163765 236680 ) ( * 236650 )
NEW met2 ( 2163765 236360 ) ( 2163885 * )
NEW met2 ( 2163765 216170 ) ( * 236220 )
NEW met2 ( 2163270 216030 ) ( 2164220 * )
NEW met2 ( 2163745 215940 ) via_1090_260_hv
NEW li1 ( 2163285 215965 ) ( 2164205 * )
NEW li1 ( 2163745 215935 ) mcon_1090_170
NEW met2 ( 2163270 215850 ) ( 2164220 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[7] ( sky130_fd_sc_hd__buf_8_170 X )
Corrected the verilog and the layout for the caravan version of the signal buffering (verilog was missing one of the buffers, and the layout had some of the labels at the top accidentally erased).
2022-10-16 20:06:27 -05:00
+ ROUTED met1 ( 218385 3059305 ) ( * 3061770 )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
NEW met1 ( 218105 3059165 ) ( 218385 * )
NEW met1 ( 218105 3013775 ) ( * 3059025 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
NEW met1 ( 217985 3013635 ) ( 218105 * )
NEW met1 ( 218045 3013545 ) via_260_260_vh ( * 3013485 )
( 221530 * )
NEW met2 ( 203655 3013485 ) ( 217845 * )
NEW met2 ( 203160 3013480 ) via_850_260_hv mcon_850_170
NEW met2 ( 202805 3013570 ) ( 203515 * )
NEW met2 ( 202805 3013390 ) ( 203515 * )
NEW met1 ( 217985 3013455 ) ( 218105 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_buf[14] ( sky130_fd_sc_hd__buf_8_90 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 3356430 1116275 ) ( * 1119620 )
NEW met1 ( 3356150 1116135 ) ( 3356430 * )
NEW met1 ( 3356150 228210 ) ( * 1115995 )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
NEW met1 ( 2515730 228070 ) ( 3356150 * )
NEW met1 ( 2515730 222210 ) ( * 227930 )
NEW met1 ( 2437690 222070 ) ( 2515730 * )
NEW met1 ( 2437690 222210 ) ( * 236930 )
NEW met1 ( 2163055 237070 ) ( 2437690 * )
NEW met1 ( 2162855 237010 ) via_260_260_hv ( * 237100 )
( 2162915 * )
NEW met2 ( 2162795 237240 ) ( * 237155 )
NEW met2 ( 2162795 236920 ) ( 2162915 * )
NEW met2 ( 2162795 213370 ) ( * 236780 )
NEW met1 ( 2162730 213290 ) ( 2162850 * )
NEW met1 ( 2162730 212460 ) ( 2162850 * )
NEW met1 ( 2162790 212875 ) via_260_850_vh
NEW met1 ( 2162795 212875 ) mcon_170_850 ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[2] ( sky130_fd_sc_hd__buf_8_9 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 665685 220830 ) ( 790250 * ) ( * 220890 )
via_260_260_hv ( * 220980 ) ( 790310 * )
NEW met2 ( 790190 221120 ) ( * 232275 )
NEW met2 ( 790190 220800 ) ( 790310 * )
NEW met2 ( 790190 216430 ) ( * 220660 )
NEW met1 ( 790140 216350 ) ( 790260 * )
NEW met1 ( 790140 215520 ) ( 790260 * )
NEW met1 ( 790200 215935 ) via_260_850_vh
NEW met1 ( 790205 215935 ) mcon_170_850 ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
- sky130_fd_sc_hd__buf_8_9/A ( sky130_fd_sc_hd__buf_8_9 A )
( sky130_fd_sc_hd__buf_8_127 X )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met1 ( 794385 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 793910 216030 ) ( 794860 * )
NEW met2 ( 794405 216170 ) ( * 220680 )
NEW met2 ( 794405 220820 ) ( 794525 * )
NEW met2 ( 794465 220910 ) via_260_260_hv
NEW met2 ( 794405 221000 ) ( 794525 * )
NEW met2 ( 794405 221140 ) ( * 232275 )
NEW met1 ( 794665 220970 ) ( 2267250 * ) ( * 221030 )
via_260_260_hv ( * 221120 ) ( 2267310 * )
NEW met2 ( 2267190 221260 ) ( * 232415 )
NEW met2 ( 2267190 220940 ) ( 2267310 * )
NEW met2 ( 2267190 216430 ) ( * 220800 )
NEW met1 ( 2267140 216350 ) ( 2267260 * )
NEW met1 ( 2267140 215520 ) ( 2267260 * )
NEW met1 ( 2267200 215935 ) via_260_850_vh
NEW met1 ( 2267205 215935 ) mcon_170_850
NEW met2 ( 793910 215850 ) ( 794860 * )
NEW li1 ( 793925 215965 ) ( 794845 * ) ;
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
- vssd ( sky130_fd_sc_hd__tapvpwrvgnd_1_29 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_1 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_275 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_272 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_24 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_28 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_25 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_13 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_25 VNB )
( sky130_fd_sc_hd__buf_8_24 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_274 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_13 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_301 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_184 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_185 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_302 VGND )
( sky130_ef_sc_hd__decap_12_36 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_171 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_36 VGND )
( sky130_fd_sc_hd__buf_8_172 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_37 VNB )
( sky130_ef_sc_hd__decap_12_37 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_187 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_170 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_186 VGND )
( sky130_fd_sc_hd__buf_8_171 VNB )
( sky130_fd_sc_hd__buf_8_170 VNB )
( sky130_fd_sc_hd__buf_8_173 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_173 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_172 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_300 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_175 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_35 VNB )
( sky130_ef_sc_hd__decap_12_35 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_298 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_189 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_188 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_175 VNB )
( sky130_fd_sc_hd__buf_8_174 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_174 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_193 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_191 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_177 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_51 VNB )
( sky130_ef_sc_hd__decap_12_51 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_299 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_177 VNB )
( sky130_fd_sc_hd__buf_8_176 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_176 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_192 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_190 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_179 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_52 VNB )
( sky130_ef_sc_hd__decap_12_52 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_297 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_179 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_178 VNB )
( sky130_fd_sc_hd__buf_8_178 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_195 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_194 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_16 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_17 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_269 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_37 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_54 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_35 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_36 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_36 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_37 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_38 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_39 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_35 VNB )
( sky130_fd_sc_hd__buf_8_34 VNB )
( sky130_fd_sc_hd__buf_8_34 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_53 VGND )
( sky130_ef_sc_hd__decap_12_54 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_266 VGND )
( sky130_ef_sc_hd__decap_12_53 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_62 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_52 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_63 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_60 VGND )
( sky130_fd_sc_hd__buf_8_52 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_61 VGND )
( sky130_fd_sc_hd__buf_8_53 VGND )
( sky130_ef_sc_hd__decap_12_55 VGND )
( sky130_fd_sc_hd__buf_8_53 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_267 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_265 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_55 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_58 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_50 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_50 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_59 VGND )
( sky130_fd_sc_hd__buf_8_51 VGND )
( sky130_ef_sc_hd__decap_12_57 VGND )
( sky130_fd_sc_hd__buf_8_51 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_263 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_57 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_56 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_48 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_48 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_57 VGND )
( sky130_fd_sc_hd__buf_8_49 VGND )
( sky130_ef_sc_hd__decap_12_56 VGND )
( sky130_fd_sc_hd__buf_8_49 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_264 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_56 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_54 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_47 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_47 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_55 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_46 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_46 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_59 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_52 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_59 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_261 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_12 VGND )
( sky130_fd_sc_hd__buf_8_12 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_53 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_13 VGND )
( sky130_ef_sc_hd__decap_12_58 VGND )
( sky130_fd_sc_hd__buf_8_13 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_262 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_58 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_318 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_158 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_159 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_50 VNB )
( sky130_ef_sc_hd__decap_12_50 VGND )
( sky130_fd_sc_hd__buf_8_149 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_317 VGND )
( sky130_ef_sc_hd__decap_12_48 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_48 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_148 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_141 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_148 VGND )
( sky130_fd_sc_hd__buf_8_149 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_160 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_161 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_141 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_140 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_140 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_315 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_316 VGND )
( sky130_ef_sc_hd__decap_12_49 VNB )
( sky130_ef_sc_hd__decap_12_49 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_153 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_143 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_152 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_155 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_142 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_154 VGND )
( sky130_fd_sc_hd__buf_8_143 VNB )
( sky130_fd_sc_hd__buf_8_142 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_314 VGND )
( sky130_ef_sc_hd__decap_12_47 VNB )
( sky130_ef_sc_hd__decap_12_47 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_147 VGND )
( sky130_fd_sc_hd__buf_8_134 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_146 VGND )
( sky130_fd_sc_hd__buf_8_135 VGND )
( sky130_fd_sc_hd__buf_8_135 VNB )
( sky130_fd_sc_hd__buf_8_134 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_313 VGND )
( sky130_ef_sc_hd__decap_12_45 VNB )
( sky130_ef_sc_hd__decap_12_45 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_149 VGND )
( sky130_fd_sc_hd__buf_8_136 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_148 VGND )
( sky130_fd_sc_hd__buf_8_137 VGND )
( sky130_fd_sc_hd__buf_8_137 VNB )
( sky130_fd_sc_hd__buf_8_136 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_311 VGND )
( sky130_ef_sc_hd__decap_12_46 VNB )
( sky130_ef_sc_hd__decap_12_46 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_151 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_139 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_150 VGND )
( sky130_fd_sc_hd__buf_8_138 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_139 VNB )
( sky130_fd_sc_hd__buf_8_138 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_312 VGND )
( sky130_ef_sc_hd__decap_12_44 VNB )
( sky130_ef_sc_hd__decap_12_44 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_145 VGND )
( sky130_fd_sc_hd__buf_8_132 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_133 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_144 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_133 VNB )
( sky130_fd_sc_hd__buf_8_132 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_310 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_12 VNB )
( sky130_ef_sc_hd__decap_12_12 VGND )
( sky130_ef_sc_hd__decap_12_14 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_130 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_14 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_143 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_128 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_131 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_142 VGND )
( sky130_fd_sc_hd__buf_8_131 VNB )
( sky130_fd_sc_hd__buf_8_130 VNB )
( sky130_fd_sc_hd__buf_8_129 VNB )
( sky130_fd_sc_hd__buf_8_129 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_128 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_141 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_309 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_140 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_20 VNB )
( sky130_ef_sc_hd__decap_12_20 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_127 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_235 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_237 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_236 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_19 VNB )
( sky130_ef_sc_hd__decap_12_19 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_233 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_126 VGND )
( sky130_ef_sc_hd__decap_12_17 VNB )
( sky130_ef_sc_hd__decap_12_17 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_234 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_123 VGND )
( sky130_ef_sc_hd__decap_12_18 VNB )
( sky130_ef_sc_hd__decap_12_18 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_232 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_120 VGND )
( sky130_ef_sc_hd__decap_12_16 VNB )
( sky130_ef_sc_hd__decap_12_16 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_231 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_118 VGND )
( sky130_ef_sc_hd__decap_12_5 VNB )
( sky130_ef_sc_hd__decap_12_5 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_221 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_117 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_226 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_11 VNB )
( sky130_ef_sc_hd__decap_12_11 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_225 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_10 VGND )
( sky130_ef_sc_hd__decap_12_9 VNB )
( sky130_ef_sc_hd__decap_12_9 VGND )
( sky130_ef_sc_hd__decap_12_8 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_104 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_8 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_103 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_224 VGND )
( sky130_ef_sc_hd__decap_12_7 VNB )
( sky130_ef_sc_hd__decap_12_7 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_223 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_99 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_6 VNB )
( sky130_ef_sc_hd__decap_12_6 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_98 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_222 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_2 VGND )
( sky130_ef_sc_hd__decap_12_0 VNB )
( sky130_ef_sc_hd__decap_12_0 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_220 VGND )
( sky130_fd_sc_hd__buf_8_94 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_4 VNB )
( sky130_ef_sc_hd__decap_12_4 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_219 VGND )
( sky130_fd_sc_hd__buf_8_92 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_3 VNB )
( sky130_ef_sc_hd__decap_12_3 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_218 VGND )
( sky130_fd_sc_hd__buf_8_91 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_2 VNB )
( sky130_ef_sc_hd__decap_12_2 VGND )
( sky130_ef_sc_hd__decap_12_1 VNB )
( sky130_ef_sc_hd__decap_12_1 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_239 VGND )
( sky130_fd_sc_hd__buf_8_88 VGND )
( sky130_fd_sc_hd__buf_8_86 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_43 VNB )
( sky130_ef_sc_hd__decap_12_43 VGND )
( sky130_fd_sc_hd__buf_8_9 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_260 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_326 VGND )
( sky130_fd_sc_hd__buf_8_7 VGND )
( sky130_ef_sc_hd__decap_12_41 VNB )
( sky130_ef_sc_hd__decap_12_41 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_258 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_5 VGND )
( sky130_ef_sc_hd__decap_12_42 VNB )
( sky130_ef_sc_hd__decap_12_42 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_259 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_84 VGND )
( sky130_ef_sc_hd__decap_12_38 VNB )
( sky130_ef_sc_hd__decap_12_38 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_255 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_3 VGND )
( sky130_ef_sc_hd__decap_12_40 VNB )
( sky130_ef_sc_hd__decap_12_40 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_257 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_55 VGND )
( sky130_ef_sc_hd__decap_12_34 VNB )
( sky130_ef_sc_hd__decap_12_34 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_256 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_250 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_248 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_33 VNB )
( sky130_ef_sc_hd__decap_12_33 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_249 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_31 VGND )
( sky130_ef_sc_hd__decap_12_32 VNB )
( sky130_ef_sc_hd__decap_12_32 VGND )
( sky130_ef_sc_hd__decap_12_30 VNB )
( sky130_ef_sc_hd__decap_12_30 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_247 VGND )
( sky130_fd_sc_hd__buf_8_69 VGND )
( sky130_fd_sc_hd__buf_8_71 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_245 VGND )
( sky130_ef_sc_hd__decap_12_28 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_73 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_28 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_246 VGND )
( sky130_ef_sc_hd__decap_12_29 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_75 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_29 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_244 VGND )
( sky130_ef_sc_hd__decap_12_27 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_77 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_27 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_243 VGND )
( sky130_ef_sc_hd__decap_12_25 VNB )
( sky130_ef_sc_hd__decap_12_25 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_242 VGND )
( sky130_fd_sc_hd__buf_8_78 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_26 VNB )
( sky130_ef_sc_hd__decap_12_26 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_240 VGND )
( sky130_fd_sc_hd__buf_8_81 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_23 VNB )
( sky130_ef_sc_hd__decap_12_23 VGND )
( sky130_ef_sc_hd__decap_12_24 VNB )
( sky130_ef_sc_hd__decap_12_24 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_241 VGND )
( sky130_fd_sc_hd__buf_8_83 VGND )
( sky130_fd_sc_hd__buf_8_1 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_125 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_125 VGND )
( sky130_fd_sc_hd__buf_8_127 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_135 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_136 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_138 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_139 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_137 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_134 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_124 VGND )
( sky130_fd_sc_hd__buf_8_126 VNB )
( sky130_fd_sc_hd__buf_8_124 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_133 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_132 VGND )
( sky130_fd_sc_hd__buf_8_122 VGND )
( sky130_fd_sc_hd__buf_8_123 VNB )
( sky130_fd_sc_hd__buf_8_122 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_131 VGND )
( sky130_fd_sc_hd__buf_8_121 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_130 VGND )
( sky130_fd_sc_hd__buf_8_121 VNB )
( sky130_fd_sc_hd__buf_8_120 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_129 VGND )
( sky130_fd_sc_hd__buf_8_119 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_128 VGND )
( sky130_fd_sc_hd__buf_8_119 VNB )
( sky130_fd_sc_hd__buf_8_118 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_127 VGND )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_15 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_126 VGND )
( sky130_fd_sc_hd__buf_8_117 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_15 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_117 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_116 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_115 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_113 VGND )
( sky130_fd_sc_hd__buf_8_102 VGND )
( sky130_fd_sc_hd__buf_8_102 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_10 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_114 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_112 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_101 VGND )
( sky130_fd_sc_hd__buf_8_104 VNB )
( sky130_fd_sc_hd__buf_8_101 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_103 VNB )
( sky130_fd_sc_hd__buf_8_100 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_100 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_111 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_108 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_99 VNB )
( sky130_fd_sc_hd__buf_8_97 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_97 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_110 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_107 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_98 VNB )
( sky130_fd_sc_hd__buf_8_96 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_96 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_109 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_106 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_103 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_102 VGND )
( sky130_fd_sc_hd__buf_8_95 VGND )
( sky130_fd_sc_hd__buf_8_95 VNB )
( sky130_fd_sc_hd__buf_8_94 VNB )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_105 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_104 VGND )
( sky130_fd_sc_hd__buf_8_93 VGND )
( sky130_fd_sc_hd__buf_8_93 VNB )
( sky130_fd_sc_hd__buf_8_92 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_101 VGND )
( sky130_fd_sc_hd__buf_8_90 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_100 VGND )
( sky130_fd_sc_hd__buf_8_91 VNB )
( sky130_fd_sc_hd__buf_8_90 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_99 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_98 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_89 VGND )
( sky130_fd_sc_hd__buf_8_89 VNB )
( sky130_fd_sc_hd__buf_8_88 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_86 VNB )
( sky130_ef_sc_hd__decap_12_22 VGND )
( sky130_ef_sc_hd__decap_12_22 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_97 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_96 VGND )
( sky130_fd_sc_hd__buf_8_8 VNB )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_8 VGND )
( sky130_fd_sc_hd__buf_8_9 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_10 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_11 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_12 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_13 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_7 VNB )
( sky130_fd_sc_hd__buf_8_6 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_6 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_9 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_8 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_5 VNB )
( sky130_fd_sc_hd__buf_8_4 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_4 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_5 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_4 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_85 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_85 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_84 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_95 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_94 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_3 VNB )
( sky130_fd_sc_hd__buf_8_2 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_2 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_7 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_6 VGND )
Fixes issues with the GPIO signal buffering by applying a bounding box to the layout, so that LEF and DEF positions are correct.
2022-10-15 09:31:35 -05:00
( sky130_fd_sc_hd__buf_8_55 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_39 VNB )
( sky130_ef_sc_hd__decap_12_39 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_64 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_65 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_75 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_74 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_77 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_76 VGND )
( sky130_fd_sc_hd__buf_8_67 VGND )
( sky130_fd_sc_hd__buf_8_67 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_31 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_79 VGND )
( sky130_fd_sc_hd__buf_8_68 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_78 VGND )
( sky130_fd_sc_hd__buf_8_69 VNB )
( sky130_fd_sc_hd__buf_8_68 VNB )
( sky130_fd_sc_hd__buf_8_71 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_70 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__buf_8_70 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_81 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_80 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_83 VGND )
( sky130_fd_sc_hd__buf_8_72 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_82 VGND )
( sky130_fd_sc_hd__buf_8_73 VNB )
( sky130_fd_sc_hd__buf_8_72 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_85 VGND )
( sky130_fd_sc_hd__buf_8_74 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_84 VGND )
( sky130_fd_sc_hd__buf_8_75 VNB )
( sky130_fd_sc_hd__buf_8_74 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_87 VGND )
( sky130_fd_sc_hd__buf_8_76 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_86 VGND )
( sky130_fd_sc_hd__buf_8_77 VNB )
( sky130_fd_sc_hd__buf_8_76 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_89 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_88 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_79 VGND )
( sky130_fd_sc_hd__buf_8_79 VNB )
( sky130_fd_sc_hd__buf_8_78 VNB )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_91 VGND )
( sky130_fd_sc_hd__buf_8_80 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_90 VGND )
( sky130_fd_sc_hd__buf_8_81 VNB )
( sky130_fd_sc_hd__buf_8_80 VNB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_93 VGND )
( sky130_fd_sc_hd__buf_8_82 VGND )
( sky130_fd_sc_hd__tapvpwrvgnd_1_92 VGND )
( sky130_fd_sc_hd__buf_8_83 VNB )
( sky130_fd_sc_hd__buf_8_82 VNB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_1 VNB )
( sky130_ef_sc_hd__decap_12_21 VGND )
( sky130_ef_sc_hd__decap_12_21 VNB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_238 VGND )
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_3 VGND )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met3 TAPERRULE met3_width_1740 ( 2208245 210670 ) ( 2209810 * )
NEW met3 ( 2208245 211690 ) ( 2207980 * )
NEW met3 TAPERRULE met3_width_1865 ( 2209027.5 211990 ) ( * 216800 )
NEW met3 ( 2208245 217100 ) ( 2207980 * )
NEW met3 ( 2208245 217175 ) ( 2209810 * )
NEW met3 ( 2210065 217100 ) ( 2209810 * )
NEW met2 ( 2208160 217240 ) ( 2209885 * )
NEW met2 ( 2208160 216950 ) ( 2209885 * )
NEW met2 ( 2209022.5 217100 ) via2_1785_300_vx
NEW met1 ( 2206210 217295 ) ( 2235700 * )
NEW met1 TAPERRULE met1_width_300 ( 2209985 217100 ) ( 2235700 * )
NEW met1 ( 2206210 216955 ) ( 2235700 * )
NEW met1 TAPERRULE met1_width_300 ( 2206210 217100 ) ( 2209022.5 * ) via_1785_300_hh
NEW met3 ( 2210065 211690 ) ( 2209810 * )
NEW met2 ( 2208160 211815 ) ( 2209885 * )
NEW met2 ( 2208160 211525 ) ( 2209885 * )
NEW met2 ( 2209022.5 211690 ) via2_1785_300_vx
NEW met1 ( 2206210 211855 ) ( 2235700 * )
NEW met1 TAPERRULE met1_width_300 ( 2209985 211690 ) ( 2235700 * )
NEW met1 ( 2206210 211515 ) ( 2235700 * )
NEW met1 TAPERRULE met1_width_300 ( 2206210 211690 ) ( 2209022.5 * ) via_1785_300_hh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[1] ( sky130_fd_sc_hd__buf_8_8 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 664685 221390 ) ( 789630 * ) ( * 221450 )
via_260_260_hv ( * 221540 ) ( 789690 * )
NEW met2 ( 789570 221680 ) ( * 232275 )
NEW met2 ( 789570 221360 ) ( 789690 * )
NEW met2 ( 789570 214310 ) ( * 221220 )
NEW met2 ( 789570 214170 ) ( 790205 * )
NEW met2 ( 790205 213370 ) ( * 214030 )
NEW met1 ( 790150 213290 ) ( 790270 * )
NEW met1 ( 790150 212460 ) ( 790270 * )
NEW met1 ( 790210 212875 ) via_260_850_vh
NEW met1 ( 790205 212875 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_8/A ( sky130_fd_sc_hd__buf_8_8 A )
( sky130_fd_sc_hd__buf_8_125 X )
+ ROUTED met1 ( 793885 212875 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 793410 212970 ) ( 794360 * )
NEW met2 ( 794070 213110 ) ( * 214030 )
NEW met2 ( 793435 214170 ) ( 794070 * )
NEW met2 ( 793435 214310 ) ( * 221240 )
NEW met2 ( 793435 221380 ) ( 793555 * )
NEW met2 ( 793495 221470 ) via_260_260_hv
NEW met2 ( 793435 221560 ) ( 793555 * )
NEW met2 ( 793435 221700 ) ( * 232275 )
NEW met1 ( 793695 221530 ) ( 2266630 * ) ( * 221590 )
via_260_260_hv ( * 221680 ) ( 2266690 * )
NEW met2 ( 2266570 221820 ) ( * 232415 )
NEW met2 ( 2266570 221500 ) ( 2266690 * )
NEW met2 ( 2266570 214240 ) ( * 221360 )
NEW met2 ( 2266570 214100 ) ( 2267205 * )
NEW met2 ( 2267205 213370 ) ( * 213960 )
NEW met1 ( 2267150 213290 ) ( 2267270 * )
NEW met1 ( 2267150 212460 ) ( 2267270 * )
NEW met1 ( 2267210 212875 ) via_260_850_vh
NEW met1 ( 2267205 212875 ) mcon_170_850
NEW met2 ( 793410 212790 ) ( 794360 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_oeb_buf[0] ( sky130_fd_sc_hd__buf_8_7 X )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 663685 221950 ) ( 784270 * ) ( * 222010 )
via_260_260_hv ( * 222100 ) ( 784330 * )
NEW met2 ( 784210 222240 ) ( * 232275 )
NEW met2 ( 784210 221920 ) ( 784330 * )
NEW met2 ( 784210 216430 ) ( * 221780 )
NEW met1 ( 784160 216350 ) ( 784280 * )
NEW met1 ( 784160 215520 ) ( 784280 * )
NEW met1 ( 784220 215935 ) via_260_850_vh
NEW met1 ( 784225 215935 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_7/A ( sky130_fd_sc_hd__buf_8_7 A )
( sky130_fd_sc_hd__buf_8_126 X )
+ ROUTED met1 ( 788405 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 787930 216030 ) ( 788880 * )
NEW met2 ( 788425 216170 ) ( * 221800 )
NEW met2 ( 788305 221940 ) ( 788425 * )
NEW met2 ( 788365 222030 ) via_260_260_hv
NEW met2 ( 788305 222120 ) ( 788425 * )
NEW met2 ( 788425 222260 ) ( * 232275 )
NEW met1 ( 788565 222090 ) ( 2261270 * ) ( * 222150 )
via_260_260_hv ( * 222240 ) ( 2261330 * )
NEW met2 ( 2261210 222380 ) ( * 232415 )
NEW met2 ( 2261210 222060 ) ( 2261330 * )
NEW met2 ( 2261210 216430 ) ( * 221920 )
NEW met1 ( 2261160 216350 ) ( 2261280 * )
NEW met1 ( 2261160 215520 ) ( 2261280 * )
NEW met1 ( 2261220 215935 ) via_260_850_vh
NEW met1 ( 2261225 215935 ) mcon_170_850
NEW met2 ( 787930 215850 ) ( 788880 * )
NEW li1 ( 787945 215965 ) ( 788865 * ) ;
- sky130_fd_sc_hd__buf_8_6/X ( sky130_fd_sc_hd__buf_8_6 X )
( sky130_fd_sc_hd__buf_8_124 A )
+ ROUTED met1 ( 787455 212875 ) mcon_170_850
NEW met1 ( 787390 213290 ) ( 787510 * )
NEW met2 ( 787455 213370 ) ( * 222360 )
NEW met2 ( 787455 222500 ) ( 787575 * )
NEW met2 ( 787515 222590 ) via_260_260_hv
NEW met2 ( 787455 222680 ) ( 787575 * )
NEW met2 ( 787455 222820 ) ( * 232275 )
NEW met1 ( 787715 222650 ) ( 2260650 * ) ( * 222710 )
via_260_260_hv ( * 222800 ) ( 2260710 * )
NEW met2 ( 2260590 222940 ) ( * 232415 )
NEW met2 ( 2260590 222620 ) ( 2260710 * )
NEW met2 ( 2260590 213110 ) ( * 222480 )
NEW met2 ( 2260300 212970 ) ( 2261250 * )
NEW met2 ( 2260775 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2260300 212790 ) ( 2261250 * )
NEW met1 ( 787390 212460 ) ( 787510 * )
NEW met1 ( 787450 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[19] ( sky130_fd_sc_hd__buf_8_6 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 662685 222510 ) ( 783650 * ) ( * 222570 )
via_260_260_hv ( * 222660 ) ( 783710 * )
NEW met2 ( 783590 222800 ) ( * 232275 )
NEW met2 ( 783590 222480 ) ( 783710 * )
NEW met2 ( 783590 213110 ) ( * 222340 )
NEW met2 ( 783300 212970 ) ( 784250 * )
NEW met2 ( 783775 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 783300 212790 ) ( 784250 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[19] ( sky130_fd_sc_hd__buf_8_5 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 661825 222930 ) ( 665515 * )
NEW met1 ( 665515 222790 ) ( 778290 * ) ( * 222850 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
via_260_260_hv ( * 222940 ) ( 778350 * )
NEW met2 ( 778230 223080 ) ( * 232275 )
NEW met2 ( 778230 222760 ) ( 778350 * )
NEW met2 ( 778230 216430 ) ( * 222620 )
NEW met1 ( 778180 216350 ) ( 778300 * )
NEW met1 ( 778180 215520 ) ( 778300 * )
NEW met1 ( 778240 215935 ) via_260_850_vh
NEW met1 ( 778245 215935 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_5/A ( sky130_fd_sc_hd__buf_8_5 A )
( sky130_fd_sc_hd__buf_8_123 X )
+ ROUTED met1 ( 782425 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 781950 216030 ) ( 782900 * )
NEW met2 ( 782445 216170 ) ( * 222640 )
NEW met2 ( 782445 222780 ) ( 782565 * )
NEW met2 ( 782505 222870 ) via_260_260_hv
NEW met2 ( 782445 222960 ) ( 782565 * )
NEW met2 ( 782445 223100 ) ( * 232275 )
NEW met1 ( 782705 222930 ) ( 2255290 * ) ( * 222990 )
via_260_260_hv ( * 223080 ) ( 2255350 * )
NEW met2 ( 2255230 223220 ) ( * 232415 )
NEW met2 ( 2255230 222900 ) ( 2255350 * )
NEW met2 ( 2255230 216430 ) ( * 222760 )
NEW met1 ( 2255180 216350 ) ( 2255300 * )
NEW met1 ( 2255180 215520 ) ( 2255300 * )
NEW met1 ( 2255240 215935 ) via_260_850_vh
NEW met1 ( 2255245 215935 ) mcon_170_850
NEW met2 ( 781950 215850 ) ( 782900 * )
NEW li1 ( 781965 215965 ) ( 782885 * ) ;
- sky130_fd_sc_hd__buf_8_4/X ( sky130_fd_sc_hd__buf_8_4 X )
( sky130_fd_sc_hd__buf_8_122 A )
+ ROUTED met1 ( 781475 212875 ) mcon_170_850
NEW met1 ( 781410 213290 ) ( 781530 * )
NEW met2 ( 781475 213370 ) ( * 223200 )
NEW met2 ( 781475 223340 ) ( 781595 * )
NEW met2 ( 781535 223430 ) via_260_260_hv
NEW met2 ( 781475 223520 ) ( 781595 * )
NEW met2 ( 781475 223660 ) ( * 232275 )
NEW met1 ( 781735 223490 ) ( 2254670 * ) ( * 223550 )
via_260_260_hv ( * 223640 ) ( 2254730 * )
NEW met2 ( 2254610 223780 ) ( * 232415 )
NEW met2 ( 2254610 223460 ) ( 2254730 * )
NEW met2 ( 2254610 213110 ) ( * 223320 )
NEW met2 ( 2254320 212970 ) ( 2255270 * )
NEW met2 ( 2254795 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2254320 212790 ) ( 2255270 * )
NEW met1 ( 781410 212460 ) ( 781530 * )
NEW met1 ( 781470 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[18] ( sky130_fd_sc_hd__buf_8_4 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 660685 223350 ) ( 777670 * ) ( * 223410 )
via_260_260_hv ( * 223500 ) ( 777730 * )
NEW met2 ( 777610 223640 ) ( * 232275 )
NEW met2 ( 777610 223320 ) ( 777730 * )
NEW met2 ( 777610 213110 ) ( * 223180 )
NEW met2 ( 777320 212970 ) ( 778270 * )
NEW met2 ( 777795 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 777320 212790 ) ( 778270 * ) ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_out_buf[17] ( sky130_fd_sc_hd__buf_8_3 X )
Another change to the pin endpoint positions to make sure that they have at least 0.28um spacing to the next wire. Not sure that this is going to solve the router errors, though.
2022-10-16 13:15:12 -05:00
+ ROUTED met1 ( 657825 224610 ) ( 661570 * )
NEW met1 ( 661570 224470 ) ( 766330 * ) ( * 224530 )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
via_260_260_hv ( * 224620 ) ( 766390 * )
NEW met2 ( 766270 224760 ) ( * 232275 )
NEW met2 ( 766270 224440 ) ( 766390 * )
NEW met2 ( 766270 216430 ) ( * 224300 )
NEW met1 ( 766220 216350 ) ( 766340 * )
NEW met1 ( 766220 215520 ) ( 766340 * )
NEW met1 ( 766280 215935 ) via_260_850_vh
NEW met1 ( 766285 215935 ) mcon_170_850 ;
- sky130_fd_sc_hd__buf_8_3/A ( sky130_fd_sc_hd__buf_8_3 A )
( sky130_fd_sc_hd__buf_8_118 X )
+ ROUTED met1 ( 770465 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 769990 216030 ) ( 770940 * )
NEW met2 ( 770485 216170 ) ( * 224320 )
NEW met2 ( 770485 224460 ) ( 770605 * )
NEW met2 ( 770545 224550 ) via_260_260_hv
NEW met2 ( 770485 224640 ) ( 770605 * )
NEW met2 ( 770485 224780 ) ( * 232275 )
NEW met1 ( 770745 224610 ) ( 2243330 * ) ( * 224670 )
via_260_260_hv ( * 224760 ) ( 2243390 * )
NEW met2 ( 2243270 224900 ) ( * 232415 )
NEW met2 ( 2243270 224580 ) ( 2243390 * )
NEW met2 ( 2243270 216430 ) ( * 224440 )
NEW met1 ( 2243220 216350 ) ( 2243340 * )
NEW met1 ( 2243220 215520 ) ( 2243340 * )
NEW met1 ( 2243280 215935 ) via_260_850_vh
NEW met1 ( 2243285 215935 ) mcon_170_850
NEW met2 ( 769990 215850 ) ( 770940 * )
NEW li1 ( 770005 215965 ) ( 770925 * ) ;
- sky130_fd_sc_hd__buf_8_2/X ( sky130_fd_sc_hd__buf_8_2 X )
( sky130_fd_sc_hd__buf_8_119 A )
+ ROUTED met1 ( 769515 212875 ) mcon_170_850
NEW met1 ( 769450 213290 ) ( 769570 * )
NEW met2 ( 769515 213370 ) ( * 224880 )
NEW met2 ( 769515 225020 ) ( 769635 * )
NEW met2 ( 769575 225110 ) via_260_260_hv
NEW met2 ( 769515 225200 ) ( 769635 * )
NEW met2 ( 769515 225340 ) ( * 232275 )
NEW met1 ( 769775 225170 ) ( 2242710 * ) ( * 225230 )
via_260_260_hv ( * 225320 ) ( 2242770 * )
NEW met2 ( 2242650 225460 ) ( * 232415 )
NEW met2 ( 2242650 225140 ) ( 2242770 * )
NEW met2 ( 2242650 213110 ) ( * 225000 )
NEW met2 ( 2242360 212970 ) ( 2243310 * )
NEW met2 ( 2242835 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 2242360 212790 ) ( 2243310 * )
NEW met1 ( 769450 212460 ) ( 769570 * )
NEW met1 ( 769510 212875 ) via_260_850_vh ;
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
- mgmt_io_in_unbuf[16] ( sky130_fd_sc_hd__buf_8_2 A )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
+ ROUTED met1 ( 656685 225030 ) ( 765710 * ) ( * 225090 )
via_260_260_hv ( * 225180 ) ( 765770 * )
NEW met2 ( 765650 225320 ) ( * 232275 )
NEW met2 ( 765650 225000 ) ( 765770 * )
NEW met2 ( 765650 213110 ) ( * 224860 )
NEW met2 ( 765360 212970 ) ( 766310 * )
NEW met2 ( 765835 212880 ) via_1090_260_hv mcon_1090_170
NEW met2 ( 765360 212790 ) ( 766310 * ) ;
- sky130_fd_sc_hd__buf_8_1/X ( sky130_fd_sc_hd__buf_8_1 X )
( sky130_fd_sc_hd__buf_8_129 A )
+ ROUTED met1 ( 670605 215935 ) mcon_170_850
NEW met1 ( 670540 216350 ) ( 670660 * )
NEW met2 ( 670590 216430 ) ( * 237740 )
NEW met2 ( 670590 237880 ) ( 670710 * )
NEW met2 ( 670650 237970 ) via_260_260_hv
NEW met2 ( 670590 238060 ) ( 670710 * )
NEW met2 ( 670590 238200 ) ( * 238155 )
NEW met1 ( 226785 237910 ) ( 670450 * )
NEW met1 ( 226785 238050 ) ( * 1673705 )
NEW met1 ( 226785 1673845 ) ( 226905 * )
NEW met1 ( 226845 1673935 ) via_260_260_vh
NEW met1 ( 226785 1674025 ) ( 226905 * )
NEW met2 ( 227045 1673875 ) ( 227030 * )
NEW met2 ( 203475 1673875 ) ( 226645 * )
NEW met1 ( 203215 1674595 ) ( 203335 * )
NEW met1 ( 203215 1673525 ) ( 203335 * )
NEW met1 ( 203275 1674060 ) via_260_1090_vh
NEW met1 ( 203270 1674060 ) mcon_170_1090
NEW met1 ( 670540 215520 ) ( 670660 * )
NEW met1 ( 670600 215935 ) via_260_850_vh ;
- sky130_fd_sc_hd__buf_8_1/A ( sky130_fd_sc_hd__buf_8_1 A )
( sky130_fd_sc_hd__buf_8_86 X )
+ ROUTED met1 ( 674785 215935 ) mcon_1090_170 via_1090_260_hv
NEW met2 ( 674310 216030 ) ( 675260 * )
NEW met2 ( 674805 216170 ) ( * 237760 )
NEW met2 ( 674805 237900 ) ( 674925 * )
NEW met2 ( 674865 237990 ) via_260_260_hv
NEW met2 ( 674805 238080 ) ( 674925 * )
NEW met2 ( 674805 238220 ) ( * 238155 )
NEW met1 ( 675065 238050 ) ( 706275 * )
NEW met1 ( 706275 235390 ) ( * 237910 )
NEW met1 ( 706275 235250 ) ( 778085 * )
NEW met1 ( 778085 235390 ) ( * 237910 )
NEW met1 ( 778085 238050 ) ( 2147650 * ) ( * 238110 )
via_260_260_hv ( * 238200 ) ( 2147710 * )
NEW met2 ( 2147590 238340 ) ( * 238295 )
NEW met2 ( 2147590 238020 ) ( 2147710 * )
NEW met2 ( 2147590 216430 ) ( * 237880 )
NEW met1 ( 2147540 216350 ) ( 2147660 * )
NEW met1 ( 2147540 215520 ) ( 2147660 * )
NEW met1 ( 2147600 215935 ) via_260_850_vh
NEW met1 ( 2147605 215935 ) mcon_170_850
NEW met2 ( 674310 215850 ) ( 675260 * )
NEW li1 ( 674325 215965 ) ( 675245 * ) ;
- vccd ( sky130_fd_sc_hd__tapvpwrvgnd_1_29 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_1 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_272 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_28 VPWR )
( sky130_fd_sc_hd__buf_8_25 VPWR )
( sky130_fd_sc_hd__buf_8_24 VPWR )
( sky130_fd_sc_hd__buf_8_25 VPB )
( sky130_fd_sc_hd__buf_8_24 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_275 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_274 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_13 VPWR )
( sky130_ef_sc_hd__decap_12_13 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_301 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_302 VPWR )
( sky130_ef_sc_hd__decap_12_36 VPWR )
( sky130_ef_sc_hd__decap_12_36 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_37 VPWR )
( sky130_ef_sc_hd__decap_12_37 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_300 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_35 VPWR )
( sky130_ef_sc_hd__decap_12_35 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_298 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_51 VPWR )
( sky130_ef_sc_hd__decap_12_51 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_299 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_52 VPWR )
( sky130_ef_sc_hd__decap_12_52 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_297 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_184 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_185 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_187 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_186 VPWR )
( sky130_fd_sc_hd__buf_8_171 VPWR )
( sky130_fd_sc_hd__buf_8_170 VPWR )
( sky130_fd_sc_hd__buf_8_171 VPB )
( sky130_fd_sc_hd__buf_8_170 VPB )
( sky130_fd_sc_hd__buf_8_173 VPWR )
( sky130_fd_sc_hd__buf_8_173 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_172 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_172 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_189 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_188 VPWR )
( sky130_fd_sc_hd__buf_8_175 VPWR )
( sky130_fd_sc_hd__buf_8_175 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_174 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_174 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_193 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_191 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_177 VPWR )
( sky130_fd_sc_hd__buf_8_177 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_176 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_176 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_192 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_190 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_179 VPWR )
( sky130_fd_sc_hd__buf_8_179 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_178 VPWR )
( sky130_fd_sc_hd__buf_8_178 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_195 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_194 VPWR )
( sky130_fd_sc_hd__buf_8_36 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_16 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_17 VPWR )
( sky130_fd_sc_hd__buf_8_36 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_37 VPWR )
( sky130_fd_sc_hd__buf_8_37 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_38 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_39 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_35 VPWR )
( sky130_fd_sc_hd__buf_8_35 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_62 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_34 VPWR )
( sky130_fd_sc_hd__buf_8_34 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_63 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_60 VPWR )
( sky130_fd_sc_hd__buf_8_52 VPWR )
( sky130_fd_sc_hd__buf_8_52 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_61 VPWR )
( sky130_fd_sc_hd__buf_8_53 VPWR )
( sky130_fd_sc_hd__buf_8_53 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_58 VPWR )
( sky130_fd_sc_hd__buf_8_50 VPWR )
( sky130_fd_sc_hd__buf_8_50 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_59 VPWR )
( sky130_fd_sc_hd__buf_8_51 VPWR )
( sky130_fd_sc_hd__buf_8_51 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_56 VPWR )
( sky130_fd_sc_hd__buf_8_48 VPWR )
( sky130_fd_sc_hd__buf_8_48 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_57 VPWR )
( sky130_fd_sc_hd__buf_8_49 VPWR )
( sky130_fd_sc_hd__buf_8_49 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_54 VPWR )
( sky130_fd_sc_hd__buf_8_47 VPWR )
( sky130_fd_sc_hd__buf_8_47 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_55 VPWR )
( sky130_fd_sc_hd__buf_8_46 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_46 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_261 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_12 VPWR )
( sky130_fd_sc_hd__buf_8_12 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_53 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_13 VPWR )
( sky130_fd_sc_hd__buf_8_13 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_54 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_269 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_54 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_266 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_267 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_53 VPWR )
( sky130_ef_sc_hd__decap_12_53 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_265 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_55 VPWR )
( sky130_ef_sc_hd__decap_12_55 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_263 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_57 VPWR )
( sky130_ef_sc_hd__decap_12_57 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_264 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_56 VPWR )
( sky130_ef_sc_hd__decap_12_56 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_52 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_59 VPWR )
( sky130_ef_sc_hd__decap_12_59 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_262 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_58 VPWR )
( sky130_ef_sc_hd__decap_12_58 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_ef_sc_hd__decap_12_50 VPWR )
( sky130_ef_sc_hd__decap_12_50 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_317 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_315 VPWR )
( sky130_ef_sc_hd__decap_12_48 VPWR )
( sky130_ef_sc_hd__decap_12_48 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_316 VPWR )
( sky130_ef_sc_hd__decap_12_49 VPWR )
( sky130_ef_sc_hd__decap_12_49 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_314 VPWR )
( sky130_ef_sc_hd__decap_12_47 VPWR )
( sky130_ef_sc_hd__decap_12_47 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_313 VPWR )
( sky130_ef_sc_hd__decap_12_45 VPWR )
( sky130_ef_sc_hd__decap_12_45 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_311 VPWR )
( sky130_ef_sc_hd__decap_12_46 VPWR )
( sky130_ef_sc_hd__decap_12_46 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_312 VPWR )
( sky130_ef_sc_hd__decap_12_44 VPWR )
( sky130_ef_sc_hd__decap_12_44 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_310 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_12 VPWR )
( sky130_ef_sc_hd__decap_12_12 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_141 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_14 VPWR )
( sky130_ef_sc_hd__decap_12_14 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_318 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_148 VPWR )
( sky130_fd_sc_hd__buf_8_148 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_149 VPWR )
( sky130_fd_sc_hd__buf_8_149 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_160 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_161 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_153 VPWR )
( sky130_fd_sc_hd__buf_8_141 VPWR )
( sky130_fd_sc_hd__buf_8_140 VPWR )
( sky130_fd_sc_hd__buf_8_141 VPB )
( sky130_fd_sc_hd__buf_8_140 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_152 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_155 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_154 VPWR )
( sky130_fd_sc_hd__buf_8_143 VPWR )
( sky130_fd_sc_hd__buf_8_142 VPWR )
( sky130_fd_sc_hd__buf_8_143 VPB )
( sky130_fd_sc_hd__buf_8_142 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_147 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_146 VPWR )
( sky130_fd_sc_hd__buf_8_135 VPWR )
( sky130_fd_sc_hd__buf_8_134 VPWR )
( sky130_fd_sc_hd__buf_8_135 VPB )
( sky130_fd_sc_hd__buf_8_134 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_149 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_148 VPWR )
( sky130_fd_sc_hd__buf_8_137 VPWR )
( sky130_fd_sc_hd__buf_8_136 VPWR )
( sky130_fd_sc_hd__buf_8_137 VPB )
( sky130_fd_sc_hd__buf_8_136 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_151 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_150 VPWR )
( sky130_fd_sc_hd__buf_8_139 VPWR )
( sky130_fd_sc_hd__buf_8_138 VPWR )
( sky130_fd_sc_hd__buf_8_139 VPB )
( sky130_fd_sc_hd__buf_8_138 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_145 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_144 VPWR )
( sky130_fd_sc_hd__buf_8_133 VPWR )
( sky130_fd_sc_hd__buf_8_132 VPWR )
( sky130_fd_sc_hd__buf_8_133 VPB )
( sky130_fd_sc_hd__buf_8_132 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_143 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_142 VPWR )
( sky130_fd_sc_hd__buf_8_131 VPWR )
( sky130_fd_sc_hd__buf_8_130 VPWR )
( sky130_fd_sc_hd__buf_8_131 VPB )
( sky130_fd_sc_hd__buf_8_130 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_309 VPWR )
( sky130_fd_sc_hd__buf_8_129 VPWR )
( sky130_fd_sc_hd__buf_8_128 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_140 VPWR )
( sky130_fd_sc_hd__buf_8_129 VPB )
( sky130_fd_sc_hd__buf_8_128 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_158 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_159 VPWR )
( sky130_ef_sc_hd__decap_12_20 VPWR )
( sky130_ef_sc_hd__decap_12_20 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_237 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_235 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_236 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_19 VPWR )
( sky130_ef_sc_hd__decap_12_19 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_233 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_17 VPWR )
( sky130_ef_sc_hd__decap_12_17 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_234 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_18 VPWR )
( sky130_ef_sc_hd__decap_12_18 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_232 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_16 VPWR )
( sky130_ef_sc_hd__decap_12_16 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_231 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_5 VPWR )
( sky130_ef_sc_hd__decap_12_5 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_221 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_226 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_11 VPWR )
( sky130_ef_sc_hd__decap_12_11 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_225 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_9 VPWR )
( sky130_ef_sc_hd__decap_12_9 VPB )
( sky130_ef_sc_hd__decap_12_8 VPWR )
( sky130_ef_sc_hd__decap_12_8 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_224 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_7 VPWR )
( sky130_ef_sc_hd__decap_12_7 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_223 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_6 VPWR )
( sky130_ef_sc_hd__decap_12_6 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_222 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_2 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_0 VPWR )
( sky130_ef_sc_hd__decap_12_0 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_220 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_4 VPWR )
( sky130_ef_sc_hd__decap_12_4 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_219 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_3 VPWR )
( sky130_ef_sc_hd__decap_12_3 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_218 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_2 VPWR )
( sky130_ef_sc_hd__decap_12_2 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_239 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_1 VPWR )
( sky130_ef_sc_hd__decap_12_1 VPB )
( sky130_ef_sc_hd__decap_12_43 VPWR )
( sky130_ef_sc_hd__decap_12_43 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_326 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_260 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_41 VPWR )
( sky130_ef_sc_hd__decap_12_41 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_258 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_42 VPWR )
( sky130_ef_sc_hd__decap_12_42 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_259 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_38 VPWR )
( sky130_ef_sc_hd__decap_12_38 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_255 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_40 VPWR )
( sky130_ef_sc_hd__decap_12_40 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_257 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_34 VPWR )
( sky130_ef_sc_hd__decap_12_34 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_256 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_250 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_248 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_33 VPWR )
( sky130_ef_sc_hd__decap_12_33 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_249 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_32 VPWR )
( sky130_ef_sc_hd__decap_12_32 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_247 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_30 VPWR )
( sky130_ef_sc_hd__decap_12_30 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_245 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_28 VPWR )
( sky130_ef_sc_hd__decap_12_28 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_246 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_29 VPWR )
( sky130_ef_sc_hd__decap_12_29 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_244 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_27 VPWR )
( sky130_ef_sc_hd__decap_12_27 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_243 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_25 VPWR )
( sky130_ef_sc_hd__decap_12_25 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_242 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_26 VPWR )
( sky130_ef_sc_hd__decap_12_26 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_240 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_23 VPWR )
( sky130_ef_sc_hd__decap_12_23 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_241 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_24 VPWR )
( sky130_ef_sc_hd__decap_12_24 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_125 VPWR )
( sky130_fd_sc_hd__buf_8_125 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_127 VPWR )
( sky130_fd_sc_hd__buf_8_127 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_136 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_139 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_135 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_138 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_137 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_134 VPWR )
( sky130_fd_sc_hd__buf_8_126 VPWR )
( sky130_fd_sc_hd__buf_8_124 VPWR )
( sky130_fd_sc_hd__buf_8_126 VPB )
( sky130_fd_sc_hd__buf_8_124 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_133 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_132 VPWR )
( sky130_fd_sc_hd__buf_8_123 VPWR )
( sky130_fd_sc_hd__buf_8_122 VPWR )
( sky130_fd_sc_hd__buf_8_123 VPB )
( sky130_fd_sc_hd__buf_8_122 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_131 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_130 VPWR )
( sky130_fd_sc_hd__buf_8_121 VPWR )
( sky130_fd_sc_hd__buf_8_120 VPWR )
( sky130_fd_sc_hd__buf_8_121 VPB )
( sky130_fd_sc_hd__buf_8_120 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_129 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_128 VPWR )
( sky130_fd_sc_hd__buf_8_119 VPWR )
( sky130_fd_sc_hd__buf_8_118 VPWR )
( sky130_fd_sc_hd__buf_8_119 VPB )
( sky130_fd_sc_hd__buf_8_118 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_127 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_126 VPWR )
( sky130_fd_sc_hd__buf_8_117 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_15 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_117 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_15 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_117 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_116 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_115 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_113 VPWR )
( sky130_fd_sc_hd__buf_8_102 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_10 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_102 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_10 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_114 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_112 VPWR )
( sky130_fd_sc_hd__buf_8_104 VPWR )
( sky130_fd_sc_hd__buf_8_101 VPWR )
( sky130_fd_sc_hd__buf_8_104 VPB )
( sky130_fd_sc_hd__buf_8_101 VPB )
( sky130_fd_sc_hd__buf_8_103 VPWR )
( sky130_fd_sc_hd__buf_8_103 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_100 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_100 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_111 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_108 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_99 VPWR )
( sky130_fd_sc_hd__buf_8_99 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_97 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_97 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_110 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_107 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_98 VPWR )
( sky130_fd_sc_hd__buf_8_98 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_96 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_96 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_109 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_106 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_103 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_102 VPWR )
( sky130_fd_sc_hd__buf_8_95 VPWR )
( sky130_fd_sc_hd__buf_8_94 VPWR )
( sky130_fd_sc_hd__buf_8_95 VPB )
( sky130_fd_sc_hd__buf_8_94 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_105 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_104 VPWR )
( sky130_fd_sc_hd__buf_8_93 VPWR )
( sky130_fd_sc_hd__buf_8_92 VPWR )
( sky130_fd_sc_hd__buf_8_93 VPB )
( sky130_fd_sc_hd__buf_8_92 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_101 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_100 VPWR )
( sky130_fd_sc_hd__buf_8_91 VPWR )
( sky130_fd_sc_hd__buf_8_90 VPWR )
( sky130_fd_sc_hd__buf_8_91 VPB )
( sky130_fd_sc_hd__buf_8_90 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_99 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_98 VPWR )
( sky130_fd_sc_hd__buf_8_89 VPWR )
( sky130_fd_sc_hd__buf_8_88 VPWR )
( sky130_fd_sc_hd__buf_8_89 VPB )
( sky130_fd_sc_hd__buf_8_88 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_97 VPWR )
( sky130_fd_sc_hd__buf_8_86 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_22 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_96 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_86 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_22 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_8 VPWR )
( sky130_fd_sc_hd__buf_8_8 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_9 VPWR )
( sky130_fd_sc_hd__buf_8_9 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_12 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_13 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_10 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_11 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_7 VPWR )
( sky130_fd_sc_hd__buf_8_7 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_6 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_6 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_9 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_8 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_5 VPWR )
( sky130_fd_sc_hd__buf_8_5 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_4 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_4 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_5 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_4 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_85 VPWR )
( sky130_fd_sc_hd__buf_8_85 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_84 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_84 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_95 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_94 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_3 VPWR )
( sky130_fd_sc_hd__buf_8_3 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__buf_8_2 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_2 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_7 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_6 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_55 VPWR )
( sky130_fd_sc_hd__buf_8_55 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_39 VPWR )
( sky130_ef_sc_hd__decap_12_39 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_64 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_65 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_75 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_74 VPWR )
( sky130_fd_sc_hd__buf_8_1 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_77 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_76 VPWR )
( sky130_fd_sc_hd__buf_8_67 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_31 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__buf_8_67 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_31 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_79 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_78 VPWR )
( sky130_fd_sc_hd__buf_8_69 VPWR )
( sky130_fd_sc_hd__buf_8_68 VPWR )
( sky130_fd_sc_hd__buf_8_69 VPB )
( sky130_fd_sc_hd__buf_8_68 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_81 VPWR )
( sky130_fd_sc_hd__buf_8_71 VPWR )
( sky130_fd_sc_hd__buf_8_70 VPWR )
( sky130_fd_sc_hd__buf_8_71 VPB )
( sky130_fd_sc_hd__buf_8_70 VPB )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_80 VPWR )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
( sky130_fd_sc_hd__tapvpwrvgnd_1_83 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_82 VPWR )
( sky130_fd_sc_hd__buf_8_73 VPWR )
( sky130_fd_sc_hd__buf_8_72 VPWR )
( sky130_fd_sc_hd__buf_8_73 VPB )
( sky130_fd_sc_hd__buf_8_72 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_85 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_84 VPWR )
( sky130_fd_sc_hd__buf_8_75 VPWR )
( sky130_fd_sc_hd__buf_8_74 VPWR )
( sky130_fd_sc_hd__buf_8_75 VPB )
( sky130_fd_sc_hd__buf_8_74 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_87 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_86 VPWR )
( sky130_fd_sc_hd__buf_8_77 VPWR )
( sky130_fd_sc_hd__buf_8_76 VPWR )
( sky130_fd_sc_hd__buf_8_77 VPB )
( sky130_fd_sc_hd__buf_8_76 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_89 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_88 VPWR )
( sky130_fd_sc_hd__buf_8_79 VPWR )
( sky130_fd_sc_hd__buf_8_78 VPWR )
( sky130_fd_sc_hd__buf_8_79 VPB )
( sky130_fd_sc_hd__buf_8_78 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_91 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_90 VPWR )
( sky130_fd_sc_hd__buf_8_81 VPWR )
( sky130_fd_sc_hd__buf_8_80 VPWR )
( sky130_fd_sc_hd__buf_8_81 VPB )
( sky130_fd_sc_hd__buf_8_80 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_93 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_92 VPWR )
( sky130_fd_sc_hd__buf_8_83 VPWR )
( sky130_fd_sc_hd__buf_8_82 VPWR )
( sky130_fd_sc_hd__buf_8_83 VPB )
( sky130_fd_sc_hd__buf_8_82 VPB )
( sky130_fd_sc_hd__tapvpwrvgnd_1_238 VPWR )
( sky130_fd_sc_hd__buf_8_1 VPWR )
Additional modification to move pins up into an uncongested area above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
2022-10-16 09:52:53 -05:00
( sky130_ef_sc_hd__decap_12_21 VPWR )
( sky130_fd_sc_hd__tapvpwrvgnd_1_3 VPWR )
( sky130_ef_sc_hd__decap_12_21 VPB )
Adjustments to the top level buffering cells to do various things like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
2022-10-15 16:35:17 -05:00
+ ROUTED met3 TAPERRULE met3_width_1850 ( 2203045 209950 ) ( * 214095 )
NEW met3 ( 2202270 214395 ) ( 2202000 * )
NEW met3 TAPERRULE met3_width_1850 ( 2203045 214695 ) ( * 219535 )
NEW met3 ( 2202270 219835 ) ( 2202000 * )
NEW met3 ( 2202270 219905 ) ( 2203820 * )
NEW met3 ( 2204085 219835 ) ( 2203820 * )
NEW met2 ( 2202180 219985 ) ( 2203905 * )
NEW met2 ( 2202180 219695 ) ( 2203905 * )
NEW met2 ( 2203042.5 219835 ) via2_1785_300_vx
NEW met2 ( 2203042.5 219835 ) via_1785_300_vh
NEW met3 ( 2204085 214395 ) ( 2203820 * )
NEW met2 ( 2202180 214545 ) ( 2203905 * )
NEW met2 ( 2202180 214255 ) ( 2203905 * )
NEW met2 ( 2203042.5 214395 ) via2_1785_300_vx
NEW met2 ( 2203042.5 214395 ) via_1785_300_vh ;
Added layout views (.mag, GDS, DEF, and LEF) for the caravan variant of the top level GPIO signal buffering (module gpio_signal_buffering_alt).
2022-10-14 15:06:11 -05:00
END NETS
END DESIGN