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caravel/mag/simple_por.mag

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Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
magic
tech sky130A
magscale 1 2
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
timestamp 1650914729
Updates for LVS. Only LVS issue remaining for caravel is how to get the ground domains to extract independently.
2021-11-22 11:00:55 -06:00
<< isosubstrate >>
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect -52 7354 7222 8450
rect -52 -62 11288 7354
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
<< nwell >>
rect 70 7344 6652 7795
rect 7401 6799 10893 7301
<< pwell >>
rect 463 6569 519 6579
rect 2635 5816 2853 6026
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
<< psubdiff >>
rect 38 8568 62 8640
rect 11170 8568 11194 8640
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
<< mvpsubdiff >>
rect 7438 7387 10856 7455
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect 3164 6326 3188 6728
rect 6990 6326 7014 6728
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
<< mvnsubdiff >>
rect 7467 7201 10827 7235
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
<< psubdiffcont >>
rect 62 8568 11170 8640
<< mvpsubdiffcont >>
rect 3188 6326 6990 6728
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
<< locali >>
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect -14 8552 26 8676
rect 11178 8552 11218 8676
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 41 8275 183 8288
rect 41 8190 57 8275
rect 169 8190 183 8275
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rect 35 6388 121 7179
rect 3043 7022 6927 7305
rect 7110 7322 7134 7435
rect 7110 7201 10829 7322
rect 7110 7022 7134 7201
rect 3043 7005 7134 7022
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect 2907 6728 7134 6838
rect 2907 6388 3188 6728
rect 35 6326 3188 6388
rect 6990 6388 7134 6728
rect 6990 6326 10860 6388
rect 35 6320 3220 6326
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 35 6318 505 6320
rect 35 6192 48 6318
rect 286 6192 505 6318
rect 35 6191 505 6192
rect 2951 6253 3220 6320
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect 6116 6253 10860 6326
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 2951 6191 10860 6253
rect 35 6143 10860 6191
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rect 9883 165 10270 381
rect 10655 165 10835 381
<< viali >>
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect 26 8640 11178 8676
rect 26 8568 62 8640
rect 62 8568 11170 8640
rect 11170 8568 11178 8640
rect 26 8552 11178 8568
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 57 8190 169 8275
rect 6936 8112 7117 8273
rect 9224 7854 9270 8060
rect 7604 7754 7807 7801
rect 9459 7754 9796 7801
rect 10785 7683 10819 7879
rect 6927 7022 7110 7435
rect 7870 6775 8128 6834
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect 3220 6326 6116 6693
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 8439 6684 8506 6878
rect 8650 6720 8853 6767
rect 10270 6735 10316 6896
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect 48 6192 286 6318
rect 505 6191 2951 6320
rect 3220 6253 6116 6326
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 2648 5829 2840 6015
rect 10202 5598 10340 6030
<< metal1 >>
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
rect -14 8676 11218 8684
rect -14 8552 26 8676
rect 11178 8552 11218 8676
rect -14 8544 11218 8552
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 40 8275 7133 8286
rect 40 8190 57 8275
rect 169 8273 7133 8275
rect 169 8269 6936 8273
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rect 25 2348 133 2748
rect 10805 2348 10867 2748
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<< via1 >>
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 92 8568 11148 8640
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 60 8201 169 8269
rect 169 8201 624 8269
rect 1026 8193 6936 8260
rect 6936 8193 7093 8260
rect 719 8082 801 8144
rect 719 7544 801 7606
rect 7318 8153 10802 8252
rect 2275 7003 2351 7074
rect 10138 7999 10290 8053
rect 8339 7748 8519 7807
rect 10753 7683 10785 7728
rect 10785 7683 10819 7728
rect 10819 7683 10905 7728
rect 10753 7674 10905 7683
rect 4331 6693 5278 6819
rect 2275 6460 2350 6533
rect 4331 6270 5278 6693
rect 6432 6623 6803 7036
rect 7306 7449 8343 7543
rect 8618 7449 10649 7543
rect 7171 7124 8320 7299
rect 8602 7124 10750 7299
rect 8439 6684 8506 6878
rect 10507 6765 10672 6834
rect 10233 6187 10700 6260
<< metal2 >>
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect -14 8640 11218 8684
rect -14 8568 92 8640
rect 11148 8568 11218 8640
rect -14 8544 11218 8568
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 985 8286 7132 8287
rect 38 8269 7132 8286
rect 38 8201 60 8269
rect 624 8261 7132 8269
rect 38 8104 77 8201
rect 634 8187 886 8261
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rect 10700 6187 10716 6260
rect 10221 6176 10716 6187
<< via2 >>
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 92 8568 11148 8640
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 77 8201 624 8261
rect 624 8201 634 8261
rect 77 8104 634 8201
rect 886 8260 7091 8261
rect 886 8193 1026 8260
rect 1026 8193 7091 8260
rect 886 8104 7091 8193
rect 7318 8153 10802 8252
rect 10138 8053 10290 8056
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rect 7306 7449 8343 7543
rect 4331 6819 5278 6849
rect 4331 6522 5278 6819
rect 6432 6623 6803 7036
rect 10753 7728 10905 7731
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rect 8618 7449 10649 7543
rect 10757 6765 10909 6834
<< metal3 >>
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect -14 8674 11214 8684
rect -14 8640 7260 8674
rect 7724 8640 11214 8674
rect -14 8568 92 8640
rect 11148 8568 11214 8640
rect -14 8554 7260 8568
rect 7724 8554 11214 8568
rect -14 8438 11214 8554
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 38 8261 7126 8283
rect 38 8244 77 8261
rect 634 8244 886 8261
rect 38 8000 73 8244
rect 7091 8104 7126 8261
rect 7284 8252 10841 8278
rect 7284 8153 7318 8252
rect 10802 8153 10841 8252
rect 7284 8125 10841 8153
rect 7073 8000 7126 8104
rect 38 7965 7126 8000
rect 10128 8056 10295 8064
rect 10128 7996 10138 8056
rect 10290 7996 10431 8056
rect 10128 7991 10295 7996
rect 10371 7916 10431 7996
rect 10371 7856 11343 7916
rect 10743 7731 10910 7739
rect 10743 7671 10753 7731
rect 10905 7671 10910 7731
rect 10743 7666 10910 7671
rect 7279 7543 10667 7570
rect 7279 7449 7306 7543
rect 10649 7449 10667 7543
rect 10792 7551 10852 7666
rect 10792 7491 11344 7551
rect 7279 7417 10667 7449
rect 4111 7277 5299 7317
rect 4111 6849 4350 7277
rect 5268 6849 5299 7277
rect 4111 6522 4331 6849
rect 5278 6522 5299 6849
rect 6408 7036 6825 7065
rect 6408 6623 6432 7036
rect 6803 6623 6825 7036
rect 10747 6834 10918 6840
rect 10747 6765 10757 6834
rect 10909 6765 11342 6834
rect 10747 6758 10918 6765
rect 6408 6600 6825 6623
rect 4111 6494 5299 6522
rect 4111 6251 4307 6494
<< via3 >>
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 7260 8640 7724 8674
rect 7260 8568 7724 8640
rect 7260 8554 7724 8568
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 73 8104 77 8244
rect 77 8104 634 8244
rect 634 8104 886 8244
rect 886 8104 7073 8244
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 7928 8153 10802 8252
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 73 8000 7073 8104
rect 7306 7449 8343 7543
rect 8343 7449 8618 7543
rect 8618 7449 10649 7543
rect 4350 6849 5268 7277
rect 4350 6558 5268 6849
rect 6432 6623 6803 7036
<< metal4 >>
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 7248 8674 7736 8684
rect 7248 8554 7260 8674
rect 7724 8554 7736 8674
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 38 8244 7126 8283
rect 38 8000 73 8244
rect 7073 8000 7126 8244
rect 38 7965 7126 8000
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 7248 7655 7736 8554
rect 7918 8252 11180 8291
rect 7918 8153 7928 8252
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 10802 8153 11180 8252
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 7918 7962 11180 8153
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 10843 7755 11178 7774
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 38 7277 6984 7655
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 38 7255 4350 7277
rect 3817 6558 4350 7255
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
rect 5268 7255 6984 7277
rect 7248 7543 10667 7655
rect 7248 7449 7306 7543
rect 10649 7449 10667 7543
rect 7248 7255 10667 7449
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
rect 5268 6558 5299 7255
rect 10843 7074 10879 7755
rect 6386 7036 10879 7074
rect 6386 6623 6432 7036
rect 6803 6623 10879 7036
rect 6386 6615 10879 6623
rect 11146 6615 11178 7755
rect 6386 6591 11178 6615
rect 3817 6522 5299 6558
rect 3817 51 4011 6522
rect 4101 51 4793 6251
<< via4 >>
rect 4350 6558 5268 7247
rect 10879 6615 11146 7755
<< metal5 >>
rect 10851 7755 11171 7779
rect 4313 7247 5299 7317
rect 4313 6558 4350 7247
rect 5268 6558 5299 7247
rect 4313 6494 5299 6558
rect 4507 6135 5299 6494
rect 10851 6615 10879 7755
rect 11146 6615 11171 7755
rect 10851 6242 11171 6615
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_pr__cap_mim_m3_1_WRT4AW sky130_fd_pr__cap_mim_m3_1_WRT4AW_0 primitives
timestamp 1606502073
transform -1 0 7027 0 1 3151
box -3136 -3100 3136 3100
use sky130_fd_pr__cap_mim_m3_2_W5U4AW sky130_fd_pr__cap_mim_m3_2_W5U4AW_0 primitives
timestamp 1606502073
transform 1 0 7970 0 1 3151
box -3179 -3101 3201 3101
use sky130_fd_pr__nfet_g5v0d10v5_PKVMTM sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 primitives
timestamp 1625577137
transform 1 0 2660 0 1 6770
box -308 -458 308 458
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
use sky130_fd_pr__nfet_g5v0d10v5_TGFUGS sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 primitives
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
timestamp 1606063140
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
transform 1 0 1515 0 1 6769
box -962 -458 962 458
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
use sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 primitives
timestamp 1605994897
transform -1 0 371 0 1 6769
box -308 -458 308 458
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 primitives
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
timestamp 1606063140
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
transform 1 0 3392 0 1 7841
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
box -338 -497 338 497
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
timestamp 1606063140
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
transform 1 0 3878 0 1 7841
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
box -338 -497 338 497
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
timestamp 1606063140
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
transform 1 0 6644 0 1 7841
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
box -338 -497 338 497
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
timestamp 1606063140
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
transform 1 0 408 0 1 7841
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
box -338 -497 338 497
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
use sky130_fd_pr__pfet_g5v0d10v5_YEUEBV sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 primitives
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
timestamp 1606063140
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
transform 1 0 5018 0 1 7841
box -992 -497 992 497
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_pr__pfet_g5v0d10v5_YUHPBG sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 primitives
timestamp 1606063140
transform 1 0 2906 0 1 7841
box -338 -497 338 497
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
use sky130_fd_pr__pfet_g5v0d10v5_YUHPXE sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 primitives
timestamp 1606063140
transform 1 0 6158 0 1 7841
box -338 -497 338 497
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 primitives
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
timestamp 1606063140
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
transform 1 0 1657 0 1 7841
box -1101 -497 1101 497
use sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 primitives
timestamp 1606074388
transform 1 0 5446 0 1 3098
box -5446 -3098 5446 3098
use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
timestamp 1646116156
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
transform 1 0 8523 0 1 6404
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
box -66 -43 1986 897
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_1
timestamp 1646116156
transform 1 0 7477 0 1 7438
box -66 -43 1986 897
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
use sky130_fd_sc_hvl__fill_4 sky130_fd_sc_hvl__fill_4_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
timestamp 1646116156
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
transform 1 0 10443 0 1 6404
box -66 -43 450 897
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
use sky130_fd_sc_hvl__inv_8 sky130_fd_sc_hvl__inv_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
timestamp 1646116156
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
transform 1 0 9397 0 1 7438
box -66 -43 1506 897
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
use sky130_fd_sc_hvl__schmittbuf_1 sky130_fd_sc_hvl__schmittbuf_1_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
timestamp 1646116156
transform 1 0 7467 0 1 6404
box -66 -43 1122 897
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
<< labels >>
flabel metal4 s 38 7965 73 8283 0 FreeSans 320 0 0 0 vdd3v3
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
port 0 nsew power bidirectional
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
flabel metal4 s 10974 7962 11180 8291 0 FreeSans 320 0 0 0 vdd1v8
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
port 1 nsew power bidirectional
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
flabel metal3 11189 7491 11344 7551 0 FreeSans 320 0 0 0 por_l
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
port 4 nsew signal output
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
flabel metal3 11188 7856 11343 7916 0 FreeSans 320 0 0 0 porb_l
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
port 5 nsew signal output
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
flabel metal3 10969 6765 11342 6834 0 FreeSans 320 0 0 0 porb_h
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
port 3 nsew signal output
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
flabel metal1 -14 8544 58 8684 0 FreeSans 800 0 0 0 vss1v8
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
port 6 nsew ground bidirectional
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
flabel metal4 s 38 7255 232 7655 0 FreeSans 320 0 0 0 vss3v3
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
port 2 nsew ground bidirectional
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
<< properties >>
string FIXED_BBOX 0 0 11344 8338
Changed "simple_por" in both caravel and caravan to be an abstract view pointing to the contents of ../gds/ so that when the assembled chip's GDS is generated with "cif *hier write disable", the POR will continue to have the GDS with the proper hierarchical processing.
2021-11-27 10:51:30 -06:00
string GDS_FILE ../gds/simple_por.gds
string GDS_START 0
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) * Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. This commit does the following: (1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds. (2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds. (3) Corrects the xschem testbench to connect to both grounds of simple_por. (4) Corrects the simple_por layout to remove the 1.8V logic from the 3.3V ground and connect it instead to the 1.8V ground. (5) Extends the top-level power routing of caravel and caravan to make a better connection to the simple_por 1.8V ground. (6) Adds an LVS script to properly check the simple_por layout against the xschem-generated schematic netlist. NOTE: None of these modifications change the function of any circuit. The 1.8V and 3.3V ground nets are only logically separated in the netlists but share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds within the simple_por, where they were previously mingled. It also ensures that the full LVS for caravel and caravan can now include the simple_por at the transistor level and still pass. * Updated the GDS of simple_por (previously did not remove GDS_FILE from the .mag file and so it just overwrote the original GDS file with itself). * Corrected a route to simple_por in the top level of both caravel and caravan that was shorting to the extra metals put on top of the substrate contact across the top (bottom, in the top level) of the simple_por layout.
2022-05-09 00:51:29 -05:00
string LEFclass BLOCK
Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.
2021-11-15 09:34:52 -06:00
<< end >>