mirror of https://github.com/efabless/caravel.git
32 lines
971 B
Plaintext
32 lines
971 B
Plaintext
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Max transition on internal signals: 1.25ns
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Hold WNS (F2F): 0.00
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Setup WNS (F2F): -0.52 (ss-max)
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lvs clean: Y
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drc clean: Y
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cvc clean: Y
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Antenna Violations: 0
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Antenna Violations (400-500): 0
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Antenna Violations (500-800): 0
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Antenna Violations (800-1000): 0
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non-physical cells: 1530 - 1216 = 314
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decap cell count: 460
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% decap: 460 / 1530 * 100 = 30.1%
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max ir drop: 8.10e-10 V
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Verilog "assign" in the netlist: N
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Does the netlist show cells from different libraries: N
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Does the macro have mixed power domains powered cells: N
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Any internal macros with floating input ports: N
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Output ports not connected to any logic inside the macro: N
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Input ports not connected to any logic inside the macro: N
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Tri-state cells are connected directly to output ports: N
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Analog Signals are not digitally buffered: N
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Output ports are properly buffred (>=buf_4): Y
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buffer cells count: 49
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logic cells that are not buffers count: 265
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buf_1 & buf_2 cells count: 12
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0.5mm or longer wire count: 0
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