caravel/signoff/caravel_core/metrics.csv

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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_MAX_FANOUT,SYNTH_STRATEGY
/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core,caravel_core,23_04_11_05_23,flow completed,1h34m34s0ms,-1,5312.855528944219,15.087555,2656.4277644721096,17.15,80.0,7599.31,23756,0,0,0,0,0,0,16,22,22,-1,-1,-1,3963478,384634,-15.49,-1.36,-1,-2.6,0.0,-3717.86,-73.68,-1,-235.84,0.0,3492601925.0,0.0,22.16,20.07,6.93,2.91,4.02,16946,40270,4063,26506,0,0,0,21208,852,36,445,493,2745,738,98,4383,6959,7530,15,213540,67559,42710,32944,40079,396832,14916786.380800001,-1,-1,-1,-1,-1,-1,-1,-1,-1,20.97,25.0,40.0,25,1,50,360,264,0.06,1,0.29,1,sky130_fd_sc_hd,12,DELAY 1