mirror of https://github.com/efabless/caravel.git
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1.8 KiB
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43 lines
1.8 KiB
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<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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Programming
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===========
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The RISC-V architecture has a ``gcc`` compiler.
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The best reference for getting the correct cross-compiler version is the PicoRV32 source
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in the `cliffordwolf/picorv32 repository <https://github.com/cliffordwolf/picorv32>`_.
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Specifically, see the top-level ``README.md`` file section
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`Building a pure RV32I Toolchain <https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain>`_.
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For programming examples specifically for the Caravel chip
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(assuming a correct installation of a RISC-V ``gcc`` toolchain as described above),
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see `efabless/caravel repository <https://github.com/efabless/caravel>`_.
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The directory ``verilog/dv`` contains example source code to program the Ravenna chip
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along with the header file ``defs.h`` that defines the memory-mapped locations
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as described throughout this text.
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The ``verilog/dv`` directory contains a ``Makefile`` that compiles ``hex`` files
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and runs simulations of a number of test programs that exercise various features of the chip.
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Additional documentation exists on the same site for the provided demonstration circuit board and driver software.
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