330 lines
9.0 KiB
Plaintext
330 lines
9.0 KiB
Plaintext
# Alliance VLSI CAD System
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# Copyright (C) 1990, 2002 ASIM/LIP6/UPMC
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#
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# Home page : http://asim.lip6.fr/alliance/
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# E-mail support : mailto:alliance-support@asim.lip6.fr
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# ftp site : ftp://asim.lip6.fr/pub/alliance/
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#
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# NOTE: You can find the latest revision of this file at:
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# http://asim.lip6.fr/pub/alliance/unstable/cvstree/alliance/
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#
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# $Id: CHANGES,v 1.10 2002/02/21 11:04:52 czo Exp $
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This document lists the main differences between each Alliance's revisions.
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--------------------------------------------------------------------------------
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ALLIANCE revision 4.9.0 (2002/02/14)
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1/ New tools
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Place and Route:
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ocp and ocr replace scr.
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2/ This is pre-release 5.0 version.
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We have decided to remove in Alliance 5.0 all tools, libs, cell
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libs and documentation wich doesn't work or are obsolete :
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removed tools:
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ali algue amg bbr bop bsg c4map dlx_asm dlx_asm_v0_2 dpr fpgen fpmap
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genscan genview genview_cc1 genview_cpp genview_gcc glop grog k2f l2p
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mips_asm obsolete_bop obsolete_genscan obsolete_glop obsolete_scmap pocpag
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rage rfg rsa scmap scr sicc xvpn
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removed cells:
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amg bsg dplib fplib grog padlib rage rf2lib rfg rflib rsa sc2sxlib sclib
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3/ Renamed tools
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lynx is renamed cougar
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ali is renamed ale
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This is to avoid name clash with well known internet tools
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(btw: we had the anteriority of the name lynx...)
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--------------------------------------------------------------------------------
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ALLIANCE revision 4.5.0 (2001/10/11)
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1/ New tools
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Datapath:
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dpgen replaces fpgen and dpr is dead
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Synthesys :
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boom replaces bop
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boog replaces scmap
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loon replaces glop
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scanpath:
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scapin replace genscan
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2/ AP and AL format :
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new layers, new transistors
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--------------------------------------------------------------------------------
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ALLIANCE revision 4.0.9 (2001/02/21)
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1/ SXlib (man sxlib)
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is now the default standard cells library. sclib will be thrown away
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some day...
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2/ New Tools for place and route with silicon ensemble : (to replace scr)
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a2def
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a2lef
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def2a
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sea
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seplace
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seroute
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--------------------------------------------------------------------------------
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ALLIANCE release 4.0.6 (01/02/2000)
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1/ Public release
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2/ Fixed some Y2K small bugs
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- Dates on Alliance's parser/driver are in now the form : "dd/mm/YYYY"
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- Dates on Compass's parser/driver are in now the form : "dd-MON-YYYY"
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--------------------------------------------------------------------------------
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ALLIANCE revision 4.0 (15/10/99)
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1/ New Standard Cells Library : sxlib
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sxlib allows multi-layer over cell routing
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and all transitions are now on rising edge (man sxlib)
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2/ Improved Tools :
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- asimut is now a temporal logic simulator.
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You *must* modify your old pattern files to allow delays (man asimut)
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- syf can now handle vbe statements in .fsm
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- dreal : New viewing options ( like -install for private colormap)
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- graal : New viewing options ( like -install for private colormap)
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Input scale changeable, Hierarchy browser, real view (.cif/.gds)
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3/ New Tools :
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algue : ALliance Graphic User Environment
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ali : gives information on Alliance Environment
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b2f : FSM Abstraction from .vbe
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k2f : Translate kiss2 format <-> FSM format
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vasy : Translate .vhd format (Synopsys) <-> .vbe format
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xsch : Netlist viewer
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xfsm : FSM viewer
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xpat : patterns (with delay) viewer
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--------------------------------------------------------------------------------
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ALLIANCE revision 3.5 (19/06/98)
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1/ Lots of improvements and bug fixes
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2/ AP : Now supports ten layers of metal
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3/ AL : New support for RC net in losig. Parsers al, spice, vti modified.
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Modified Data Structures :
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- lotrs : added field BULK TRNAME
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- locon : added field PNODE
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- losig : added field PRCN, CAPA deleted
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Modified functions (the CAPA field has moved) :
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addlosig, addlotrs, dellosig
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4/ RCN : New library for RC support : Resistances on losig and capcitances
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between losig.
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--------------------------------------------------------------------------------
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ALLIANCE revision 3.2c (20/03/98)
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1/ Ap format :
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Alliance ap format now supports
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- half grid spacing
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- connectors somewhere else than abutment box.
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2/ VERILOG driver :
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Support added for Alliance-Cadence Toolbox
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3/ MBK_SCALE_X now defaults to 100
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--------------------------------------------------------------------------------
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ALLIANCE release 3.2b (15/12/97)
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1/ Easy install
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A "configure" script is now available to configure
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Alliance on any UNIX system
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2/ New driver :
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Support to VERILOG netlist as been added.
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Only driver exits. This means you can save your
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netlists to VERILOG format 'vlg'
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3/ New names :
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- Logic has been splited in 3 parts,
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. bop : boolean optimizer (logic -o)
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. scmap : Std cell mapping (logic -s)
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. c4map : CCCC mapping (logic -c)
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- Desb is replaced by yagle
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- Alligator is replaced by fpmap (X4000)
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- Netoptim is replaced glop
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4/ Cells libraries
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The tree of directories containing the cells
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libraries has been simplified
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--------------------------------------------------------------------------------
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ALLIANCE revision 3.2 (17/05/97)
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1/ GRAPHICAL PATTERN VIEWER
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In order to see the patterns resulting from a simulation,
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the XPAT tools has been developed.
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2/ GRAPHICAL FSM VIEWER
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In order to see the state's graph of an FSM the XFSM tools has
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been developed.
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3/ RECTANGLE LAYOUT VIEWER
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Now, DREAL is also a real layout editor.
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--------------------------------------------------------------------------------
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ALLIANCE release 3.0 (17/05/94)
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1/ FPGA SYNTHESIS
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A logic synthesis tools that maps on FPGA is now available.
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It works for X3000 devices
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2/ FLOOR-PLAN ROUTING
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Binaries of the CHEOPS router from BULL are available for sparc.
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3/ TIMING ANALYSIS
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The static timing analysis tools TAS is finally available.
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It can be targeted to several processes though the use of a technological
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file suffixed `elp'.
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4/ RECTANGLE LAYOUT VIEWER
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In order to see the layout resulting from a symbolic to real translation,
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the DREAL tools has been developed.
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--------------------------------------------------------------------------------
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ALLIANCE release 2.0 (14/02/94) versus ALLIANCE 1.2
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1/ SYMBOLIC LAYOUT EDITOR
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The symbolic layout editor ALC has been replaced by GRAAL.
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GRAAL provides the same functionalities than ALC, but is much
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more reliable. GRAAL support both CMOS and GaAs symbolic layout.
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> man graal
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2/ DESIGN RULE CHECKER
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The Design Rule Checker VERSATIL has been replaced by DRUC.
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DRUC provides the same functionnalities than VERSATIL.
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A hierarchical version will be distributed in the next ALLIANCE release.
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> man druc
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3/ LOGIC SYNTHESIS
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The logic synthesis tool LOGIC has been strongly improved.
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The new tool NETOPTIM is a gate-level net-list optimizer
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that allows to minimize delays in a synthesized gate net-list.
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The Finite-state-machine synthesizer SYF allows to describe and
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synthesize high complexity FSM (more than 100 states)
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It is possible to describe hierarchical FSM using stack (subroutines).
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> man logic
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> man syf
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> man netoptim
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4/ DATA-PATH COMPILER
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FPGEN is a data-path compiler using a dedicated macro-cells library.
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DPR is the place and route tool that creates optimized data-path blocks
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from the gate net-list generated by FPGEN.
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> man fpgen
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> man dpr
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5/ PARAMETERIZED MACRO-CELLS
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Six parameterized generators are part of this release:
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> man rsa # fast adder generator
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> man bsg # barrel shifter generator
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> man amg # multiplier generator
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> man rfg # register file generator
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> man grog # high speed ROM generator
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> man rage # static RAM generator
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6/ PROCEDURAL LAYOUT DEBUGGER
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The graphic debugger GENVIEW allows to debug custom blocks
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described with the procedural language GENLIB.
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It makes possible to design new parameterized generators, using the
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GENLIB language.
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> man genview
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7/ POSTSCIPT DRIVER
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The postscript driver MBK2PS has been replaced by L2P, in order to
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obtain a printable postscript file from a cell layout.
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This tool accept not only symbolic layout (.ap files) but also
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physical layout (.cif or .gds files).
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> man l2p
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8/ FLOOR-PLAN ROUTER
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There is no floor-plan router in this release.
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If you need to interconnect two blocks, you can use the BBR tool
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that is actually a simple gridless channel router.
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> man bbr
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9/ FILE FORMATS
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Both file formats .ap (symbolic layout) and .al (net-list)
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have been modified, with upward compatibility: all files
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created with ALLIANCE release 1.2 are readable and usable with
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ALLIANCE release 2.0.
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> man ap
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> man al
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10/ PROCESS MAPPING
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The S2R tool that performs the physical mapping to a target process
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has been documented: the procedure to parameterize the technology
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file is described in the doc/misc/process_mapping.ps file.
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The technology file format has been modified.
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> man s2r
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> man prol
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# EOF
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