997 lines
36 KiB
Plaintext
997 lines
36 KiB
Plaintext
#===============================================================================
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#
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# ALLIANCE VLSI CAD SYSTEM
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# (R)ectangle (D)ata (S)tructure parameter file for GaAs
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# (c) copyright 1995 Laboratoire UPMC/MASI/CAO-VLSI
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# all rights reserved
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# e-mail : cao-vlsi@masi.ibp.fr
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#
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# file : asga_6.rds
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# version : 6
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# last modif : July 02, 1995
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#
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#===============================================================================
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#-------------------------------------------------------------------------------
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# Title of the file : Symbolic to Symbolic on a 'one lambda equals lambda
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# microns' basis for Vitesse 0.8 micron GaAs technology
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#
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#-------------------------------------------------------------------------------
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#
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# Description of the file :
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# This file contains all the needed parameters to translate a symbolic layout to
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# a real layout.
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#
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#-------------------------------------------------------------------------------
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#
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# Note : all numeric values are in microns unless otherwise indicated.
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#
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#-------------------------------------------------------------------------------
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#
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# General information :
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# A few words on symbolic layout versus real layout :
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#
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# Symbolic layout is used to ease the designers work by using objects that
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# have a well specified semantic.
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# The C data structure used for the internal representation of these objects
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# is called ``MBK'', and comprehends, on a strictly layout point of view :
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#
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# - Connectors, they are the terminals for routers, simulation tools, etc...
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# these MBK primitives may be:
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# NWELL N type bulk connector
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# PWELL P type bulk connector
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# NTIE N type implant in P bulk connector
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# PTIE P type implant in N bulk connector
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# NDIF N type diffusion connector
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# PDIF P type diffusion connector
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# NTRANS N type transistor connector
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# PTRANS P type transistor connector
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# POLY polysilicon connector
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# ALU1 first metal connector
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# ALU2 second metal connector
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# ALU3 third metal connector
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# TPOLY polysilicon through route connector
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# TALU1 first metal through route connector
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# TALU2 second metal through route connector
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# TALU3 third metal through route connector
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#
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# - Segments, they are runs of a layer for leaf cells construction and
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# for routing; these may be:
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# NWELL N type bulk segment
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# PWELL P type bulk segment
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# NTIE N type implant in P bulk segment
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# PTIE P type implant in N bulk segment
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# NDIF N type diffusion segment
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# PDIF P type diffusion segment
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# NTRANS N type transistor segment
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# PTRANS P type transistor segment
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# POLY polysilicon segment
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# ALU1 first metal segment
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# ALU2 second metal segment
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# ALU3 third metal segment
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# TPOLY polysilicon through route segment
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# TALU1 first metal through route segment
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# TALU2 second metal through route segment
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# TALU3 third metal through route segment
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# note that transistors also are considered as segments.
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#
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# - References, for assigning a name to a symbolic object; these may be:
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# REF_CON used for multi-access connectors
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# REF_REF used for any other purpose
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#
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# - Vias, for connecting two segments of distinct layers together; these
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# MBK primitives may be:
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# CONT_BODY_P connects PWELL and ALU1
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# CONT_BODY_N connects NWELL and ALU1
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# CONT_DIF_N connects NDIF and ALU1
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# CONT_DIF_P connects PDIF and ALU1
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# CONT_POLY connects POLY and ALU1
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# CONT_VIA connects ALU1 and ALU2
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# CONT_VIA2 connects ALU2 and ALU3
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# CONT_VIA3 connects ALU3 and ALU4
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# C_X_N L shaped N transistor corner filling
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# C_X_P L shaped P transistor corner filling
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#
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# Factories usually only understand real layout which is given in terms of
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# rectangles or polygons. And some tools work only with rectangles. The data
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# structure based on such rectangles is called ``RDS'', for Rectangle Data
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# Structure. Extractors and DRCs also need rectangles to work on. Here is the
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# complete set of RDS layers:
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# RDS_NWELL N type bulk
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# RDS_PWELL P type bulk
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# RDS_NTIE N type implant in P type bulk
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# RDS_PTIE P type implant in N type bulk
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# RDS_NDIF N type diffusion
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# RDS_PDIF P type diffusion
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# RDS_ACTIV active area layer
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# RDS_NIMP N type implant
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# RDS_PIMP P type implant
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# RDS_POLY polysilicon
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# RDS_TPOLY polysilicon through route
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# RDS_CONT contact hole in isolation between a low
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# level layer and first metal
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# RDS_GATE transistor gate layer
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# RDS_ALU1 first metal
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# RDS_TALU1 first metal through route
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# RDS_VIA1 via hole in isolation between first metal
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# and second metal
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# RDS_ALU2 second metal
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# RDS_TALU2 second metal through route
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# RDS_VIA2 via hole in isolation between second metal
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# and third metal
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# RDS_ALU3 third metal
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# RDS_TALU3 third metal through route
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# RDS_VIA3 via hole in isolation between third metal
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# and fourth metal
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# RDS_ALU4 fourth metal
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# RDS_CPAS passivation contact layer
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# RDS_REF virtual layer for the representation of
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# symbolic references
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# RDS_USER0 user oriented layer
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# RDS_USER1 user oriented layer
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# RDS_USER2 user oriented layer
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# RDS_ABOX virtual layer containing information on the
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# abutment box of a model
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#
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# (Refer to documentation for more information)
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# physical_grid :
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#
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# Warning : physical_grid must be the first value to be declared.
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#
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# Most technolgies require that a layout be aligned on a physical grid. This
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# implies that all the coordinates and values given here after have to be
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# multiples of the value physical_grid. Misaligned objects in an input figure
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# is a problem that some tools like s2r solve by allowing themselves to expand
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# the width of these objects to have them snap to the grid.
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#-------------------------------------------------------------------------------
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DEFINE PHYSICAL_GRID 0.5
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#-------------------------------------------------------------------------------
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# lambda :
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#
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# Defines the value of lambda in the real or pseudo real (1 lambda = 1 micron)
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# technology. It is chosen, after a carefull observation of real design
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# rules.
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#
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# (Refer to documentation for more information)
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#-------------------------------------------------------------------------------
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DEFINE LAMBDA 1.0
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#-------------------------------------------------------------------------------
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# mbk_to_rds_segment table :
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#
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# This table describes how to translate one symbolic segment (MBK data
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# structure) to 1, 2, 3 or more physical rectangles (RDS data structure).
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#
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# o A transistor segment (MBK NTRANS or PTRANS layer) will generate in
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# general 3 to 6 rectangles (RDS_ACTIV, RDS_NIMP, RDS_POLY, [RDS_NDIF]*2).
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#
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# o An ohmic metal segment (MBK NDIF layer) will generate 2 rectangles
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# (RDS_ACTIV, RDS_NDIF).
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#
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# o All other MBK layers will generate one rectangle.
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#
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# For each physical rectangle (RDS layer) generated from an MBK segment, five
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# parameters are given :
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# - the RDS layer
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# - the type of offset of the rectangle : (L)eft, (R)igth, (U)p, (D)own, or
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# ()no offset
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# - the type of width of the rectangle : variable width (VW) or constant
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# width (CW)
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# - the physical length extension : DLR
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# and
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# - the physical width oversize : DWR for variable width rectangles
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# or
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# - the physical width : WR for constant width rectangles
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# and
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# - the value of the offset which is defined as the distance between the
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# edge of the RDS rectangle being processed that is closest to the center
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# of the given segment and the (R)ight or (L)eft edge of that segment
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# - the tool(s) concerned by the given translation. This parameter is needed
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# for Alliance editor graal (DRC) and extractor lynx (EXT) that require a
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# special transistor representation in order to properly detect
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# equipotential signals (i.e. no possible equipotential signal propagation
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# under transistors)
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#
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# The physical length of a rectangle is then given by :
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# - Physical LENGTH = Symbolic LENGTH * lambda + (2 * DLR)
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#
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# The physical width of a variable width rectangle is then given by :
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# - Physical WIDTH = Symbolic WIDTH * lambda + DWR
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#
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# The physical width of a constant width rectangle is then given by :
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# - Physical WIDTH = WR
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#
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# Note that most cases concern variable width rectangles where as constant
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# width rectangles are rarely encountered.
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#
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# This table is defined as follows :
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# The first column gives the MBK layer name that needs to be translated, the
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# following columns each represent an RDS layer with its associated parameters
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# described above. It is important that the first RDS layer of each composed
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# segment be the most representative, that it stands as the back bone of the
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# segment.
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#
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# MBK RDS layer i
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# name name type DLR (D)WR OFFSET TOOL\
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# name type DLR (D)WR OFFSET TOOL\
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# ...
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# name type DLR (D)WR OFFSET TOOL
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#-------------------------------------------------------------------------------
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TABLE MBK_TO_RDS_SEGMENT
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NDIF RDS_NDIF VW 1.0 0.0 0.0 ALL
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NTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \
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RDS_NDIF LCW -2.0 2.0 1.5 ALL \
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RDS_NDIF RCW -2.0 2.0 1.5 ALL \
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RDS_ACTIV VW -2.0 7.0 0.0 ALL
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# this layer is present only for educational and aesthetical purposes
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NWELL RDS_POLY VW 0.0 0.0 0.0 ALL \
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RDS_NDIF LCW -2.0 2.0 1.5 ALL \
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RDS_NDIF RCW -2.0 2.0 1.5 ALL \
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RDS_ACTIV LCW -2.0 3.0 0.5 ALL \
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RDS_ACTIV RCW -2.0 3.0 0.5 ALL \
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RDS_NIMP VW -1.5 1.0 0.0 ALL
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# these 3 layers are present only for educational and aesthetical purposes
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PTRANS RDS_POLY VW 0.0 0.0 0.0 ALL \
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RDS_POLY RCW 0.0 1.5 0.0 ALL \
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RDS_NDIF LCW -2.0 2.0 1.5 ALL \
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RDS_NDIF RCW -2.0 3.5 0.0 ALL \
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RDS_ACTIV LCW -2.0 3.0 0.5 ALL \
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RDS_ACTIV RCW -2.0 1.5 2.0 ALL \
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RDS_NIMP VW -1.5 1.0 0.0 ALL \
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RDS_NIMP RCW -1.5 2.0 0.0 ALL
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# these 4 last layers are present only for educational and aesthetical purposes
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POLY RDS_POLY VW 0.5 0.0 0.0 ALL
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ALU1 RDS_ALU1 VW 0.5 0.0 0.0 ALL
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ALU2 RDS_ALU2 VW 1.0 0.0 0.0 ALL
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ALU3 RDS_ALU3 VW 2.5 0.0 0.0 ALL
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TPOLY RDS_TPOLY VW 0.5 0.0 0.0 ALL
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TALU1 RDS_TALU1 VW 0.5 0.0 0.0 ALL
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TALU2 RDS_TALU2 VW 1.0 0.0 0.0 ALL
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TALU3 RDS_TALU3 VW 2.5 0.0 0.0 ALL
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END
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#-------------------------------------------------------------------------------
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# mbk_to_rds_connector table :
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#
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# This table explains how to translate symbolic connectors.
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#
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# one symbolic connector (MBK data structure) is translated into one physical
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# rectangle (RDS data structure) using 3 parameters :
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# - RDS layer
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# - physical width oversize : DWR
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# - physical extension on each side of the ABUTMENT BOX : DER
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#
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# Physical WIDTH = Symbolic WIDTH * lambda + DWR
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# Physical EXTENSION = 2 * DER
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#
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# This table is defined below :
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# The first column is the MBK layer name to be translated, after which there is
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# an RDS layer name, it's DWR value and it's DER value.
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#
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# MBK RDS layer
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# name name DER DWR
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#-------------------------------------------------------------------------------
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TABLE MBK_TO_RDS_CONNECTOR
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NDIF RDS_NDIF 1.0 0
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POLY RDS_POLY 0.5 0
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ALU1 RDS_ALU1 0.5 0
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ALU2 RDS_ALU2 1.0 0
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ALU3 RDS_ALU3 2.5 0
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END
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#-------------------------------------------------------------------------------
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# mbk_to_rds_reference table :
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#
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# This table explains how to translate symbolic references. These references,
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# both translated into an RDS_REF RDS layer offer the possibility to associate
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# a name to a point (a couple of coordinates). The REF_CON primitive is
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# exclusively used for the naming of vias while the other primitive is
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# reserved for any other naming purpose.
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#
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# (Refer to documentation for more information)
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#
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# MBK reference RDS layer
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# name name width
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#-------------------------------------------------------------------------------
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TABLE MBK_TO_RDS_REFERENCE
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REF_CON RDS_REF 1
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REF_REF RDS_REF 1
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END
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#-------------------------------------------------------------------------------
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# mbk_to_rds_via table :
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#
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# This table describes how to translate one symbolic via or primitive, (MBK
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# data structure) into 2, 3 or 4 physical rectangles (RDS data structure).
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#
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# This table is defined as follows :
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# The first column is the MBK via name to translate, after which comes a certain
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# number of groups of 2 columns. In a group the first column is the RDS layer
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# name, the second one is the RDS layer width.
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#
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# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4
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# name name width name width name width name width
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#-------------------------------------------------------------------------------
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TABLE MBK_TO_RDS_VIA
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CONT_DIF_N RDS_NDIF 2.0 ALL RDS_CONT 1.0 ALL RDS_ALU1 1.0 ALL
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CONT_POLY RDS_POLY 2.0 ALL RDS_CONT 1.0 ALL RDS_ALU1 1.0 ALL
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CONT_VIA RDS_ALU1 2.0 ALL RDS_VIA1 2.0 ALL RDS_ALU2 3.0 ALL
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CONT_VIA2 RDS_ALU2 5.0 ALL RDS_VIA2 3.0 ALL RDS_ALU3 5.0 ALL
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CONT_VIA3 RDS_ALU3 6.0 ALL RDS_VIA3 4.0 ALL RDS_ALU4 10.0 ALL
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END
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#-------------------------------------------------------------------------------
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# lynx_graph table :
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#
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# This table gives all the possible interconnections between RDS layers for
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# the propagation of equipotential signals. Each line in this table is to be
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# read independently as follows : RDS layer of first column is connected to
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# an RDS layer of another column if they overlap or touch. This table is useful
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# to any tool requirering equipotential analysis like lynx or graal.
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#-------------------------------------------------------------------------------
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TABLE LYNX_GRAPH
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RDS_NDIF RDS_POLY RDS_CONT RDS_NDIF
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RDS_POLY RDS_NDIF RDS_CONT RDS_POLY
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RDS_CONT RDS_NDIF RDS_POLY RDS_ALU1 RDS_CONT
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RDS_ALU1 RDS_CONT RDS_VIA1 RDS_REF RDS_ALU1
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RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1
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RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2
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RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2
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RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3
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RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3
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RDS_ALU4 RDS_VIA3 RDS_ALU4
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RDS_REF RDS_ALU1 RDS_REF
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END
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#-------------------------------------------------------------------------------
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# lynx_capa table :
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#
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# RDS layer Capacitance
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# name pF / Lambda^2
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#-------------------------------------------------------------------------------
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TABLE LYNX_CAPA
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RDS_POLY 0.791e-04
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RDS_ALU1 0.574e-04
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RDS_ALU2 0.347e-04
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RDS_ALU3 0.227e-04
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RDS_ALU4 0.083e-04
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END
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#---------------------------------------------------------------------
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# TABLE LYNX_RESISTOR :
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#
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# RDS layer Surface resistor
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# name Ohm / Micron^2
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#---------------------------------------------------------------------
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TABLE LYNX_RESISTOR
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END
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#-------------------------------------------------------------------------------
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# lynx_transistor table :
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#
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# MBK layer RDS layer Corner junction
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# name name name
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#-------------------------------------------------------------------------------
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TABLE LYNX_TRANSISTOR
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NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_ACTIV
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PTRANS PTRANS C_X_P RDS_POLY RDS_NDIF RDS_ACTIV
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NWELL PTRANS C_X_N RDS_POLY RDS_NDIF NULL
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END
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#-------------------------------------------------------------------------------
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# lynx_diffusion table :
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#
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# RDS layer RDS layer
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# name name
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#-------------------------------------------------------------------------------
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TABLE LYNX_DIFFUSION
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END
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#-------------------------------------------------------------------------------
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# cif_layer table :
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#
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# Equivalency table between RDS layer names and cif layer names.
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# RDS/cif parser and driver typically need this table.
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#-------------------------------------------------------------------------------
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TABLE CIF_LAYER
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RDS_NDIF LNDIF
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RDS_NIMP LNIMP
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RDS_ACTIV LACTIV
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RDS_POLY LPOLY
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RDS_TPOLY LTPOLY
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RDS_CONT LCONT
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RDS_ALU1 LALU1
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RDS_TALU1 LTALU1
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RDS_VIA1 LVIA1
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RDS_ALU2 LALU2
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RDS_TALU2 LTALU2
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RDS_VIA2 LVIA2
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RDS_ALU3 LALU3
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RDS_TALU3 LTALU3
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RDS_VIA3 LVIA3
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RDS_ALU4 LALU4
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RDS_REF LREF
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END
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#-------------------------------------------------------------------------------
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# gds_layer table :
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#
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# Equivalency table between RDS layer names and gds layer number.
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# RDS/gds parser and driver typically need this table.
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#-------------------------------------------------------------------------------
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TABLE GDS_LAYER
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RDS_NDIF 1
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RDS_NIMP 2
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RDS_ACTIV 3
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RDS_POLY 4
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RDS_TPOLY 5
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RDS_CONT 6
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RDS_ALU1 7
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RDS_TALU1 8
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RDS_VIA1 9
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RDS_ALU2 10
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RDS_TALU2 11
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RDS_VIA2 12
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RDS_ALU3 13
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RDS_TALU3 14
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RDS_VIA3 15
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RDS_ALU4 16
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RDS_REF 17
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END
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#-------------------------------------------------------------------------------
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# oversize_denotch table :
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#
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# This table contains the oversize value needed to erase notches. All the
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# rectangles in the same RDS layer are oversized by this value and then merged
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# all together and finally undersized by the same value.
|
|
#
|
|
# For some RDS layers, like RDS_NWELL, RDS_NIMP and RDS_PIMP, if two rectangles
|
|
# are separated from a distance that is smaller or equal to the minimun spacing
|
|
# design rule, then they must be merged as a single one. In this case, the
|
|
# oversize value is equal to the minimum spacing rule between two edges of the
|
|
# same layer divided by 2.
|
|
#
|
|
# Some other RDS layers, like RDS_ALU1, ..., must not be merged. In this case,
|
|
# the oversize value is equal to the minimum spacing rule between two edges of
|
|
# the same layer divided by 2, minus the physical grid.
|
|
#
|
|
# Some layers never create notches, such as RDS_VIA1 or RDS_CONT, so the
|
|
# oversize value is null.
|
|
#
|
|
# This table is useful for tools like s2r that work on a real level.
|
|
#-------------------------------------------------------------------------------
|
|
|
|
TABLE S2R_OVERSIZE_DENOTCH
|
|
|
|
# RDS_NDIF 0
|
|
# RDS_ACTIV 0
|
|
# RDS_NIMP 0
|
|
# RDS_POLY 0
|
|
# RDS_TPOLY 0
|
|
# RDS_CONT 0
|
|
# RDS_ALU1 0
|
|
# RDS_TALU1 0
|
|
# RDS_VIA1 0
|
|
# RDS_ALU2 0
|
|
# RDS_TALU2 0
|
|
# RDS_VIA2 0
|
|
# RDS_ALU3 0
|
|
# RDS_TALU3 0
|
|
# RDS_VIA3 0
|
|
# RDS_ALU4 0
|
|
# RDS_CPAS 0
|
|
# RDS_REF 0
|
|
# RDS_USER0 0
|
|
# RDS_USER1 0
|
|
# RDS_USER2 0
|
|
# RDS_ABOX 0
|
|
|
|
END
|
|
|
|
#-------------------------------------------------------------------------------
|
|
# bloc_ring_width table :
|
|
#
|
|
# The normal ring width is the minimum spacing design rule between 2 segments of
|
|
# the same RDS layer.
|
|
#
|
|
# A zero means that no ring is wanted for that RDS layer.
|
|
#
|
|
# s2r for example must merge segments to erase notches even if those segments
|
|
# are in two different hierarchical level blocs, for example, two blocs abuted
|
|
# side by side. So, it must be able to fetch segments inside blocs. It is not
|
|
# needed to flatten the entire bloc, only a ring is necessary. The ring is
|
|
# computed from the abutment box edges or from the envelope edges of the
|
|
# overlapping blocs.
|
|
#
|
|
# This table is useful for tools like s2r and druc that work on a real level.
|
|
#-------------------------------------------------------------------------------
|
|
|
|
TABLE S2R_BLOC_RING_WIDTH
|
|
|
|
RDS_NDIF 2.0
|
|
RDS_ACTIV 0
|
|
RDS_NIMP 0
|
|
RDS_POLY 2.0
|
|
RDS_TPOLY 0
|
|
# RDS_CONT 2.0
|
|
RDS_ALU1 2.5
|
|
RDS_TALU1 0
|
|
# RDS_VIA1 3.0
|
|
RDS_ALU2 2.0
|
|
RDS_TALU2 0
|
|
# RDS_VIA2 3.0
|
|
RDS_ALU3 6.0
|
|
RDS_TALU3 0
|
|
# RDS_VIA3 4.0
|
|
RDS_ALU4 0
|
|
RDS_CPAS 0
|
|
RDS_REF 0
|
|
RDS_USER0 0
|
|
RDS_USER1 0
|
|
RDS_USER2 0
|
|
RDS_ABOX 0
|
|
|
|
END
|
|
|
|
#-------------------------------------------------------------------------------
|
|
# minimum_layer_width table :
|
|
#
|
|
# This table contains the minimum width of each RDS layer. It is used by s2r for
|
|
# example to avoid creating rectangles having widths that are below the required
|
|
# minimum, during the merging operation.
|
|
#
|
|
# A zero can be specified, when it is certain that the given layer will not be
|
|
# merged.
|
|
#
|
|
# This table is useful for tools like s2r and druc that work on a real level.
|
|
#-------------------------------------------------------------------------------
|
|
|
|
TABLE S2R_MINIMUM_LAYER_WIDTH
|
|
|
|
RDS_NDIF 2.0
|
|
RDS_ACTIV 0
|
|
RDS_NIMP 0
|
|
RDS_POLY 1.0
|
|
RDS_TPOLY 0
|
|
RDS_CONT 1.0
|
|
RDS_ALU1 1.0
|
|
RDS_TALU1 0
|
|
RDS_VIA1 1.0
|
|
RDS_ALU2 2.0
|
|
RDS_TALU2 0
|
|
RDS_VIA2 3.0
|
|
RDS_ALU3 5.0
|
|
RDS_TALU3 0
|
|
RDS_VIA3 4.0
|
|
RDS_ALU4 0
|
|
RDS_CPAS 0
|
|
RDS_REF 0
|
|
RDS_USER0 0
|
|
RDS_USER1 0
|
|
RDS_USER2 0
|
|
RDS_ABOX 0
|
|
|
|
END
|
|
|
|
#-------------------------------------------------------------------------------
|
|
# s2r_post_treat table :
|
|
#
|
|
# This table tells s2r which RDS layers must be post-treated. And more
|
|
# specificaly if a layer is only to be be translated, or if it has to be
|
|
# translated and then post-treated.
|
|
# To translate means to translate and fit from symbolic to real.
|
|
# To post-treat means that it should also be merged with its neighbours.
|
|
# For example, it is not necessary to merge cut layers such as RDS_CONT.
|
|
#
|
|
# If set to NOTREAT, the first parameter indicates a translation.
|
|
# If set to TREAT, then the layer is translated and then post-treated.
|
|
#
|
|
# To post-treat creates problems with implantation layers. It is possible to
|
|
# have a good symbolic layout (no symbolic design rule errors), and have a
|
|
# resulting layout with drc violations; this case is usually the result of a
|
|
# poor post-treatement. This is due to the fact that these layers do not exist
|
|
# in symbolic, so it is not possible to apply to them any symbolic drc
|
|
# verifications. If two rectangles of these layers are too close (less than a
|
|
# given value), they must be merged. Generally, there is no problem, but when
|
|
# corners are too near it is impossible to merge with the classical algorithms :
|
|
# expand,
|
|
# merge,
|
|
# shrink.
|
|
# Rectangles, known as scotches, are in such a case created for merging.
|
|
# Here is an example :
|
|
#
|
|
# +--------+ +--------+ +-----+--+
|
|
# |////////| |////////| |/////|//|
|
|
# |//+--+//| |//+--+//| |//+--|//|
|
|
# |//| |//| gives -> |//| |//| or -> |//| |//|
|
|
# |//+--+//| +-----------+ |//+--|//|
|
|
# |////////| |///////////| |/////|//|
|
|
# +--------+ +--------+//| +-----|//|
|
|
# ^ +--------+ |//|-----+ |//+--------+
|
|
# | |////////| |//|/////| |///////////|
|
|
# o--->|//+--+//| |//|--+//| +-----------+
|
|
# | |//| |//| |//| |//| |//| |//|
|
|
# implant |//+--+//| |//|--+//| |//|--+//|
|
|
# areas |////////| |//|/////| |//|/////|
|
|
# +--------+ +--+-----+ +--+-----+
|
|
#
|
|
# An N implantation layer should not overlap a P implantation layer. We say
|
|
# that P implantations and N implantations are complementary. A scotch will
|
|
# not be created if it intersects with any of the rectangles of the
|
|
# complementary layers.
|
|
#
|
|
# If a record contains in the second field an RDS layer that is different
|
|
# from NULL, it indicates the complementary layer. This implies that if it
|
|
# is a layer that might need scotches the algorithm will try not to intersect
|
|
# with it when creating scotches.
|
|
#-------------------------------------------------------------------------------
|
|
|
|
TABLE S2R_POST_TREAT
|
|
|
|
RDS_NDIF TREAT NULL
|
|
RDS_ACTIV NOTREAT NULL
|
|
RDS_NIMP NOTREAT NULL
|
|
RDS_POLY TREAT NULL
|
|
RDS_TPOLY NOTREAT NULL
|
|
RDS_CONT NOTREAT NULL
|
|
RDS_ALU1 TREAT NULL
|
|
RDS_TALU1 NOTREAT NULL
|
|
RDS_VIA1 NOTREAT NULL
|
|
RDS_ALU2 TREAT NULL
|
|
RDS_TALU2 NOTREAT NULL
|
|
RDS_VIA2 NOTREAT NULL
|
|
RDS_ALU3 TREAT NULL
|
|
RDS_TALU3 NOTREAT NULL
|
|
RDS_VIA3 NOTREAT NULL
|
|
RDS_ALU4 NOTREAT NULL
|
|
RDS_CPAS NOTREAT NULL
|
|
RDS_REF NOTREAT NULL
|
|
RDS_USER0 NOTREAT NULL
|
|
RDS_USER1 NOTREAT NULL
|
|
RDS_USER2 NOTREAT NULL
|
|
RDS_ABOX NOTREAT NULL
|
|
|
|
END
|
|
DRC_RULES
|
|
layer RDS_ACTIV 2.0;
|
|
layer RDS_POLY 1.0;
|
|
layer RDS_NDIF 2.0;
|
|
layer RDS_ALU1 1.0;
|
|
layer RDS_CONT 1.0;
|
|
layer RDS_ALU2 2.0;
|
|
layer RDS_VIA1 2.0;
|
|
layer RDS_ALU3 5.0;
|
|
layer RDS_VIA2 3.0;
|
|
layer RDS_VIA3 4.0;
|
|
|
|
regles
|
|
|
|
caracterise RDS_POLY (
|
|
regle 100 : longueur_inter min 1.0;
|
|
regle 101 : notch >= 2.0;
|
|
);
|
|
|
|
relation RDS_POLY, RDS_POLY (
|
|
regle 102 : distance axiale min 2.0;
|
|
);
|
|
|
|
relation RDS_POLY, RDS_NDIF (
|
|
regle 103 : distance axiale min 1.5;
|
|
regle 104 : enveloppe inferieure min 1.0;
|
|
regle 105 : marge penetre_inter min 1.5;
|
|
regle 106 : marge inferieure min 1.0;
|
|
regle 107 : croix perpendiculaire_inter min 1.5;
|
|
regle 108 : croix longueur_min min 1.0;
|
|
);
|
|
|
|
relation RDS_POLY, RDS_NDIF (
|
|
regle 109 : intersection longueur_inter min 2.0;
|
|
regle 110 : intersection largeur_inter min 1.5;
|
|
regle 111 : intersection inferieure min 1.0;
|
|
regle 112 : extension largeur_inter min 1.5;
|
|
regle 113 : extension longueur_min min 1.0;
|
|
);
|
|
|
|
caracterise RDS_NDIF (
|
|
regle 120 : longueur_inter min 2.0;
|
|
regle 121 : notch >= 2.0;
|
|
);
|
|
|
|
relation RDS_NDIF, RDS_NDIF (
|
|
regle 122 : distance axiale min 2.0;
|
|
);
|
|
|
|
relation RDS_NDIF, RDS_POLY (
|
|
regle 123 : enveloppe superieure min 2.0;
|
|
regle 124 : enveloppe inferieure min 1.0;
|
|
regle 125 : enveloppe largeur_inter min 1.5;
|
|
regle 126 : marge longueur_max min 2.0;
|
|
regle 127 : marge inferieure min 1.0;
|
|
);
|
|
|
|
relation RDS_NDIF, RDS_POLY (
|
|
regle 128 : croix longueur_max min 2.0;
|
|
regle 129 : croix longueur_min min 1.0;
|
|
regle 130 : intersection longueur_max min 2.0;
|
|
regle 131 : intersection largeur_min min 1.0;
|
|
regle 132 : extension longueur_min min 2.0;
|
|
);
|
|
|
|
caracterise RDS_ALU1 (
|
|
regle 140 : longueur_inter min 1.0;
|
|
regle 141 : notch >= 3.0;
|
|
);
|
|
|
|
relation RDS_ALU1, RDS_ALU1 (
|
|
regle 142 : distance axiale min 3.0;
|
|
);
|
|
|
|
caracterise RDS_CONT (
|
|
regle 160 : longueur_inter min 1.0;
|
|
regle 161 : notch >= 2.0;
|
|
);
|
|
|
|
relation RDS_CONT, RDS_CONT (
|
|
regle 162 : distance axiale min 2.0;
|
|
);
|
|
|
|
define RDS_CONT, RDS_POLY inclusion -> CONTinPOLY;
|
|
|
|
relation CONTinPOLY, CONTinPOLY (
|
|
regle 163 : distance axiale min 4.0;
|
|
);
|
|
|
|
define RDS_CONT, RDS_NDIF inclusion -> CONTinNDIF;
|
|
|
|
relation RDS_NDIF, CONTinNDIF (
|
|
regle 170 : distance axiale min 3.0;
|
|
);
|
|
|
|
#relation RDS_ACTIV, CONTinNDIF (
|
|
# regle 171 : distance axiale <> 2.5;
|
|
#);
|
|
|
|
relation CONTinNDIF, CONTinPOLY (
|
|
regle 172 : distance axiale min 4.0;
|
|
);
|
|
|
|
relation CONTinNDIF, CONTinNDIF (
|
|
regle 173 : distance axiale min 4.0;
|
|
);
|
|
|
|
define RDS_CONT, CONTinNDIF exclusion -> CONT_NDIF;
|
|
|
|
relation CONT_NDIF, RDS_NDIF (
|
|
regle 174 : distance axiale min 1.0;
|
|
regle 175 : enveloppe surface_inter < 0.0;
|
|
regle 176 : marge surface_inter < 0.0;
|
|
regle 177 : croix surface_inter < 0.0;
|
|
regle 178 : intersection surface_inter < 0.0;
|
|
regle 179 : extension surface_inter < 0.0;
|
|
);
|
|
|
|
undefine CONT_NDIF;
|
|
undefine CONTinNDIF;
|
|
undefine CONTinPOLY;
|
|
|
|
caracterise RDS_VIA1 (
|
|
regle 180 : longueur < 6.0;
|
|
regle 181 : longueur_inter min 2.0;
|
|
regle 182 : notch >= 2.0;
|
|
);
|
|
|
|
relation RDS_VIA1, RDS_VIA1 (
|
|
regle 183 : distance axiale min 2.0;
|
|
);
|
|
|
|
relation RDS_VIA1, RDS_CONT (
|
|
regle 184 : distance axiale min 1.5;
|
|
regle 185 : enveloppe longueur_inter < 0.0;
|
|
regle 186 : marge longueur_inter < 0.0;
|
|
regle 187 : croix longueur_inter < 0.0;
|
|
regle 188 : intersection longueur_inter < 0.0;
|
|
regle 189 : extension longueur_inter < 0.0;
|
|
regle 190 : inclusion longueur_inter < 0.0;
|
|
);
|
|
|
|
caracterise RDS_ALU2 (
|
|
regle 200 : longueur_inter min 2.0;
|
|
regle 201 : notch >= 2.0;
|
|
);
|
|
|
|
relation RDS_ALU2, RDS_ALU2 (
|
|
regle 202 : distance axiale min 2.0;
|
|
);
|
|
|
|
caracterise RDS_VIA2 (
|
|
regle 220 : longueur_inter min 3.0;
|
|
regle 221 : notch >= 3.0;
|
|
);
|
|
|
|
relation RDS_VIA2, RDS_VIA2 (
|
|
regle 222 : distance axiale min 3.0;
|
|
);
|
|
|
|
relation RDS_VIA2, RDS_VIA1 (
|
|
regle 223 : distance axiale min 1.0;
|
|
regle 224 : enveloppe longueur_inter < 0.0;
|
|
regle 225 : marge longueur_inter < 0.0;
|
|
regle 226 : croix longueur_inter < 0.0;
|
|
regle 227 : intersection longueur_inter < 0.0;
|
|
regle 228 : extension longueur_inter < 0.0;
|
|
regle 229 : inclusion longueur_inter < 0.0;
|
|
);
|
|
|
|
caracterise RDS_ALU3 (
|
|
regle 240 : longueur_inter min 5.0;
|
|
regle 241 : notch >= 6.0;
|
|
);
|
|
|
|
relation RDS_ALU3, RDS_ALU3 (
|
|
regle 242 : distance axiale min 6.0;
|
|
);
|
|
|
|
relation RDS_VIA1, RDS_ALU3 (
|
|
regle 250 : enveloppe superieure max 3.0;
|
|
regle 251 : marge superieure max 3.0;
|
|
regle 252 : croix longueur_max max 3.0;
|
|
regle 253 : intersection superieure max 3.0;
|
|
regle 254 : extension longueur_max max 3.0;
|
|
);
|
|
|
|
caracterise RDS_VIA3 (
|
|
regle 260 : longueur_inter min 4.0;
|
|
regle 261 : notch >= 4.0;
|
|
);
|
|
|
|
relation RDS_VIA3, RDS_VIA3 (
|
|
regle 262 : distance axiale min 4.0;
|
|
);
|
|
|
|
define RDS_NDIF, RDS_POLY intersection -> CONT_O;
|
|
|
|
relation CONT_O, RDS_CONT (
|
|
regle 300 : marge frontale min 2.0;
|
|
regle 301 : enveloppe inferieure min 2.0;
|
|
);
|
|
|
|
define RDS_CONT, RDS_NDIF inclusion -> CONTinNDIF;
|
|
|
|
relation CONT_O, CONTinNDIF (
|
|
regle 302 : distance axiale min 1.0;
|
|
regle 303 : croix surface_inter < 0.0;
|
|
regle 304 : intersection surface_inter < 0.0;
|
|
regle 305 : extension surface_inter < 0.0;
|
|
regle 306 : inclusion longueur_inter < 0.0;
|
|
);
|
|
|
|
undefine CONTinNDIF;
|
|
undefine CONT_O;
|
|
|
|
fin regles
|
|
END_DRC_RULES
|
|
DRC_COMMENT
|
|
END_DRC_COMMENT
|
|
100 error : minimum Gate intersection width is 1.0
|
|
101 error : minimum Gate notch is 2.0
|
|
102 error : minimum Gate/Gate edge to edge distance is 2.0
|
|
103 error : minimum Gate/Ohm edge to edge distance is 1.5
|
|
104 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
|
|
105 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
|
|
106 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
|
|
107 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
|
|
108 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
|
|
109 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
|
|
110 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
|
|
111 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
|
|
112 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
|
|
113 error : minimum Gate/Ohm extension is 1.0 for a contact0 structure
|
|
120 error : minimum Ohm intersection width is 2.0
|
|
121 error : minimum Ohm notch is 2.0
|
|
122 error : minimum Ohm/Ohm edge to edge distance is 2.0
|
|
123 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
|
|
124 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
|
|
125 warning : minimum Gate/Ohm intersection geometry is 1.5 x 2.0 for a contact0 structure
|
|
126 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
|
|
127 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
|
|
128 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
|
|
129 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
|
|
130 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
|
|
131 error : minimum Ohm/Gate extension is 1.0 for a contact0 structure
|
|
132 error : Ohm/Gate extension must be at least 2.0 on one of the largest side of a contact0 structure
|
|
140 error : minimum Alu1 intersection width is 1.0
|
|
141 error : minimum Alu1 notch is 3.0
|
|
142 error : minimum Alu1/Alu1 edge to edge distance is 3.0
|
|
160 error : minimum via1 intersection width is 1.0
|
|
161 error : minimum via1 notch is 2.0
|
|
162 error : minimum via1/via1 edge to edge distance is 2.0
|
|
163 error : minimum Cont_Gate/Cont_Gate edge to edge distance is 3.0
|
|
170 error : minimum Cont_Ohm/Ohm edge to edge distance is 2.5
|
|
#171 error : minimum Cont_Ohm/Active edge to edge distance is 2.5
|
|
172 error : minimum Cont_Ohm/Cont_Gate edge to edge distance is 3.0
|
|
173 error : minimum Cont_Ohm/Cont_Ohm edge to edge distance is 3.0
|
|
174 error : minimum via1/Ohm edge to edge distance is 1.0
|
|
175 error : via1 must be either completely internal to or external to Ohm
|
|
176 error : via1 must be either completely internal to or external to Ohm
|
|
177 error : via1 must be either completely internal to or external to Ohm
|
|
178 error : via1 must be either completely internal to or external to Ohm
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179 error : via1 must be either completely internal to or external to Ohm
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180 warning : maximum geometry of intersecting via2s is 5 x 5
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181 error : minimum via2 intersection width is 2.0
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182 error : minimum via2 notch is 2.0
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183 error : minimum via2/via2 edge to edge distance is 2.0
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184 error : minimum via2/via1 edge to edge distance is 1.5
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185 error : via1 may not be nested in via2
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186 error : via2 and via1 may not intersect
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187 error : via2 and via1 may not intersect
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188 error : via2 and via1 may not intersect
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189 error : via2 and via1 may not intersect
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190 error : via2 may not be nested in via1
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200 error : minimum Alu2 intersection width is 2.0
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201 error : minimum Alu2 notch is 2.0
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202 error : minimum Alu2/Alu2 edge to edge distance is 2.0
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220 error : minimum via3 intersection width is 3.0
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221 error : minimum via3 notch is 3.0
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222 error : minimum via3/via3 edge to edge distance is 3.0
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223 error : minimum via3/via2 edge to edge distance is 1.0
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224 error : via2 may not be nested in via3
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225 error : via3 and via2 may not intersect
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226 error : via3 and via2 may not intersect
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227 error : via3 and via2 may not intersect
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228 error : via3 and via2 may not intersect
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229 error : via3 may not be nested in via2
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240 error : minimum Alu3 intersection width is 5.0
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241 error : minimum Alu3 notch is 6.0
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242 error : minimum Alu3/Alu3 edge to edge distance is 6.0
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250 error : minimum via2/Alu3 extension may not exceed 3
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251 error : minimum via2/Alu3 extension may not exceed 3
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252 error : minimum via2/Alu3 extension may not exceed 3
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253 error : minimum via2/Alu3 extension may not exceed 3
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254 error : minimum via2/Alu3 extension may not exceed 3
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260 error : minimum via4 intersection width is 4.0
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261 error : minimum via4 notch is 4.0
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262 error : minimum via4/via4 edge to edge distance is 4.0
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300 error : minimum cont0/via1 frontal extension is 2.0
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301 error : minimum cont0/via1 extension is 2.0
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302 error : minimum cont0/via1 edge to edge distance is 1.0
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303 error : contact0 and via1 may not intersect in this way
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304 error : contact0 and via1 may not intersect in this way
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305 error : contact0 and via1 may not intersect in this way
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306 error : contact0 and via1 may not intersect in this way
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